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* [PATCH RESEND] drm/i915: Revert DisplayPort fast link training feature
@ 2016-06-20  8:10 ` Mika Kahola
  0 siblings, 0 replies; 5+ messages in thread
From: Mika Kahola @ 2016-06-20  8:10 UTC (permalink / raw)
  To: intel-gfx; +Cc: stable

It has been found out that in some HW combination the DisplayPort
fast link training feature caused screen flickering. Let's revert
this feature for now until we can ensure that the feature works for
all platforms.

This is a manual revert of commits 5fa836a9d859 ("drm/i915: DP link
training optimization") and 4e96c97742f4 ("drm/i915: eDP link training
optimization").

Fixes: 5fa836a9d859 ("drm/i915: DP link training optimization")
Fixes: 4e96c97742f4 ("drm/i915: eDP link training optimization")
Cc: <stable@vger.kernel.org> # v4.2+

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c               |  3 ---
 drivers/gpu/drm/i915/intel_dp_link_training.c | 26 ++------------------------
 drivers/gpu/drm/i915/intel_drv.h              |  2 --
 3 files changed, 2 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index be08351..3cdea4d7a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4621,9 +4621,6 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
 	intel_display_power_get(dev_priv, power_domain);
 
 	if (long_hpd) {
-		/* indicate that we need to restart link training */
-		intel_dp->train_set_valid = false;
-
 		intel_dp_long_pulse(intel_dp->attached_connector);
 		if (intel_dp->is_mst)
 			ret = IRQ_HANDLED;
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
index 0b8eefc..60fb39c 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -85,8 +85,7 @@ static bool
 intel_dp_reset_link_train(struct intel_dp *intel_dp,
 			uint8_t dp_train_pat)
 {
-	if (!intel_dp->train_set_valid)
-		memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
+	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
 	intel_dp_set_signal_levels(intel_dp);
 	return intel_dp_set_link_train(intel_dp, dp_train_pat);
 }
@@ -161,23 +160,6 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 			break;
 		}
 
-		/*
-		 * if we used previously trained voltage and pre-emphasis values
-		 * and we don't get clock recovery, reset link training values
-		 */
-		if (intel_dp->train_set_valid) {
-			DRM_DEBUG_KMS("clock recovery not ok, reset");
-			/* clear the flag as we are not reusing train set */
-			intel_dp->train_set_valid = false;
-			if (!intel_dp_reset_link_train(intel_dp,
-						       DP_TRAINING_PATTERN_1 |
-						       DP_LINK_SCRAMBLING_DISABLE)) {
-				DRM_ERROR("failed to enable link training\n");
-				return;
-			}
-			continue;
-		}
-
 		/* Check to see if we've tried the max voltage */
 		for (i = 0; i < intel_dp->lane_count; i++)
 			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
@@ -284,7 +266,6 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 		/* Make sure clock is still ok */
 		if (!drm_dp_clock_recovery_ok(link_status,
 					      intel_dp->lane_count)) {
-			intel_dp->train_set_valid = false;
 			intel_dp_link_training_clock_recovery(intel_dp);
 			intel_dp_set_link_train(intel_dp,
 						training_pattern |
@@ -301,7 +282,6 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 
 		/* Try 5 times, then try clock recovery if that fails */
 		if (tries > 5) {
-			intel_dp->train_set_valid = false;
 			intel_dp_link_training_clock_recovery(intel_dp);
 			intel_dp_set_link_train(intel_dp,
 						training_pattern |
@@ -322,10 +302,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 
 	intel_dp_set_idle_link_train(intel_dp);
 
-	if (channel_eq) {
-		intel_dp->train_set_valid = true;
+	if (channel_eq)
 		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
-	}
 }
 
 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0c1dc9b..9257f08 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -894,8 +894,6 @@ struct intel_dp {
 	/* This is called before a link training is starterd */
 	void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 
-	bool train_set_valid;
-
 	/* Displayport compliance testing */
 	unsigned long compliance_test_type;
 	unsigned long compliance_test_data;
-- 
1.9.1


^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [PATCH RESEND] drm/i915: Revert DisplayPort fast link training feature
@ 2016-06-20  8:10 ` Mika Kahola
  0 siblings, 0 replies; 5+ messages in thread
From: Mika Kahola @ 2016-06-20  8:10 UTC (permalink / raw)
  To: intel-gfx; +Cc: stable

It has been found out that in some HW combination the DisplayPort
fast link training feature caused screen flickering. Let's revert
this feature for now until we can ensure that the feature works for
all platforms.

This is a manual revert of commits 5fa836a9d859 ("drm/i915: DP link
training optimization") and 4e96c97742f4 ("drm/i915: eDP link training
optimization").

Fixes: 5fa836a9d859 ("drm/i915: DP link training optimization")
Fixes: 4e96c97742f4 ("drm/i915: eDP link training optimization")
Cc: <stable@vger.kernel.org> # v4.2+

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c               |  3 ---
 drivers/gpu/drm/i915/intel_dp_link_training.c | 26 ++------------------------
 drivers/gpu/drm/i915/intel_drv.h              |  2 --
 3 files changed, 2 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index be08351..3cdea4d7a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4621,9 +4621,6 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
 	intel_display_power_get(dev_priv, power_domain);
 
 	if (long_hpd) {
-		/* indicate that we need to restart link training */
-		intel_dp->train_set_valid = false;
-
 		intel_dp_long_pulse(intel_dp->attached_connector);
 		if (intel_dp->is_mst)
 			ret = IRQ_HANDLED;
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
index 0b8eefc..60fb39c 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -85,8 +85,7 @@ static bool
 intel_dp_reset_link_train(struct intel_dp *intel_dp,
 			uint8_t dp_train_pat)
 {
-	if (!intel_dp->train_set_valid)
-		memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
+	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
 	intel_dp_set_signal_levels(intel_dp);
 	return intel_dp_set_link_train(intel_dp, dp_train_pat);
 }
@@ -161,23 +160,6 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 			break;
 		}
 
-		/*
-		 * if we used previously trained voltage and pre-emphasis values
-		 * and we don't get clock recovery, reset link training values
-		 */
-		if (intel_dp->train_set_valid) {
-			DRM_DEBUG_KMS("clock recovery not ok, reset");
-			/* clear the flag as we are not reusing train set */
-			intel_dp->train_set_valid = false;
-			if (!intel_dp_reset_link_train(intel_dp,
-						       DP_TRAINING_PATTERN_1 |
-						       DP_LINK_SCRAMBLING_DISABLE)) {
-				DRM_ERROR("failed to enable link training\n");
-				return;
-			}
-			continue;
-		}
-
 		/* Check to see if we've tried the max voltage */
 		for (i = 0; i < intel_dp->lane_count; i++)
 			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
@@ -284,7 +266,6 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 		/* Make sure clock is still ok */
 		if (!drm_dp_clock_recovery_ok(link_status,
 					      intel_dp->lane_count)) {
-			intel_dp->train_set_valid = false;
 			intel_dp_link_training_clock_recovery(intel_dp);
 			intel_dp_set_link_train(intel_dp,
 						training_pattern |
@@ -301,7 +282,6 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 
 		/* Try 5 times, then try clock recovery if that fails */
 		if (tries > 5) {
-			intel_dp->train_set_valid = false;
 			intel_dp_link_training_clock_recovery(intel_dp);
 			intel_dp_set_link_train(intel_dp,
 						training_pattern |
@@ -322,10 +302,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 
 	intel_dp_set_idle_link_train(intel_dp);
 
-	if (channel_eq) {
-		intel_dp->train_set_valid = true;
+	if (channel_eq)
 		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
-	}
 }
 
 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0c1dc9b..9257f08 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -894,8 +894,6 @@ struct intel_dp {
 	/* This is called before a link training is starterd */
 	void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 
-	bool train_set_valid;
-
 	/* Displayport compliance testing */
 	unsigned long compliance_test_type;
 	unsigned long compliance_test_data;
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* ✓ Ro.CI.BAT: success for drm/i915: Revert DisplayPort fast link training feature (rev2)
  2016-06-20  8:10 ` Mika Kahola
  (?)
@ 2016-06-20  8:27 ` Patchwork
  -1 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2016-06-20  8:27 UTC (permalink / raw)
  To: Mika Kahola; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Revert DisplayPort fast link training feature (rev2)
URL   : https://patchwork.freedesktop.org/series/8828/
State : success

== Summary ==

Series 8828v2 drm/i915: Revert DisplayPort fast link training feature
http://patchwork.freedesktop.org/api/1.0/series/8828/revisions/2/mbox


ro-bsw-n3050     total:223  pass:18   dwarn:0   dfail:0   fail:0   skip:205
ro-bdw-i5-5250u failed to connect after reboot
ro-bdw-i7-5557U failed to connect after reboot
ro-bdw-i7-5600u failed to connect after reboot
ro-byt-n2820 failed to connect after reboot
ro-hsw-i3-4010u failed to connect after reboot
ro-hsw-i7-4770r failed to connect after reboot
ro-ilk1-i5-650 failed to connect after reboot
ro-ilk-i7-620lm failed to connect after reboot
ro-ivb2-i7-3770 failed to connect after reboot
ro-ivb-i7-3770 failed to connect after reboot
ro-skl3-i5-6260u failed to connect after reboot
ro-snb-i7-2620M failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1231/

43b4244 drm-intel-nightly: 2016y-06m-19d-22h-30m-37s UTC integration manifest
d5ac0f5 drm/i915: Revert DisplayPort fast link training feature

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH RESEND] drm/i915: Revert DisplayPort fast link training feature
  2016-06-20  8:10 ` Mika Kahola
@ 2016-06-20  9:48   ` Jani Nikula
  -1 siblings, 0 replies; 5+ messages in thread
From: Jani Nikula @ 2016-06-20  9:48 UTC (permalink / raw)
  To: Mika Kahola, intel-gfx; +Cc: stable

On Mon, 20 Jun 2016, Mika Kahola <mika.kahola@intel.com> wrote:
> It has been found out that in some HW combination the DisplayPort
> fast link training feature caused screen flickering. Let's revert
> this feature for now until we can ensure that the feature works for
> all platforms.
>
> This is a manual revert of commits 5fa836a9d859 ("drm/i915: DP link
> training optimization") and 4e96c97742f4 ("drm/i915: eDP link training
> optimization").
>
> Fixes: 5fa836a9d859 ("drm/i915: DP link training optimization")
> Fixes: 4e96c97742f4 ("drm/i915: eDP link training optimization")
> Cc: <stable@vger.kernel.org> # v4.2+
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

Pushed to drm-intel-next-queued, thanks for the patch.

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/intel_dp.c               |  3 ---
>  drivers/gpu/drm/i915/intel_dp_link_training.c | 26 ++------------------------
>  drivers/gpu/drm/i915/intel_drv.h              |  2 --
>  3 files changed, 2 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index be08351..3cdea4d7a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4621,9 +4621,6 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
>  	intel_display_power_get(dev_priv, power_domain);
>  
>  	if (long_hpd) {
> -		/* indicate that we need to restart link training */
> -		intel_dp->train_set_valid = false;
> -
>  		intel_dp_long_pulse(intel_dp->attached_connector);
>  		if (intel_dp->is_mst)
>  			ret = IRQ_HANDLED;
> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
> index 0b8eefc..60fb39c 100644
> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> @@ -85,8 +85,7 @@ static bool
>  intel_dp_reset_link_train(struct intel_dp *intel_dp,
>  			uint8_t dp_train_pat)
>  {
> -	if (!intel_dp->train_set_valid)
> -		memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
> +	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
>  	intel_dp_set_signal_levels(intel_dp);
>  	return intel_dp_set_link_train(intel_dp, dp_train_pat);
>  }
> @@ -161,23 +160,6 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
>  			break;
>  		}
>  
> -		/*
> -		 * if we used previously trained voltage and pre-emphasis values
> -		 * and we don't get clock recovery, reset link training values
> -		 */
> -		if (intel_dp->train_set_valid) {
> -			DRM_DEBUG_KMS("clock recovery not ok, reset");
> -			/* clear the flag as we are not reusing train set */
> -			intel_dp->train_set_valid = false;
> -			if (!intel_dp_reset_link_train(intel_dp,
> -						       DP_TRAINING_PATTERN_1 |
> -						       DP_LINK_SCRAMBLING_DISABLE)) {
> -				DRM_ERROR("failed to enable link training\n");
> -				return;
> -			}
> -			continue;
> -		}
> -
>  		/* Check to see if we've tried the max voltage */
>  		for (i = 0; i < intel_dp->lane_count; i++)
>  			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
> @@ -284,7 +266,6 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
>  		/* Make sure clock is still ok */
>  		if (!drm_dp_clock_recovery_ok(link_status,
>  					      intel_dp->lane_count)) {
> -			intel_dp->train_set_valid = false;
>  			intel_dp_link_training_clock_recovery(intel_dp);
>  			intel_dp_set_link_train(intel_dp,
>  						training_pattern |
> @@ -301,7 +282,6 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
>  
>  		/* Try 5 times, then try clock recovery if that fails */
>  		if (tries > 5) {
> -			intel_dp->train_set_valid = false;
>  			intel_dp_link_training_clock_recovery(intel_dp);
>  			intel_dp_set_link_train(intel_dp,
>  						training_pattern |
> @@ -322,10 +302,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
>  
>  	intel_dp_set_idle_link_train(intel_dp);
>  
> -	if (channel_eq) {
> -		intel_dp->train_set_valid = true;
> +	if (channel_eq)
>  		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
> -	}
>  }
>  
>  void intel_dp_stop_link_train(struct intel_dp *intel_dp)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 0c1dc9b..9257f08 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -894,8 +894,6 @@ struct intel_dp {
>  	/* This is called before a link training is starterd */
>  	void (*prepare_link_retrain)(struct intel_dp *intel_dp);
>  
> -	bool train_set_valid;
> -
>  	/* Displayport compliance testing */
>  	unsigned long compliance_test_type;
>  	unsigned long compliance_test_data;

-- 
Jani Nikula, Intel Open Source Technology Center

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH RESEND] drm/i915: Revert DisplayPort fast link training feature
@ 2016-06-20  9:48   ` Jani Nikula
  0 siblings, 0 replies; 5+ messages in thread
From: Jani Nikula @ 2016-06-20  9:48 UTC (permalink / raw)
  To: Mika Kahola, intel-gfx; +Cc: stable

On Mon, 20 Jun 2016, Mika Kahola <mika.kahola@intel.com> wrote:
> It has been found out that in some HW combination the DisplayPort
> fast link training feature caused screen flickering. Let's revert
> this feature for now until we can ensure that the feature works for
> all platforms.
>
> This is a manual revert of commits 5fa836a9d859 ("drm/i915: DP link
> training optimization") and 4e96c97742f4 ("drm/i915: eDP link training
> optimization").
>
> Fixes: 5fa836a9d859 ("drm/i915: DP link training optimization")
> Fixes: 4e96c97742f4 ("drm/i915: eDP link training optimization")
> Cc: <stable@vger.kernel.org> # v4.2+
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

Pushed to drm-intel-next-queued, thanks for the patch.

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/intel_dp.c               |  3 ---
>  drivers/gpu/drm/i915/intel_dp_link_training.c | 26 ++------------------------
>  drivers/gpu/drm/i915/intel_drv.h              |  2 --
>  3 files changed, 2 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index be08351..3cdea4d7a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4621,9 +4621,6 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
>  	intel_display_power_get(dev_priv, power_domain);
>  
>  	if (long_hpd) {
> -		/* indicate that we need to restart link training */
> -		intel_dp->train_set_valid = false;
> -
>  		intel_dp_long_pulse(intel_dp->attached_connector);
>  		if (intel_dp->is_mst)
>  			ret = IRQ_HANDLED;
> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
> index 0b8eefc..60fb39c 100644
> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> @@ -85,8 +85,7 @@ static bool
>  intel_dp_reset_link_train(struct intel_dp *intel_dp,
>  			uint8_t dp_train_pat)
>  {
> -	if (!intel_dp->train_set_valid)
> -		memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
> +	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
>  	intel_dp_set_signal_levels(intel_dp);
>  	return intel_dp_set_link_train(intel_dp, dp_train_pat);
>  }
> @@ -161,23 +160,6 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
>  			break;
>  		}
>  
> -		/*
> -		 * if we used previously trained voltage and pre-emphasis values
> -		 * and we don't get clock recovery, reset link training values
> -		 */
> -		if (intel_dp->train_set_valid) {
> -			DRM_DEBUG_KMS("clock recovery not ok, reset");
> -			/* clear the flag as we are not reusing train set */
> -			intel_dp->train_set_valid = false;
> -			if (!intel_dp_reset_link_train(intel_dp,
> -						       DP_TRAINING_PATTERN_1 |
> -						       DP_LINK_SCRAMBLING_DISABLE)) {
> -				DRM_ERROR("failed to enable link training\n");
> -				return;
> -			}
> -			continue;
> -		}
> -
>  		/* Check to see if we've tried the max voltage */
>  		for (i = 0; i < intel_dp->lane_count; i++)
>  			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
> @@ -284,7 +266,6 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
>  		/* Make sure clock is still ok */
>  		if (!drm_dp_clock_recovery_ok(link_status,
>  					      intel_dp->lane_count)) {
> -			intel_dp->train_set_valid = false;
>  			intel_dp_link_training_clock_recovery(intel_dp);
>  			intel_dp_set_link_train(intel_dp,
>  						training_pattern |
> @@ -301,7 +282,6 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
>  
>  		/* Try 5 times, then try clock recovery if that fails */
>  		if (tries > 5) {
> -			intel_dp->train_set_valid = false;
>  			intel_dp_link_training_clock_recovery(intel_dp);
>  			intel_dp_set_link_train(intel_dp,
>  						training_pattern |
> @@ -322,10 +302,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
>  
>  	intel_dp_set_idle_link_train(intel_dp);
>  
> -	if (channel_eq) {
> -		intel_dp->train_set_valid = true;
> +	if (channel_eq)
>  		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
> -	}
>  }
>  
>  void intel_dp_stop_link_train(struct intel_dp *intel_dp)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 0c1dc9b..9257f08 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -894,8 +894,6 @@ struct intel_dp {
>  	/* This is called before a link training is starterd */
>  	void (*prepare_link_retrain)(struct intel_dp *intel_dp);
>  
> -	bool train_set_valid;
> -
>  	/* Displayport compliance testing */
>  	unsigned long compliance_test_type;
>  	unsigned long compliance_test_data;

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2016-06-20  9:48 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-06-20  8:10 [PATCH RESEND] drm/i915: Revert DisplayPort fast link training feature Mika Kahola
2016-06-20  8:10 ` Mika Kahola
2016-06-20  8:27 ` ✓ Ro.CI.BAT: success for drm/i915: Revert DisplayPort fast link training feature (rev2) Patchwork
2016-06-20  9:48 ` [Intel-gfx] [PATCH RESEND] drm/i915: Revert DisplayPort fast link training feature Jani Nikula
2016-06-20  9:48   ` Jani Nikula

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