From: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> To: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Cc: Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>, Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>, Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Subject: [PATCH 2/2] clk: tegra: Micro-optimize Tegra210 clock setup Date: Thu, 23 Jun 2016 12:52:31 +0200 [thread overview] Message-ID: <20160623105231.24383-2-thierry.reding@gmail.com> (raw) In-Reply-To: <20160623105231.24383-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> sor_safe being the parent of the dpaux and dpaux1 clocks, it's not only natural, but also slightly more efficient, to initialize it before its children. This avoids orphaning the dpaux and dpaux1 clocks only to get them reparented when the sor_safe clock is registered. Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> --- drivers/clk/tegra/clk-tegra210.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index fe295b4102ca..b4df5c46642f 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -2466,6 +2466,10 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, 1, 2); clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk; + clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base, + 1, 17, 222); + clks[TEGRA210_CLK_SOR_SAFE] = clk; + clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base, 1, 17, 181); clks[TEGRA210_CLK_DPAUX] = clk; @@ -2474,10 +2478,6 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, 1, 17, 207); clks[TEGRA210_CLK_DPAUX1] = clk; - clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base, - 1, 17, 222); - clks[TEGRA210_CLK_SOR_SAFE] = clk; - /* pll_d_dsi_out */ clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0, clk_base + PLLD_MISC0, 21, 0, &pll_d_lock); -- 2.8.3
WARNING: multiple messages have this Message-ID (diff)
From: Thierry Reding <thierry.reding@gmail.com> To: Thierry Reding <thierry.reding@gmail.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com>, Rhyland Klein <rklein@nvidia.com>, Jon Hunter <jonathanh@nvidia.com>, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 2/2] clk: tegra: Micro-optimize Tegra210 clock setup Date: Thu, 23 Jun 2016 12:52:31 +0200 [thread overview] Message-ID: <20160623105231.24383-2-thierry.reding@gmail.com> (raw) In-Reply-To: <20160623105231.24383-1-thierry.reding@gmail.com> From: Thierry Reding <treding@nvidia.com> sor_safe being the parent of the dpaux and dpaux1 clocks, it's not only natural, but also slightly more efficient, to initialize it before its children. This avoids orphaning the dpaux and dpaux1 clocks only to get them reparented when the sor_safe clock is registered. Signed-off-by: Thierry Reding <treding@nvidia.com> --- drivers/clk/tegra/clk-tegra210.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index fe295b4102ca..b4df5c46642f 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -2466,6 +2466,10 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, 1, 2); clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk; + clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base, + 1, 17, 222); + clks[TEGRA210_CLK_SOR_SAFE] = clk; + clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base, 1, 17, 181); clks[TEGRA210_CLK_DPAUX] = clk; @@ -2474,10 +2478,6 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, 1, 17, 207); clks[TEGRA210_CLK_DPAUX1] = clk; - clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base, - 1, 17, 222); - clks[TEGRA210_CLK_SOR_SAFE] = clk; - /* pll_d_dsi_out */ clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0, clk_base + PLLD_MISC0, 21, 0, &pll_d_lock); -- 2.8.3
next prev parent reply other threads:[~2016-06-23 10:52 UTC|newest] Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-06-23 10:52 [PATCH 1/2] clk: tegra: Make sor_safe the parent of dpaux and dpaux1 Thierry Reding 2016-06-23 10:52 ` Thierry Reding [not found] ` <20160623105231.24383-1-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2016-06-23 10:52 ` Thierry Reding [this message] 2016-06-23 10:52 ` [PATCH 2/2] clk: tegra: Micro-optimize Tegra210 clock setup Thierry Reding 2016-06-23 12:26 ` Jon Hunter 2016-06-23 12:26 ` Jon Hunter 2016-06-23 15:28 ` Rhyland Klein 2016-06-23 15:28 ` Rhyland Klein 2016-06-23 12:25 ` [PATCH 1/2] clk: tegra: Make sor_safe the parent of dpaux and dpaux1 Jon Hunter 2016-06-23 12:25 ` Jon Hunter 2016-06-23 15:27 ` Rhyland Klein 2016-06-23 15:27 ` Rhyland Klein
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20160623105231.24383-2-thierry.reding@gmail.com \ --to=thierry.reding-re5jqeeqqe8avxtiumwx3w@public.gmane.org \ --cc=jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org \ --cc=linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \ --cc=linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \ --cc=pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org \ --cc=rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.