* [PATCH v5 0/2] MIPS non-executable stack support
@ 2016-07-08 10:06 ` Paul Burton
0 siblings, 0 replies; 12+ messages in thread
From: Paul Burton @ 2016-07-08 10:06 UTC (permalink / raw)
To: linux-mips, Ralf Baechle
Cc: Leonid Yegoshin, Maciej Rozycki, Faraz Shahbazker, Raghu Gandham,
Matthew Fortune, Paul Burton
This series allows us to support non-executable stacks on systems with
RIXI by moving delay slot instruction emulation off of the user stack &
into a dedicated page.
This is a revision of patches 6114/6125 & 6115 from a few years back:
https://patchwork.linux-mips.org/patch/6114
https://patchwork.linux-mips.org/patch/6125
https://patchwork.linux-mips.org/patch/6115
The series applies atop v4.7-rc6.
Paul Burton (2):
MIPS: use per-mm page to execute branch delay slot instructions
MIPS: non-exec stack & heap when non-exec PT_GNU_STACK is present
arch/mips/Kconfig | 1 +
arch/mips/include/asm/dsemul.h | 92 ++++++++++
arch/mips/include/asm/elf.h | 3 +
arch/mips/include/asm/fpu_emulator.h | 17 +-
arch/mips/include/asm/mmu.h | 9 +
arch/mips/include/asm/mmu_context.h | 6 +
arch/mips/include/asm/page.h | 6 +-
arch/mips/include/asm/processor.h | 18 +-
arch/mips/kernel/elf.c | 19 ++
arch/mips/kernel/mips-r2-to-r6-emul.c | 8 +-
arch/mips/kernel/process.c | 14 ++
arch/mips/kernel/signal.c | 8 +
arch/mips/kernel/vdso.c | 10 +
arch/mips/math-emu/cp1emu.c | 8 +-
arch/mips/math-emu/dsemul.c | 333 +++++++++++++++++++++++-----------
15 files changed, 417 insertions(+), 135 deletions(-)
create mode 100644 arch/mips/include/asm/dsemul.h
--
2.9.0
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v5 0/2] MIPS non-executable stack support @ 2016-07-08 10:06 ` Paul Burton 0 siblings, 0 replies; 12+ messages in thread From: Paul Burton @ 2016-07-08 10:06 UTC (permalink / raw) To: linux-mips, Ralf Baechle Cc: Leonid Yegoshin, Maciej Rozycki, Faraz Shahbazker, Raghu Gandham, Matthew Fortune, Paul Burton This series allows us to support non-executable stacks on systems with RIXI by moving delay slot instruction emulation off of the user stack & into a dedicated page. This is a revision of patches 6114/6125 & 6115 from a few years back: https://patchwork.linux-mips.org/patch/6114 https://patchwork.linux-mips.org/patch/6125 https://patchwork.linux-mips.org/patch/6115 The series applies atop v4.7-rc6. Paul Burton (2): MIPS: use per-mm page to execute branch delay slot instructions MIPS: non-exec stack & heap when non-exec PT_GNU_STACK is present arch/mips/Kconfig | 1 + arch/mips/include/asm/dsemul.h | 92 ++++++++++ arch/mips/include/asm/elf.h | 3 + arch/mips/include/asm/fpu_emulator.h | 17 +- arch/mips/include/asm/mmu.h | 9 + arch/mips/include/asm/mmu_context.h | 6 + arch/mips/include/asm/page.h | 6 +- arch/mips/include/asm/processor.h | 18 +- arch/mips/kernel/elf.c | 19 ++ arch/mips/kernel/mips-r2-to-r6-emul.c | 8 +- arch/mips/kernel/process.c | 14 ++ arch/mips/kernel/signal.c | 8 + arch/mips/kernel/vdso.c | 10 + arch/mips/math-emu/cp1emu.c | 8 +- arch/mips/math-emu/dsemul.c | 333 +++++++++++++++++++++++----------- 15 files changed, 417 insertions(+), 135 deletions(-) create mode 100644 arch/mips/include/asm/dsemul.h -- 2.9.0 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v5 1/2] MIPS: use per-mm page to execute branch delay slot instructions @ 2016-07-08 10:06 ` Paul Burton 0 siblings, 0 replies; 12+ messages in thread From: Paul Burton @ 2016-07-08 10:06 UTC (permalink / raw) To: linux-mips, Ralf Baechle Cc: Leonid Yegoshin, Maciej Rozycki, Faraz Shahbazker, Raghu Gandham, Matthew Fortune, Paul Burton In some cases the kernel needs to execute an instruction from the delay slot of an emulated branch instruction. These cases include: - Emulated floating point branch instructions (bc1[ft]l?) for systems which don't include an FPU, or upon which the kernel is run with the "nofpu" parameter. - MIPSr6 systems running binaries targeting older revisions of the architecture, which may include branch instructions whose encodings are no longer valid in MIPSr6. Executing instructions from such delay slots is done by writing the instruction to memory followed by a trap, as part of an "emuframe", and executing it. This avoids the requirement of an emulator for the entire MIPS instruction set. Prior to this patch such emuframes are written to the user stack and executed from there. This patch moves FP branch delay emuframes off of the user stack and into a per-mm page. Allocating a page per-mm leaves userland with access to only what it had access to previously, and compared to other solutions is relatively simple. When a thread requires a delay slot emulation, it is allocated a frame. A thread may only have one frame allocated at any one time, since it may only ever be executing one instruction at any one time. In order to ensure that we can free up allocated frame later, its index is recorded in struct thread_struct. In the typical case, after executing the delay slot instruction we'll execute a break instruction with the BRK_MEMU code. This traps back to the kernel & leads to a call to do_dsemulret which frees the allocated frame & moves the user PC back to the instruction that would have executed following the emulated branch. In some cases the delay slot instruction may be invalid, such as a branch, or may trigger an exception. In these cases the BRK_MEMU break instruction will not be hit. In order to ensure that frames are freed this patch introduces dsemul_thread_cleanup() and calls it to free any allocated frame upon thread exit. If the instruction generated an exception & leads to a signal being delivered to the thread, or indeed if a signal simply happens to be delivered to the thread whilst it is executing from the struct emuframe, then we need to take care to exit the frame appropriately. This is done by either rolling back the user PC to the branch or advancing it to the continuation PC prior to signal delivery, using dsemul_thread_rollback(). If this were not done then a sigreturn would return to the struct emuframe, and if that frame had meanwhile been used in response to an emulated branch instruction within the signal handler then we would execute the wrong user code. Whilst a user could theoretically place something like a compact branch to self in a delay slot and cause their thread to become stuck in an infinite loop with the frame never being deallocated, this would: - Only affect the users single process. - Be architecturally invalid since there would be a branch in the delay slot, which is forbidden. - Be extremely unlikely to happen by mistake, and provide a program with no more ability to harm the system than a simple infinite loop would. If a thread requires a delay slot emulation & no frame is available to it (ie. the process has enough other threads that all frames are currently in use) then the thread joins a waitqueue. It will sleep until a frame is freed by another thread in the process. Since we now know whether a thread has an allocated frame due to our tracking of its index, the cookie field of struct emuframe is removed as we can be more certain whether we have a valid frame. Since a thread may only ever have a single frame at any given time, the epc field of struct emuframe is also removed & the PC to continue from is instead stored in struct thread_struct. Together these changes simplify & shrink struct emuframe somewhat, allowing twice as many frames to fit into the page allocated for them. The primary benefit of this patch is that we are now free to mark the user stack non-executable where that is possible. Signed-off-by: Paul Burton <paul.burton@imgtec.com> --- v2 of this patch can be found here: https://patchwork.linux-mips.org/patch/6125/ This has become a higher priority than it was at the time of v2 since Android has begun marking its stacks non-executable & on MIPSr6 devices we use mips_dsemul() in the emulation of pre-r6 instructions. Since the Android NDK MIPS target is MIPS32, this is important to backwards compatibility for apps on MIPSr6 systems. Changes in v5: - Fix 64 bit use by casting BD_EMUFRAME_NONE value to int. - Use a spinlock instead of a mutex to protect the emupage variables to avoid sleeping in atomic context. - Don't bother checking for frames to cleanup when exiting kernel threads. - Use the tsk parameter provided to exit_thread rather than current. - Lock the task to preserve its mm whilst freeing up frames, in case the thread is part of a currently exiting process. - Map the page in arch_setup_additional_pages() since we can't mmap from atomic context. Unfortunately we'll need to allocate a page for all processes. - The address of the page is static, so stop storing it in mm_context_t. Changes in v4: - Include asm/dsemul.h. - If a thread is executing somewhere unexpected in the emupage when a rollback (signal) occurs, free the threads allocated frame anyway. Changes in v3: - Rebase atop v4.7-rc5. - Select CONFIG_HAVE_EXIT_THREAD. - Track allocated frames per thread, allowing cleanup on exit or signal delivery. - Remove signal blocking & thread information flag now we have other means to ensure frames are cleaned up. - Introduce asm/dsemul.h to group prototypes & definitions logically. - Avoid using 'fp' in names, since this isn't exclusive to FP branch emulation. - Document with kerneldoc. - Return a frame index from alloc_emuframe such that mips_dsemul can record it in struct thread_struct. - Use bool return type for do_dsemulret rather than a bool-like int. - Rework commit message. Changes in v2: - s/kernels/kernel's/ - Use (mm_)isBranchInstr in mips_dsemul rather than duplicating similar logic. arch/mips/Kconfig | 1 + arch/mips/include/asm/dsemul.h | 92 ++++++++++ arch/mips/include/asm/fpu_emulator.h | 17 +- arch/mips/include/asm/mmu.h | 9 + arch/mips/include/asm/mmu_context.h | 6 + arch/mips/include/asm/processor.h | 18 +- arch/mips/kernel/mips-r2-to-r6-emul.c | 8 +- arch/mips/kernel/process.c | 14 ++ arch/mips/kernel/signal.c | 8 + arch/mips/kernel/vdso.c | 10 + arch/mips/math-emu/cp1emu.c | 8 +- arch/mips/math-emu/dsemul.c | 333 +++++++++++++++++++++++----------- 12 files changed, 391 insertions(+), 133 deletions(-) create mode 100644 arch/mips/include/asm/dsemul.h diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ac91939..49a5396 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -64,6 +64,7 @@ config MIPS select GENERIC_TIME_VSYSCALL select ARCH_CLOCKSOURCE_DATA select HANDLE_DOMAIN_IRQ + select HAVE_EXIT_THREAD menu "Machine selection" diff --git a/arch/mips/include/asm/dsemul.h b/arch/mips/include/asm/dsemul.h new file mode 100644 index 0000000..a6e0678 --- /dev/null +++ b/arch/mips/include/asm/dsemul.h @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2016 Imagination Technologies + * Author: Paul Burton <paul.burton@imgtec.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __MIPS_ASM_DSEMUL_H__ +#define __MIPS_ASM_DSEMUL_H__ + +#include <asm/break.h> +#include <asm/inst.h> + +/* Break instruction with special math emu break code set */ +#define BREAK_MATH(micromips) (((micromips) ? 0x7 : 0xd) | (BRK_MEMU << 16)) + +/* When used as a frame index, indicates the lack of a frame */ +#define BD_EMUFRAME_NONE ((int)BIT(31)) + +struct mm_struct; +struct pt_regs; +struct task_struct; + +/** + * mips_dsemul() - 'Emulate' an instruction from a branch delay slot + * @regs: User thread register context. + * @ir: The instruction to be 'emulated'. + * @branch_pc: The PC of the branch instruction. + * @cont_pc: The PC to continue at following 'emulation'. + * + * Emulate or execute an arbitrary MIPS instruction within the context of + * the current user thread. This is used primarily to handle instructions + * in the delay slots of emulated branch instructions, for example FP + * branch instructions on systems without an FPU. + * + * Return: Zero on success, negative if ir is a NOP, signal number on failure. + */ +extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, + unsigned long branch_pc, unsigned long cont_pc); + +/** + * do_dsemulret() - Return from a delay slot 'emulation' frame + * @xcp: User thread register context. + * + * Call in response to the BRK_MEMU break instruction used to return to + * the kernel from branch delay slot 'emulation' frames following a call + * to mips_dsemul(). Restores the user thread PC to the value that was + * passed as the cpc parameter to mips_dsemul(). + * + * Return: True if an emulation frame was returned from, else false. + */ +extern bool do_dsemulret(struct pt_regs *xcp); + +/** + * dsemul_thread_cleanup() - Cleanup thread 'emulation' frame + * @tsk: The task structure associated with the thread + * + * If the thread @tsk has a branch delay slot 'emulation' frame + * allocated to it then free that frame. + * + * Return: True if a frame was freed, else false. + */ +extern bool dsemul_thread_cleanup(struct task_struct *tsk); + +/** + * dsemul_thread_rollback() - Rollback from an 'emulation' frame + * @regs: User thread register context. + * + * If the current thread, whose register context is represented by @regs, + * is executing within a delay slot 'emulation' frame then exit that + * frame. The PC will be rolled back to the branch if the instruction + * that was being 'emulated' has not yet executed, or advanced to the + * continuation PC if it has. + * + * Return: True if a frame was exited, else false. + */ +extern bool dsemul_thread_rollback(struct pt_regs *regs); + +/** + * dsemul_mm_cleanup() - Cleanup per-mm delay slot 'emulation' state + * @mm: The struct mm_struct to cleanup state for. + * + * Cleanup state for the given @mm, ensuring that any memory allocated + * for delay slot 'emulation' book-keeping is freed. This is to be called + * before @mm is freed in order to avoid memory leaks. + */ +extern void dsemul_mm_cleanup(struct mm_struct *mm); + +#endif /* __MIPS_ASM_DSEMUL_H__ */ diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h index 3225c3c..355dc25 100644 --- a/arch/mips/include/asm/fpu_emulator.h +++ b/arch/mips/include/asm/fpu_emulator.h @@ -24,7 +24,7 @@ #define _ASM_FPU_EMULATOR_H #include <linux/sched.h> -#include <asm/break.h> +#include <asm/dsemul.h> #include <asm/thread_info.h> #include <asm/inst.h> #include <asm/local.h> @@ -60,27 +60,16 @@ do { \ #define MIPS_FPU_EMU_INC_STATS(M) do { } while (0) #endif /* CONFIG_DEBUG_FS */ -extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, - unsigned long cpc); -extern int do_dsemulret(struct pt_regs *xcp); extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, int has_fpu, void *__user *fault_addr); int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31); +int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, + unsigned long *contpc); int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, unsigned long *contpc); -/* - * Instruction inserted following the badinst to further tag the sequence - */ -#define BD_COOKIE 0x0000bd36 /* tne $0, $0 with baggage */ - -/* - * Break instruction with special math emu break code set - */ -#define BREAK_MATH(micromips) (((micromips) ? 0x7 : 0xd) | (BRK_MEMU << 16)) - #define SIGNALLING_NAN 0x7ff800007ff80000LL static inline void fpu_emulator_init_fpu(void) diff --git a/arch/mips/include/asm/mmu.h b/arch/mips/include/asm/mmu.h index 1afa1f9..f6ba08d 100644 --- a/arch/mips/include/asm/mmu.h +++ b/arch/mips/include/asm/mmu.h @@ -2,11 +2,20 @@ #define __ASM_MMU_H #include <linux/atomic.h> +#include <linux/spinlock.h> +#include <linux/wait.h> typedef struct { unsigned long asid[NR_CPUS]; void *vdso; atomic_t fp_mode_switching; + + /* lock to be held whilst modifying fp_bd_emupage_allocmap */ + spinlock_t bd_emupage_lock; + /* bitmap tracking allocation of fp_bd_emupage */ + unsigned long *bd_emupage_allocmap; + /* wait queue for threads requiring an emuframe */ + wait_queue_head_t bd_emupage_queue; } mm_context_t; #endif /* __ASM_MMU_H */ diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index fc57e13..ddd57ad 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -16,6 +16,7 @@ #include <linux/smp.h> #include <linux/slab.h> #include <asm/cacheflush.h> +#include <asm/dsemul.h> #include <asm/hazards.h> #include <asm/tlbflush.h> #include <asm-generic/mm_hooks.h> @@ -128,6 +129,10 @@ init_new_context(struct task_struct *tsk, struct mm_struct *mm) atomic_set(&mm->context.fp_mode_switching, 0); + mm->context.bd_emupage_allocmap = NULL; + spin_lock_init(&mm->context.bd_emupage_lock); + init_waitqueue_head(&mm->context.bd_emupage_queue); + return 0; } @@ -162,6 +167,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, */ static inline void destroy_context(struct mm_struct *mm) { + dsemul_mm_cleanup(mm); } #define deactivate_mm(tsk, mm) do { } while (0) diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index 7e78b62..0d36c87 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -11,12 +11,14 @@ #ifndef _ASM_PROCESSOR_H #define _ASM_PROCESSOR_H +#include <linux/atomic.h> #include <linux/cpumask.h> #include <linux/threads.h> #include <asm/cachectl.h> #include <asm/cpu.h> #include <asm/cpu-info.h> +#include <asm/dsemul.h> #include <asm/mipsregs.h> #include <asm/prefetch.h> @@ -78,7 +80,11 @@ extern unsigned int vced_count, vcei_count; #endif -#define STACK_TOP (TASK_SIZE & PAGE_MASK) +/* + * One page above the stack is used for branch delay slot "emulation". + * See dsemul.c for details. + */ +#define STACK_TOP ((TASK_SIZE & PAGE_MASK) - PAGE_SIZE) /* * This decides where the kernel will search for a free chunk of vm @@ -256,6 +262,12 @@ struct thread_struct { /* Saved fpu/fpu emulator stuff. */ struct mips_fpu_struct fpu FPU_ALIGN; + /* Assigned branch delay slot 'emulation' frame */ + atomic_t bd_emu_frame; + /* PC of the branch from a branch delay slot 'emulation' */ + unsigned long bd_emu_branch_pc; + /* PC to continue from following a branch delay slot 'emulation' */ + unsigned long bd_emu_cont_pc; #ifdef CONFIG_MIPS_MT_FPAFF /* Emulated instruction count */ unsigned long emulated_fp; @@ -323,6 +335,10 @@ struct thread_struct { * FPU affinity state (null if not FPAFF) \ */ \ FPAFF_INIT \ + /* Delay slot emulation */ \ + .bd_emu_frame = ATOMIC_INIT(BD_EMUFRAME_NONE), \ + .bd_emu_branch_pc = 0, \ + .bd_emu_cont_pc = 0, \ /* \ * Saved DSP stuff \ */ \ diff --git a/arch/mips/kernel/mips-r2-to-r6-emul.c b/arch/mips/kernel/mips-r2-to-r6-emul.c index 7ff2a55..ef23c61 100644 --- a/arch/mips/kernel/mips-r2-to-r6-emul.c +++ b/arch/mips/kernel/mips-r2-to-r6-emul.c @@ -283,7 +283,7 @@ static int jr_func(struct pt_regs *regs, u32 ir) err = mipsr6_emul(regs, nir); if (err > 0) { regs->cp0_epc = nepc; - err = mips_dsemul(regs, nir, cepc); + err = mips_dsemul(regs, nir, epc, cepc); if (err == SIGILL) err = SIGEMT; MIPS_R2_STATS(dsemul); @@ -1033,7 +1033,7 @@ repeat: if (nir) { err = mipsr6_emul(regs, nir); if (err > 0) { - err = mips_dsemul(regs, nir, cpc); + err = mips_dsemul(regs, nir, epc, cpc); if (err == SIGILL) err = SIGEMT; MIPS_R2_STATS(dsemul); @@ -1082,7 +1082,7 @@ repeat: if (nir) { err = mipsr6_emul(regs, nir); if (err > 0) { - err = mips_dsemul(regs, nir, cpc); + err = mips_dsemul(regs, nir, epc, cpc); if (err == SIGILL) err = SIGEMT; MIPS_R2_STATS(dsemul); @@ -1149,7 +1149,7 @@ repeat: if (nir) { err = mipsr6_emul(regs, nir); if (err > 0) { - err = mips_dsemul(regs, nir, cpc); + err = mips_dsemul(regs, nir, epc, cpc); if (err == SIGILL) err = SIGEMT; MIPS_R2_STATS(dsemul); diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 813ed78..7429ad0 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -30,6 +30,7 @@ #include <asm/asm.h> #include <asm/bootinfo.h> #include <asm/cpu.h> +#include <asm/dsemul.h> #include <asm/dsp.h> #include <asm/fpu.h> #include <asm/msa.h> @@ -68,11 +69,22 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) lose_fpu(0); clear_thread_flag(TIF_MSA_CTX_LIVE); clear_used_math(); + atomic_set(¤t->thread.bd_emu_frame, BD_EMUFRAME_NONE); init_dsp(); regs->cp0_epc = pc; regs->regs[29] = sp; } +void exit_thread(struct task_struct *tsk) +{ + /* + * User threads may have allocated a delay slot emulation frame. + * If so, clean up that allocation. + */ + if (!(current->flags & PF_KTHREAD)) + dsemul_thread_cleanup(tsk); +} + int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) { /* @@ -159,6 +171,8 @@ int copy_thread(unsigned long clone_flags, unsigned long usp, clear_tsk_thread_flag(p, TIF_FPUBOUND); #endif /* CONFIG_MIPS_MT_FPAFF */ + atomic_set(&p->thread.bd_emu_frame, BD_EMUFRAME_NONE); + if (clone_flags & CLONE_SETTLS) ti->tp_value = regs->regs[7]; diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index ae42314..9383635 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -772,6 +772,14 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs) struct mips_abi *abi = current->thread.abi; void *vdso = current->mm->context.vdso; + /* + * If we were emulating a delay slot instruction, exit that frame such + * that addresses in the sigframe are as expected for userland and we + * don't have a problem if we reuse the thread's frame for an + * instruction within the signal handler. + */ + dsemul_thread_rollback(regs); + if (regs->regs[0]) { switch(regs->regs[2]) { case ERESTART_RESTARTBLOCK: diff --git a/arch/mips/kernel/vdso.c b/arch/mips/kernel/vdso.c index 54e1663..9abe447 100644 --- a/arch/mips/kernel/vdso.c +++ b/arch/mips/kernel/vdso.c @@ -107,6 +107,16 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) if (down_write_killable(&mm->mmap_sem)) return -EINTR; + /* Map delay slot emulation page */ + base = mmap_region(NULL, STACK_TOP, PAGE_SIZE, + VM_READ|VM_WRITE|VM_EXEC| + VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC, + 0); + if (IS_ERR_VALUE(base)) { + ret = base; + goto out; + } + /* * Determine total area size. This includes the VDSO data itself, the * data page, and the GIC user page if present. Always create a mapping diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index d96e912..8afa090 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -434,8 +434,8 @@ static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) * a single subroutine should be used across both * modules. */ -static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, - unsigned long *contpc) +int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, + unsigned long *contpc) { union mips_instruction insn = (union mips_instruction)dec_insn.insn; unsigned int fcr31; @@ -1268,7 +1268,7 @@ branch_common: * instruction in the dslot. */ sig = mips_dsemul(xcp, ir, - contpc); + bcpc, contpc); if (sig < 0) break; if (sig) @@ -1323,7 +1323,7 @@ branch_common: * Single step the non-cp1 * instruction in the dslot */ - sig = mips_dsemul(xcp, ir, contpc); + sig = mips_dsemul(xcp, ir, bcpc, contpc); if (sig < 0) break; if (sig) diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c index 4707488..72a4642 100644 --- a/arch/mips/math-emu/dsemul.c +++ b/arch/mips/math-emu/dsemul.c @@ -1,3 +1,6 @@ +#include <linux/err.h> +#include <linux/slab.h> + #include <asm/branch.h> #include <asm/cacheflush.h> #include <asm/fpu_emulator.h> @@ -5,43 +8,211 @@ #include <asm/mipsregs.h> #include <asm/uaccess.h> -#include "ieee754.h" - -/* - * Emulate the arbitrary instruction ir at xcp->cp0_epc. Required when - * we have to emulate the instruction in a COP1 branch delay slot. Do - * not change cp0_epc due to the instruction +/** + * struct emuframe - The 'emulation' frame structure + * @emul: The instruction to 'emulate'. + * @badinst: A break instruction to cause a return to the kernel. * - * According to the spec: - * 1) it shouldn't be a branch :-) - * 2) it can be a COP instruction :-( - * 3) if we are tring to run a protected memory space we must take - * special care on memory access instructions :-( - */ - -/* - * "Trampoline" return routine to catch exception following - * execution of delay-slot instruction execution. + * This structure defines the frames placed within the delay slot emulation + * page in response to a call to mips_dsemul(). Each thread may be allocated + * only one frame at any given time. The kernel stores within it the + * instruction to be 'emulated' followed by a break instruction, then + * executes the frame in user mode. The break causes a trap to the kernel + * which leads to do_dsemulret() being called unless the instruction in + * @emul causes a trap itself, is a branch, or a signal is delivered to + * the thread. In these cases the allocated frame will either be reused by + * a subsequent delay slot 'emulation', or be freed during signal delivery or + * upon thread exit. + * + * This approach is used because: + * + * - Actually emulating all instructions isn't feasible. We would need to + * be able to handle instructions from all revisions of the MIPS ISA, + * all ASEs & all vendor instruction set extensions. This would be a + * whole lot of work & continual maintenance burden as new instructions + * are introduced, and in the case of some vendor extensions may not + * even be possible. Thus we need to take the approach of actually + * executing the instruction. + * + * - We must execute the instruction within user context. If we were to + * execute the instruction in kernel mode then it would have access to + * kernel resources without very careful checks, leaving us with a + * high potential for security or stability issues to arise. + * + * - We used to place the frame on the users stack, but this requires + * that the stack be executable. This is bad for security so the + * per-process page is now used instead. + * + * - The instruction in @emul may be something entirely invalid for a + * delay slot. The user may (intentionally or otherwise) place a branch + * in a delay slot, or a kernel mode instruction, or something else + * which generates an exception. Thus we can't rely upon the break in + * @badinst always being hit. For this reason we track the index of the + * frame allocated to each thread, allowing us to clean it up at later + * points such as signal delivery or thread exit. + * + * - The user may generate a fake struct emuframe if they wish, invoking + * the BRK_MEMU break instruction themselves. We must therefore not + * trust that BRK_MEMU means there's actually a valid frame allocated + * to the thread, and must not allow the user to do anything they + * couldn't already. */ - struct emuframe { mips_instruction emul; mips_instruction badinst; - mips_instruction cookie; - unsigned long epc; }; -/* - * Set up an emulation frame for instruction IR, from a delay slot of - * a branch jumping to CPC. Return 0 if successful, -1 if no emulation - * required, otherwise a signal number causing a frame setup failure. - */ -int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) +static const int emupage_frame_count = PAGE_SIZE / sizeof(struct emuframe); + +static inline __user struct emuframe *dsemul_page(void) +{ + return (__user struct emuframe *)STACK_TOP; +} + +static int alloc_emuframe(void) +{ + mm_context_t *mm_ctx = ¤t->mm->context; + int idx; + +retry: + spin_lock(&mm_ctx->bd_emupage_lock); + + /* Ensure we have an allocation bitmap */ + if (!mm_ctx->bd_emupage_allocmap) { + mm_ctx->bd_emupage_allocmap = + kcalloc(BITS_TO_LONGS(emupage_frame_count), + sizeof(unsigned long), + GFP_ATOMIC); + + if (!mm_ctx->bd_emupage_allocmap) { + idx = BD_EMUFRAME_NONE; + goto out_unlock; + } + } + + /* Attempt to allocate a single bit/frame */ + idx = bitmap_find_free_region(mm_ctx->bd_emupage_allocmap, + emupage_frame_count, 0); + if (idx < 0) { + /* + * Failed to allocate a frame. We'll wait until one becomes + * available. We unlock the page so that other threads actually + * get the opportunity to free their frames, which means + * technically the result of bitmap_full may be incorrect. + * However the worst case is that we repeat all this and end up + * back here again. + */ + spin_unlock(&mm_ctx->bd_emupage_lock); + if (!wait_event_killable(mm_ctx->bd_emupage_queue, + !bitmap_full(mm_ctx->bd_emupage_allocmap, + emupage_frame_count))) + goto retry; + + /* Received a fatal signal - just give in */ + return BD_EMUFRAME_NONE; + } + + /* Success! */ + pr_debug("allocate emuframe %d to %d\n", idx, current->pid); +out_unlock: + spin_unlock(&mm_ctx->bd_emupage_lock); + return idx; +} + +static void free_emuframe(int idx, struct mm_struct *mm) +{ + mm_context_t *mm_ctx = &mm->context; + + spin_lock(&mm_ctx->bd_emupage_lock); + + pr_debug("free emuframe %d from %d\n", idx, current->pid); + bitmap_clear(mm_ctx->bd_emupage_allocmap, idx, 1); + + /* If some thread is waiting for a frame, now's its chance */ + wake_up(&mm_ctx->bd_emupage_queue); + + spin_unlock(&mm_ctx->bd_emupage_lock); +} + +static bool within_emuframe(struct pt_regs *regs) +{ + unsigned long base = (unsigned long)dsemul_page(); + + if (regs->cp0_epc < base) + return false; + if (regs->cp0_epc >= (base + PAGE_SIZE)) + return false; + + return true; +} + +bool dsemul_thread_cleanup(struct task_struct *tsk) +{ + int fr_idx; + + /* Clear any allocated frame, retrieving its index */ + fr_idx = atomic_xchg(&tsk->thread.bd_emu_frame, BD_EMUFRAME_NONE); + + /* If no frame was allocated, we're done */ + if (fr_idx == BD_EMUFRAME_NONE) + return false; + + task_lock(tsk); + + /* Free the frame that this thread had allocated */ + if (tsk->mm) + free_emuframe(fr_idx, tsk->mm); + + task_unlock(tsk); + return true; +} + +bool dsemul_thread_rollback(struct pt_regs *regs) +{ + struct emuframe __user *fr; + int fr_idx; + + /* Do nothing if we're not executing from a frame */ + if (!within_emuframe(regs)) + return false; + + /* Find the frame being executed */ + fr_idx = atomic_read(¤t->thread.bd_emu_frame); + if (fr_idx == BD_EMUFRAME_NONE) + return false; + fr = &dsemul_page()[fr_idx]; + + /* + * If the PC is at the emul instruction, roll back to the branch. If + * PC is at the badinst (break) instruction, we've already emulated the + * instruction so progress to the continue PC. If it's anything else + * then something is amiss & the user has branched into some other area + * of the emupage - we'll free the allocated frame anyway. + */ + if (msk_isa16_mode(regs->cp0_epc) == (unsigned long)&fr->emul) + regs->cp0_epc = current->thread.bd_emu_branch_pc; + else if (msk_isa16_mode(regs->cp0_epc) == (unsigned long)&fr->badinst) + regs->cp0_epc = current->thread.bd_emu_cont_pc; + + atomic_set(¤t->thread.bd_emu_frame, BD_EMUFRAME_NONE); + free_emuframe(fr_idx, current->mm); + return true; +} + +void dsemul_mm_cleanup(struct mm_struct *mm) +{ + mm_context_t *mm_ctx = &mm->context; + + kfree(mm_ctx->bd_emupage_allocmap); +} + +int mips_dsemul(struct pt_regs *regs, mips_instruction ir, + unsigned long branch_pc, unsigned long cont_pc) { int isa16 = get_isa16_mode(regs->cp0_epc); mips_instruction break_math; struct emuframe __user *fr; - int err; + int err, fr_idx; /* NOP is easy */ if (ir == 0) @@ -68,30 +239,20 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) } } - pr_debug("dsemul %lx %lx\n", regs->cp0_epc, cpc); + pr_debug("dsemul 0x%08lx cont at 0x%08lx\n", regs->cp0_epc, cont_pc); - /* - * The strategy is to push the instruction onto the user stack - * and put a trap after it which we can catch and jump to - * the required address any alternative apart from full - * instruction emulation!!. - * - * Algorithmics used a system call instruction, and - * borrowed that vector. MIPS/Linux version is a bit - * more heavyweight in the interests of portability and - * multiprocessor support. For Linux we use a BREAK 514 - * instruction causing a breakpoint exception. - */ - break_math = BREAK_MATH(isa16); - - /* Ensure that the two instructions are in the same cache line */ - fr = (struct emuframe __user *) - ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7); - - /* Verify that the stack pointer is not completely insane */ - if (unlikely(!access_ok(VERIFY_WRITE, fr, sizeof(struct emuframe)))) + /* Allocate a frame if we don't already have one */ + fr_idx = atomic_read(¤t->thread.bd_emu_frame); + if (fr_idx == BD_EMUFRAME_NONE) + fr_idx = alloc_emuframe(); + if (fr_idx == BD_EMUFRAME_NONE) return SIGBUS; + fr = &dsemul_page()[fr_idx]; + + /* Retrieve the appropriately encoded break instruction */ + break_math = BREAK_MATH(isa16); + /* Write the instructions to the frame */ if (isa16) { err = __put_user(ir >> 16, (u16 __user *)(&fr->emul)); @@ -106,84 +267,36 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) err |= __put_user(break_math, &fr->badinst); } - err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie); - err |= __put_user(cpc, &fr->epc); - if (unlikely(err)) { MIPS_FPU_EMU_INC_STATS(errors); + free_emuframe(fr_idx, current->mm); return SIGBUS; } + /* Record the PC of the branch, PC to continue from & frame index */ + current->thread.bd_emu_branch_pc = branch_pc; + current->thread.bd_emu_cont_pc = cont_pc; + atomic_set(¤t->thread.bd_emu_frame, fr_idx); + + /* Change user register context to execute the frame */ regs->cp0_epc = (unsigned long)&fr->emul | isa16; + /* Ensure the icache observes our newly written frame */ flush_cache_sigtramp((unsigned long)&fr->emul); return 0; } -int do_dsemulret(struct pt_regs *xcp) +bool do_dsemulret(struct pt_regs *xcp) { - int isa16 = get_isa16_mode(xcp->cp0_epc); - struct emuframe __user *fr; - unsigned long epc; - u32 insn, cookie; - int err = 0; - u16 instr[2]; - - fr = (struct emuframe __user *) - (msk_isa16_mode(xcp->cp0_epc) - sizeof(mips_instruction)); - - /* - * If we can't even access the area, something is very wrong, but we'll - * leave that to the default handling - */ - if (!access_ok(VERIFY_READ, fr, sizeof(struct emuframe))) - return 0; - - /* - * Do some sanity checking on the stackframe: - * - * - Is the instruction pointed to by the EPC an BREAK_MATH? - * - Is the following memory word the BD_COOKIE? - */ - if (isa16) { - err = __get_user(instr[0], - (u16 __user *)(&fr->badinst)); - err |= __get_user(instr[1], - (u16 __user *)((long)(&fr->badinst) + 2)); - insn = (instr[0] << 16) | instr[1]; - } else { - err = __get_user(insn, &fr->badinst); - } - err |= __get_user(cookie, &fr->cookie); - - if (unlikely(err || - insn != BREAK_MATH(isa16) || cookie != BD_COOKIE)) { + /* Cleanup the allocated frame, returning if there wasn't one */ + if (!dsemul_thread_cleanup(current)) { MIPS_FPU_EMU_INC_STATS(errors); - return 0; - } - - /* - * At this point, we are satisfied that it's a BD emulation trap. Yes, - * a user might have deliberately put two malformed and useless - * instructions in a row in his program, in which case he's in for a - * nasty surprise - the next instruction will be treated as a - * continuation address! Alas, this seems to be the only way that we - * can handle signals, recursion, and longjmps() in the context of - * emulating the branch delay instruction. - */ - - pr_debug("dsemulret\n"); - - if (__get_user(epc, &fr->epc)) { /* Saved EPC */ - /* This is not a good situation to be in */ - force_sig(SIGBUS, current); - - return 0; + return false; } /* Set EPC to return to post-branch instruction */ - xcp->cp0_epc = epc; - MIPS_FPU_EMU_INC_STATS(ds_emul); - return 1; + xcp->cp0_epc = current->thread.bd_emu_cont_pc; + pr_debug("dsemulret to 0x%08lx\n", xcp->cp0_epc); + return true; } -- 2.9.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v5 1/2] MIPS: use per-mm page to execute branch delay slot instructions @ 2016-07-08 10:06 ` Paul Burton 0 siblings, 0 replies; 12+ messages in thread From: Paul Burton @ 2016-07-08 10:06 UTC (permalink / raw) To: linux-mips, Ralf Baechle Cc: Leonid Yegoshin, Maciej Rozycki, Faraz Shahbazker, Raghu Gandham, Matthew Fortune, Paul Burton In some cases the kernel needs to execute an instruction from the delay slot of an emulated branch instruction. These cases include: - Emulated floating point branch instructions (bc1[ft]l?) for systems which don't include an FPU, or upon which the kernel is run with the "nofpu" parameter. - MIPSr6 systems running binaries targeting older revisions of the architecture, which may include branch instructions whose encodings are no longer valid in MIPSr6. Executing instructions from such delay slots is done by writing the instruction to memory followed by a trap, as part of an "emuframe", and executing it. This avoids the requirement of an emulator for the entire MIPS instruction set. Prior to this patch such emuframes are written to the user stack and executed from there. This patch moves FP branch delay emuframes off of the user stack and into a per-mm page. Allocating a page per-mm leaves userland with access to only what it had access to previously, and compared to other solutions is relatively simple. When a thread requires a delay slot emulation, it is allocated a frame. A thread may only have one frame allocated at any one time, since it may only ever be executing one instruction at any one time. In order to ensure that we can free up allocated frame later, its index is recorded in struct thread_struct. In the typical case, after executing the delay slot instruction we'll execute a break instruction with the BRK_MEMU code. This traps back to the kernel & leads to a call to do_dsemulret which frees the allocated frame & moves the user PC back to the instruction that would have executed following the emulated branch. In some cases the delay slot instruction may be invalid, such as a branch, or may trigger an exception. In these cases the BRK_MEMU break instruction will not be hit. In order to ensure that frames are freed this patch introduces dsemul_thread_cleanup() and calls it to free any allocated frame upon thread exit. If the instruction generated an exception & leads to a signal being delivered to the thread, or indeed if a signal simply happens to be delivered to the thread whilst it is executing from the struct emuframe, then we need to take care to exit the frame appropriately. This is done by either rolling back the user PC to the branch or advancing it to the continuation PC prior to signal delivery, using dsemul_thread_rollback(). If this were not done then a sigreturn would return to the struct emuframe, and if that frame had meanwhile been used in response to an emulated branch instruction within the signal handler then we would execute the wrong user code. Whilst a user could theoretically place something like a compact branch to self in a delay slot and cause their thread to become stuck in an infinite loop with the frame never being deallocated, this would: - Only affect the users single process. - Be architecturally invalid since there would be a branch in the delay slot, which is forbidden. - Be extremely unlikely to happen by mistake, and provide a program with no more ability to harm the system than a simple infinite loop would. If a thread requires a delay slot emulation & no frame is available to it (ie. the process has enough other threads that all frames are currently in use) then the thread joins a waitqueue. It will sleep until a frame is freed by another thread in the process. Since we now know whether a thread has an allocated frame due to our tracking of its index, the cookie field of struct emuframe is removed as we can be more certain whether we have a valid frame. Since a thread may only ever have a single frame at any given time, the epc field of struct emuframe is also removed & the PC to continue from is instead stored in struct thread_struct. Together these changes simplify & shrink struct emuframe somewhat, allowing twice as many frames to fit into the page allocated for them. The primary benefit of this patch is that we are now free to mark the user stack non-executable where that is possible. Signed-off-by: Paul Burton <paul.burton@imgtec.com> --- v2 of this patch can be found here: https://patchwork.linux-mips.org/patch/6125/ This has become a higher priority than it was at the time of v2 since Android has begun marking its stacks non-executable & on MIPSr6 devices we use mips_dsemul() in the emulation of pre-r6 instructions. Since the Android NDK MIPS target is MIPS32, this is important to backwards compatibility for apps on MIPSr6 systems. Changes in v5: - Fix 64 bit use by casting BD_EMUFRAME_NONE value to int. - Use a spinlock instead of a mutex to protect the emupage variables to avoid sleeping in atomic context. - Don't bother checking for frames to cleanup when exiting kernel threads. - Use the tsk parameter provided to exit_thread rather than current. - Lock the task to preserve its mm whilst freeing up frames, in case the thread is part of a currently exiting process. - Map the page in arch_setup_additional_pages() since we can't mmap from atomic context. Unfortunately we'll need to allocate a page for all processes. - The address of the page is static, so stop storing it in mm_context_t. Changes in v4: - Include asm/dsemul.h. - If a thread is executing somewhere unexpected in the emupage when a rollback (signal) occurs, free the threads allocated frame anyway. Changes in v3: - Rebase atop v4.7-rc5. - Select CONFIG_HAVE_EXIT_THREAD. - Track allocated frames per thread, allowing cleanup on exit or signal delivery. - Remove signal blocking & thread information flag now we have other means to ensure frames are cleaned up. - Introduce asm/dsemul.h to group prototypes & definitions logically. - Avoid using 'fp' in names, since this isn't exclusive to FP branch emulation. - Document with kerneldoc. - Return a frame index from alloc_emuframe such that mips_dsemul can record it in struct thread_struct. - Use bool return type for do_dsemulret rather than a bool-like int. - Rework commit message. Changes in v2: - s/kernels/kernel's/ - Use (mm_)isBranchInstr in mips_dsemul rather than duplicating similar logic. arch/mips/Kconfig | 1 + arch/mips/include/asm/dsemul.h | 92 ++++++++++ arch/mips/include/asm/fpu_emulator.h | 17 +- arch/mips/include/asm/mmu.h | 9 + arch/mips/include/asm/mmu_context.h | 6 + arch/mips/include/asm/processor.h | 18 +- arch/mips/kernel/mips-r2-to-r6-emul.c | 8 +- arch/mips/kernel/process.c | 14 ++ arch/mips/kernel/signal.c | 8 + arch/mips/kernel/vdso.c | 10 + arch/mips/math-emu/cp1emu.c | 8 +- arch/mips/math-emu/dsemul.c | 333 +++++++++++++++++++++++----------- 12 files changed, 391 insertions(+), 133 deletions(-) create mode 100644 arch/mips/include/asm/dsemul.h diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ac91939..49a5396 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -64,6 +64,7 @@ config MIPS select GENERIC_TIME_VSYSCALL select ARCH_CLOCKSOURCE_DATA select HANDLE_DOMAIN_IRQ + select HAVE_EXIT_THREAD menu "Machine selection" diff --git a/arch/mips/include/asm/dsemul.h b/arch/mips/include/asm/dsemul.h new file mode 100644 index 0000000..a6e0678 --- /dev/null +++ b/arch/mips/include/asm/dsemul.h @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2016 Imagination Technologies + * Author: Paul Burton <paul.burton@imgtec.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __MIPS_ASM_DSEMUL_H__ +#define __MIPS_ASM_DSEMUL_H__ + +#include <asm/break.h> +#include <asm/inst.h> + +/* Break instruction with special math emu break code set */ +#define BREAK_MATH(micromips) (((micromips) ? 0x7 : 0xd) | (BRK_MEMU << 16)) + +/* When used as a frame index, indicates the lack of a frame */ +#define BD_EMUFRAME_NONE ((int)BIT(31)) + +struct mm_struct; +struct pt_regs; +struct task_struct; + +/** + * mips_dsemul() - 'Emulate' an instruction from a branch delay slot + * @regs: User thread register context. + * @ir: The instruction to be 'emulated'. + * @branch_pc: The PC of the branch instruction. + * @cont_pc: The PC to continue at following 'emulation'. + * + * Emulate or execute an arbitrary MIPS instruction within the context of + * the current user thread. This is used primarily to handle instructions + * in the delay slots of emulated branch instructions, for example FP + * branch instructions on systems without an FPU. + * + * Return: Zero on success, negative if ir is a NOP, signal number on failure. + */ +extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, + unsigned long branch_pc, unsigned long cont_pc); + +/** + * do_dsemulret() - Return from a delay slot 'emulation' frame + * @xcp: User thread register context. + * + * Call in response to the BRK_MEMU break instruction used to return to + * the kernel from branch delay slot 'emulation' frames following a call + * to mips_dsemul(). Restores the user thread PC to the value that was + * passed as the cpc parameter to mips_dsemul(). + * + * Return: True if an emulation frame was returned from, else false. + */ +extern bool do_dsemulret(struct pt_regs *xcp); + +/** + * dsemul_thread_cleanup() - Cleanup thread 'emulation' frame + * @tsk: The task structure associated with the thread + * + * If the thread @tsk has a branch delay slot 'emulation' frame + * allocated to it then free that frame. + * + * Return: True if a frame was freed, else false. + */ +extern bool dsemul_thread_cleanup(struct task_struct *tsk); + +/** + * dsemul_thread_rollback() - Rollback from an 'emulation' frame + * @regs: User thread register context. + * + * If the current thread, whose register context is represented by @regs, + * is executing within a delay slot 'emulation' frame then exit that + * frame. The PC will be rolled back to the branch if the instruction + * that was being 'emulated' has not yet executed, or advanced to the + * continuation PC if it has. + * + * Return: True if a frame was exited, else false. + */ +extern bool dsemul_thread_rollback(struct pt_regs *regs); + +/** + * dsemul_mm_cleanup() - Cleanup per-mm delay slot 'emulation' state + * @mm: The struct mm_struct to cleanup state for. + * + * Cleanup state for the given @mm, ensuring that any memory allocated + * for delay slot 'emulation' book-keeping is freed. This is to be called + * before @mm is freed in order to avoid memory leaks. + */ +extern void dsemul_mm_cleanup(struct mm_struct *mm); + +#endif /* __MIPS_ASM_DSEMUL_H__ */ diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h index 3225c3c..355dc25 100644 --- a/arch/mips/include/asm/fpu_emulator.h +++ b/arch/mips/include/asm/fpu_emulator.h @@ -24,7 +24,7 @@ #define _ASM_FPU_EMULATOR_H #include <linux/sched.h> -#include <asm/break.h> +#include <asm/dsemul.h> #include <asm/thread_info.h> #include <asm/inst.h> #include <asm/local.h> @@ -60,27 +60,16 @@ do { \ #define MIPS_FPU_EMU_INC_STATS(M) do { } while (0) #endif /* CONFIG_DEBUG_FS */ -extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, - unsigned long cpc); -extern int do_dsemulret(struct pt_regs *xcp); extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, int has_fpu, void *__user *fault_addr); int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31); +int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, + unsigned long *contpc); int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, unsigned long *contpc); -/* - * Instruction inserted following the badinst to further tag the sequence - */ -#define BD_COOKIE 0x0000bd36 /* tne $0, $0 with baggage */ - -/* - * Break instruction with special math emu break code set - */ -#define BREAK_MATH(micromips) (((micromips) ? 0x7 : 0xd) | (BRK_MEMU << 16)) - #define SIGNALLING_NAN 0x7ff800007ff80000LL static inline void fpu_emulator_init_fpu(void) diff --git a/arch/mips/include/asm/mmu.h b/arch/mips/include/asm/mmu.h index 1afa1f9..f6ba08d 100644 --- a/arch/mips/include/asm/mmu.h +++ b/arch/mips/include/asm/mmu.h @@ -2,11 +2,20 @@ #define __ASM_MMU_H #include <linux/atomic.h> +#include <linux/spinlock.h> +#include <linux/wait.h> typedef struct { unsigned long asid[NR_CPUS]; void *vdso; atomic_t fp_mode_switching; + + /* lock to be held whilst modifying fp_bd_emupage_allocmap */ + spinlock_t bd_emupage_lock; + /* bitmap tracking allocation of fp_bd_emupage */ + unsigned long *bd_emupage_allocmap; + /* wait queue for threads requiring an emuframe */ + wait_queue_head_t bd_emupage_queue; } mm_context_t; #endif /* __ASM_MMU_H */ diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index fc57e13..ddd57ad 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -16,6 +16,7 @@ #include <linux/smp.h> #include <linux/slab.h> #include <asm/cacheflush.h> +#include <asm/dsemul.h> #include <asm/hazards.h> #include <asm/tlbflush.h> #include <asm-generic/mm_hooks.h> @@ -128,6 +129,10 @@ init_new_context(struct task_struct *tsk, struct mm_struct *mm) atomic_set(&mm->context.fp_mode_switching, 0); + mm->context.bd_emupage_allocmap = NULL; + spin_lock_init(&mm->context.bd_emupage_lock); + init_waitqueue_head(&mm->context.bd_emupage_queue); + return 0; } @@ -162,6 +167,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, */ static inline void destroy_context(struct mm_struct *mm) { + dsemul_mm_cleanup(mm); } #define deactivate_mm(tsk, mm) do { } while (0) diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index 7e78b62..0d36c87 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -11,12 +11,14 @@ #ifndef _ASM_PROCESSOR_H #define _ASM_PROCESSOR_H +#include <linux/atomic.h> #include <linux/cpumask.h> #include <linux/threads.h> #include <asm/cachectl.h> #include <asm/cpu.h> #include <asm/cpu-info.h> +#include <asm/dsemul.h> #include <asm/mipsregs.h> #include <asm/prefetch.h> @@ -78,7 +80,11 @@ extern unsigned int vced_count, vcei_count; #endif -#define STACK_TOP (TASK_SIZE & PAGE_MASK) +/* + * One page above the stack is used for branch delay slot "emulation". + * See dsemul.c for details. + */ +#define STACK_TOP ((TASK_SIZE & PAGE_MASK) - PAGE_SIZE) /* * This decides where the kernel will search for a free chunk of vm @@ -256,6 +262,12 @@ struct thread_struct { /* Saved fpu/fpu emulator stuff. */ struct mips_fpu_struct fpu FPU_ALIGN; + /* Assigned branch delay slot 'emulation' frame */ + atomic_t bd_emu_frame; + /* PC of the branch from a branch delay slot 'emulation' */ + unsigned long bd_emu_branch_pc; + /* PC to continue from following a branch delay slot 'emulation' */ + unsigned long bd_emu_cont_pc; #ifdef CONFIG_MIPS_MT_FPAFF /* Emulated instruction count */ unsigned long emulated_fp; @@ -323,6 +335,10 @@ struct thread_struct { * FPU affinity state (null if not FPAFF) \ */ \ FPAFF_INIT \ + /* Delay slot emulation */ \ + .bd_emu_frame = ATOMIC_INIT(BD_EMUFRAME_NONE), \ + .bd_emu_branch_pc = 0, \ + .bd_emu_cont_pc = 0, \ /* \ * Saved DSP stuff \ */ \ diff --git a/arch/mips/kernel/mips-r2-to-r6-emul.c b/arch/mips/kernel/mips-r2-to-r6-emul.c index 7ff2a55..ef23c61 100644 --- a/arch/mips/kernel/mips-r2-to-r6-emul.c +++ b/arch/mips/kernel/mips-r2-to-r6-emul.c @@ -283,7 +283,7 @@ static int jr_func(struct pt_regs *regs, u32 ir) err = mipsr6_emul(regs, nir); if (err > 0) { regs->cp0_epc = nepc; - err = mips_dsemul(regs, nir, cepc); + err = mips_dsemul(regs, nir, epc, cepc); if (err == SIGILL) err = SIGEMT; MIPS_R2_STATS(dsemul); @@ -1033,7 +1033,7 @@ repeat: if (nir) { err = mipsr6_emul(regs, nir); if (err > 0) { - err = mips_dsemul(regs, nir, cpc); + err = mips_dsemul(regs, nir, epc, cpc); if (err == SIGILL) err = SIGEMT; MIPS_R2_STATS(dsemul); @@ -1082,7 +1082,7 @@ repeat: if (nir) { err = mipsr6_emul(regs, nir); if (err > 0) { - err = mips_dsemul(regs, nir, cpc); + err = mips_dsemul(regs, nir, epc, cpc); if (err == SIGILL) err = SIGEMT; MIPS_R2_STATS(dsemul); @@ -1149,7 +1149,7 @@ repeat: if (nir) { err = mipsr6_emul(regs, nir); if (err > 0) { - err = mips_dsemul(regs, nir, cpc); + err = mips_dsemul(regs, nir, epc, cpc); if (err == SIGILL) err = SIGEMT; MIPS_R2_STATS(dsemul); diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 813ed78..7429ad0 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -30,6 +30,7 @@ #include <asm/asm.h> #include <asm/bootinfo.h> #include <asm/cpu.h> +#include <asm/dsemul.h> #include <asm/dsp.h> #include <asm/fpu.h> #include <asm/msa.h> @@ -68,11 +69,22 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) lose_fpu(0); clear_thread_flag(TIF_MSA_CTX_LIVE); clear_used_math(); + atomic_set(¤t->thread.bd_emu_frame, BD_EMUFRAME_NONE); init_dsp(); regs->cp0_epc = pc; regs->regs[29] = sp; } +void exit_thread(struct task_struct *tsk) +{ + /* + * User threads may have allocated a delay slot emulation frame. + * If so, clean up that allocation. + */ + if (!(current->flags & PF_KTHREAD)) + dsemul_thread_cleanup(tsk); +} + int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) { /* @@ -159,6 +171,8 @@ int copy_thread(unsigned long clone_flags, unsigned long usp, clear_tsk_thread_flag(p, TIF_FPUBOUND); #endif /* CONFIG_MIPS_MT_FPAFF */ + atomic_set(&p->thread.bd_emu_frame, BD_EMUFRAME_NONE); + if (clone_flags & CLONE_SETTLS) ti->tp_value = regs->regs[7]; diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index ae42314..9383635 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -772,6 +772,14 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs) struct mips_abi *abi = current->thread.abi; void *vdso = current->mm->context.vdso; + /* + * If we were emulating a delay slot instruction, exit that frame such + * that addresses in the sigframe are as expected for userland and we + * don't have a problem if we reuse the thread's frame for an + * instruction within the signal handler. + */ + dsemul_thread_rollback(regs); + if (regs->regs[0]) { switch(regs->regs[2]) { case ERESTART_RESTARTBLOCK: diff --git a/arch/mips/kernel/vdso.c b/arch/mips/kernel/vdso.c index 54e1663..9abe447 100644 --- a/arch/mips/kernel/vdso.c +++ b/arch/mips/kernel/vdso.c @@ -107,6 +107,16 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) if (down_write_killable(&mm->mmap_sem)) return -EINTR; + /* Map delay slot emulation page */ + base = mmap_region(NULL, STACK_TOP, PAGE_SIZE, + VM_READ|VM_WRITE|VM_EXEC| + VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC, + 0); + if (IS_ERR_VALUE(base)) { + ret = base; + goto out; + } + /* * Determine total area size. This includes the VDSO data itself, the * data page, and the GIC user page if present. Always create a mapping diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index d96e912..8afa090 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -434,8 +434,8 @@ static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) * a single subroutine should be used across both * modules. */ -static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, - unsigned long *contpc) +int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, + unsigned long *contpc) { union mips_instruction insn = (union mips_instruction)dec_insn.insn; unsigned int fcr31; @@ -1268,7 +1268,7 @@ branch_common: * instruction in the dslot. */ sig = mips_dsemul(xcp, ir, - contpc); + bcpc, contpc); if (sig < 0) break; if (sig) @@ -1323,7 +1323,7 @@ branch_common: * Single step the non-cp1 * instruction in the dslot */ - sig = mips_dsemul(xcp, ir, contpc); + sig = mips_dsemul(xcp, ir, bcpc, contpc); if (sig < 0) break; if (sig) diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c index 4707488..72a4642 100644 --- a/arch/mips/math-emu/dsemul.c +++ b/arch/mips/math-emu/dsemul.c @@ -1,3 +1,6 @@ +#include <linux/err.h> +#include <linux/slab.h> + #include <asm/branch.h> #include <asm/cacheflush.h> #include <asm/fpu_emulator.h> @@ -5,43 +8,211 @@ #include <asm/mipsregs.h> #include <asm/uaccess.h> -#include "ieee754.h" - -/* - * Emulate the arbitrary instruction ir at xcp->cp0_epc. Required when - * we have to emulate the instruction in a COP1 branch delay slot. Do - * not change cp0_epc due to the instruction +/** + * struct emuframe - The 'emulation' frame structure + * @emul: The instruction to 'emulate'. + * @badinst: A break instruction to cause a return to the kernel. * - * According to the spec: - * 1) it shouldn't be a branch :-) - * 2) it can be a COP instruction :-( - * 3) if we are tring to run a protected memory space we must take - * special care on memory access instructions :-( - */ - -/* - * "Trampoline" return routine to catch exception following - * execution of delay-slot instruction execution. + * This structure defines the frames placed within the delay slot emulation + * page in response to a call to mips_dsemul(). Each thread may be allocated + * only one frame at any given time. The kernel stores within it the + * instruction to be 'emulated' followed by a break instruction, then + * executes the frame in user mode. The break causes a trap to the kernel + * which leads to do_dsemulret() being called unless the instruction in + * @emul causes a trap itself, is a branch, or a signal is delivered to + * the thread. In these cases the allocated frame will either be reused by + * a subsequent delay slot 'emulation', or be freed during signal delivery or + * upon thread exit. + * + * This approach is used because: + * + * - Actually emulating all instructions isn't feasible. We would need to + * be able to handle instructions from all revisions of the MIPS ISA, + * all ASEs & all vendor instruction set extensions. This would be a + * whole lot of work & continual maintenance burden as new instructions + * are introduced, and in the case of some vendor extensions may not + * even be possible. Thus we need to take the approach of actually + * executing the instruction. + * + * - We must execute the instruction within user context. If we were to + * execute the instruction in kernel mode then it would have access to + * kernel resources without very careful checks, leaving us with a + * high potential for security or stability issues to arise. + * + * - We used to place the frame on the users stack, but this requires + * that the stack be executable. This is bad for security so the + * per-process page is now used instead. + * + * - The instruction in @emul may be something entirely invalid for a + * delay slot. The user may (intentionally or otherwise) place a branch + * in a delay slot, or a kernel mode instruction, or something else + * which generates an exception. Thus we can't rely upon the break in + * @badinst always being hit. For this reason we track the index of the + * frame allocated to each thread, allowing us to clean it up at later + * points such as signal delivery or thread exit. + * + * - The user may generate a fake struct emuframe if they wish, invoking + * the BRK_MEMU break instruction themselves. We must therefore not + * trust that BRK_MEMU means there's actually a valid frame allocated + * to the thread, and must not allow the user to do anything they + * couldn't already. */ - struct emuframe { mips_instruction emul; mips_instruction badinst; - mips_instruction cookie; - unsigned long epc; }; -/* - * Set up an emulation frame for instruction IR, from a delay slot of - * a branch jumping to CPC. Return 0 if successful, -1 if no emulation - * required, otherwise a signal number causing a frame setup failure. - */ -int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) +static const int emupage_frame_count = PAGE_SIZE / sizeof(struct emuframe); + +static inline __user struct emuframe *dsemul_page(void) +{ + return (__user struct emuframe *)STACK_TOP; +} + +static int alloc_emuframe(void) +{ + mm_context_t *mm_ctx = ¤t->mm->context; + int idx; + +retry: + spin_lock(&mm_ctx->bd_emupage_lock); + + /* Ensure we have an allocation bitmap */ + if (!mm_ctx->bd_emupage_allocmap) { + mm_ctx->bd_emupage_allocmap = + kcalloc(BITS_TO_LONGS(emupage_frame_count), + sizeof(unsigned long), + GFP_ATOMIC); + + if (!mm_ctx->bd_emupage_allocmap) { + idx = BD_EMUFRAME_NONE; + goto out_unlock; + } + } + + /* Attempt to allocate a single bit/frame */ + idx = bitmap_find_free_region(mm_ctx->bd_emupage_allocmap, + emupage_frame_count, 0); + if (idx < 0) { + /* + * Failed to allocate a frame. We'll wait until one becomes + * available. We unlock the page so that other threads actually + * get the opportunity to free their frames, which means + * technically the result of bitmap_full may be incorrect. + * However the worst case is that we repeat all this and end up + * back here again. + */ + spin_unlock(&mm_ctx->bd_emupage_lock); + if (!wait_event_killable(mm_ctx->bd_emupage_queue, + !bitmap_full(mm_ctx->bd_emupage_allocmap, + emupage_frame_count))) + goto retry; + + /* Received a fatal signal - just give in */ + return BD_EMUFRAME_NONE; + } + + /* Success! */ + pr_debug("allocate emuframe %d to %d\n", idx, current->pid); +out_unlock: + spin_unlock(&mm_ctx->bd_emupage_lock); + return idx; +} + +static void free_emuframe(int idx, struct mm_struct *mm) +{ + mm_context_t *mm_ctx = &mm->context; + + spin_lock(&mm_ctx->bd_emupage_lock); + + pr_debug("free emuframe %d from %d\n", idx, current->pid); + bitmap_clear(mm_ctx->bd_emupage_allocmap, idx, 1); + + /* If some thread is waiting for a frame, now's its chance */ + wake_up(&mm_ctx->bd_emupage_queue); + + spin_unlock(&mm_ctx->bd_emupage_lock); +} + +static bool within_emuframe(struct pt_regs *regs) +{ + unsigned long base = (unsigned long)dsemul_page(); + + if (regs->cp0_epc < base) + return false; + if (regs->cp0_epc >= (base + PAGE_SIZE)) + return false; + + return true; +} + +bool dsemul_thread_cleanup(struct task_struct *tsk) +{ + int fr_idx; + + /* Clear any allocated frame, retrieving its index */ + fr_idx = atomic_xchg(&tsk->thread.bd_emu_frame, BD_EMUFRAME_NONE); + + /* If no frame was allocated, we're done */ + if (fr_idx == BD_EMUFRAME_NONE) + return false; + + task_lock(tsk); + + /* Free the frame that this thread had allocated */ + if (tsk->mm) + free_emuframe(fr_idx, tsk->mm); + + task_unlock(tsk); + return true; +} + +bool dsemul_thread_rollback(struct pt_regs *regs) +{ + struct emuframe __user *fr; + int fr_idx; + + /* Do nothing if we're not executing from a frame */ + if (!within_emuframe(regs)) + return false; + + /* Find the frame being executed */ + fr_idx = atomic_read(¤t->thread.bd_emu_frame); + if (fr_idx == BD_EMUFRAME_NONE) + return false; + fr = &dsemul_page()[fr_idx]; + + /* + * If the PC is at the emul instruction, roll back to the branch. If + * PC is at the badinst (break) instruction, we've already emulated the + * instruction so progress to the continue PC. If it's anything else + * then something is amiss & the user has branched into some other area + * of the emupage - we'll free the allocated frame anyway. + */ + if (msk_isa16_mode(regs->cp0_epc) == (unsigned long)&fr->emul) + regs->cp0_epc = current->thread.bd_emu_branch_pc; + else if (msk_isa16_mode(regs->cp0_epc) == (unsigned long)&fr->badinst) + regs->cp0_epc = current->thread.bd_emu_cont_pc; + + atomic_set(¤t->thread.bd_emu_frame, BD_EMUFRAME_NONE); + free_emuframe(fr_idx, current->mm); + return true; +} + +void dsemul_mm_cleanup(struct mm_struct *mm) +{ + mm_context_t *mm_ctx = &mm->context; + + kfree(mm_ctx->bd_emupage_allocmap); +} + +int mips_dsemul(struct pt_regs *regs, mips_instruction ir, + unsigned long branch_pc, unsigned long cont_pc) { int isa16 = get_isa16_mode(regs->cp0_epc); mips_instruction break_math; struct emuframe __user *fr; - int err; + int err, fr_idx; /* NOP is easy */ if (ir == 0) @@ -68,30 +239,20 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) } } - pr_debug("dsemul %lx %lx\n", regs->cp0_epc, cpc); + pr_debug("dsemul 0x%08lx cont at 0x%08lx\n", regs->cp0_epc, cont_pc); - /* - * The strategy is to push the instruction onto the user stack - * and put a trap after it which we can catch and jump to - * the required address any alternative apart from full - * instruction emulation!!. - * - * Algorithmics used a system call instruction, and - * borrowed that vector. MIPS/Linux version is a bit - * more heavyweight in the interests of portability and - * multiprocessor support. For Linux we use a BREAK 514 - * instruction causing a breakpoint exception. - */ - break_math = BREAK_MATH(isa16); - - /* Ensure that the two instructions are in the same cache line */ - fr = (struct emuframe __user *) - ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7); - - /* Verify that the stack pointer is not completely insane */ - if (unlikely(!access_ok(VERIFY_WRITE, fr, sizeof(struct emuframe)))) + /* Allocate a frame if we don't already have one */ + fr_idx = atomic_read(¤t->thread.bd_emu_frame); + if (fr_idx == BD_EMUFRAME_NONE) + fr_idx = alloc_emuframe(); + if (fr_idx == BD_EMUFRAME_NONE) return SIGBUS; + fr = &dsemul_page()[fr_idx]; + + /* Retrieve the appropriately encoded break instruction */ + break_math = BREAK_MATH(isa16); + /* Write the instructions to the frame */ if (isa16) { err = __put_user(ir >> 16, (u16 __user *)(&fr->emul)); @@ -106,84 +267,36 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) err |= __put_user(break_math, &fr->badinst); } - err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie); - err |= __put_user(cpc, &fr->epc); - if (unlikely(err)) { MIPS_FPU_EMU_INC_STATS(errors); + free_emuframe(fr_idx, current->mm); return SIGBUS; } + /* Record the PC of the branch, PC to continue from & frame index */ + current->thread.bd_emu_branch_pc = branch_pc; + current->thread.bd_emu_cont_pc = cont_pc; + atomic_set(¤t->thread.bd_emu_frame, fr_idx); + + /* Change user register context to execute the frame */ regs->cp0_epc = (unsigned long)&fr->emul | isa16; + /* Ensure the icache observes our newly written frame */ flush_cache_sigtramp((unsigned long)&fr->emul); return 0; } -int do_dsemulret(struct pt_regs *xcp) +bool do_dsemulret(struct pt_regs *xcp) { - int isa16 = get_isa16_mode(xcp->cp0_epc); - struct emuframe __user *fr; - unsigned long epc; - u32 insn, cookie; - int err = 0; - u16 instr[2]; - - fr = (struct emuframe __user *) - (msk_isa16_mode(xcp->cp0_epc) - sizeof(mips_instruction)); - - /* - * If we can't even access the area, something is very wrong, but we'll - * leave that to the default handling - */ - if (!access_ok(VERIFY_READ, fr, sizeof(struct emuframe))) - return 0; - - /* - * Do some sanity checking on the stackframe: - * - * - Is the instruction pointed to by the EPC an BREAK_MATH? - * - Is the following memory word the BD_COOKIE? - */ - if (isa16) { - err = __get_user(instr[0], - (u16 __user *)(&fr->badinst)); - err |= __get_user(instr[1], - (u16 __user *)((long)(&fr->badinst) + 2)); - insn = (instr[0] << 16) | instr[1]; - } else { - err = __get_user(insn, &fr->badinst); - } - err |= __get_user(cookie, &fr->cookie); - - if (unlikely(err || - insn != BREAK_MATH(isa16) || cookie != BD_COOKIE)) { + /* Cleanup the allocated frame, returning if there wasn't one */ + if (!dsemul_thread_cleanup(current)) { MIPS_FPU_EMU_INC_STATS(errors); - return 0; - } - - /* - * At this point, we are satisfied that it's a BD emulation trap. Yes, - * a user might have deliberately put two malformed and useless - * instructions in a row in his program, in which case he's in for a - * nasty surprise - the next instruction will be treated as a - * continuation address! Alas, this seems to be the only way that we - * can handle signals, recursion, and longjmps() in the context of - * emulating the branch delay instruction. - */ - - pr_debug("dsemulret\n"); - - if (__get_user(epc, &fr->epc)) { /* Saved EPC */ - /* This is not a good situation to be in */ - force_sig(SIGBUS, current); - - return 0; + return false; } /* Set EPC to return to post-branch instruction */ - xcp->cp0_epc = epc; - MIPS_FPU_EMU_INC_STATS(ds_emul); - return 1; + xcp->cp0_epc = current->thread.bd_emu_cont_pc; + pr_debug("dsemulret to 0x%08lx\n", xcp->cp0_epc); + return true; } -- 2.9.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v5 2/2] MIPS: non-exec stack & heap when non-exec PT_GNU_STACK is present @ 2016-07-08 10:06 ` Paul Burton 0 siblings, 0 replies; 12+ messages in thread From: Paul Burton @ 2016-07-08 10:06 UTC (permalink / raw) To: linux-mips, Ralf Baechle Cc: Leonid Yegoshin, Maciej Rozycki, Faraz Shahbazker, Raghu Gandham, Matthew Fortune, Paul Burton The stack and heap have both been executable by default on MIPS until now. This patch changes the default to be non-executable, but only for ELF binaries with a non-executable PT_GNU_STACK header present. This does apply to both the heap & the stack, despite the name PT_GNU_STACK, and this matches the behaviour of other architectures like ARM & x86. Current MIPS toolchains do not produce the PT_GNU_STACK header, which means that we can rely upon this patch not changing the behaviour of existing binaries. The new default will only take effect for newly compiled binaries once toolchains are updated to support PT_GNU_STACK, and since those binaries are newly compiled they can be compiled expecting the change in default behaviour. Again this matches the way in which the ARM & x86 architectures handled their implementations of non-executable memory. Signed-off-by: Paul Burton <paul.burton@imgtec.com> --- Changes in v5: - Use void* for the ELF header parameter to avoid build failures on 64 bit. Changes in v4: None Changes in v3: - Rebase atop v4.7-rc5. Changes in v2: None arch/mips/include/asm/elf.h | 3 +++ arch/mips/include/asm/page.h | 6 ++++-- arch/mips/kernel/elf.c | 19 +++++++++++++++++++ 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h index f5f4571..e81cc55 100644 --- a/arch/mips/include/asm/elf.h +++ b/arch/mips/include/asm/elf.h @@ -498,4 +498,7 @@ extern int arch_check_elf(void *ehdr, bool has_interpreter, void *interp_ehdr, extern void mips_set_personality_nan(struct arch_elf_state *state); extern void mips_set_personality_fp(struct arch_elf_state *state); +#define elf_read_implies_exec(ex, stk) mips_elf_read_implies_exec(&(ex), stk) +extern int mips_elf_read_implies_exec(void *elf_ex, int exstack); + #endif /* _ASM_ELF_H */ diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h index 21ed715..74cb004 100644 --- a/arch/mips/include/asm/page.h +++ b/arch/mips/include/asm/page.h @@ -229,8 +229,10 @@ extern int __virt_addr_valid(const volatile void *kaddr); #define virt_addr_valid(kaddr) \ __virt_addr_valid((const volatile void *) (kaddr)) -#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ - VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) +#define VM_DATA_DEFAULT_FLAGS \ + (VM_READ | VM_WRITE | \ + ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0) | \ + VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) #define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE) #define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET) diff --git a/arch/mips/kernel/elf.c b/arch/mips/kernel/elf.c index 891f5ee..824b037 100644 --- a/arch/mips/kernel/elf.c +++ b/arch/mips/kernel/elf.c @@ -8,9 +8,12 @@ * option) any later version. */ +#include <linux/binfmts.h> #include <linux/elf.h> +#include <linux/export.h> #include <linux/sched.h> +#include <asm/cpu-features.h> #include <asm/cpu-info.h> /* Whether to accept legacy-NaN and 2008-NaN user binaries. */ @@ -326,3 +329,19 @@ void mips_set_personality_nan(struct arch_elf_state *state) BUG(); } } + +int mips_elf_read_implies_exec(void *elf_ex, int exstack) +{ + if (exstack != EXSTACK_DISABLE_X) { + /* The binary doesn't request a non-executable stack */ + return 1; + } + + if (!cpu_has_rixi) { + /* The CPU doesn't support non-executable memory */ + return 1; + } + + return 0; +} +EXPORT_SYMBOL(mips_elf_read_implies_exec); -- 2.9.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v5 2/2] MIPS: non-exec stack & heap when non-exec PT_GNU_STACK is present @ 2016-07-08 10:06 ` Paul Burton 0 siblings, 0 replies; 12+ messages in thread From: Paul Burton @ 2016-07-08 10:06 UTC (permalink / raw) To: linux-mips, Ralf Baechle Cc: Leonid Yegoshin, Maciej Rozycki, Faraz Shahbazker, Raghu Gandham, Matthew Fortune, Paul Burton The stack and heap have both been executable by default on MIPS until now. This patch changes the default to be non-executable, but only for ELF binaries with a non-executable PT_GNU_STACK header present. This does apply to both the heap & the stack, despite the name PT_GNU_STACK, and this matches the behaviour of other architectures like ARM & x86. Current MIPS toolchains do not produce the PT_GNU_STACK header, which means that we can rely upon this patch not changing the behaviour of existing binaries. The new default will only take effect for newly compiled binaries once toolchains are updated to support PT_GNU_STACK, and since those binaries are newly compiled they can be compiled expecting the change in default behaviour. Again this matches the way in which the ARM & x86 architectures handled their implementations of non-executable memory. Signed-off-by: Paul Burton <paul.burton@imgtec.com> --- Changes in v5: - Use void* for the ELF header parameter to avoid build failures on 64 bit. Changes in v4: None Changes in v3: - Rebase atop v4.7-rc5. Changes in v2: None arch/mips/include/asm/elf.h | 3 +++ arch/mips/include/asm/page.h | 6 ++++-- arch/mips/kernel/elf.c | 19 +++++++++++++++++++ 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h index f5f4571..e81cc55 100644 --- a/arch/mips/include/asm/elf.h +++ b/arch/mips/include/asm/elf.h @@ -498,4 +498,7 @@ extern int arch_check_elf(void *ehdr, bool has_interpreter, void *interp_ehdr, extern void mips_set_personality_nan(struct arch_elf_state *state); extern void mips_set_personality_fp(struct arch_elf_state *state); +#define elf_read_implies_exec(ex, stk) mips_elf_read_implies_exec(&(ex), stk) +extern int mips_elf_read_implies_exec(void *elf_ex, int exstack); + #endif /* _ASM_ELF_H */ diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h index 21ed715..74cb004 100644 --- a/arch/mips/include/asm/page.h +++ b/arch/mips/include/asm/page.h @@ -229,8 +229,10 @@ extern int __virt_addr_valid(const volatile void *kaddr); #define virt_addr_valid(kaddr) \ __virt_addr_valid((const volatile void *) (kaddr)) -#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ - VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) +#define VM_DATA_DEFAULT_FLAGS \ + (VM_READ | VM_WRITE | \ + ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0) | \ + VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) #define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE) #define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET) diff --git a/arch/mips/kernel/elf.c b/arch/mips/kernel/elf.c index 891f5ee..824b037 100644 --- a/arch/mips/kernel/elf.c +++ b/arch/mips/kernel/elf.c @@ -8,9 +8,12 @@ * option) any later version. */ +#include <linux/binfmts.h> #include <linux/elf.h> +#include <linux/export.h> #include <linux/sched.h> +#include <asm/cpu-features.h> #include <asm/cpu-info.h> /* Whether to accept legacy-NaN and 2008-NaN user binaries. */ @@ -326,3 +329,19 @@ void mips_set_personality_nan(struct arch_elf_state *state) BUG(); } } + +int mips_elf_read_implies_exec(void *elf_ex, int exstack) +{ + if (exstack != EXSTACK_DISABLE_X) { + /* The binary doesn't request a non-executable stack */ + return 1; + } + + if (!cpu_has_rixi) { + /* The CPU doesn't support non-executable memory */ + return 1; + } + + return 0; +} +EXPORT_SYMBOL(mips_elf_read_implies_exec); -- 2.9.0 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v5 2/2] MIPS: non-exec stack & heap when non-exec PT_GNU_STACK is present @ 2016-07-08 16:36 ` Maciej W. Rozycki 0 siblings, 0 replies; 12+ messages in thread From: Maciej W. Rozycki @ 2016-07-08 16:36 UTC (permalink / raw) To: Paul Burton Cc: linux-mips, Ralf Baechle, Leonid Yegoshin, Faraz Shahbazker, Raghu Gandham, Matthew Fortune Paul, You wrote: > Current MIPS toolchains do not produce the PT_GNU_STACK header, which > means that we can rely upon this patch not changing the behaviour of > existing binaries. The new default will only take effect for newly > compiled binaries once toolchains are updated to support PT_GNU_STACK, > and since those binaries are newly compiled they can be compiled > expecting the change in default behaviour. Again this matches the way in > which the ARM & x86 architectures handled their implementations of > non-executable memory. however IIUC this is inaccurate to say the least I'm afraid, as generic PT_GNU_STACK support went in to binutils with: commit 04c3a75556c018feb1f609404c627414a7ef672e Author: Nathan Sidwell <nathan@codesourcery.com> Date: Tue Oct 23 09:33:56 2012 +0000 <https://sourceware.org/ml/binutils/2012-10/msg00317.html>, ("cleanup PT_GNU_STACK size handling"), replacing an earlier target-specific implementation previously present, and the MIPS port specifically has been updated to actually report this at the EI_ABIVERSION offset of the `e_ident' array of the ELF header with commit 17733f5be961 ("Increment the ABIVERSION to 5 for MIPS objects with non-executable stacks."), earlier this year (it's not clear to me offhand why we need to do this rather than relying on the lone presence of PT_GNU_STACK, but I'm sure someone will enlighten me). By the time this kernel update hits the street I expect we'll have this feature present in a proper binutils release even as 2.27 is currently being rolled out already. Have I missed anything? Maciej ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v5 2/2] MIPS: non-exec stack & heap when non-exec PT_GNU_STACK is present @ 2016-07-08 16:36 ` Maciej W. Rozycki 0 siblings, 0 replies; 12+ messages in thread From: Maciej W. Rozycki @ 2016-07-08 16:36 UTC (permalink / raw) To: Paul Burton Cc: linux-mips, Ralf Baechle, Leonid Yegoshin, Faraz Shahbazker, Raghu Gandham, Matthew Fortune Paul, You wrote: > Current MIPS toolchains do not produce the PT_GNU_STACK header, which > means that we can rely upon this patch not changing the behaviour of > existing binaries. The new default will only take effect for newly > compiled binaries once toolchains are updated to support PT_GNU_STACK, > and since those binaries are newly compiled they can be compiled > expecting the change in default behaviour. Again this matches the way in > which the ARM & x86 architectures handled their implementations of > non-executable memory. however IIUC this is inaccurate to say the least I'm afraid, as generic PT_GNU_STACK support went in to binutils with: commit 04c3a75556c018feb1f609404c627414a7ef672e Author: Nathan Sidwell <nathan@codesourcery.com> Date: Tue Oct 23 09:33:56 2012 +0000 <https://sourceware.org/ml/binutils/2012-10/msg00317.html>, ("cleanup PT_GNU_STACK size handling"), replacing an earlier target-specific implementation previously present, and the MIPS port specifically has been updated to actually report this at the EI_ABIVERSION offset of the `e_ident' array of the ELF header with commit 17733f5be961 ("Increment the ABIVERSION to 5 for MIPS objects with non-executable stacks."), earlier this year (it's not clear to me offhand why we need to do this rather than relying on the lone presence of PT_GNU_STACK, but I'm sure someone will enlighten me). By the time this kernel update hits the street I expect we'll have this feature present in a proper binutils release even as 2.27 is currently being rolled out already. Have I missed anything? Maciej ^ permalink raw reply [flat|nested] 12+ messages in thread
[parent not found: <577FF4A1.5000200@imgtec.com>]
* Re: [PATCH v5 2/2] MIPS: non-exec stack & heap when non-exec PT_GNU_STACK is present @ 2016-07-08 19:53 ` Maciej W. Rozycki 0 siblings, 0 replies; 12+ messages in thread From: Maciej W. Rozycki @ 2016-07-08 19:53 UTC (permalink / raw) To: Faraz Shahbazker Cc: Paul Burton, linux-mips, Ralf Baechle, Leonid Yegoshin, Raghu Gandham, Matthew Fortune On Fri, 8 Jul 2016, Faraz Shahbazker wrote: > On 07/08/2016 09:36 AM, Maciej W. Rozycki wrote: > > implementation previously present, and the MIPS port specifically has been > > updated to actually report this at the EI_ABIVERSION offset of the > > `e_ident' array of the ELF header with commit 17733f5be961 ("Increment the > > ABIVERSION to 5 for MIPS objects with non-executable stacks."), earlier > > this year (it's not clear to me offhand why we need to do this rather than > > relying on the lone presence of PT_GNU_STACK, but I'm sure someone will > > enlighten me). > > This was simply to be able to check whether the tools support a safe non-exec > stack scheme, before enabling it as a default in the compiler. Refer to the > attached e-mail from Matthew. Neither linker nor compiler patch is upstream. Hmm, now I am really confused: what problem are we trying to solve on the toolchain side? As I understand the current state of affairs, we have now have a situation where the toolchain may be asked (although it is not on by default) to produce a MIPS PT_GNU_STACK binary, which will be happily executed by the kernel with the execution permission disabled for the stack memory (where supported by hardware, i.e. RIXI), however then it will itself happily try to execute from that stack memory in the FPU emulator. So first of all we need to address the problem in the kernel by making the FPU emulator avoid stack execution. That will fix PT_GNU_STACK support on our target. Second we want to enforce the non-executable-stack policy in the userland by adding a check early on in glibc startup for a flag, such as in the FLAGS entry of the auxiliary vector, set by a fixed kernel only, telling glibc that the presence of PT_GNU_STACK has been respected by the kernel, and make the startup bail out right away if the flag is not there. So where does the static linker EI_ABIVERSION update fit here? What is it needed for? What have I missed? Maciej ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v5 2/2] MIPS: non-exec stack & heap when non-exec PT_GNU_STACK is present @ 2016-07-08 19:53 ` Maciej W. Rozycki 0 siblings, 0 replies; 12+ messages in thread From: Maciej W. Rozycki @ 2016-07-08 19:53 UTC (permalink / raw) To: Faraz Shahbazker Cc: Paul Burton, linux-mips, Ralf Baechle, Leonid Yegoshin, Raghu Gandham, Matthew Fortune On Fri, 8 Jul 2016, Faraz Shahbazker wrote: > On 07/08/2016 09:36 AM, Maciej W. Rozycki wrote: > > implementation previously present, and the MIPS port specifically has been > > updated to actually report this at the EI_ABIVERSION offset of the > > `e_ident' array of the ELF header with commit 17733f5be961 ("Increment the > > ABIVERSION to 5 for MIPS objects with non-executable stacks."), earlier > > this year (it's not clear to me offhand why we need to do this rather than > > relying on the lone presence of PT_GNU_STACK, but I'm sure someone will > > enlighten me). > > This was simply to be able to check whether the tools support a safe non-exec > stack scheme, before enabling it as a default in the compiler. Refer to the > attached e-mail from Matthew. Neither linker nor compiler patch is upstream. Hmm, now I am really confused: what problem are we trying to solve on the toolchain side? As I understand the current state of affairs, we have now have a situation where the toolchain may be asked (although it is not on by default) to produce a MIPS PT_GNU_STACK binary, which will be happily executed by the kernel with the execution permission disabled for the stack memory (where supported by hardware, i.e. RIXI), however then it will itself happily try to execute from that stack memory in the FPU emulator. So first of all we need to address the problem in the kernel by making the FPU emulator avoid stack execution. That will fix PT_GNU_STACK support on our target. Second we want to enforce the non-executable-stack policy in the userland by adding a check early on in glibc startup for a flag, such as in the FLAGS entry of the auxiliary vector, set by a fixed kernel only, telling glibc that the presence of PT_GNU_STACK has been respected by the kernel, and make the startup bail out right away if the flag is not there. So where does the static linker EI_ABIVERSION update fit here? What is it needed for? What have I missed? Maciej ^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH v5 2/2] MIPS: non-exec stack & heap when non-exec PT_GNU_STACK is present 2016-07-08 19:53 ` Maciej W. Rozycki (?) @ 2016-07-18 11:55 ` Matthew Fortune 2016-09-12 10:54 ` Maciej W. Rozycki -1 siblings, 1 reply; 12+ messages in thread From: Matthew Fortune @ 2016-07-18 11:55 UTC (permalink / raw) To: Maciej Rozycki, Faraz Shahbazker Cc: Paul Burton, linux-mips, Ralf Baechle, Leonid Yegoshin, Raghu Gandham Maciej Rozycki <Maciej.Rozycki@imgtec.com> writes: > On Fri, 8 Jul 2016, Faraz Shahbazker wrote: > > > On 07/08/2016 09:36 AM, Maciej W. Rozycki wrote: > > > implementation previously present, and the MIPS port specifically > > > has been updated to actually report this at the EI_ABIVERSION offset > > > of the `e_ident' array of the ELF header with commit 17733f5be961 > > > ("Increment the ABIVERSION to 5 for MIPS objects with non-executable > > > stacks."), earlier this year (it's not clear to me offhand why we > > > need to do this rather than relying on the lone presence of > > > PT_GNU_STACK, but I'm sure someone will enlighten me). > > > > This was simply to be able to check whether the tools support a safe > > non-exec stack scheme, before enabling it as a default in the > > compiler. Refer to the attached e-mail from Matthew. Neither linker > nor compiler patch is upstream. > > Hmm, now I am really confused: what problem are we trying to solve on > the toolchain side? The problem was that if we just turn on no-exec-stack support in GCC then when someone combines that with an older binutils and/or build glibc from source (using those tools) then they would get an executable that asked for a non-executable stack and the kernel would willingly do so. However, this would then crash. So we need a way to prevent the generic logic in glibc's build system from creating a no-exec-stack library until we have the kernel checks in place in glibc to undo no-exec-stack. This then leads to the convoluted system of increased EI_ABIVERSION (or some other equally complex plan) to ensure mix-and-match of new and old tools glibc and kernel all behave nicely. > As I understand the current state of affairs, we have now have a > situation where the toolchain may be asked (although it is not on by > default) to produce a MIPS PT_GNU_STACK binary, which will be happily > executed by the kernel with the execution permission disabled for the > stack memory (where supported by hardware, i.e. RIXI), however then it > will itself happily try to execute from that stack memory in the FPU > emulator. > > So first of all we need to address the problem in the kernel by making > the FPU emulator avoid stack execution. That will fix PT_GNU_STACK > support on our target. Yes. > Second we want to enforce the non-executable-stack policy in the > userland by adding a check early on in glibc startup for a flag, such as > in the FLAGS entry of the auxiliary vector, set by a fixed kernel only, > telling glibc that the presence of PT_GNU_STACK has been respected by > the kernel, and make the startup bail out right away if the flag is not > there. Yes. > So where does the static linker EI_ABIVERSION update fit here? What is > it needed for? What have I missed? Making sure new GCC + new binutils + old glibc (from source) does not create executables that crash. My proposal was to also make sure that a MIPS GCC with no-exec-stack support would fail the generic glibc build system test for no-exec-stack and instead need a new MIPS specific test so that old glibc built from source never ended up with no-exec-stack support for MIPS. I'd love to simplify all this if for some reason this isn't actually a problem. I was trying to stick to the principle of all combinations of old and new tools/libraries should just work. Matthew ^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH v5 2/2] MIPS: non-exec stack & heap when non-exec PT_GNU_STACK is present 2016-07-18 11:55 ` Matthew Fortune @ 2016-09-12 10:54 ` Maciej W. Rozycki 0 siblings, 0 replies; 12+ messages in thread From: Maciej W. Rozycki @ 2016-09-12 10:54 UTC (permalink / raw) To: Matthew Fortune Cc: Faraz Shahbazker, Paul Burton, linux-mips, Ralf Baechle, Leonid Yegoshin, Raghu Gandham, James Cowgill, Aurelien Jarno Matthew, I meant to reply sooner, but somehow lost this from my radar. Given the recent failure report from what Debian distribution developers observed: <https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=834096> I think the design of this feature needs to be reevaluated. On Mon, 18 Jul 2016, Matthew Fortune wrote: > Maciej Rozycki <Maciej.Rozycki@imgtec.com> writes: > > On Fri, 8 Jul 2016, Faraz Shahbazker wrote: > > > > > On 07/08/2016 09:36 AM, Maciej W. Rozycki wrote: > > > > implementation previously present, and the MIPS port specifically > > > > has been updated to actually report this at the EI_ABIVERSION offset > > > > of the `e_ident' array of the ELF header with commit 17733f5be961 > > > > ("Increment the ABIVERSION to 5 for MIPS objects with non-executable > > > > stacks."), earlier this year (it's not clear to me offhand why we > > > > need to do this rather than relying on the lone presence of > > > > PT_GNU_STACK, but I'm sure someone will enlighten me). > > > > > > This was simply to be able to check whether the tools support a safe > > > non-exec stack scheme, before enabling it as a default in the > > > compiler. Refer to the attached e-mail from Matthew. Neither linker > > nor compiler patch is upstream. > > > > Hmm, now I am really confused: what problem are we trying to solve on > > the toolchain side? > > The problem was that if we just turn on no-exec-stack support in GCC then > when someone combines that with an older binutils and/or build glibc > from source (using those tools) then they would get an executable that > asked for a non-executable stack and the kernel would willingly do so. > > However, this would then crash. So we need a way to prevent the generic > logic in glibc's build system from creating a no-exec-stack library until > we have the kernel checks in place in glibc to undo no-exec-stack. This > then leads to the convoluted system of increased EI_ABIVERSION (or some > other equally complex plan) to ensure mix-and-match of new and old tools > glibc and kernel all behave nicely. How exactly is this supposed to work? > > As I understand the current state of affairs, we have now have a > > situation where the toolchain may be asked (although it is not on by > > default) to produce a MIPS PT_GNU_STACK binary, which will be happily > > executed by the kernel with the execution permission disabled for the > > stack memory (where supported by hardware, i.e. RIXI), however then it > > will itself happily try to execute from that stack memory in the FPU > > emulator. > > > > So first of all we need to address the problem in the kernel by making > > the FPU emulator avoid stack execution. That will fix PT_GNU_STACK > > support on our target. > > Yes. > > > Second we want to enforce the non-executable-stack policy in the > > userland by adding a check early on in glibc startup for a flag, such as > > in the FLAGS entry of the auxiliary vector, set by a fixed kernel only, > > telling glibc that the presence of PT_GNU_STACK has been respected by > > the kernel, and make the startup bail out right away if the flag is not > > there. > > Yes. > > > So where does the static linker EI_ABIVERSION update fit here? What is > > it needed for? What have I missed? > > Making sure new GCC + new binutils + old glibc (from source) does not create > executables that crash. My proposal was to also make sure that a MIPS GCC > with no-exec-stack support would fail the generic glibc build system test > for no-exec-stack and instead need a new MIPS specific test so that old > glibc built from source never ended up with no-exec-stack support for MIPS. Please elaborate on what "crash" means here -- what is the reason causing a `noexecstack' binary built with new GCC/binutils and old glibc sources to crash? We need to be precise with specifying failure conditions so that someone who (for whatever reason) cannot immediately reproduce the failure concerned is able to understand what is going on. > I'd love to simplify all this if for some reason this isn't actually a > problem. I was trying to stick to the principle of all combinations of old > and new tools/libraries should just work. From my understanding so far the version of binutils does not matter as PT_GNU_STACK support has been correct in binutils for the MIPS target since the introduction of the feature sometime in the past. It's only the interaction between the kernel and glibc that matters here (the interaction with GCC WRT nested function trampolines has been sorted with the use of the `.note.GNU-stack' special section, ultimately interpreted by the static linker, so it can be moved out of the picture). So AFAICT we don't need any change to binutils, and all MIPS binaries already in existence which carry a PT_GNU_STACK segment will execute correctly with the stack protected on new versions of the Linux kernel that have an updated FPU emulator implemented. So we have no backwards compatibility problem. What we only want to have is a run-time check in new glibc (`ld.so' and static startup), which will ensure a PT_GNU_STACK binary terminates right away on old versions of the Linux kernel that require an executable stack for the FPU emulator. So it looks to me we ought to ditch any EI_ABIVERSION checks related to this feature and merely include a piece of code in glibc to verify that PT_GNU_STACK has been respected by the kernel. This might be either passive, such as by peeking at a bit in the FLAGS entry of the auxiliary vector (which won't have been set by old kernels), or active, by invoking a syscall such as prctl(2) (which will return ENOSYS on old kernels), and then acting accordingly. Have I missed anything? Maciej ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2016-09-12 10:55 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
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2016-07-08 10:06 [PATCH v5 0/2] MIPS non-executable stack support Paul Burton
2016-07-08 10:06 ` Paul Burton
2016-07-08 10:06 ` [PATCH v5 1/2] MIPS: use per-mm page to execute branch delay slot instructions Paul Burton
2016-07-08 10:06 ` Paul Burton
2016-07-08 10:06 ` [PATCH v5 2/2] MIPS: non-exec stack & heap when non-exec PT_GNU_STACK is present Paul Burton
2016-07-08 10:06 ` Paul Burton
2016-07-08 16:36 ` Maciej W. Rozycki
2016-07-08 16:36 ` Maciej W. Rozycki
[not found] ` <577FF4A1.5000200@imgtec.com>
2016-07-08 19:53 ` Maciej W. Rozycki
2016-07-08 19:53 ` Maciej W. Rozycki
2016-07-18 11:55 ` Matthew Fortune
2016-09-12 10:54 ` Maciej W. Rozycki
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