* [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h
@ 2016-06-29 11:38 Chris Wilson
2016-06-29 11:38 ` [PATCH igt 02/17] intel_chipset: Convert IS_MOBILE to intel_device_info Chris Wilson
` (16 more replies)
0 siblings, 17 replies; 21+ messages in thread
From: Chris Wilson @ 2016-06-29 11:38 UTC (permalink / raw)
To: intel-gfx
Several years ago we made the plan of only having one canonical source
for i915_pciids.h, the kernel and everyone importing their definitions
from that. For consistency, we style the intel_device_info after the
kernel, most notably using a generation mask and a per-codename bitfield.
This first step converts looking up the generation for a devid tree from
a massive if(devid)-chain to a (cached) table lookup.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/Makefile.sources | 3 +-
lib/drmtest.c | 2 +-
lib/i915_pciids.h | 132 +++++++++++++++++-
lib/intel_chipset.c | 31 -----
lib/intel_chipset.h | 116 +++++++---------
lib/intel_device_info.c | 288 ++++++++++++++++++++++++++++++++++++++
overlay/i915_pciids.h | 339 ---------------------------------------------
overlay/igfx.c | 2 +-
tools/intel_audio_dump.c | 12 +-
tools/intel_error_decode.c | 2 +-
tools/intel_reg.c | 21 +--
11 files changed, 476 insertions(+), 472 deletions(-)
create mode 100644 lib/intel_device_info.c
delete mode 100644 overlay/i915_pciids.h
diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 3589e26..8cad9d5 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -26,11 +26,12 @@ libintel_tools_la_SOURCES = \
instdone.h \
intel_batchbuffer.c \
intel_batchbuffer.h \
+ intel_chipset.c \
intel_chipset.h \
+ intel_device_info.c \
intel_os.c \
intel_io.h \
intel_mmio.c \
- intel_chipset.c \
intel_reg.h \
ioctl_wrappers.c \
ioctl_wrappers.h \
diff --git a/lib/drmtest.c b/lib/drmtest.c
index 884fe7c..62dd042 100644
--- a/lib/drmtest.c
+++ b/lib/drmtest.c
@@ -127,7 +127,7 @@ static bool has_known_intel_chipset(int fd)
if (ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp, sizeof(gp)))
return false;
- if (!IS_INTEL(devid))
+ if (!intel_gen(devid))
return false;
__drm_device_id = devid;
diff --git a/lib/i915_pciids.h b/lib/i915_pciids.h
index 8a10f5c..33466bf 100644
--- a/lib/i915_pciids.h
+++ b/lib/i915_pciids.h
@@ -191,8 +191,8 @@
INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
- INTEL_VGA_DEVICE(0x0A0E, info), /* ULT GT1 reserved */ \
- INTEL_VGA_DEVICE(0x0A1E, info), /* ULT GT2 reserved */ \
+ INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
+ INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
@@ -208,4 +208,132 @@
#define INTEL_VLV_D_IDS(info) \
INTEL_VGA_DEVICE(0x0155, info)
+#define INTEL_BDW_GT12M_IDS(info) \
+ INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
+ INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
+ INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
+ INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
+ INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
+ INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
+ INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
+ INTEL_VGA_DEVICE(0x161E, info) /* GT2 ULX */
+
+#define INTEL_BDW_GT12D_IDS(info) \
+ INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
+ INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \
+ INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
+ INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */
+
+#define INTEL_BDW_GT3M_IDS(info) \
+ INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
+ INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
+ INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \
+ INTEL_VGA_DEVICE(0x162E, info) /* ULX */
+
+#define INTEL_BDW_GT3D_IDS(info) \
+ INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
+ INTEL_VGA_DEVICE(0x162D, info) /* Workstation */
+
+#define INTEL_BDW_RSVDM_IDS(info) \
+ INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \
+ INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
+ INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \
+ INTEL_VGA_DEVICE(0x163E, info) /* ULX */
+
+#define INTEL_BDW_RSVDD_IDS(info) \
+ INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
+ INTEL_VGA_DEVICE(0x163D, info) /* Workstation */
+
+#define INTEL_BDW_M_IDS(info) \
+ INTEL_BDW_GT12M_IDS(info), \
+ INTEL_BDW_GT3M_IDS(info), \
+ INTEL_BDW_RSVDM_IDS(info)
+
+#define INTEL_BDW_D_IDS(info) \
+ INTEL_BDW_GT12D_IDS(info), \
+ INTEL_BDW_GT3D_IDS(info), \
+ INTEL_BDW_RSVDD_IDS(info)
+
+#define INTEL_CHV_IDS(info) \
+ INTEL_VGA_DEVICE(0x22b0, info), \
+ INTEL_VGA_DEVICE(0x22b1, info), \
+ INTEL_VGA_DEVICE(0x22b2, info), \
+ INTEL_VGA_DEVICE(0x22b3, info)
+
+#define INTEL_SKL_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
+ INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
+ INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \
+ INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
+ INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
+
+#define INTEL_SKL_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
+ INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \
+ INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \
+ INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \
+ INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
+ INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
+ INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */
+
+#define INTEL_SKL_GT3_IDS(info) \
+ INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
+ INTEL_VGA_DEVICE(0x192A, info) /* SRV GT3 */
+
+#define INTEL_SKL_GT4_IDS(info) \
+ INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
+ INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \
+ INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \
+ INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4 */
+
+#define INTEL_SKL_IDS(info) \
+ INTEL_SKL_GT1_IDS(info), \
+ INTEL_SKL_GT2_IDS(info), \
+ INTEL_SKL_GT3_IDS(info), \
+ INTEL_SKL_GT4_IDS(info)
+
+#define INTEL_BXT_IDS(info) \
+ INTEL_VGA_DEVICE(0x0A84, info), \
+ INTEL_VGA_DEVICE(0x1A84, info), \
+ INTEL_VGA_DEVICE(0x1A85, info), \
+ INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
+ INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */
+
+#define INTEL_KBL_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
+ INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
+ INTEL_VGA_DEVICE(0x5917, info), /* DT GT1.5 */ \
+ INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
+ INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
+ INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
+ INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
+ INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
+ INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
+
+#define INTEL_KBL_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
+ INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
+ INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
+ INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \
+ INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
+ INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
+ INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
+
+#define INTEL_KBL_GT3_IDS(info) \
+ INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */
+
+#define INTEL_KBL_GT4_IDS(info) \
+ INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
+
+#define INTEL_KBL_IDS(info) \
+ INTEL_KBL_GT1_IDS(info), \
+ INTEL_KBL_GT2_IDS(info), \
+ INTEL_KBL_GT3_IDS(info), \
+ INTEL_KBL_GT4_IDS(info)
+
#endif /* _I915_PCIIDS_H */
diff --git a/lib/intel_chipset.c b/lib/intel_chipset.c
index 56746b0..777dfa7 100644
--- a/lib/intel_chipset.c
+++ b/lib/intel_chipset.c
@@ -141,37 +141,6 @@ intel_get_drm_devid(int fd)
}
/**
- * intel_gen:
- * @devid: pci device id
- *
- * Computes the Intel GFX generation for the give device id.
- *
- * Returns:
- * The GFX generation on successful lookup, -1 on failure.
- */
-int intel_gen(uint32_t devid)
-{
- if (IS_GEN2(devid))
- return 2;
- if (IS_GEN3(devid))
- return 3;
- if (IS_GEN4(devid))
- return 4;
- if (IS_GEN5(devid))
- return 5;
- if (IS_GEN6(devid))
- return 6;
- if (IS_GEN7(devid))
- return 7;
- if (IS_GEN8(devid))
- return 8;
- if (IS_GEN9(devid))
- return 9;
-
- return -1;
-}
-
-/**
* intel_check_pch:
*
* Detects the PCH chipset type of the running systems and fills in the results
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index e1e552c..69c878b 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -29,10 +29,44 @@
#define _INTEL_CHIPSET_H
#include <pciaccess.h>
+#include <stdbool.h>
struct pci_device *intel_get_pci_device(void);
uint32_t intel_get_drm_devid(int fd);
-int intel_gen(uint32_t devid);
+
+const struct intel_device_info {
+ unsigned gen;
+ bool is_mobile : 1;
+ bool is_whitney : 1;
+ bool is_almador : 1;
+ bool is_brookdale : 1;
+ bool is_montara : 1;
+ bool is_springdale : 1;
+ bool is_grantsdale : 1;
+ bool is_alviso : 1;
+ bool is_lakeport : 1;
+ bool is_calistoga : 1;
+ bool is_bearlake : 1;
+ bool is_pineview : 1;
+ bool is_broadwater : 1;
+ bool is_crestline : 1;
+ bool is_eaglelake : 1;
+ bool is_cantiga : 1;
+ bool is_ironlake : 1;
+ bool is_arrandale : 1;
+ bool is_sandybridge : 1;
+ bool is_ivybridge : 1;
+ bool is_valleyview : 1;
+ bool is_haswell : 1;
+ bool is_broadwell : 1;
+ bool is_cherryview : 1;
+ bool is_skylake : 1;
+ bool is_broxton : 1;
+ bool is_kabylake : 1;
+ const char *codename;
+} *intel_device_info(uint16_t devid) __attribute__((pure));
+
+unsigned intel_gen(uint16_t devid) __attribute__((pure));
extern enum pch_type intel_pch;
@@ -275,36 +309,6 @@ void intel_check_pch(void);
(devid) == PCI_CHIP_Q33_G || \
(devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
-#define IS_GEN2(devid) ((devid) == PCI_CHIP_I830_M || \
- (devid) == PCI_CHIP_845_G || \
- (devid) == PCI_CHIP_I854_G || \
- (devid) == PCI_CHIP_I855_GM || \
- (devid) == PCI_CHIP_I865_G)
-
-#define IS_GEN3(devid) (IS_945(devid) || IS_915(devid))
-
-#define IS_GEN4(devid) ((devid) == PCI_CHIP_I965_G || \
- (devid) == PCI_CHIP_I965_Q || \
- (devid) == PCI_CHIP_I965_G_1 || \
- (devid) == PCI_CHIP_I965_GM || \
- (devid) == PCI_CHIP_I965_GME || \
- (devid) == PCI_CHIP_I946_GZ || \
- IS_G4X(devid))
-
-#define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid))
-
-#define IS_GEN6(devid) ((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \
- (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
- (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
- (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
- (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
- (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
- (devid) == PCI_CHIP_SANDYBRIDGE_S)
-
-#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
- IS_HASWELL(devid) || \
- IS_VALLEYVIEW(devid))
-
#define IS_IVYBRIDGE(devid) ((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
(devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
(devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
@@ -396,9 +400,6 @@ void intel_check_pch(void);
(devid) == PCI_CHIP_CHERRYVIEW_2 || \
(devid) == PCI_CHIP_CHERRYVIEW_3)
-#define IS_GEN8(devid) (IS_BROADWELL(devid) || \
- IS_CHERRYVIEW(devid))
-
#define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \
(devid) == PCI_CHIP_SKYLAKE_ULX_GT1 || \
(devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \
@@ -462,10 +463,6 @@ void intel_check_pch(void);
(devid) == PCI_CHIP_BROXTON_3 || \
(devid) == PCI_CHIP_BROXTON_4)
-#define IS_GEN9(devid) (IS_KABYLAKE(devid) || \
- IS_SKYLAKE(devid) || \
- IS_BROXTON(devid))
-
#define IS_965(devid) (IS_GEN4(devid) || \
IS_GEN5(devid) || \
IS_GEN6(devid) || \
@@ -473,32 +470,6 @@ void intel_check_pch(void);
IS_GEN8(devid) || \
IS_GEN9(devid))
-#define IS_INTEL(devid) (IS_GEN2(devid) || \
- IS_GEN3(devid) || \
- IS_GEN4(devid) || \
- IS_GEN5(devid) || \
- IS_GEN6(devid) || \
- IS_GEN7(devid) || \
- IS_GEN8(devid) || \
- IS_GEN9(devid))
-
-#define HAS_PCH_SPLIT(devid) (IS_GEN5(devid) || \
- IS_GEN6(devid) || \
- IS_IVYBRIDGE(devid) || IS_HASWELL(devid) || \
- IS_BROADWELL(devid) || \
- IS_SKYLAKE(devid))
-
-#define HAS_BLT_RING(devid) (IS_GEN6(devid) || \
- IS_GEN7(devid) || \
- IS_GEN8(devid) || \
- IS_GEN9(devid))
-
-#define HAS_BSD_RING(devid) (IS_GEN5(devid) || \
- IS_GEN6(devid) || \
- IS_GEN7(devid) || \
- IS_GEN8(devid) || \
- IS_GEN9(devid))
-
#define IS_BROADWATER(devid) ((devid) == PCI_CHIP_I946_GZ || \
(devid) == PCI_CHIP_I965_G_1 || \
(devid) == PCI_CHIP_I965_Q || \
@@ -507,6 +478,21 @@ void intel_check_pch(void);
#define IS_CRESTLINE(devid) ((devid) == PCI_CHIP_I965_GM || \
(devid) == PCI_CHIP_I965_GME)
-#define HAS_VEBOX_RING(devid) (IS_HASWELL(devid))
+#define IS_GEN(devid, x) (intel_device_info(devid)->gen & (1u << ((x)-1)))
+#define AT_LEAST_GEN(devid, x) (intel_device_info(devid)->gen & -(1u << ((x)-1)))
+
+#define IS_GEN2(devid) IS_GEN(devid, 2)
+#define IS_GEN3(devid) IS_GEN(devid, 3)
+#define IS_GEN4(devid) IS_GEN(devid, 4)
+#define IS_GEN5(devid) IS_GEN(devid, 5)
+#define IS_GEN6(devid) IS_GEN(devid, 6)
+#define IS_GEN7(devid) IS_GEN(devid, 7)
+#define IS_GEN8(devid) IS_GEN(devid, 8)
+#define IS_GEN9(devid) IS_GEN(devid, 9)
+
+#define HAS_BSD_RING(devid) AT_LEAST_GEN(devid, 5)
+#define HAS_BLT_RING(devid) AT_LEAST_GEN(devid, 6)
+
+#define HAS_PCH_SPLIT(devid) AT_LEAST_GEN(devid, 5) /* XXX Valleyview? */
#endif /* _INTEL_CHIPSET_H */
diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
new file mode 100644
index 0000000..7e26406
--- /dev/null
+++ b/lib/intel_device_info.c
@@ -0,0 +1,288 @@
+#include "intel_chipset.h"
+#include "i915_pciids.h"
+
+#include <strings.h> /* ffs() */
+
+#define BIT(x) (1<<(x))
+
+static const struct intel_device_info intel_generic_info = {
+ .gen = 0,
+};
+
+static const struct intel_device_info intel_i81x_info = {
+ .gen = BIT(0),
+ .is_whitney = true,
+ .codename = "solano/whitney"
+};
+
+static const struct intel_device_info intel_i830_info = {
+ .gen = BIT(1),
+ .is_almador = true,
+ .codename = "almador"
+};
+static const struct intel_device_info intel_i845_info = {
+ .gen = BIT(1),
+ .is_brookdale = true,
+ .codename = "brookdale"
+};
+static const struct intel_device_info intel_i855_info = {
+ .gen = BIT(1),
+ .is_mobile = true,
+ .is_montara = true,
+ .codename = "montara"
+};
+static const struct intel_device_info intel_i865_info = {
+ .gen = BIT(1),
+ .is_springdale = true,
+ .codename = "spingdale"
+};
+
+static const struct intel_device_info intel_i915_info = {
+ .gen = BIT(2),
+ .is_grantsdale = true,
+ .codename = "grantsdale"
+};
+static const struct intel_device_info intel_i915m_info = {
+ .gen = BIT(2),
+ .is_mobile = true,
+ .is_alviso = true,
+ .codename = "alviso"
+};
+static const struct intel_device_info intel_i945_info = {
+ .gen = BIT(2),
+ .is_lakeport = true,
+ .codename = "lakeport"
+};
+static const struct intel_device_info intel_i945m_info = {
+ .gen = BIT(2),
+ .is_mobile = true,
+ .is_calistoga = true,
+ .codename = "calistoga"
+};
+
+static const struct intel_device_info intel_g33_info = {
+ .gen = BIT(2),
+ .is_bearlake = true,
+ .codename = "bearlake"
+};
+static const struct intel_device_info intel_pineview_info = {
+ .gen = BIT(2),
+ .is_mobile = true,
+ .is_pineview = true,
+ .codename = "pineview"
+};
+
+static const struct intel_device_info intel_i965_info = {
+ .gen = BIT(3),
+ .is_broadwater = true,
+ .codename = "broadwater"
+};
+
+static const struct intel_device_info intel_i965m_info = {
+ .gen = BIT(3),
+ .is_mobile = true,
+ .is_crestline = true,
+ .codename = "crestline"
+};
+
+static const struct intel_device_info intel_g45_info = {
+ .gen = BIT(3),
+ .is_eaglelake = true,
+ .codename = "aaglelake"
+};
+static const struct intel_device_info intel_gm45_info = {
+ .gen = BIT(3),
+ .is_mobile = true,
+ .is_cantiga = true,
+ .codename = "cantiga"
+};
+
+static const struct intel_device_info intel_ironlake_info = {
+ .gen = BIT(4),
+ .is_ironlake = true,
+ .codename = "ironlake"
+};
+static const struct intel_device_info intel_ironlake_m_info = {
+ .gen = BIT(4),
+ .is_mobile = true,
+ .is_arrandale = true,
+ .codename = "arrandale"
+};
+
+static const struct intel_device_info intel_sandybridge_info = {
+ .gen = BIT(5),
+ .is_sandybridge = true,
+ .codename = "sandybridge"
+};
+static const struct intel_device_info intel_sandybridge_m_info = {
+ .gen = BIT(5),
+ .is_mobile = true,
+ .is_sandybridge = true,
+ .codename = "sandybridge"
+};
+
+static const struct intel_device_info intel_ivybridge_info = {
+ .gen = BIT(6),
+ .is_ivybridge = true,
+ .codename = "ivybridge"
+};
+static const struct intel_device_info intel_ivybridge_m_info = {
+ .gen = BIT(6),
+ .is_mobile = true,
+ .is_ivybridge = true,
+ .codename = "ivybridge"
+};
+
+static const struct intel_device_info intel_valleyview_info = {
+ .gen = BIT(6),
+ .is_valleyview = true,
+ .codename = "valleyview"
+};
+static const struct intel_device_info intel_valleyview_m_info = {
+ .gen = BIT(6),
+ .is_mobile = true,
+ .is_valleyview = true,
+ .codename = "valleyview"
+};
+
+static const struct intel_device_info intel_haswell_info = {
+ .gen = BIT(6),
+ .is_haswell = true,
+ .codename = "haswell"
+};
+static const struct intel_device_info intel_haswell_m_info = {
+ .gen = BIT(6),
+ .is_mobile = true,
+ .is_haswell = true,
+ .codename = "haswell"
+};
+
+static const struct intel_device_info intel_broadwell_info = {
+ .gen = BIT(7),
+ .is_broadwell = true,
+ .codename = "broadwell"
+};
+static const struct intel_device_info intel_broadwell_m_info = {
+ .gen = BIT(7),
+ .is_mobile = true,
+ .is_broadwell = true,
+ .codename = "broadwell"
+};
+
+static const struct intel_device_info intel_cherryview_info = {
+ .gen = BIT(7),
+ .is_cherryview = true,
+ .codename = "cherryview"
+};
+
+static const struct intel_device_info intel_skylake_info = {
+ .gen = BIT(8),
+ .is_skylake = true,
+ .codename = "skylake"
+};
+
+static const struct intel_device_info intel_broxton_info = {
+ .gen = BIT(8),
+ .is_broxton = true,
+ .codename = "broxton"
+};
+
+static const struct intel_device_info intel_kabylake_info = {
+ .gen = BIT(8),
+ .is_kabylake = true,
+ .codename = "kabylake"
+};
+
+static const struct pci_id_match intel_device_match[] = {
+ INTEL_I830_IDS(&intel_i830_info),
+ INTEL_I845G_IDS(&intel_i845_info),
+ INTEL_I85X_IDS(&intel_i855_info),
+ INTEL_I865G_IDS(&intel_i865_info),
+
+ INTEL_I915G_IDS(&intel_i915_info),
+ INTEL_I915GM_IDS(&intel_i915m_info),
+ INTEL_I945G_IDS(&intel_i945_info),
+ INTEL_I945GM_IDS(&intel_i945m_info),
+
+ INTEL_G33_IDS(&intel_g33_info),
+ INTEL_PINEVIEW_IDS(&intel_pineview_info),
+
+ INTEL_I965G_IDS(&intel_i965_info),
+ INTEL_I965GM_IDS(&intel_i965_info),
+
+ INTEL_G45_IDS(&intel_g45_info),
+ INTEL_GM45_IDS(&intel_gm45_info),
+
+ INTEL_IRONLAKE_D_IDS(&intel_ironlake_info),
+ INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
+
+ INTEL_SNB_D_IDS(&intel_sandybridge_info),
+ INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
+
+ INTEL_IVB_D_IDS(&intel_ivybridge_info),
+ INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
+
+ INTEL_HSW_D_IDS(&intel_haswell_info),
+ INTEL_HSW_M_IDS(&intel_haswell_m_info),
+
+ INTEL_VLV_D_IDS(&intel_valleyview_info),
+ INTEL_VLV_M_IDS(&intel_valleyview_m_info),
+
+ INTEL_BDW_D_IDS(&intel_broadwell_info),
+ INTEL_BDW_M_IDS(&intel_broadwell_m_info),
+
+ INTEL_CHV_IDS(&intel_cherryview_info),
+
+ INTEL_SKL_IDS(&intel_skylake_info),
+
+ INTEL_BXT_IDS(&intel_broxton_info),
+
+ INTEL_KBL_IDS(&intel_kabylake_info),
+
+ INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info),
+};
+
+/**
+ * intel_device_info:
+ * @devid: pci device id
+ *
+ * Looks up the Intel GFX device info for the given device id.
+ *
+ * Returns:
+ * The associated intel_device_info
+ */
+const struct intel_device_info *intel_device_info(uint16_t devid)
+{
+ static const struct intel_device_info *cache = &intel_generic_info;
+ static uint16_t cached_devid;
+ int i;
+
+ if (cached_devid == devid)
+ goto out;
+
+ /* XXX Presort table and bsearch! */
+ for (i = 0; intel_device_match[i].device_id != PCI_MATCH_ANY; i++) {
+ if (devid == intel_device_match[i].device_id)
+ break;
+ }
+
+ cached_devid = devid;
+ cache = (void *)intel_device_match[i].match_data;
+
+out:
+ return cache;
+}
+
+/**
+ * intel_gen:
+ * @devid: pci device id
+ *
+ * Computes the Intel GFX generation for the given device id.
+ *
+ * Returns:
+ * The GFX generation on successful lookup, 0 on failure.
+ */
+unsigned intel_gen(uint16_t devid)
+{
+ return ffs(intel_device_info(devid)->gen);
+}
diff --git a/overlay/i915_pciids.h b/overlay/i915_pciids.h
deleted file mode 100644
index 33466bf..0000000
--- a/overlay/i915_pciids.h
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
- * Copyright 2013 Intel Corporation
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-#ifndef _I915_PCIIDS_H
-#define _I915_PCIIDS_H
-
-/*
- * A pci_device_id struct {
- * __u32 vendor, device;
- * __u32 subvendor, subdevice;
- * __u32 class, class_mask;
- * kernel_ulong_t driver_data;
- * };
- * Don't use C99 here because "class" is reserved and we want to
- * give userspace flexibility.
- */
-#define INTEL_VGA_DEVICE(id, info) { \
- 0x8086, id, \
- ~0, ~0, \
- 0x030000, 0xff0000, \
- (unsigned long) info }
-
-#define INTEL_QUANTA_VGA_DEVICE(info) { \
- 0x8086, 0x16a, \
- 0x152d, 0x8990, \
- 0x030000, 0xff0000, \
- (unsigned long) info }
-
-#define INTEL_I830_IDS(info) \
- INTEL_VGA_DEVICE(0x3577, info)
-
-#define INTEL_I845G_IDS(info) \
- INTEL_VGA_DEVICE(0x2562, info)
-
-#define INTEL_I85X_IDS(info) \
- INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \
- INTEL_VGA_DEVICE(0x358e, info)
-
-#define INTEL_I865G_IDS(info) \
- INTEL_VGA_DEVICE(0x2572, info) /* I865_G */
-
-#define INTEL_I915G_IDS(info) \
- INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \
- INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */
-
-#define INTEL_I915GM_IDS(info) \
- INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */
-
-#define INTEL_I945G_IDS(info) \
- INTEL_VGA_DEVICE(0x2772, info) /* I945_G */
-
-#define INTEL_I945GM_IDS(info) \
- INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \
- INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */
-
-#define INTEL_I965G_IDS(info) \
- INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \
- INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \
- INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \
- INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */
-
-#define INTEL_G33_IDS(info) \
- INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \
- INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \
- INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */
-
-#define INTEL_I965GM_IDS(info) \
- INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \
- INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */
-
-#define INTEL_GM45_IDS(info) \
- INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */
-
-#define INTEL_G45_IDS(info) \
- INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \
- INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \
- INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \
- INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \
- INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
- INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */
-
-#define INTEL_PINEVIEW_IDS(info) \
- INTEL_VGA_DEVICE(0xa001, info), \
- INTEL_VGA_DEVICE(0xa011, info)
-
-#define INTEL_IRONLAKE_D_IDS(info) \
- INTEL_VGA_DEVICE(0x0042, info)
-
-#define INTEL_IRONLAKE_M_IDS(info) \
- INTEL_VGA_DEVICE(0x0046, info)
-
-#define INTEL_SNB_D_IDS(info) \
- INTEL_VGA_DEVICE(0x0102, info), \
- INTEL_VGA_DEVICE(0x0112, info), \
- INTEL_VGA_DEVICE(0x0122, info), \
- INTEL_VGA_DEVICE(0x010A, info)
-
-#define INTEL_SNB_M_IDS(info) \
- INTEL_VGA_DEVICE(0x0106, info), \
- INTEL_VGA_DEVICE(0x0116, info), \
- INTEL_VGA_DEVICE(0x0126, info)
-
-#define INTEL_IVB_M_IDS(info) \
- INTEL_VGA_DEVICE(0x0156, info), /* GT1 mobile */ \
- INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
-
-#define INTEL_IVB_D_IDS(info) \
- INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
- INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
- INTEL_VGA_DEVICE(0x015a, info), /* GT1 server */ \
- INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */
-
-#define INTEL_IVB_Q_IDS(info) \
- INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
-
-#define INTEL_HSW_D_IDS(info) \
- INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
- INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
- INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
- INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
- INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
- INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
- INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
- INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
- INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
- INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
- INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
- INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
- INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
- INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
- INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
- INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
- INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
- INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
- INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
- INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
- INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
- INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
- INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
- INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
- INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
- INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
- INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
- INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
- INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
- INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
- INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
- INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
- INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
- INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
- INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
- INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
- INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
- INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
- INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
- INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
- INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
- INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
- INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
- INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
- INTEL_VGA_DEVICE(0x0D2E, info) /* CRW GT3 reserved */ \
-
-#define INTEL_HSW_M_IDS(info) \
- INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
- INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
- INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
- INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
- INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
- INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
- INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
- INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
- INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
- INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
- INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
- INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
- INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
- INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
- INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */
-
-#define INTEL_VLV_M_IDS(info) \
- INTEL_VGA_DEVICE(0x0f30, info), \
- INTEL_VGA_DEVICE(0x0f31, info), \
- INTEL_VGA_DEVICE(0x0f32, info), \
- INTEL_VGA_DEVICE(0x0f33, info), \
- INTEL_VGA_DEVICE(0x0157, info)
-
-#define INTEL_VLV_D_IDS(info) \
- INTEL_VGA_DEVICE(0x0155, info)
-
-#define INTEL_BDW_GT12M_IDS(info) \
- INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
- INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
- INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
- INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
- INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
- INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
- INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
- INTEL_VGA_DEVICE(0x161E, info) /* GT2 ULX */
-
-#define INTEL_BDW_GT12D_IDS(info) \
- INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
- INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \
- INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
- INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */
-
-#define INTEL_BDW_GT3M_IDS(info) \
- INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
- INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
- INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \
- INTEL_VGA_DEVICE(0x162E, info) /* ULX */
-
-#define INTEL_BDW_GT3D_IDS(info) \
- INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
- INTEL_VGA_DEVICE(0x162D, info) /* Workstation */
-
-#define INTEL_BDW_RSVDM_IDS(info) \
- INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \
- INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
- INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \
- INTEL_VGA_DEVICE(0x163E, info) /* ULX */
-
-#define INTEL_BDW_RSVDD_IDS(info) \
- INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
- INTEL_VGA_DEVICE(0x163D, info) /* Workstation */
-
-#define INTEL_BDW_M_IDS(info) \
- INTEL_BDW_GT12M_IDS(info), \
- INTEL_BDW_GT3M_IDS(info), \
- INTEL_BDW_RSVDM_IDS(info)
-
-#define INTEL_BDW_D_IDS(info) \
- INTEL_BDW_GT12D_IDS(info), \
- INTEL_BDW_GT3D_IDS(info), \
- INTEL_BDW_RSVDD_IDS(info)
-
-#define INTEL_CHV_IDS(info) \
- INTEL_VGA_DEVICE(0x22b0, info), \
- INTEL_VGA_DEVICE(0x22b1, info), \
- INTEL_VGA_DEVICE(0x22b2, info), \
- INTEL_VGA_DEVICE(0x22b3, info)
-
-#define INTEL_SKL_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
- INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
- INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \
- INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
- INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
-
-#define INTEL_SKL_GT2_IDS(info) \
- INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
- INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \
- INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \
- INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \
- INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
- INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
- INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */
-
-#define INTEL_SKL_GT3_IDS(info) \
- INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
- INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
- INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
- INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
- INTEL_VGA_DEVICE(0x192A, info) /* SRV GT3 */
-
-#define INTEL_SKL_GT4_IDS(info) \
- INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
- INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \
- INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \
- INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4 */
-
-#define INTEL_SKL_IDS(info) \
- INTEL_SKL_GT1_IDS(info), \
- INTEL_SKL_GT2_IDS(info), \
- INTEL_SKL_GT3_IDS(info), \
- INTEL_SKL_GT4_IDS(info)
-
-#define INTEL_BXT_IDS(info) \
- INTEL_VGA_DEVICE(0x0A84, info), \
- INTEL_VGA_DEVICE(0x1A84, info), \
- INTEL_VGA_DEVICE(0x1A85, info), \
- INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
- INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */
-
-#define INTEL_KBL_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
- INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
- INTEL_VGA_DEVICE(0x5917, info), /* DT GT1.5 */ \
- INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
- INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
- INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
- INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
- INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
- INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
-
-#define INTEL_KBL_GT2_IDS(info) \
- INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
- INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
- INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
- INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \
- INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
- INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
- INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
-
-#define INTEL_KBL_GT3_IDS(info) \
- INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \
- INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
- INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */
-
-#define INTEL_KBL_GT4_IDS(info) \
- INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
-
-#define INTEL_KBL_IDS(info) \
- INTEL_KBL_GT1_IDS(info), \
- INTEL_KBL_GT2_IDS(info), \
- INTEL_KBL_GT3_IDS(info), \
- INTEL_KBL_GT4_IDS(info)
-
-#endif /* _I915_PCIIDS_H */
diff --git a/overlay/igfx.c b/overlay/igfx.c
index 604ae5f..fa046e7 100644
--- a/overlay/igfx.c
+++ b/overlay/igfx.c
@@ -29,7 +29,7 @@
#include <stdio.h>
#include "igfx.h"
-#include "i915_pciids.h"
+#include "../lib/i915_pciids.h"
static const struct igfx_info generic_info = {
.gen = -1,
diff --git a/tools/intel_audio_dump.c b/tools/intel_audio_dump.c
index aec4177..aacd52f 100644
--- a/tools/intel_audio_dump.c
+++ b/tools/intel_audio_dump.c
@@ -2476,31 +2476,21 @@ int main(int argc, char **argv)
else
intel_mmio_use_pci_bar(pci_dev);
+ printf("%s audio registers:\n\n", intel_device_info(devid)->codename);
if (IS_VALLEYVIEW(devid)) {
- printf("Valleyview audio registers:\n\n");
dump_ironlake();
} else if (IS_GEN9(devid)
|| IS_BROADWELL(devid) || IS_HASWELL(devid)) {
- printf("%s audio registers:\n\n",
- IS_BROXTON(devid) ? "Broxton" :
- (IS_KABYLAKE(devid) ? "Kabylake" :
- (IS_SKYLAKE(devid) ? "Skylake" :
- (IS_BROADWELL(devid) ? "Broadwell" : "Haswell"))));
dump_hsw_plus();
} else if (IS_GEN6(devid) || IS_GEN7(devid)
|| getenv("HAS_PCH_SPLIT")) {
- printf("%s audio registers:\n\n",
- IS_GEN6(devid) ? "SandyBridge" : "IvyBridge");
intel_check_pch();
dump_cpt();
} else if (IS_GEN5(devid)) {
- printf("Ironlake audio registers:\n\n");
dump_ironlake();
} else if (IS_G4X(devid)) {
- printf("G45 audio registers:\n\n");
dump_eaglelake();
} else if (IS_CHERRYVIEW(devid)) {
- printf("Braswell audio registers:\n\n");
dump_braswell();
}
diff --git a/tools/intel_error_decode.c b/tools/intel_error_decode.c
index 371aa42..7959fff 100644
--- a/tools/intel_error_decode.c
+++ b/tools/intel_error_decode.c
@@ -847,4 +847,4 @@ main(int argc, char *argv[])
return 0;
}
-/* vim: set ts=8 sw=8 tw=0 noet :*/
+/* vim: set ts=8 sw=8 tw=0 cino=:0,(0 noet :*/
diff --git a/tools/intel_reg.c b/tools/intel_reg.c
index 92be1ce..73fbd6d 100644
--- a/tools/intel_reg.c
+++ b/tools/intel_reg.c
@@ -657,26 +657,7 @@ static int intel_reg_help(struct config *config, int argc, char *argv[])
*/
static const char *get_codename(uint32_t devid)
{
- if (IS_GEN5(devid))
- return "ironlake";
- else if (IS_GEN6(devid))
- return "sandybridge";
- else if (IS_IVYBRIDGE(devid))
- return "ivybridge";
- else if (IS_HASWELL(devid))
- return "haswell";
- else if (IS_BROADWELL(devid))
- return "broadwell";
- else if (IS_SKYLAKE(devid))
- return "skylake";
- else if (IS_KABYLAKE(devid))
- return "kabylake";
- else if (IS_CHERRYVIEW(devid))
- return "cherryview";
- else if (IS_VALLEYVIEW(devid))
- return "valleyview";
-
- return NULL;
+ return intel_device_info(devid)->codename;
}
/*
--
2.8.1
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH igt 02/17] intel_chipset: Convert IS_MOBILE to intel_device_info
2016-06-29 11:38 [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h Chris Wilson
@ 2016-06-29 11:38 ` Chris Wilson
2016-06-29 11:38 ` [PATCH igt 03/17] intel_chipset: Convert IS_965 to use intel_gen() Chris Wilson
` (15 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chris Wilson @ 2016-06-29 11:38 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_chipset.h | 12 ++----------
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 69c878b..ce130ed 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -273,16 +273,6 @@ void intel_check_pch(void);
#endif /* __GTK_DOC_IGNORE__ */
-#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
- (devid) == PCI_CHIP_I915_GM || \
- (devid) == PCI_CHIP_I945_GM || \
- (devid) == PCI_CHIP_I945_GME || \
- (devid) == PCI_CHIP_I965_GM || \
- (devid) == PCI_CHIP_I965_GME || \
- (devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \
- (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
- (devid) == PCI_CHIP_IVYBRIDGE_M_GT2)
-
#define IS_G45(devid) ((devid) == PCI_CHIP_IGD_E_G || \
(devid) == PCI_CHIP_Q45_G || \
(devid) == PCI_CHIP_G45_G || \
@@ -490,6 +480,8 @@ void intel_check_pch(void);
#define IS_GEN8(devid) IS_GEN(devid, 8)
#define IS_GEN9(devid) IS_GEN(devid, 9)
+#define IS_MOBILE(devid) (intel_device_info(devid)->is_mobile)
+
#define HAS_BSD_RING(devid) AT_LEAST_GEN(devid, 5)
#define HAS_BLT_RING(devid) AT_LEAST_GEN(devid, 6)
--
2.8.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH igt 03/17] intel_chipset: Convert IS_965 to use intel_gen()
2016-06-29 11:38 [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h Chris Wilson
2016-06-29 11:38 ` [PATCH igt 02/17] intel_chipset: Convert IS_MOBILE to intel_device_info Chris Wilson
@ 2016-06-29 11:38 ` Chris Wilson
2016-06-29 11:38 ` [PATCH igt 04/17] intel_chipset: Convert IS_BROADWATER, IS_CRESTLINE to device info Chris Wilson
` (14 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chris Wilson @ 2016-06-29 11:38 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_chipset.h | 8 +-------
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index ce130ed..8f159ea 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -453,13 +453,6 @@ void intel_check_pch(void);
(devid) == PCI_CHIP_BROXTON_3 || \
(devid) == PCI_CHIP_BROXTON_4)
-#define IS_965(devid) (IS_GEN4(devid) || \
- IS_GEN5(devid) || \
- IS_GEN6(devid) || \
- IS_GEN7(devid) || \
- IS_GEN8(devid) || \
- IS_GEN9(devid))
-
#define IS_BROADWATER(devid) ((devid) == PCI_CHIP_I946_GZ || \
(devid) == PCI_CHIP_I965_G_1 || \
(devid) == PCI_CHIP_I965_Q || \
@@ -481,6 +474,7 @@ void intel_check_pch(void);
#define IS_GEN9(devid) IS_GEN(devid, 9)
#define IS_MOBILE(devid) (intel_device_info(devid)->is_mobile)
+#define IS_965(devid) AT_LEAST_GEN(devid, 4)
#define HAS_BSD_RING(devid) AT_LEAST_GEN(devid, 5)
#define HAS_BLT_RING(devid) AT_LEAST_GEN(devid, 6)
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH igt 04/17] intel_chipset: Convert IS_BROADWATER, IS_CRESTLINE to device info
2016-06-29 11:38 [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h Chris Wilson
2016-06-29 11:38 ` [PATCH igt 02/17] intel_chipset: Convert IS_MOBILE to intel_device_info Chris Wilson
2016-06-29 11:38 ` [PATCH igt 03/17] intel_chipset: Convert IS_965 to use intel_gen() Chris Wilson
@ 2016-06-29 11:38 ` Chris Wilson
2016-06-29 11:38 ` [PATCH igt 05/17] intel_chipset: Convert IS_BROXTON " Chris Wilson
` (13 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chris Wilson @ 2016-06-29 11:38 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_chipset.h | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 8f159ea..6f7f26d 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -453,13 +453,8 @@ void intel_check_pch(void);
(devid) == PCI_CHIP_BROXTON_3 || \
(devid) == PCI_CHIP_BROXTON_4)
-#define IS_BROADWATER(devid) ((devid) == PCI_CHIP_I946_GZ || \
- (devid) == PCI_CHIP_I965_G_1 || \
- (devid) == PCI_CHIP_I965_Q || \
- (devid) == PCI_CHIP_I965_G)
-
-#define IS_CRESTLINE(devid) ((devid) == PCI_CHIP_I965_GM || \
- (devid) == PCI_CHIP_I965_GME)
+#define IS_BROADWATER(devid) (intel_device_info(devid)->is_broadwater)
+#define IS_CRESTLINE(devid) (intel_device_info(devid)->is_crestline)
#define IS_GEN(devid, x) (intel_device_info(devid)->gen & (1u << ((x)-1)))
#define AT_LEAST_GEN(devid, x) (intel_device_info(devid)->gen & -(1u << ((x)-1)))
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH igt 05/17] intel_chipset: Convert IS_BROXTON to device info
2016-06-29 11:38 [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h Chris Wilson
` (2 preceding siblings ...)
2016-06-29 11:38 ` [PATCH igt 04/17] intel_chipset: Convert IS_BROADWATER, IS_CRESTLINE to device info Chris Wilson
@ 2016-06-29 11:38 ` Chris Wilson
2016-06-29 11:38 ` [PATCH igt 06/17] intel_chipset: Convert IS_SKYLAKE " Chris Wilson
` (12 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chris Wilson @ 2016-06-29 11:38 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_chipset.h | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 6f7f26d..37f8ed0 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -447,11 +447,7 @@ void intel_check_pch(void);
IS_SKL_GT3(devid) || \
IS_SKL_GT4(devid))
-#define IS_BROXTON(devid) ((devid) == PCI_CHIP_BROXTON_0 || \
- (devid) == PCI_CHIP_BROXTON_1 || \
- (devid) == PCI_CHIP_BROXTON_2 || \
- (devid) == PCI_CHIP_BROXTON_3 || \
- (devid) == PCI_CHIP_BROXTON_4)
+#define IS_BROXTON(devid) (intel_device_info(devid)->is_broxton)
#define IS_BROADWATER(devid) (intel_device_info(devid)->is_broadwater)
#define IS_CRESTLINE(devid) (intel_device_info(devid)->is_crestline)
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH igt 06/17] intel_chipset: Convert IS_SKYLAKE to device info
2016-06-29 11:38 [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h Chris Wilson
` (3 preceding siblings ...)
2016-06-29 11:38 ` [PATCH igt 05/17] intel_chipset: Convert IS_BROXTON " Chris Wilson
@ 2016-06-29 11:38 ` Chris Wilson
2016-06-29 11:38 ` [PATCH igt 07/17] intel_chipset: Convert IS_CHERRYVIEW " Chris Wilson
` (11 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chris Wilson @ 2016-06-29 11:38 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_chipset.h | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 37f8ed0..146c650 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -442,11 +442,7 @@ void intel_check_pch(void);
IS_KBL_GT3(devid) || \
IS_KBL_GT4(devid))
-#define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \
- IS_SKL_GT2(devid) || \
- IS_SKL_GT3(devid) || \
- IS_SKL_GT4(devid))
-
+#define IS_SKYLAKE(devid) (intel_device_info(devid)->is_skylake)
#define IS_BROXTON(devid) (intel_device_info(devid)->is_broxton)
#define IS_BROADWATER(devid) (intel_device_info(devid)->is_broadwater)
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH igt 07/17] intel_chipset: Convert IS_CHERRYVIEW to device info
2016-06-29 11:38 [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h Chris Wilson
` (4 preceding siblings ...)
2016-06-29 11:38 ` [PATCH igt 06/17] intel_chipset: Convert IS_SKYLAKE " Chris Wilson
@ 2016-06-29 11:38 ` Chris Wilson
2016-06-29 11:38 ` [PATCH igt 08/17] intel_chipset: Convert IS_BROADWELL " Chris Wilson
` (10 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chris Wilson @ 2016-06-29 11:38 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_chipset.h | 12 ++----------
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 146c650..c4f64dc 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -385,11 +385,6 @@ void intel_check_pch(void);
(((devid) & 0x000f) == BDW_WORKSTATION) ? 1 : \
(((devid) & 0x000f) == BDW_ULX) ? 1 : 0)
-#define IS_CHERRYVIEW(devid) ((devid) == PCI_CHIP_CHERRYVIEW_0 || \
- (devid) == PCI_CHIP_CHERRYVIEW_1 || \
- (devid) == PCI_CHIP_CHERRYVIEW_2 || \
- (devid) == PCI_CHIP_CHERRYVIEW_3)
-
#define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \
(devid) == PCI_CHIP_SKYLAKE_ULX_GT1 || \
(devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \
@@ -437,11 +432,8 @@ void intel_check_pch(void);
#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4)
-#define IS_KABYLAKE(devid) (IS_KBL_GT1(devid) || \
- IS_KBL_GT2(devid) || \
- IS_KBL_GT3(devid) || \
- IS_KBL_GT4(devid))
-
+#define IS_CHERRYVIEW(devid) (intel_device_info(devid)->is_cherryview)
+#define IS_KABYLAKE(devid) (intel_device_info(devid)->is_kabylake)
#define IS_SKYLAKE(devid) (intel_device_info(devid)->is_skylake)
#define IS_BROXTON(devid) (intel_device_info(devid)->is_broxton)
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH igt 08/17] intel_chipset: Convert IS_BROADWELL to device info
2016-06-29 11:38 [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h Chris Wilson
` (5 preceding siblings ...)
2016-06-29 11:38 ` [PATCH igt 07/17] intel_chipset: Convert IS_CHERRYVIEW " Chris Wilson
@ 2016-06-29 11:38 ` Chris Wilson
2016-06-29 11:38 ` [PATCH igt 09/17] intel_chipset: Convert IS_HASWELL " Chris Wilson
` (9 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chris Wilson @ 2016-06-29 11:38 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_chipset.h | 10 +---------
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index c4f64dc..b56457a 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -376,15 +376,6 @@ void intel_check_pch(void);
IS_HSW_GT2(devid) || \
IS_HSW_GT3(devid))
-#define IS_BROADWELL(devid) ((((devid) & 0xff00) != 0x1600) ? 0 : \
- ((((devid) & 0x00f0) >> 4) > 3) ? 0 : \
- (((devid) & 0x000f) == BDW_SPARE) ? 1 : \
- (((devid) & 0x000f) == BDW_ULT) ? 1 : \
- (((devid) & 0x000f) == BDW_HALO) ? 1 : \
- (((devid) & 0x000f) == BDW_SERVER) ? 1 : \
- (((devid) & 0x000f) == BDW_WORKSTATION) ? 1 : \
- (((devid) & 0x000f) == BDW_ULX) ? 1 : 0)
-
#define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \
(devid) == PCI_CHIP_SKYLAKE_ULX_GT1 || \
(devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \
@@ -432,6 +423,7 @@ void intel_check_pch(void);
#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4)
+#define IS_BROADWELL(devid) (intel_device_info(devid)->is_broadwell)
#define IS_CHERRYVIEW(devid) (intel_device_info(devid)->is_cherryview)
#define IS_KABYLAKE(devid) (intel_device_info(devid)->is_kabylake)
#define IS_SKYLAKE(devid) (intel_device_info(devid)->is_skylake)
--
2.8.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH igt 09/17] intel_chipset: Convert IS_HASWELL to device info
2016-06-29 11:38 [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h Chris Wilson
` (6 preceding siblings ...)
2016-06-29 11:38 ` [PATCH igt 08/17] intel_chipset: Convert IS_BROADWELL " Chris Wilson
@ 2016-06-29 11:38 ` Chris Wilson
2016-06-29 11:39 ` [PATCH igt 10/17] intel_chipset: Convert IS_VALLEYVIEW " Chris Wilson
` (8 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chris Wilson @ 2016-06-29 11:38 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_chipset.h | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index b56457a..162216e 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -372,10 +372,6 @@ void intel_check_pch(void);
(devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
(devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
-#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
- IS_HSW_GT2(devid) || \
- IS_HSW_GT3(devid))
-
#define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \
(devid) == PCI_CHIP_SKYLAKE_ULX_GT1 || \
(devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \
@@ -423,6 +419,7 @@ void intel_check_pch(void);
#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4)
+#define IS_HASWELL(devid) (intel_device_info(devid)->is_haswell)
#define IS_BROADWELL(devid) (intel_device_info(devid)->is_broadwell)
#define IS_CHERRYVIEW(devid) (intel_device_info(devid)->is_cherryview)
#define IS_KABYLAKE(devid) (intel_device_info(devid)->is_kabylake)
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH igt 10/17] intel_chipset: Convert IS_VALLEYVIEW to device info
2016-06-29 11:38 [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h Chris Wilson
` (7 preceding siblings ...)
2016-06-29 11:38 ` [PATCH igt 09/17] intel_chipset: Convert IS_HASWELL " Chris Wilson
@ 2016-06-29 11:39 ` Chris Wilson
2016-06-29 11:39 ` [PATCH igt 11/17] intel_chipset: Convert IS_IRONALKE " Chris Wilson
` (7 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chris Wilson @ 2016-06-29 11:39 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_chipset.h | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 162216e..1c167f0 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -306,11 +306,6 @@ void intel_check_pch(void);
(devid) == PCI_CHIP_IVYBRIDGE_S || \
(devid) == PCI_CHIP_IVYBRIDGE_S_GT2)
-#define IS_VALLEYVIEW(devid) ((devid) == PCI_CHIP_VALLEYVIEW_PO || \
- (devid) == PCI_CHIP_VALLEYVIEW_1 || \
- (devid) == PCI_CHIP_VALLEYVIEW_2 || \
- (devid) == PCI_CHIP_VALLEYVIEW_3)
-
#define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \
(devid) == PCI_CHIP_HASWELL_M_GT1 || \
(devid) == PCI_CHIP_HASWELL_S_GT1 || \
@@ -419,6 +414,7 @@ void intel_check_pch(void);
#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4)
+#define IS_VALLEYVIEW(devid) (intel_device_info(devid)->is_valleyview)
#define IS_HASWELL(devid) (intel_device_info(devid)->is_haswell)
#define IS_BROADWELL(devid) (intel_device_info(devid)->is_broadwell)
#define IS_CHERRYVIEW(devid) (intel_device_info(devid)->is_cherryview)
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH igt 11/17] intel_chipset: Convert IS_IRONALKE to device info
2016-06-29 11:38 [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h Chris Wilson
` (8 preceding siblings ...)
2016-06-29 11:39 ` [PATCH igt 10/17] intel_chipset: Convert IS_VALLEYVIEW " Chris Wilson
@ 2016-06-29 11:39 ` Chris Wilson
2016-06-29 11:39 ` [PATCH igt 12/17] intel_chipset: Convert IS_IRONLAKE " Chris Wilson
` (6 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chris Wilson @ 2016-06-29 11:39 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_chipset.h | 8 +-------
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 1c167f0..f516d8e 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -299,13 +299,6 @@ void intel_check_pch(void);
(devid) == PCI_CHIP_Q33_G || \
(devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
-#define IS_IVYBRIDGE(devid) ((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
- (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
- (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
- (devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \
- (devid) == PCI_CHIP_IVYBRIDGE_S || \
- (devid) == PCI_CHIP_IVYBRIDGE_S_GT2)
-
#define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \
(devid) == PCI_CHIP_HASWELL_M_GT1 || \
(devid) == PCI_CHIP_HASWELL_S_GT1 || \
@@ -414,6 +407,7 @@ void intel_check_pch(void);
#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4)
+#define IS_IVYBRIDGE(devid) (intel_device_info(devid)->is_ivybridge)
#define IS_VALLEYVIEW(devid) (intel_device_info(devid)->is_valleyview)
#define IS_HASWELL(devid) (intel_device_info(devid)->is_haswell)
#define IS_BROADWELL(devid) (intel_device_info(devid)->is_broadwell)
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH igt 12/17] intel_chipset: Convert IS_IRONLAKE to device info
2016-06-29 11:38 [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h Chris Wilson
` (9 preceding siblings ...)
2016-06-29 11:39 ` [PATCH igt 11/17] intel_chipset: Convert IS_IRONALKE " Chris Wilson
@ 2016-06-29 11:39 ` Chris Wilson
2016-06-29 11:39 ` [PATCH igt 13/17] intel_chipset: Convert IS_PINEVIEW " Chris Wilson
` (5 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chris Wilson @ 2016-06-29 11:39 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_chipset.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index f516d8e..4f532a9 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -280,9 +280,6 @@ void intel_check_pch(void);
#define IS_GM45(devid) ((devid) == PCI_CHIP_GM45_GM)
#define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
-#define IS_ILD(devid) ((devid) == PCI_CHIP_ILD_G)
-#define IS_ILM(devid) ((devid) == PCI_CHIP_ILM_G)
-
#define IS_915(devid) ((devid) == PCI_CHIP_I915_G || \
(devid) == PCI_CHIP_E7221_G || \
(devid) == PCI_CHIP_I915_GM)
@@ -407,6 +404,8 @@ void intel_check_pch(void);
#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4)
+#define IS_IRONLAKE(devid) (intel_device_info(devid)->is_ironlake)
+#define IS_ARRANDALE(devid) (intel_device_info(devid)->is_arrandale)
#define IS_IVYBRIDGE(devid) (intel_device_info(devid)->is_ivybridge)
#define IS_VALLEYVIEW(devid) (intel_device_info(devid)->is_valleyview)
#define IS_HASWELL(devid) (intel_device_info(devid)->is_haswell)
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH igt 13/17] intel_chipset: Convert IS_PINEVIEW to device info
2016-06-29 11:38 [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h Chris Wilson
` (10 preceding siblings ...)
2016-06-29 11:39 ` [PATCH igt 12/17] intel_chipset: Convert IS_IRONLAKE " Chris Wilson
@ 2016-06-29 11:39 ` Chris Wilson
2016-06-29 11:39 ` [PATCH igt 14/17] intel_chipset: Convert IS_915, IS_945 " Chris Wilson
` (4 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chris Wilson @ 2016-06-29 11:39 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_chipset.h | 12 ++++--------
tools/intel_reg_decode.c | 4 ++--
tools/intel_watermark.c | 2 +-
3 files changed, 7 insertions(+), 11 deletions(-)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 4f532a9..a40a857 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -111,10 +111,6 @@ void intel_check_pch(void);
#define PCI_CHIP_IGD_GM 0xA011
#define PCI_CHIP_IGD_G 0xA001
-#define IS_IGDGM(devid) ((devid) == PCI_CHIP_IGD_GM)
-#define IS_IGDG(devid) ((devid) == PCI_CHIP_IGD_G)
-#define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid))
-
#define PCI_CHIP_I965_G 0x29A2
#define PCI_CHIP_I965_Q 0x2992
#define PCI_CHIP_I965_G_1 0x2982
@@ -292,10 +288,6 @@ void intel_check_pch(void);
(devid) == PCI_CHIP_I945_GME || \
IS_G33(devid))
-#define IS_G33(devid) ((devid) == PCI_CHIP_G33_G || \
- (devid) == PCI_CHIP_Q33_G || \
- (devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
-
#define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \
(devid) == PCI_CHIP_HASWELL_M_GT1 || \
(devid) == PCI_CHIP_HASWELL_S_GT1 || \
@@ -404,6 +396,10 @@ void intel_check_pch(void);
#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4)
+#define IS_PINEVIEW(devid) (intel_device_info(devid)->is_pineview)
+#define IS_G33(devid) (intel_device_info(devid)->is_bearlake || \
+ intel_device_info(devid)->is_pineview)
+
#define IS_IRONLAKE(devid) (intel_device_info(devid)->is_ironlake)
#define IS_ARRANDALE(devid) (intel_device_info(devid)->is_arrandale)
#define IS_IVYBRIDGE(devid) (intel_device_info(devid)->is_ivybridge)
diff --git a/tools/intel_reg_decode.c b/tools/intel_reg_decode.c
index 2536554..71f3ead 100644
--- a/tools/intel_reg_decode.c
+++ b/tools/intel_reg_decode.c
@@ -392,7 +392,7 @@ DEBUGSTRING(i830_debug_vgacntrl)
DEBUGSTRING(i830_debug_fp)
{
- if (IS_IGD(devid)) {
+ if (IS_PINEVIEW(devid)) {
snprintf(result, len, "n = %d, m1 = %d, m2 = %d",
ffs((val & FP_N_IGD_DIV_MASK) >>
FP_N_DIV_SHIFT) - 1,
@@ -496,7 +496,7 @@ DEBUGSTRING(i830_debug_dpll)
}
#endif
} else {
- if (IS_IGD(devid)) {
+ if (IS_PINEVIEW(devid)) {
p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
} else {
diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
index 133c058..68bd8ec 100644
--- a/tools/intel_watermark.c
+++ b/tools/intel_watermark.c
@@ -909,7 +909,7 @@ int main(int argc, char *argv[])
g4x_wm_dump();
} else if (IS_GEN4(devid)) {
gen4_wm_dump();
- } else if (IS_IGD(devid)) {
+ } else if (IS_PINEVIEW(devid)) {
pnv_wm_dump();
} else if (IS_GEN3(devid)) {
gen3_wm_dump();
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH igt 14/17] intel_chipset: Convert IS_915, IS_945 to device info
2016-06-29 11:38 [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h Chris Wilson
` (11 preceding siblings ...)
2016-06-29 11:39 ` [PATCH igt 13/17] intel_chipset: Convert IS_PINEVIEW " Chris Wilson
@ 2016-06-29 11:39 ` Chris Wilson
2016-06-29 11:39 ` [PATCH igt 15/17] intel_chipset: Convert IS_G4X " Chris Wilson
` (3 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chris Wilson @ 2016-06-29 11:39 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_chipset.h | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index a40a857..9806f2f 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -276,18 +276,6 @@ void intel_check_pch(void);
#define IS_GM45(devid) ((devid) == PCI_CHIP_GM45_GM)
#define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
-#define IS_915(devid) ((devid) == PCI_CHIP_I915_G || \
- (devid) == PCI_CHIP_E7221_G || \
- (devid) == PCI_CHIP_I915_GM)
-
-#define IS_945GM(devid) ((devid) == PCI_CHIP_I945_GM || \
- (devid) == PCI_CHIP_I945_GME)
-
-#define IS_945(devid) ((devid) == PCI_CHIP_I945_G || \
- (devid) == PCI_CHIP_I945_GM || \
- (devid) == PCI_CHIP_I945_GME || \
- IS_G33(devid))
-
#define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \
(devid) == PCI_CHIP_HASWELL_M_GT1 || \
(devid) == PCI_CHIP_HASWELL_S_GT1 || \
@@ -396,6 +384,18 @@ void intel_check_pch(void);
#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4)
+#define IS_915G(devid) (intel_device_info(devid)->is_grantsdale)
+#define IS_915GM(devid) (intel_device_info(devid)->is_alviso)
+
+#define IS_915(devid) (IS_915G(devid) || IS_915GM(devid))
+
+#define IS_945G(devid) (intel_device_info(devid)->is_lakeport)
+#define IS_945GM(devid) (intel_device_info(devid)->is_calistoga)
+
+#define IS_945(devid) (IS_945G(devid) || \
+ IS_945GM(devid) || \
+ IS_G33(devid))
+
#define IS_PINEVIEW(devid) (intel_device_info(devid)->is_pineview)
#define IS_G33(devid) (intel_device_info(devid)->is_bearlake || \
intel_device_info(devid)->is_pineview)
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH igt 15/17] intel_chipset: Convert IS_G4X to device info
2016-06-29 11:38 [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h Chris Wilson
` (12 preceding siblings ...)
2016-06-29 11:39 ` [PATCH igt 14/17] intel_chipset: Convert IS_915, IS_945 " Chris Wilson
@ 2016-06-29 11:39 ` Chris Wilson
2016-06-29 11:39 ` [PATCH igt 16/17] intel_chipset: Replace lookup of GT size with computation Chris Wilson
` (2 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chris Wilson @ 2016-06-29 11:39 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_chipset.h | 17 +++++++----------
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 9806f2f..e3e97ff 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -269,13 +269,6 @@ void intel_check_pch(void);
#endif /* __GTK_DOC_IGNORE__ */
-#define IS_G45(devid) ((devid) == PCI_CHIP_IGD_E_G || \
- (devid) == PCI_CHIP_Q45_G || \
- (devid) == PCI_CHIP_G45_G || \
- (devid) == PCI_CHIP_G41_G)
-#define IS_GM45(devid) ((devid) == PCI_CHIP_GM45_GM)
-#define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
-
#define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \
(devid) == PCI_CHIP_HASWELL_M_GT1 || \
(devid) == PCI_CHIP_HASWELL_S_GT1 || \
@@ -400,6 +393,13 @@ void intel_check_pch(void);
#define IS_G33(devid) (intel_device_info(devid)->is_bearlake || \
intel_device_info(devid)->is_pineview)
+#define IS_BROADWATER(devid) (intel_device_info(devid)->is_broadwater)
+#define IS_CRESTLINE(devid) (intel_device_info(devid)->is_crestline)
+
+#define IS_GM45(devid) (intel_device_info(devid)->is_cantiga)
+#define IS_G45(devid) (intel_device_info(devid)->is_eaglelake)
+#define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
+
#define IS_IRONLAKE(devid) (intel_device_info(devid)->is_ironlake)
#define IS_ARRANDALE(devid) (intel_device_info(devid)->is_arrandale)
#define IS_IVYBRIDGE(devid) (intel_device_info(devid)->is_ivybridge)
@@ -411,9 +411,6 @@ void intel_check_pch(void);
#define IS_SKYLAKE(devid) (intel_device_info(devid)->is_skylake)
#define IS_BROXTON(devid) (intel_device_info(devid)->is_broxton)
-#define IS_BROADWATER(devid) (intel_device_info(devid)->is_broadwater)
-#define IS_CRESTLINE(devid) (intel_device_info(devid)->is_crestline)
-
#define IS_GEN(devid, x) (intel_device_info(devid)->gen & (1u << ((x)-1)))
#define AT_LEAST_GEN(devid, x) (intel_device_info(devid)->gen & -(1u << ((x)-1)))
--
2.8.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH igt 16/17] intel_chipset: Replace lookup of GT size with computation
2016-06-29 11:38 [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h Chris Wilson
` (13 preceding siblings ...)
2016-06-29 11:39 ` [PATCH igt 15/17] intel_chipset: Convert IS_G4X " Chris Wilson
@ 2016-06-29 11:39 ` Chris Wilson
2016-06-29 11:39 ` [PATCH igt 17/17] intel_chipset: Remove unused PCI_CHIP ids Chris Wilson
2016-07-13 12:40 ` [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h Daniel Vetter
16 siblings, 0 replies; 21+ messages in thread
From: Chris Wilson @ 2016-06-29 11:39 UTC (permalink / raw)
To: intel-gfx
Instead of a large if-chain for matching devid to GT, we can just
compute it directly from the encoded devid.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
debugger/eudb.c | 14 +++---
lib/intel_chipset.h | 109 +---------------------------------------------
lib/intel_device_info.c | 23 ++++++++++
tools/intel_l3_parity.c | 15 +++----
tools/intel_reg_checker.c | 19 ++++----
5 files changed, 46 insertions(+), 134 deletions(-)
diff --git a/debugger/eudb.c b/debugger/eudb.c
index 47d5d92..866d4b5 100644
--- a/debugger/eudb.c
+++ b/debugger/eudb.c
@@ -351,16 +351,14 @@ die(int reason) {
static int
identify_device(int devid) {
- switch(devid) {
- case PCI_CHIP_SANDYBRIDGE_GT1:
- case PCI_CHIP_SANDYBRIDGE_M_GT1:
- case PCI_CHIP_SANDYBRIDGE_S:
+ if (!IS_SANDYBRIDGE(devid))
+ return -ENODEV;
+
+ switch (intel_gt(devid)) {
+ case 0:
eu_info = >1;
break;
- case PCI_CHIP_SANDYBRIDGE_GT2:
- case PCI_CHIP_SANDYBRIDGE_GT2_PLUS:
- case PCI_CHIP_SANDYBRIDGE_M_GT2:
- case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS:
+ case 1:
eu_info = >2;
break;
default:
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index e3e97ff..4234361 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -67,6 +67,7 @@ const struct intel_device_info {
} *intel_device_info(uint16_t devid) __attribute__((pure));
unsigned intel_gen(uint16_t devid) __attribute__((pure));
+unsigned intel_gt(uint16_t devid) __attribute__((pure));
extern enum pch_type intel_pch;
@@ -269,114 +270,6 @@ void intel_check_pch(void);
#endif /* __GTK_DOC_IGNORE__ */
-#define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \
- (devid) == PCI_CHIP_HASWELL_M_GT1 || \
- (devid) == PCI_CHIP_HASWELL_S_GT1 || \
- (devid) == PCI_CHIP_HASWELL_B_GT1 || \
- (devid) == PCI_CHIP_HASWELL_E_GT1 || \
- (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
- (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
- (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
- (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
- (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
- (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
- (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
- (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
- (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
- (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
- (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
- (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
- (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
- (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
- (devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
-#define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \
- (devid) == PCI_CHIP_HASWELL_M_GT2 || \
- (devid) == PCI_CHIP_HASWELL_S_GT2 || \
- (devid) == PCI_CHIP_HASWELL_B_GT2 || \
- (devid) == PCI_CHIP_HASWELL_E_GT2 || \
- (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
- (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
- (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
- (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
- (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
- (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
- (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
- (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
- (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
- (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
- (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
- (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
- (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
- (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
- (devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
-#define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \
- (devid) == PCI_CHIP_HASWELL_M_GT3 || \
- (devid) == PCI_CHIP_HASWELL_S_GT3 || \
- (devid) == PCI_CHIP_HASWELL_B_GT3 || \
- (devid) == PCI_CHIP_HASWELL_E_GT3 || \
- (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
- (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
- (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
- (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \
- (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \
- (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
- (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
- (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
- (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \
- (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \
- (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
- (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
- (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \
- (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
- (devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
-
-#define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \
- (devid) == PCI_CHIP_SKYLAKE_ULX_GT1 || \
- (devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \
- (devid) == PCI_CHIP_SKYLAKE_HALO_GT1 || \
- (devid) == PCI_CHIP_SKYLAKE_SRV_GT1)
-
-#define IS_SKL_GT2(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT2 || \
- (devid) == PCI_CHIP_SKYLAKE_ULT_GT2F || \
- (devid) == PCI_CHIP_SKYLAKE_ULX_GT2 || \
- (devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \
- (devid) == PCI_CHIP_SKYLAKE_HALO_GT2 || \
- (devid) == PCI_CHIP_SKYLAKE_SRV_GT2 || \
- (devid) == PCI_CHIP_SKYLAKE_WKS_GT2)
-
-#define IS_SKL_GT3(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT3 || \
- (devid) == PCI_CHIP_SKYLAKE_HALO_GT3 || \
- (devid) == PCI_CHIP_SKYLAKE_SRV_GT3)
-
-#define IS_SKL_GT4(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT4 || \
- (devid) == PCI_CHIP_SKYLAKE_HALO_GT4 || \
- (devid) == PCI_CHIP_SKYLAKE_WKS_GT4 || \
- (devid) == PCI_CHIP_SKYLAKE_SRV_GT4)
-
-#define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5|| \
- (devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5|| \
- (devid) == PCI_CHIP_KABYLAKE_DT_GT1_5|| \
- (devid) == PCI_CHIP_KABYLAKE_ULT_GT1|| \
- (devid) == PCI_CHIP_KABYLAKE_ULX_GT1|| \
- (devid) == PCI_CHIP_KABYLAKE_DT_GT1|| \
- (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_0|| \
- (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_1|| \
- (devid) == PCI_CHIP_KABYLAKE_SRV_GT1)
-
-#define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2|| \
- (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F|| \
- (devid) == PCI_CHIP_KABYLAKE_ULX_GT2|| \
- (devid) == PCI_CHIP_KABYLAKE_DT_GT2|| \
- (devid) == PCI_CHIP_KABYLAKE_HALO_GT2|| \
- (devid) == PCI_CHIP_KABYLAKE_SRV_GT2|| \
- (devid) == PCI_CHIP_KABYLAKE_WKS_GT2)
-
-#define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0|| \
- (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1|| \
- (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_2)
-
-#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4)
-
#define IS_915G(devid) (intel_device_info(devid)->is_grantsdale)
#define IS_915GM(devid) (intel_device_info(devid)->is_alviso)
diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
index 7e26406..419f9f6 100644
--- a/lib/intel_device_info.c
+++ b/lib/intel_device_info.c
@@ -286,3 +286,26 @@ unsigned intel_gen(uint16_t devid)
{
return ffs(intel_device_info(devid)->gen);
}
+
+/**
+ * intel_gt:
+ * @devid: pci device id
+ *
+ * Computes the Intel GFX GT size for the given device id.
+ *
+ * Returns:
+ * The GT size.
+ */
+unsigned intel_gt(uint16_t devid)
+{
+ unsigned mask = intel_gen(devid);
+
+ if (mask >= 8)
+ mask = 0xf;
+ else if (mask >= 6)
+ mask = 0x3;
+ else
+ mask = 0;
+
+ return (devid >> 4) & mask;
+}
diff --git a/tools/intel_l3_parity.c b/tools/intel_l3_parity.c
index 4810f7a..ecc0c61 100644
--- a/tools/intel_l3_parity.c
+++ b/tools/intel_l3_parity.c
@@ -51,14 +51,11 @@ static unsigned int devid;
/* L3 size is always a function of banks. The number of banks cannot be
* determined by number of slices however */
static inline int num_banks(void) {
- if (IS_HSW_GT3(devid))
- return 8; /* 4 per each slice */
- else if (IS_HSW_GT1(devid) ||
- devid == PCI_CHIP_IVYBRIDGE_GT1 ||
- devid == PCI_CHIP_IVYBRIDGE_M_GT1)
- return 2;
- else
- return 4;
+ switch (intel_gt(devid)) {
+ case 2: return 8;
+ case 1: return 4;
+ default: return 2;
+ }
}
#define NUM_SUBBANKS 8
#define BYTES_PER_BANK (128 << 10)
@@ -68,7 +65,7 @@ static inline int num_banks(void) {
#define MAX_ROW (1<<12)
#define MAX_BANKS_PER_SLICE 4
#define NUM_REGS (MAX_BANKS_PER_SLICE * NUM_SUBBANKS)
-#define MAX_SLICES (IS_HSW_GT3(devid) ? 2 : 1)
+#define MAX_SLICES (intel_gt(devid) > 1 ? 2 : 1)
#define REAL_MAX_SLICES 2
/* TODO support SLM config */
#define L3_SIZE ((MAX_ROW * 4) * NUM_SUBBANKS * num_banks())
diff --git a/tools/intel_reg_checker.c b/tools/intel_reg_checker.c
index 2d6da70..6bde63e 100644
--- a/tools/intel_reg_checker.c
+++ b/tools/intel_reg_checker.c
@@ -162,16 +162,17 @@ check_gt_mode(void)
if (gen == 6)
check_perf_bit(gt_mode, 8, "Full Rate Sampler Disable", false);
- /* For DevSmallGT, this bit must be set, which means disable
- * hashing.
- */
- if (devid == PCI_CHIP_SANDYBRIDGE_GT1 ||
- devid == PCI_CHIP_SANDYBRIDGE_M_GT1)
- check_bit(gt_mode, 6, "WIZ Hashing disable", true);
- else if (gen == 6)
- check_perf_bit(gt_mode, 6, "WIZ Hashing disable", false);
-
if (gen == 6) {
+ /* For DevSmallGT, this bit must be set, which means disable
+ * hashing.
+ */
+ if (intel_gt(devid) == 0)
+ check_bit(gt_mode, 6,
+ "WIZ Hashing disable", true);
+ else
+ check_perf_bit(gt_mode, 6,
+ "WIZ Hashing disable", false);
+
check_perf_bit(gt_mode, 5, "TD Four Row Dispatch Disable",
false);
check_perf_bit(gt_mode, 4, "Full Size URB Disable", false);
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH igt 17/17] intel_chipset: Remove unused PCI_CHIP ids
2016-06-29 11:38 [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h Chris Wilson
` (14 preceding siblings ...)
2016-06-29 11:39 ` [PATCH igt 16/17] intel_chipset: Replace lookup of GT size with computation Chris Wilson
@ 2016-06-29 11:39 ` Chris Wilson
2016-07-13 12:40 ` [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h Daniel Vetter
16 siblings, 0 replies; 21+ messages in thread
From: Chris Wilson @ 2016-06-29 11:39 UTC (permalink / raw)
To: intel-gfx
These are now taken from i915_pciids.h. However, some of the older ids
are still used explicitly for per-devid information, and so are not yet
removable.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/intel_chipset.h | 150 ----------------------------------------------------
1 file changed, 150 deletions(-)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 4234361..1716b83 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -105,13 +105,6 @@ void intel_check_pch(void);
#define PCI_CHIP_I945_GM 0x27A2
#define PCI_CHIP_I945_GME 0x27AE
-#define PCI_CHIP_Q35_G 0x29B2
-#define PCI_CHIP_G33_G 0x29C2
-#define PCI_CHIP_Q33_G 0x29D2
-
-#define PCI_CHIP_IGD_GM 0xA011
-#define PCI_CHIP_IGD_G 0xA001
-
#define PCI_CHIP_I965_G 0x29A2
#define PCI_CHIP_I965_Q 0x2992
#define PCI_CHIP_I965_G_1 0x2982
@@ -121,153 +114,10 @@ void intel_check_pch(void);
#define PCI_CHIP_GM45_GM 0x2A42
-#define PCI_CHIP_IGD_E_G 0x2E02
#define PCI_CHIP_Q45_G 0x2E12
#define PCI_CHIP_G45_G 0x2E22
#define PCI_CHIP_G41_G 0x2E32
-#define PCI_CHIP_ILD_G 0x0042
-#define PCI_CHIP_ILM_G 0x0046
-
-#define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* desktop */
-#define PCI_CHIP_SANDYBRIDGE_GT2 0x0112
-#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122
-#define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* mobile */
-#define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116
-#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
-#define PCI_CHIP_SANDYBRIDGE_S 0x010A /* server */
-
-#define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* desktop */
-#define PCI_CHIP_IVYBRIDGE_GT2 0x0162
-#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* mobile */
-#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
-#define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */
-#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a /* server */
-
-#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
-#define PCI_CHIP_HASWELL_GT2 0x0412
-#define PCI_CHIP_HASWELL_GT3 0x0422
-#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
-#define PCI_CHIP_HASWELL_M_GT2 0x0416
-#define PCI_CHIP_HASWELL_M_GT3 0x0426
-#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
-#define PCI_CHIP_HASWELL_S_GT2 0x041A
-#define PCI_CHIP_HASWELL_S_GT3 0x042A
-#define PCI_CHIP_HASWELL_B_GT1 0x040B /* Reserved */
-#define PCI_CHIP_HASWELL_B_GT2 0x041B
-#define PCI_CHIP_HASWELL_B_GT3 0x042B
-#define PCI_CHIP_HASWELL_E_GT1 0x040E /* Reserved */
-#define PCI_CHIP_HASWELL_E_GT2 0x041E
-#define PCI_CHIP_HASWELL_E_GT3 0x042E
-#define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
-#define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
-#define PCI_CHIP_HASWELL_SDV_GT3 0x0C22
-#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */
-#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
-#define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26
-#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
-#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
-#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A
-#define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0B /* Reserved */
-#define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1B
-#define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2B
-#define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E /* Reserved */
-#define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E
-#define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E
-#define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
-#define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
-#define PCI_CHIP_HASWELL_ULT_GT3 0x0A22
-#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
-#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
-#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26
-#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
-#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
-#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
-#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */
-#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B
-#define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B
-#define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */
-#define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E
-#define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E
-#define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
-#define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
-#define PCI_CHIP_HASWELL_CRW_GT3 0x0D22
-#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */
-#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
-#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26
-#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
-#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
-#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A
-#define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */
-#define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B
-#define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B
-#define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */
-#define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E
-#define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E
-#define BDW_SPARE 0x2
-#define BDW_ULT 0x6
-#define BDW_HALO 0xb
-#define BDW_SERVER 0xa
-#define BDW_WORKSTATION 0xd
-#define BDW_ULX 0xe
-
-#define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */
-#define PCI_CHIP_VALLEYVIEW_1 0x0f31
-#define PCI_CHIP_VALLEYVIEW_2 0x0f32
-#define PCI_CHIP_VALLEYVIEW_3 0x0f33
-
-#define PCI_CHIP_CHERRYVIEW_0 0x22b0
-#define PCI_CHIP_CHERRYVIEW_1 0x22b1
-#define PCI_CHIP_CHERRYVIEW_2 0x22b2
-#define PCI_CHIP_CHERRYVIEW_3 0x22b3
-
-#define PCI_CHIP_SKYLAKE_ULT_GT2 0x1916
-#define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906
-#define PCI_CHIP_SKYLAKE_ULT_GT3 0x1926
-#define PCI_CHIP_SKYLAKE_ULT_GT2F 0x1921
-#define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E
-#define PCI_CHIP_SKYLAKE_ULX_GT2 0x191E
-#define PCI_CHIP_SKYLAKE_DT_GT2 0x1912
-#define PCI_CHIP_SKYLAKE_DT_GT1 0x1902
-#define PCI_CHIP_SKYLAKE_DT_GT4 0x1932
-#define PCI_CHIP_SKYLAKE_HALO_GT2 0x191B
-#define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B
-#define PCI_CHIP_SKYLAKE_HALO_GT1 0x190B
-#define PCI_CHIP_SKYLAKE_HALO_GT4 0x193B
-#define PCI_CHIP_SKYLAKE_SRV_GT2 0x191A
-#define PCI_CHIP_SKYLAKE_SRV_GT3 0x192A
-#define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A
-#define PCI_CHIP_SKYLAKE_SRV_GT4 0x193A
-#define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D
-#define PCI_CHIP_SKYLAKE_WKS_GT4 0x193D
-
-#define PCI_CHIP_KABYLAKE_ULT_GT2 0x5916
-#define PCI_CHIP_KABYLAKE_ULT_GT1_5 0x5913
-#define PCI_CHIP_KABYLAKE_ULT_GT1 0x5906
-#define PCI_CHIP_KABYLAKE_ULT_GT3_0 0x5923
-#define PCI_CHIP_KABYLAKE_ULT_GT3_1 0x5926
-#define PCI_CHIP_KABYLAKE_ULT_GT3_2 0x5927
-#define PCI_CHIP_KABYLAKE_ULT_GT2F 0x5921
-#define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915
-#define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E
-#define PCI_CHIP_KABYLAKE_ULX_GT2 0x591E
-#define PCI_CHIP_KABYLAKE_DT_GT2 0x5912
-#define PCI_CHIP_KABYLAKE_DT_GT1_5 0x5917
-#define PCI_CHIP_KABYLAKE_DT_GT1 0x5902
-#define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B
-#define PCI_CHIP_KABYLAKE_HALO_GT1_0 0x5908
-#define PCI_CHIP_KABYLAKE_HALO_GT1_1 0x590B
-#define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B
-#define PCI_CHIP_KABYLAKE_SRV_GT2 0x591A
-#define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A
-#define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D
-
-#define PCI_CHIP_BROXTON_0 0x0A84
-#define PCI_CHIP_BROXTON_1 0x1A84
-#define PCI_CHIP_BROXTON_2 0x5A84
-#define PCI_CHIP_BROXTON_3 0x1A85
-#define PCI_CHIP_BROXTON_4 0x5A85
-
#endif /* __GTK_DOC_IGNORE__ */
#define IS_915G(devid) (intel_device_info(devid)->is_grantsdale)
--
2.8.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h
2016-06-29 11:38 [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h Chris Wilson
` (15 preceding siblings ...)
2016-06-29 11:39 ` [PATCH igt 17/17] intel_chipset: Remove unused PCI_CHIP ids Chris Wilson
@ 2016-07-13 12:40 ` Daniel Vetter
2016-07-13 13:34 ` Chris Wilson
16 siblings, 1 reply; 21+ messages in thread
From: Daniel Vetter @ 2016-07-13 12:40 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Wed, Jun 29, 2016 at 12:38:51PM +0100, Chris Wilson wrote:
> Several years ago we made the plan of only having one canonical source
> for i915_pciids.h, the kernel and everyone importing their definitions
> from that. For consistency, we style the intel_device_info after the
> kernel, most notably using a generation mask and a per-codename bitfield.
>
> This first step converts looking up the generation for a devid tree from
> a massive if(devid)-chain to a (cached) table lookup.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Should we extract the kernels list of chipset into intel_chipset.c too, to
make them 1:1 copies like with i915_pciids.h? With that this (entire
series) here has my ack. Without I'm not sold that much on the churn
really.
-Daniel
> ---
> lib/Makefile.sources | 3 +-
> lib/drmtest.c | 2 +-
> lib/i915_pciids.h | 132 +++++++++++++++++-
> lib/intel_chipset.c | 31 -----
> lib/intel_chipset.h | 116 +++++++---------
> lib/intel_device_info.c | 288 ++++++++++++++++++++++++++++++++++++++
> overlay/i915_pciids.h | 339 ---------------------------------------------
> overlay/igfx.c | 2 +-
> tools/intel_audio_dump.c | 12 +-
> tools/intel_error_decode.c | 2 +-
> tools/intel_reg.c | 21 +--
> 11 files changed, 476 insertions(+), 472 deletions(-)
> create mode 100644 lib/intel_device_info.c
> delete mode 100644 overlay/i915_pciids.h
>
> diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> index 3589e26..8cad9d5 100644
> --- a/lib/Makefile.sources
> +++ b/lib/Makefile.sources
> @@ -26,11 +26,12 @@ libintel_tools_la_SOURCES = \
> instdone.h \
> intel_batchbuffer.c \
> intel_batchbuffer.h \
> + intel_chipset.c \
> intel_chipset.h \
> + intel_device_info.c \
> intel_os.c \
> intel_io.h \
> intel_mmio.c \
> - intel_chipset.c \
> intel_reg.h \
> ioctl_wrappers.c \
> ioctl_wrappers.h \
> diff --git a/lib/drmtest.c b/lib/drmtest.c
> index 884fe7c..62dd042 100644
> --- a/lib/drmtest.c
> +++ b/lib/drmtest.c
> @@ -127,7 +127,7 @@ static bool has_known_intel_chipset(int fd)
> if (ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp, sizeof(gp)))
> return false;
>
> - if (!IS_INTEL(devid))
> + if (!intel_gen(devid))
> return false;
>
> __drm_device_id = devid;
> diff --git a/lib/i915_pciids.h b/lib/i915_pciids.h
> index 8a10f5c..33466bf 100644
> --- a/lib/i915_pciids.h
> +++ b/lib/i915_pciids.h
> @@ -191,8 +191,8 @@
> INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
> INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
> INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
> - INTEL_VGA_DEVICE(0x0A0E, info), /* ULT GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0A1E, info), /* ULT GT2 reserved */ \
> + INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
> + INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
> INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
> INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
> INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
> @@ -208,4 +208,132 @@
> #define INTEL_VLV_D_IDS(info) \
> INTEL_VGA_DEVICE(0x0155, info)
>
> +#define INTEL_BDW_GT12M_IDS(info) \
> + INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
> + INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
> + INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
> + INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
> + INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
> + INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
> + INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
> + INTEL_VGA_DEVICE(0x161E, info) /* GT2 ULX */
> +
> +#define INTEL_BDW_GT12D_IDS(info) \
> + INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
> + INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \
> + INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
> + INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */
> +
> +#define INTEL_BDW_GT3M_IDS(info) \
> + INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
> + INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
> + INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \
> + INTEL_VGA_DEVICE(0x162E, info) /* ULX */
> +
> +#define INTEL_BDW_GT3D_IDS(info) \
> + INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
> + INTEL_VGA_DEVICE(0x162D, info) /* Workstation */
> +
> +#define INTEL_BDW_RSVDM_IDS(info) \
> + INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \
> + INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
> + INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \
> + INTEL_VGA_DEVICE(0x163E, info) /* ULX */
> +
> +#define INTEL_BDW_RSVDD_IDS(info) \
> + INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
> + INTEL_VGA_DEVICE(0x163D, info) /* Workstation */
> +
> +#define INTEL_BDW_M_IDS(info) \
> + INTEL_BDW_GT12M_IDS(info), \
> + INTEL_BDW_GT3M_IDS(info), \
> + INTEL_BDW_RSVDM_IDS(info)
> +
> +#define INTEL_BDW_D_IDS(info) \
> + INTEL_BDW_GT12D_IDS(info), \
> + INTEL_BDW_GT3D_IDS(info), \
> + INTEL_BDW_RSVDD_IDS(info)
> +
> +#define INTEL_CHV_IDS(info) \
> + INTEL_VGA_DEVICE(0x22b0, info), \
> + INTEL_VGA_DEVICE(0x22b1, info), \
> + INTEL_VGA_DEVICE(0x22b2, info), \
> + INTEL_VGA_DEVICE(0x22b3, info)
> +
> +#define INTEL_SKL_GT1_IDS(info) \
> + INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
> + INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
> + INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \
> + INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
> + INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
> +
> +#define INTEL_SKL_GT2_IDS(info) \
> + INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
> + INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \
> + INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \
> + INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \
> + INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
> + INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
> + INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */
> +
> +#define INTEL_SKL_GT3_IDS(info) \
> + INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
> + INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
> + INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
> + INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
> + INTEL_VGA_DEVICE(0x192A, info) /* SRV GT3 */
> +
> +#define INTEL_SKL_GT4_IDS(info) \
> + INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
> + INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \
> + INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \
> + INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4 */
> +
> +#define INTEL_SKL_IDS(info) \
> + INTEL_SKL_GT1_IDS(info), \
> + INTEL_SKL_GT2_IDS(info), \
> + INTEL_SKL_GT3_IDS(info), \
> + INTEL_SKL_GT4_IDS(info)
> +
> +#define INTEL_BXT_IDS(info) \
> + INTEL_VGA_DEVICE(0x0A84, info), \
> + INTEL_VGA_DEVICE(0x1A84, info), \
> + INTEL_VGA_DEVICE(0x1A85, info), \
> + INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
> + INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */
> +
> +#define INTEL_KBL_GT1_IDS(info) \
> + INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
> + INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
> + INTEL_VGA_DEVICE(0x5917, info), /* DT GT1.5 */ \
> + INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
> + INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
> + INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
> + INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
> + INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
> + INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
> +
> +#define INTEL_KBL_GT2_IDS(info) \
> + INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
> + INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
> + INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
> + INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \
> + INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
> + INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
> + INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
> +
> +#define INTEL_KBL_GT3_IDS(info) \
> + INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \
> + INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
> + INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */
> +
> +#define INTEL_KBL_GT4_IDS(info) \
> + INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
> +
> +#define INTEL_KBL_IDS(info) \
> + INTEL_KBL_GT1_IDS(info), \
> + INTEL_KBL_GT2_IDS(info), \
> + INTEL_KBL_GT3_IDS(info), \
> + INTEL_KBL_GT4_IDS(info)
> +
> #endif /* _I915_PCIIDS_H */
> diff --git a/lib/intel_chipset.c b/lib/intel_chipset.c
> index 56746b0..777dfa7 100644
> --- a/lib/intel_chipset.c
> +++ b/lib/intel_chipset.c
> @@ -141,37 +141,6 @@ intel_get_drm_devid(int fd)
> }
>
> /**
> - * intel_gen:
> - * @devid: pci device id
> - *
> - * Computes the Intel GFX generation for the give device id.
> - *
> - * Returns:
> - * The GFX generation on successful lookup, -1 on failure.
> - */
> -int intel_gen(uint32_t devid)
> -{
> - if (IS_GEN2(devid))
> - return 2;
> - if (IS_GEN3(devid))
> - return 3;
> - if (IS_GEN4(devid))
> - return 4;
> - if (IS_GEN5(devid))
> - return 5;
> - if (IS_GEN6(devid))
> - return 6;
> - if (IS_GEN7(devid))
> - return 7;
> - if (IS_GEN8(devid))
> - return 8;
> - if (IS_GEN9(devid))
> - return 9;
> -
> - return -1;
> -}
> -
> -/**
> * intel_check_pch:
> *
> * Detects the PCH chipset type of the running systems and fills in the results
> diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
> index e1e552c..69c878b 100644
> --- a/lib/intel_chipset.h
> +++ b/lib/intel_chipset.h
> @@ -29,10 +29,44 @@
> #define _INTEL_CHIPSET_H
>
> #include <pciaccess.h>
> +#include <stdbool.h>
>
> struct pci_device *intel_get_pci_device(void);
> uint32_t intel_get_drm_devid(int fd);
> -int intel_gen(uint32_t devid);
> +
> +const struct intel_device_info {
> + unsigned gen;
> + bool is_mobile : 1;
> + bool is_whitney : 1;
> + bool is_almador : 1;
> + bool is_brookdale : 1;
> + bool is_montara : 1;
> + bool is_springdale : 1;
> + bool is_grantsdale : 1;
> + bool is_alviso : 1;
> + bool is_lakeport : 1;
> + bool is_calistoga : 1;
> + bool is_bearlake : 1;
> + bool is_pineview : 1;
> + bool is_broadwater : 1;
> + bool is_crestline : 1;
> + bool is_eaglelake : 1;
> + bool is_cantiga : 1;
> + bool is_ironlake : 1;
> + bool is_arrandale : 1;
> + bool is_sandybridge : 1;
> + bool is_ivybridge : 1;
> + bool is_valleyview : 1;
> + bool is_haswell : 1;
> + bool is_broadwell : 1;
> + bool is_cherryview : 1;
> + bool is_skylake : 1;
> + bool is_broxton : 1;
> + bool is_kabylake : 1;
> + const char *codename;
> +} *intel_device_info(uint16_t devid) __attribute__((pure));
> +
> +unsigned intel_gen(uint16_t devid) __attribute__((pure));
>
> extern enum pch_type intel_pch;
>
> @@ -275,36 +309,6 @@ void intel_check_pch(void);
> (devid) == PCI_CHIP_Q33_G || \
> (devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
>
> -#define IS_GEN2(devid) ((devid) == PCI_CHIP_I830_M || \
> - (devid) == PCI_CHIP_845_G || \
> - (devid) == PCI_CHIP_I854_G || \
> - (devid) == PCI_CHIP_I855_GM || \
> - (devid) == PCI_CHIP_I865_G)
> -
> -#define IS_GEN3(devid) (IS_945(devid) || IS_915(devid))
> -
> -#define IS_GEN4(devid) ((devid) == PCI_CHIP_I965_G || \
> - (devid) == PCI_CHIP_I965_Q || \
> - (devid) == PCI_CHIP_I965_G_1 || \
> - (devid) == PCI_CHIP_I965_GM || \
> - (devid) == PCI_CHIP_I965_GME || \
> - (devid) == PCI_CHIP_I946_GZ || \
> - IS_G4X(devid))
> -
> -#define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid))
> -
> -#define IS_GEN6(devid) ((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \
> - (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
> - (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
> - (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
> - (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
> - (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
> - (devid) == PCI_CHIP_SANDYBRIDGE_S)
> -
> -#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
> - IS_HASWELL(devid) || \
> - IS_VALLEYVIEW(devid))
> -
> #define IS_IVYBRIDGE(devid) ((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
> (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
> (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
> @@ -396,9 +400,6 @@ void intel_check_pch(void);
> (devid) == PCI_CHIP_CHERRYVIEW_2 || \
> (devid) == PCI_CHIP_CHERRYVIEW_3)
>
> -#define IS_GEN8(devid) (IS_BROADWELL(devid) || \
> - IS_CHERRYVIEW(devid))
> -
> #define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \
> (devid) == PCI_CHIP_SKYLAKE_ULX_GT1 || \
> (devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \
> @@ -462,10 +463,6 @@ void intel_check_pch(void);
> (devid) == PCI_CHIP_BROXTON_3 || \
> (devid) == PCI_CHIP_BROXTON_4)
>
> -#define IS_GEN9(devid) (IS_KABYLAKE(devid) || \
> - IS_SKYLAKE(devid) || \
> - IS_BROXTON(devid))
> -
> #define IS_965(devid) (IS_GEN4(devid) || \
> IS_GEN5(devid) || \
> IS_GEN6(devid) || \
> @@ -473,32 +470,6 @@ void intel_check_pch(void);
> IS_GEN8(devid) || \
> IS_GEN9(devid))
>
> -#define IS_INTEL(devid) (IS_GEN2(devid) || \
> - IS_GEN3(devid) || \
> - IS_GEN4(devid) || \
> - IS_GEN5(devid) || \
> - IS_GEN6(devid) || \
> - IS_GEN7(devid) || \
> - IS_GEN8(devid) || \
> - IS_GEN9(devid))
> -
> -#define HAS_PCH_SPLIT(devid) (IS_GEN5(devid) || \
> - IS_GEN6(devid) || \
> - IS_IVYBRIDGE(devid) || IS_HASWELL(devid) || \
> - IS_BROADWELL(devid) || \
> - IS_SKYLAKE(devid))
> -
> -#define HAS_BLT_RING(devid) (IS_GEN6(devid) || \
> - IS_GEN7(devid) || \
> - IS_GEN8(devid) || \
> - IS_GEN9(devid))
> -
> -#define HAS_BSD_RING(devid) (IS_GEN5(devid) || \
> - IS_GEN6(devid) || \
> - IS_GEN7(devid) || \
> - IS_GEN8(devid) || \
> - IS_GEN9(devid))
> -
> #define IS_BROADWATER(devid) ((devid) == PCI_CHIP_I946_GZ || \
> (devid) == PCI_CHIP_I965_G_1 || \
> (devid) == PCI_CHIP_I965_Q || \
> @@ -507,6 +478,21 @@ void intel_check_pch(void);
> #define IS_CRESTLINE(devid) ((devid) == PCI_CHIP_I965_GM || \
> (devid) == PCI_CHIP_I965_GME)
>
> -#define HAS_VEBOX_RING(devid) (IS_HASWELL(devid))
> +#define IS_GEN(devid, x) (intel_device_info(devid)->gen & (1u << ((x)-1)))
> +#define AT_LEAST_GEN(devid, x) (intel_device_info(devid)->gen & -(1u << ((x)-1)))
> +
> +#define IS_GEN2(devid) IS_GEN(devid, 2)
> +#define IS_GEN3(devid) IS_GEN(devid, 3)
> +#define IS_GEN4(devid) IS_GEN(devid, 4)
> +#define IS_GEN5(devid) IS_GEN(devid, 5)
> +#define IS_GEN6(devid) IS_GEN(devid, 6)
> +#define IS_GEN7(devid) IS_GEN(devid, 7)
> +#define IS_GEN8(devid) IS_GEN(devid, 8)
> +#define IS_GEN9(devid) IS_GEN(devid, 9)
> +
> +#define HAS_BSD_RING(devid) AT_LEAST_GEN(devid, 5)
> +#define HAS_BLT_RING(devid) AT_LEAST_GEN(devid, 6)
> +
> +#define HAS_PCH_SPLIT(devid) AT_LEAST_GEN(devid, 5) /* XXX Valleyview? */
>
> #endif /* _INTEL_CHIPSET_H */
> diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
> new file mode 100644
> index 0000000..7e26406
> --- /dev/null
> +++ b/lib/intel_device_info.c
> @@ -0,0 +1,288 @@
> +#include "intel_chipset.h"
> +#include "i915_pciids.h"
> +
> +#include <strings.h> /* ffs() */
> +
> +#define BIT(x) (1<<(x))
> +
> +static const struct intel_device_info intel_generic_info = {
> + .gen = 0,
> +};
> +
> +static const struct intel_device_info intel_i81x_info = {
> + .gen = BIT(0),
> + .is_whitney = true,
> + .codename = "solano/whitney"
> +};
> +
> +static const struct intel_device_info intel_i830_info = {
> + .gen = BIT(1),
> + .is_almador = true,
> + .codename = "almador"
> +};
> +static const struct intel_device_info intel_i845_info = {
> + .gen = BIT(1),
> + .is_brookdale = true,
> + .codename = "brookdale"
> +};
> +static const struct intel_device_info intel_i855_info = {
> + .gen = BIT(1),
> + .is_mobile = true,
> + .is_montara = true,
> + .codename = "montara"
> +};
> +static const struct intel_device_info intel_i865_info = {
> + .gen = BIT(1),
> + .is_springdale = true,
> + .codename = "spingdale"
> +};
> +
> +static const struct intel_device_info intel_i915_info = {
> + .gen = BIT(2),
> + .is_grantsdale = true,
> + .codename = "grantsdale"
> +};
> +static const struct intel_device_info intel_i915m_info = {
> + .gen = BIT(2),
> + .is_mobile = true,
> + .is_alviso = true,
> + .codename = "alviso"
> +};
> +static const struct intel_device_info intel_i945_info = {
> + .gen = BIT(2),
> + .is_lakeport = true,
> + .codename = "lakeport"
> +};
> +static const struct intel_device_info intel_i945m_info = {
> + .gen = BIT(2),
> + .is_mobile = true,
> + .is_calistoga = true,
> + .codename = "calistoga"
> +};
> +
> +static const struct intel_device_info intel_g33_info = {
> + .gen = BIT(2),
> + .is_bearlake = true,
> + .codename = "bearlake"
> +};
> +static const struct intel_device_info intel_pineview_info = {
> + .gen = BIT(2),
> + .is_mobile = true,
> + .is_pineview = true,
> + .codename = "pineview"
> +};
> +
> +static const struct intel_device_info intel_i965_info = {
> + .gen = BIT(3),
> + .is_broadwater = true,
> + .codename = "broadwater"
> +};
> +
> +static const struct intel_device_info intel_i965m_info = {
> + .gen = BIT(3),
> + .is_mobile = true,
> + .is_crestline = true,
> + .codename = "crestline"
> +};
> +
> +static const struct intel_device_info intel_g45_info = {
> + .gen = BIT(3),
> + .is_eaglelake = true,
> + .codename = "aaglelake"
> +};
> +static const struct intel_device_info intel_gm45_info = {
> + .gen = BIT(3),
> + .is_mobile = true,
> + .is_cantiga = true,
> + .codename = "cantiga"
> +};
> +
> +static const struct intel_device_info intel_ironlake_info = {
> + .gen = BIT(4),
> + .is_ironlake = true,
> + .codename = "ironlake"
> +};
> +static const struct intel_device_info intel_ironlake_m_info = {
> + .gen = BIT(4),
> + .is_mobile = true,
> + .is_arrandale = true,
> + .codename = "arrandale"
> +};
> +
> +static const struct intel_device_info intel_sandybridge_info = {
> + .gen = BIT(5),
> + .is_sandybridge = true,
> + .codename = "sandybridge"
> +};
> +static const struct intel_device_info intel_sandybridge_m_info = {
> + .gen = BIT(5),
> + .is_mobile = true,
> + .is_sandybridge = true,
> + .codename = "sandybridge"
> +};
> +
> +static const struct intel_device_info intel_ivybridge_info = {
> + .gen = BIT(6),
> + .is_ivybridge = true,
> + .codename = "ivybridge"
> +};
> +static const struct intel_device_info intel_ivybridge_m_info = {
> + .gen = BIT(6),
> + .is_mobile = true,
> + .is_ivybridge = true,
> + .codename = "ivybridge"
> +};
> +
> +static const struct intel_device_info intel_valleyview_info = {
> + .gen = BIT(6),
> + .is_valleyview = true,
> + .codename = "valleyview"
> +};
> +static const struct intel_device_info intel_valleyview_m_info = {
> + .gen = BIT(6),
> + .is_mobile = true,
> + .is_valleyview = true,
> + .codename = "valleyview"
> +};
> +
> +static const struct intel_device_info intel_haswell_info = {
> + .gen = BIT(6),
> + .is_haswell = true,
> + .codename = "haswell"
> +};
> +static const struct intel_device_info intel_haswell_m_info = {
> + .gen = BIT(6),
> + .is_mobile = true,
> + .is_haswell = true,
> + .codename = "haswell"
> +};
> +
> +static const struct intel_device_info intel_broadwell_info = {
> + .gen = BIT(7),
> + .is_broadwell = true,
> + .codename = "broadwell"
> +};
> +static const struct intel_device_info intel_broadwell_m_info = {
> + .gen = BIT(7),
> + .is_mobile = true,
> + .is_broadwell = true,
> + .codename = "broadwell"
> +};
> +
> +static const struct intel_device_info intel_cherryview_info = {
> + .gen = BIT(7),
> + .is_cherryview = true,
> + .codename = "cherryview"
> +};
> +
> +static const struct intel_device_info intel_skylake_info = {
> + .gen = BIT(8),
> + .is_skylake = true,
> + .codename = "skylake"
> +};
> +
> +static const struct intel_device_info intel_broxton_info = {
> + .gen = BIT(8),
> + .is_broxton = true,
> + .codename = "broxton"
> +};
> +
> +static const struct intel_device_info intel_kabylake_info = {
> + .gen = BIT(8),
> + .is_kabylake = true,
> + .codename = "kabylake"
> +};
> +
> +static const struct pci_id_match intel_device_match[] = {
> + INTEL_I830_IDS(&intel_i830_info),
> + INTEL_I845G_IDS(&intel_i845_info),
> + INTEL_I85X_IDS(&intel_i855_info),
> + INTEL_I865G_IDS(&intel_i865_info),
> +
> + INTEL_I915G_IDS(&intel_i915_info),
> + INTEL_I915GM_IDS(&intel_i915m_info),
> + INTEL_I945G_IDS(&intel_i945_info),
> + INTEL_I945GM_IDS(&intel_i945m_info),
> +
> + INTEL_G33_IDS(&intel_g33_info),
> + INTEL_PINEVIEW_IDS(&intel_pineview_info),
> +
> + INTEL_I965G_IDS(&intel_i965_info),
> + INTEL_I965GM_IDS(&intel_i965_info),
> +
> + INTEL_G45_IDS(&intel_g45_info),
> + INTEL_GM45_IDS(&intel_gm45_info),
> +
> + INTEL_IRONLAKE_D_IDS(&intel_ironlake_info),
> + INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
> +
> + INTEL_SNB_D_IDS(&intel_sandybridge_info),
> + INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
> +
> + INTEL_IVB_D_IDS(&intel_ivybridge_info),
> + INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
> +
> + INTEL_HSW_D_IDS(&intel_haswell_info),
> + INTEL_HSW_M_IDS(&intel_haswell_m_info),
> +
> + INTEL_VLV_D_IDS(&intel_valleyview_info),
> + INTEL_VLV_M_IDS(&intel_valleyview_m_info),
> +
> + INTEL_BDW_D_IDS(&intel_broadwell_info),
> + INTEL_BDW_M_IDS(&intel_broadwell_m_info),
> +
> + INTEL_CHV_IDS(&intel_cherryview_info),
> +
> + INTEL_SKL_IDS(&intel_skylake_info),
> +
> + INTEL_BXT_IDS(&intel_broxton_info),
> +
> + INTEL_KBL_IDS(&intel_kabylake_info),
> +
> + INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info),
> +};
> +
> +/**
> + * intel_device_info:
> + * @devid: pci device id
> + *
> + * Looks up the Intel GFX device info for the given device id.
> + *
> + * Returns:
> + * The associated intel_device_info
> + */
> +const struct intel_device_info *intel_device_info(uint16_t devid)
> +{
> + static const struct intel_device_info *cache = &intel_generic_info;
> + static uint16_t cached_devid;
> + int i;
> +
> + if (cached_devid == devid)
> + goto out;
> +
> + /* XXX Presort table and bsearch! */
> + for (i = 0; intel_device_match[i].device_id != PCI_MATCH_ANY; i++) {
> + if (devid == intel_device_match[i].device_id)
> + break;
> + }
> +
> + cached_devid = devid;
> + cache = (void *)intel_device_match[i].match_data;
> +
> +out:
> + return cache;
> +}
> +
> +/**
> + * intel_gen:
> + * @devid: pci device id
> + *
> + * Computes the Intel GFX generation for the given device id.
> + *
> + * Returns:
> + * The GFX generation on successful lookup, 0 on failure.
> + */
> +unsigned intel_gen(uint16_t devid)
> +{
> + return ffs(intel_device_info(devid)->gen);
> +}
> diff --git a/overlay/i915_pciids.h b/overlay/i915_pciids.h
> deleted file mode 100644
> index 33466bf..0000000
> --- a/overlay/i915_pciids.h
> +++ /dev/null
> @@ -1,339 +0,0 @@
> -/*
> - * Copyright 2013 Intel Corporation
> - * All Rights Reserved.
> - *
> - * Permission is hereby granted, free of charge, to any person obtaining a
> - * copy of this software and associated documentation files (the
> - * "Software"), to deal in the Software without restriction, including
> - * without limitation the rights to use, copy, modify, merge, publish,
> - * distribute, sub license, and/or sell copies of the Software, and to
> - * permit persons to whom the Software is furnished to do so, subject to
> - * the following conditions:
> - *
> - * The above copyright notice and this permission notice (including the
> - * next paragraph) shall be included in all copies or substantial portions
> - * of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> - * DEALINGS IN THE SOFTWARE.
> - */
> -#ifndef _I915_PCIIDS_H
> -#define _I915_PCIIDS_H
> -
> -/*
> - * A pci_device_id struct {
> - * __u32 vendor, device;
> - * __u32 subvendor, subdevice;
> - * __u32 class, class_mask;
> - * kernel_ulong_t driver_data;
> - * };
> - * Don't use C99 here because "class" is reserved and we want to
> - * give userspace flexibility.
> - */
> -#define INTEL_VGA_DEVICE(id, info) { \
> - 0x8086, id, \
> - ~0, ~0, \
> - 0x030000, 0xff0000, \
> - (unsigned long) info }
> -
> -#define INTEL_QUANTA_VGA_DEVICE(info) { \
> - 0x8086, 0x16a, \
> - 0x152d, 0x8990, \
> - 0x030000, 0xff0000, \
> - (unsigned long) info }
> -
> -#define INTEL_I830_IDS(info) \
> - INTEL_VGA_DEVICE(0x3577, info)
> -
> -#define INTEL_I845G_IDS(info) \
> - INTEL_VGA_DEVICE(0x2562, info)
> -
> -#define INTEL_I85X_IDS(info) \
> - INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \
> - INTEL_VGA_DEVICE(0x358e, info)
> -
> -#define INTEL_I865G_IDS(info) \
> - INTEL_VGA_DEVICE(0x2572, info) /* I865_G */
> -
> -#define INTEL_I915G_IDS(info) \
> - INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \
> - INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */
> -
> -#define INTEL_I915GM_IDS(info) \
> - INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */
> -
> -#define INTEL_I945G_IDS(info) \
> - INTEL_VGA_DEVICE(0x2772, info) /* I945_G */
> -
> -#define INTEL_I945GM_IDS(info) \
> - INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \
> - INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */
> -
> -#define INTEL_I965G_IDS(info) \
> - INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \
> - INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \
> - INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \
> - INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */
> -
> -#define INTEL_G33_IDS(info) \
> - INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \
> - INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \
> - INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */
> -
> -#define INTEL_I965GM_IDS(info) \
> - INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \
> - INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */
> -
> -#define INTEL_GM45_IDS(info) \
> - INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */
> -
> -#define INTEL_G45_IDS(info) \
> - INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \
> - INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \
> - INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \
> - INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \
> - INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
> - INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */
> -
> -#define INTEL_PINEVIEW_IDS(info) \
> - INTEL_VGA_DEVICE(0xa001, info), \
> - INTEL_VGA_DEVICE(0xa011, info)
> -
> -#define INTEL_IRONLAKE_D_IDS(info) \
> - INTEL_VGA_DEVICE(0x0042, info)
> -
> -#define INTEL_IRONLAKE_M_IDS(info) \
> - INTEL_VGA_DEVICE(0x0046, info)
> -
> -#define INTEL_SNB_D_IDS(info) \
> - INTEL_VGA_DEVICE(0x0102, info), \
> - INTEL_VGA_DEVICE(0x0112, info), \
> - INTEL_VGA_DEVICE(0x0122, info), \
> - INTEL_VGA_DEVICE(0x010A, info)
> -
> -#define INTEL_SNB_M_IDS(info) \
> - INTEL_VGA_DEVICE(0x0106, info), \
> - INTEL_VGA_DEVICE(0x0116, info), \
> - INTEL_VGA_DEVICE(0x0126, info)
> -
> -#define INTEL_IVB_M_IDS(info) \
> - INTEL_VGA_DEVICE(0x0156, info), /* GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
> -
> -#define INTEL_IVB_D_IDS(info) \
> - INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
> - INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
> - INTEL_VGA_DEVICE(0x015a, info), /* GT1 server */ \
> - INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */
> -
> -#define INTEL_IVB_Q_IDS(info) \
> - INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
> -
> -#define INTEL_HSW_D_IDS(info) \
> - INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
> - INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
> - INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
> - INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
> - INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
> - INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
> - INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
> - INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
> - INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
> - INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
> - INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
> - INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
> - INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
> - INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
> - INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
> - INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
> - INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
> - INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
> - INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
> - INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
> - INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
> - INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
> - INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
> - INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
> - INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0D2E, info) /* CRW GT3 reserved */ \
> -
> -#define INTEL_HSW_M_IDS(info) \
> - INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
> - INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
> - INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */
> -
> -#define INTEL_VLV_M_IDS(info) \
> - INTEL_VGA_DEVICE(0x0f30, info), \
> - INTEL_VGA_DEVICE(0x0f31, info), \
> - INTEL_VGA_DEVICE(0x0f32, info), \
> - INTEL_VGA_DEVICE(0x0f33, info), \
> - INTEL_VGA_DEVICE(0x0157, info)
> -
> -#define INTEL_VLV_D_IDS(info) \
> - INTEL_VGA_DEVICE(0x0155, info)
> -
> -#define INTEL_BDW_GT12M_IDS(info) \
> - INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
> - INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
> - INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
> - INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
> - INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
> - INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
> - INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
> - INTEL_VGA_DEVICE(0x161E, info) /* GT2 ULX */
> -
> -#define INTEL_BDW_GT12D_IDS(info) \
> - INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
> - INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \
> - INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
> - INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */
> -
> -#define INTEL_BDW_GT3M_IDS(info) \
> - INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
> - INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
> - INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \
> - INTEL_VGA_DEVICE(0x162E, info) /* ULX */
> -
> -#define INTEL_BDW_GT3D_IDS(info) \
> - INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
> - INTEL_VGA_DEVICE(0x162D, info) /* Workstation */
> -
> -#define INTEL_BDW_RSVDM_IDS(info) \
> - INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \
> - INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
> - INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \
> - INTEL_VGA_DEVICE(0x163E, info) /* ULX */
> -
> -#define INTEL_BDW_RSVDD_IDS(info) \
> - INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
> - INTEL_VGA_DEVICE(0x163D, info) /* Workstation */
> -
> -#define INTEL_BDW_M_IDS(info) \
> - INTEL_BDW_GT12M_IDS(info), \
> - INTEL_BDW_GT3M_IDS(info), \
> - INTEL_BDW_RSVDM_IDS(info)
> -
> -#define INTEL_BDW_D_IDS(info) \
> - INTEL_BDW_GT12D_IDS(info), \
> - INTEL_BDW_GT3D_IDS(info), \
> - INTEL_BDW_RSVDD_IDS(info)
> -
> -#define INTEL_CHV_IDS(info) \
> - INTEL_VGA_DEVICE(0x22b0, info), \
> - INTEL_VGA_DEVICE(0x22b1, info), \
> - INTEL_VGA_DEVICE(0x22b2, info), \
> - INTEL_VGA_DEVICE(0x22b3, info)
> -
> -#define INTEL_SKL_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
> - INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
> - INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \
> - INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
> - INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
> -
> -#define INTEL_SKL_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
> - INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \
> - INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \
> - INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \
> - INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
> - INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
> - INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */
> -
> -#define INTEL_SKL_GT3_IDS(info) \
> - INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
> - INTEL_VGA_DEVICE(0x192A, info) /* SRV GT3 */
> -
> -#define INTEL_SKL_GT4_IDS(info) \
> - INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
> - INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \
> - INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \
> - INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4 */
> -
> -#define INTEL_SKL_IDS(info) \
> - INTEL_SKL_GT1_IDS(info), \
> - INTEL_SKL_GT2_IDS(info), \
> - INTEL_SKL_GT3_IDS(info), \
> - INTEL_SKL_GT4_IDS(info)
> -
> -#define INTEL_BXT_IDS(info) \
> - INTEL_VGA_DEVICE(0x0A84, info), \
> - INTEL_VGA_DEVICE(0x1A84, info), \
> - INTEL_VGA_DEVICE(0x1A85, info), \
> - INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
> - INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */
> -
> -#define INTEL_KBL_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
> - INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
> - INTEL_VGA_DEVICE(0x5917, info), /* DT GT1.5 */ \
> - INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
> - INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
> - INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
> - INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
> - INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
> - INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
> -
> -#define INTEL_KBL_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
> - INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
> - INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
> - INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \
> - INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
> - INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
> - INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
> -
> -#define INTEL_KBL_GT3_IDS(info) \
> - INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */
> -
> -#define INTEL_KBL_GT4_IDS(info) \
> - INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
> -
> -#define INTEL_KBL_IDS(info) \
> - INTEL_KBL_GT1_IDS(info), \
> - INTEL_KBL_GT2_IDS(info), \
> - INTEL_KBL_GT3_IDS(info), \
> - INTEL_KBL_GT4_IDS(info)
> -
> -#endif /* _I915_PCIIDS_H */
> diff --git a/overlay/igfx.c b/overlay/igfx.c
> index 604ae5f..fa046e7 100644
> --- a/overlay/igfx.c
> +++ b/overlay/igfx.c
> @@ -29,7 +29,7 @@
> #include <stdio.h>
>
> #include "igfx.h"
> -#include "i915_pciids.h"
> +#include "../lib/i915_pciids.h"
>
> static const struct igfx_info generic_info = {
> .gen = -1,
> diff --git a/tools/intel_audio_dump.c b/tools/intel_audio_dump.c
> index aec4177..aacd52f 100644
> --- a/tools/intel_audio_dump.c
> +++ b/tools/intel_audio_dump.c
> @@ -2476,31 +2476,21 @@ int main(int argc, char **argv)
> else
> intel_mmio_use_pci_bar(pci_dev);
>
> + printf("%s audio registers:\n\n", intel_device_info(devid)->codename);
> if (IS_VALLEYVIEW(devid)) {
> - printf("Valleyview audio registers:\n\n");
> dump_ironlake();
> } else if (IS_GEN9(devid)
> || IS_BROADWELL(devid) || IS_HASWELL(devid)) {
> - printf("%s audio registers:\n\n",
> - IS_BROXTON(devid) ? "Broxton" :
> - (IS_KABYLAKE(devid) ? "Kabylake" :
> - (IS_SKYLAKE(devid) ? "Skylake" :
> - (IS_BROADWELL(devid) ? "Broadwell" : "Haswell"))));
> dump_hsw_plus();
> } else if (IS_GEN6(devid) || IS_GEN7(devid)
> || getenv("HAS_PCH_SPLIT")) {
> - printf("%s audio registers:\n\n",
> - IS_GEN6(devid) ? "SandyBridge" : "IvyBridge");
> intel_check_pch();
> dump_cpt();
> } else if (IS_GEN5(devid)) {
> - printf("Ironlake audio registers:\n\n");
> dump_ironlake();
> } else if (IS_G4X(devid)) {
> - printf("G45 audio registers:\n\n");
> dump_eaglelake();
> } else if (IS_CHERRYVIEW(devid)) {
> - printf("Braswell audio registers:\n\n");
> dump_braswell();
> }
>
> diff --git a/tools/intel_error_decode.c b/tools/intel_error_decode.c
> index 371aa42..7959fff 100644
> --- a/tools/intel_error_decode.c
> +++ b/tools/intel_error_decode.c
> @@ -847,4 +847,4 @@ main(int argc, char *argv[])
> return 0;
> }
>
> -/* vim: set ts=8 sw=8 tw=0 noet :*/
> +/* vim: set ts=8 sw=8 tw=0 cino=:0,(0 noet :*/
> diff --git a/tools/intel_reg.c b/tools/intel_reg.c
> index 92be1ce..73fbd6d 100644
> --- a/tools/intel_reg.c
> +++ b/tools/intel_reg.c
> @@ -657,26 +657,7 @@ static int intel_reg_help(struct config *config, int argc, char *argv[])
> */
> static const char *get_codename(uint32_t devid)
> {
> - if (IS_GEN5(devid))
> - return "ironlake";
> - else if (IS_GEN6(devid))
> - return "sandybridge";
> - else if (IS_IVYBRIDGE(devid))
> - return "ivybridge";
> - else if (IS_HASWELL(devid))
> - return "haswell";
> - else if (IS_BROADWELL(devid))
> - return "broadwell";
> - else if (IS_SKYLAKE(devid))
> - return "skylake";
> - else if (IS_KABYLAKE(devid))
> - return "kabylake";
> - else if (IS_CHERRYVIEW(devid))
> - return "cherryview";
> - else if (IS_VALLEYVIEW(devid))
> - return "valleyview";
> -
> - return NULL;
> + return intel_device_info(devid)->codename;
> }
>
> /*
> --
> 2.8.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h
2016-07-13 12:40 ` [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h Daniel Vetter
@ 2016-07-13 13:34 ` Chris Wilson
2016-07-14 10:31 ` Emil Velikov
0 siblings, 1 reply; 21+ messages in thread
From: Chris Wilson @ 2016-07-13 13:34 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Wed, Jul 13, 2016 at 02:40:49PM +0200, Daniel Vetter wrote:
> On Wed, Jun 29, 2016 at 12:38:51PM +0100, Chris Wilson wrote:
> > Several years ago we made the plan of only having one canonical source
> > for i915_pciids.h, the kernel and everyone importing their definitions
> > from that. For consistency, we style the intel_device_info after the
> > kernel, most notably using a generation mask and a per-codename bitfield.
> >
> > This first step converts looking up the generation for a devid tree from
> > a massive if(devid)-chain to a (cached) table lookup.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>
> Should we extract the kernels list of chipset into intel_chipset.c too, to
> make them 1:1 copies like with i915_pciids.h? With that this (entire
> series) here has my ack. Without I'm not sold that much on the churn
> really.
Hmm, next up would be libdrm which is almost a duplication of igt (and
can be massaged to be so). The next step would be feeding back the
commonality into the kernel, so that we really do have a single location
where we need to add new defines that can just percolate through.
So I think you mean to have the device-info stanzas shared...
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h
2016-07-13 13:34 ` Chris Wilson
@ 2016-07-14 10:31 ` Emil Velikov
2016-07-14 10:48 ` Chris Wilson
0 siblings, 1 reply; 21+ messages in thread
From: Emil Velikov @ 2016-07-14 10:31 UTC (permalink / raw)
To: Chris Wilson, Daniel Vetter, intel-gfx
On 13 July 2016 at 14:34, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> On Wed, Jul 13, 2016 at 02:40:49PM +0200, Daniel Vetter wrote:
>> On Wed, Jun 29, 2016 at 12:38:51PM +0100, Chris Wilson wrote:
>> > Several years ago we made the plan of only having one canonical source
>> > for i915_pciids.h, the kernel and everyone importing their definitions
>> > from that. For consistency, we style the intel_device_info after the
>> > kernel, most notably using a generation mask and a per-codename bitfield.
>> >
>> > This first step converts looking up the generation for a devid tree from
>> > a massive if(devid)-chain to a (cached) table lookup.
>> >
>> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>>
>> Should we extract the kernels list of chipset into intel_chipset.c too, to
>> make them 1:1 copies like with i915_pciids.h? With that this (entire
>> series) here has my ack. Without I'm not sold that much on the churn
>> really.
>
> Hmm, next up would be libdrm which is almost a duplication of igt (and
> can be massaged to be so). The next step would be feeding back the
> commonality into the kernel, so that we really do have a single location
> where we need to add new defines that can just percolate through.
>
> So I think you mean to have the device-info stanzas shared...
Fwiw I would suggest the same thing - have this this code in a single
place (be that kernel or libdrm) accessible by everyone. Otherwise
others (libva/beignet/mesa?) will copy it and it'll be a constant
chance to keep it in sync.
About the patch itself here are a few small nitpicks:
- intel_i81x_info seems to be unused
- s/aaglelake/eaglelake/
- capitalise the first letter of each codename ?
- Wikipedia lists Bearlake and Lakeport in both Gen3 and Gen4. Is it
busted or ...
- Ironlake, Clarkdale is listed as Ironlake, while Ironlake,
Arrandale as Arrandale. Guess those are the names people are more used
to ?
-Emil
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h
2016-07-14 10:31 ` Emil Velikov
@ 2016-07-14 10:48 ` Chris Wilson
0 siblings, 0 replies; 21+ messages in thread
From: Chris Wilson @ 2016-07-14 10:48 UTC (permalink / raw)
To: Emil Velikov; +Cc: intel-gfx
On Thu, Jul 14, 2016 at 11:31:08AM +0100, Emil Velikov wrote:
> On 13 July 2016 at 14:34, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > On Wed, Jul 13, 2016 at 02:40:49PM +0200, Daniel Vetter wrote:
> >> On Wed, Jun 29, 2016 at 12:38:51PM +0100, Chris Wilson wrote:
> >> > Several years ago we made the plan of only having one canonical source
> >> > for i915_pciids.h, the kernel and everyone importing their definitions
> >> > from that. For consistency, we style the intel_device_info after the
> >> > kernel, most notably using a generation mask and a per-codename bitfield.
> >> >
> >> > This first step converts looking up the generation for a devid tree from
> >> > a massive if(devid)-chain to a (cached) table lookup.
> >> >
> >> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> >>
> >> Should we extract the kernels list of chipset into intel_chipset.c too, to
> >> make them 1:1 copies like with i915_pciids.h? With that this (entire
> >> series) here has my ack. Without I'm not sold that much on the churn
> >> really.
> >
> > Hmm, next up would be libdrm which is almost a duplication of igt (and
> > can be massaged to be so). The next step would be feeding back the
> > commonality into the kernel, so that we really do have a single location
> > where we need to add new defines that can just percolate through.
> >
> > So I think you mean to have the device-info stanzas shared...
>
> Fwiw I would suggest the same thing - have this this code in a single
> place (be that kernel or libdrm) accessible by everyone. Otherwise
> others (libva/beignet/mesa?) will copy it and it'll be a constant
> chance to keep it in sync.
That's what we said many years ago! Still trying to get there.
> About the patch itself here are a few small nitpicks:
> - intel_i81x_info seems to be unused
One day! One day we will have that universal kms driver!
(It's required for the ddx at least, so I should hook up the ids as well
but really needs inclusion in i915_pciids.h first.)
> - s/aaglelake/eaglelake/
> - capitalise the first letter of each codename ?
Code already utilized codenames with the lowercase as filenames (for
register sets). I thought about making it call lowercase() - it was just
easier to match captilisation.
> - Wikipedia lists Bearlake and Lakeport in both Gen3 and Gen4. Is it
> busted or ...
Or a confusion between chipset and GPU.
From bspec,
915G, Grantsdale-G, GDG
915GM, Alviso, ALV
945G, Lakport, LPT,
945GM, Callistoga, CST
Bearlake-B is listed for gen3, but that chipset shared more in common
with the early gen4 GMCH.
> - Ironlake, Clarkdale is listed as Ironlake, while Ironlake,
> Arrandale as Arrandale. Guess those are the names people are more used
> to ?
It's just DevILK in the bspec, I'd forgotten Clarkdale but remembered
Arrandale as the mobile variant (and I wasn't actually sure if Clarkdale
was just the GPU-less chips). But since it is DevILK, we probably
should just use Ironlake, hmm or we list all the shortnames as well for
better cross-referencing.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2016-07-14 10:48 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-06-29 11:38 [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h Chris Wilson
2016-06-29 11:38 ` [PATCH igt 02/17] intel_chipset: Convert IS_MOBILE to intel_device_info Chris Wilson
2016-06-29 11:38 ` [PATCH igt 03/17] intel_chipset: Convert IS_965 to use intel_gen() Chris Wilson
2016-06-29 11:38 ` [PATCH igt 04/17] intel_chipset: Convert IS_BROADWATER, IS_CRESTLINE to device info Chris Wilson
2016-06-29 11:38 ` [PATCH igt 05/17] intel_chipset: Convert IS_BROXTON " Chris Wilson
2016-06-29 11:38 ` [PATCH igt 06/17] intel_chipset: Convert IS_SKYLAKE " Chris Wilson
2016-06-29 11:38 ` [PATCH igt 07/17] intel_chipset: Convert IS_CHERRYVIEW " Chris Wilson
2016-06-29 11:38 ` [PATCH igt 08/17] intel_chipset: Convert IS_BROADWELL " Chris Wilson
2016-06-29 11:38 ` [PATCH igt 09/17] intel_chipset: Convert IS_HASWELL " Chris Wilson
2016-06-29 11:39 ` [PATCH igt 10/17] intel_chipset: Convert IS_VALLEYVIEW " Chris Wilson
2016-06-29 11:39 ` [PATCH igt 11/17] intel_chipset: Convert IS_IRONALKE " Chris Wilson
2016-06-29 11:39 ` [PATCH igt 12/17] intel_chipset: Convert IS_IRONLAKE " Chris Wilson
2016-06-29 11:39 ` [PATCH igt 13/17] intel_chipset: Convert IS_PINEVIEW " Chris Wilson
2016-06-29 11:39 ` [PATCH igt 14/17] intel_chipset: Convert IS_915, IS_945 " Chris Wilson
2016-06-29 11:39 ` [PATCH igt 15/17] intel_chipset: Convert IS_G4X " Chris Wilson
2016-06-29 11:39 ` [PATCH igt 16/17] intel_chipset: Replace lookup of GT size with computation Chris Wilson
2016-06-29 11:39 ` [PATCH igt 17/17] intel_chipset: Remove unused PCI_CHIP ids Chris Wilson
2016-07-13 12:40 ` [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h Daniel Vetter
2016-07-13 13:34 ` Chris Wilson
2016-07-14 10:31 ` Emil Velikov
2016-07-14 10:48 ` Chris Wilson
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