[kvm-unit-tests PATCH v5 00/12] PCI bus support

[kvm-unit-tests PATCH v5 00/12] PCI bus support

[Alexander Gordeev]

Hi Andrew,

This is 5th version of PCI support. Changes since v4 are mainly addressing
nits and a rework of pci_bar_addr() function. The biggest change - the PCI
test succeeds on arm, aarch64, i386 and x86_64 (I am not posting pci-testdev
enablement for x86 though).

There are few changes (some of them to already Reviewed-by patches) worth
a notice - here are the interdiffs commented:

[08/12] pci: Add pci_print(); pci_print() function:
  - possibile devices with unimplemented gap BARs are printed correctly;
  - pci_bar_size() is called once;

diff -u b/lib/pci.c b/lib/pci.c
--- b/lib/pci.c
+++ b/lib/pci.c
@@ -146,14 +146,15 @@
 		return;
 
 	for (i = 0; i < 6; i++) {
-		phys_addr_t start, end;
+		phys_addr_t size, start, end;
 		uint32_t bar;
 
-		if (!pci_bar_is_valid(dev, i))
-			break;
+		size = pci_bar_size(dev, i);
+		if (!size)
+			continue;
 
 		start = pci_bar_get_addr(dev, i);
-		end = start + pci_bar_size(dev, i) - 1;
+		end = start + size - 1;
 
 		if (pci_bar_is64(dev, i)) {
 			printf("\tBAR#%d,%d [%" PRIx64 "-%" PRIx64 " ",

[09/12] pci: Add generic ECAM host support; pci_probe() function:
  - possibile devices with unimplemented gap BARs are scanned correctly;

@@ -276,7 +290,7 @@
 +
 +			size = pci_bar_size(dev, i);
 +			if (!size)
-+				break;
++				continue;
 +
 +			bar = pci_bar_get(dev, i);
 +			addr = pci_alloc_resource(bar, size);

[11/12] pci: Add pci-testdev PCI bus test device; pci_testdev_one() function:
  - no-eventfd vs eventfd accesses (clarified by Paolo on qemu-devel list)
    are handled now;

@@ -124,7 +124,11 @@
 		}
 	}
 
-	return (int)ops->io_readl(&test->count) == nr_writes;
+	count = ops->io_readl(&test->count);
+	if (!count)
+		return true;
+
+	return (int)count == nr_writes;
 }
 
 void pci_testdev_print(struct pci_test_dev_hdr *test,


Alexander Gordeev (12):
  [01/12] pci: Fix coding style in generic PCI files
  [02/12] pci: x86: Rename pci_config_read() to pci_config_readl()
  [03/12] pci: x86: Add remaining PCI configuration space accessors
  [04/12] pci: Rework pci_bar_addr()
  [05/12] pci: Factor out pci_bar_get()
  [06/12] pci: Add pci_bar_set_addr()
  [07/12] pci: Add pci_dev_exists()
  [08/12] pci: Add pci_print()
  [09/12] pci: Add generic ECAM host support
  [10/12] arm/arm64: pci: Add PCI bus operation test
  [11/12] pci: Add pci-testdev PCI bus test device
  [12/12] arm/arm64: pci: Add pci-testdev PCI device operation test

 arm/Makefile.common               |   6 +-
 arm/pci-test.c                    |  31 ++++
 arm/run                           |   7 +-
 lib/arm/asm/pci.h                 |  11 ++
 lib/arm64/asm/pci.h               |   1 +
 lib/asm-generic/pci-host-bridge.h |  26 ++++
 lib/pci-host-generic.c            | 295 ++++++++++++++++++++++++++++++++++++++
 lib/pci-host-generic.h            |  46 ++++++
 lib/pci-testdev.c                 | 188 ++++++++++++++++++++++++
 lib/pci.c                         | 201 +++++++++++++++++++++++---
 lib/pci.h                         |  34 ++++-
 lib/x86/asm/pci.h                 |  31 +++-
 x86/vmexit.c                      |   4 +-
 13 files changed, 853 insertions(+), 28 deletions(-)
 create mode 100644 arm/pci-test.c
 create mode 100644 lib/arm/asm/pci.h
 create mode 100644 lib/arm64/asm/pci.h
 create mode 100644 lib/asm-generic/pci-host-bridge.h
 create mode 100644 lib/pci-host-generic.c
 create mode 100644 lib/pci-host-generic.h
 create mode 100644 lib/pci-testdev.c

-- 
1.8.3.1

[kvm-unit-tests PATCH v5 01/12] pci: Fix coding style in generic PCI files

[Alexander Gordeev]

Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
 lib/pci.c | 38 ++++++++++++++++++++------------------
 lib/pci.h |  3 ++-
 2 files changed, 22 insertions(+), 19 deletions(-)

diff --git a/lib/pci.c b/lib/pci.c
index 0058d70c888d..43cd0ea4f2fa 100644
--- a/lib/pci.c
+++ b/lib/pci.c
@@ -10,34 +10,36 @@
 /* Scan bus look for a specific device. Only bus 0 scanned for now. */
 pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)
 {
-    unsigned dev;
-    for (dev = 0; dev < 256; ++dev) {
-    uint32_t id = pci_config_read(dev, 0);
-    if ((id & 0xFFFF) == vendor_id && (id >> 16) == device_id) {
-        return dev;
-    }
-    }
-    return PCIDEVADDR_INVALID;
+	pcidevaddr_t dev;
+
+	for (dev = 0; dev < 256; ++dev) {
+		uint32_t id = pci_config_read(dev, 0);
+
+		if ((id & 0xFFFF) == vendor_id && (id >> 16) == device_id)
+			return dev;
+	}
+
+	return PCIDEVADDR_INVALID;
 }
 
 unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num)
 {
-    uint32_t bar = pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
-    if (bar & PCI_BASE_ADDRESS_SPACE_IO) {
-        return bar & PCI_BASE_ADDRESS_IO_MASK;
-    } else {
-        return bar & PCI_BASE_ADDRESS_MEM_MASK;
-    }
+	uint32_t bar = pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
+
+	if (bar & PCI_BASE_ADDRESS_SPACE_IO)
+		return bar & PCI_BASE_ADDRESS_IO_MASK;
+	else
+		return bar & PCI_BASE_ADDRESS_MEM_MASK;
 }
 
 bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num)
 {
-    uint32_t bar = pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
-    return !(bar & PCI_BASE_ADDRESS_SPACE_IO);
+	uint32_t bar = pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
+
+	return !(bar & PCI_BASE_ADDRESS_SPACE_IO);
 }
 
 bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num)
 {
-    uint32_t bar = pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
-    return bar;
+	return pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
 }
diff --git a/lib/pci.h b/lib/pci.h
index 9160cfb5950d..54fbf22d634a 100644
--- a/lib/pci.h
+++ b/lib/pci.h
@@ -12,8 +12,9 @@
 
 typedef uint16_t pcidevaddr_t;
 enum {
-    PCIDEVADDR_INVALID = 0xffff,
+	PCIDEVADDR_INVALID = 0xffff,
 };
+
 pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);
 unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num);
 bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num);
-- 
1.8.3.1

[kvm-unit-tests PATCH v5 02/12] pci: x86: Rename pci_config_read() to pci_config_readl()

[Alexander Gordeev]

Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
 lib/pci.c         | 8 ++++----
 lib/x86/asm/pci.h | 2 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/lib/pci.c b/lib/pci.c
index 43cd0ea4f2fa..e0b4514244f6 100644
--- a/lib/pci.c
+++ b/lib/pci.c
@@ -13,7 +13,7 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)
 	pcidevaddr_t dev;
 
 	for (dev = 0; dev < 256; ++dev) {
-		uint32_t id = pci_config_read(dev, 0);
+		uint32_t id = pci_config_readl(dev, 0);
 
 		if ((id & 0xFFFF) == vendor_id && (id >> 16) == device_id)
 			return dev;
@@ -24,7 +24,7 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)
 
 unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num)
 {
-	uint32_t bar = pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
+	uint32_t bar = pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
 
 	if (bar & PCI_BASE_ADDRESS_SPACE_IO)
 		return bar & PCI_BASE_ADDRESS_IO_MASK;
@@ -34,12 +34,12 @@ unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num)
 
 bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num)
 {
-	uint32_t bar = pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
+	uint32_t bar = pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
 
 	return !(bar & PCI_BASE_ADDRESS_SPACE_IO);
 }
 
 bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num)
 {
-	return pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
+	return pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
 }
diff --git a/lib/x86/asm/pci.h b/lib/x86/asm/pci.h
index cddde41a7d97..d00438fe91e4 100644
--- a/lib/x86/asm/pci.h
+++ b/lib/x86/asm/pci.h
@@ -9,7 +9,7 @@
 #include "pci.h"
 #include "x86/asm/io.h"
 
-static inline uint32_t pci_config_read(pcidevaddr_t dev, uint8_t reg)
+static inline uint32_t pci_config_readl(pcidevaddr_t dev, uint8_t reg)
 {
     uint32_t index = reg | (dev << 8) | (0x1 << 31);
     outl(index, 0xCF8);
-- 
1.8.3.1

[kvm-unit-tests PATCH v5 03/12] pci: x86: Add remaining PCI configuration space accessors

[Alexander Gordeev]

Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
 lib/pci.c         |  5 ++---
 lib/x86/asm/pci.h | 23 +++++++++++++++++++++--
 2 files changed, 23 insertions(+), 5 deletions(-)

diff --git a/lib/pci.c b/lib/pci.c
index e0b4514244f6..b05ecfa3f3da 100644
--- a/lib/pci.c
+++ b/lib/pci.c
@@ -13,9 +13,8 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)
 	pcidevaddr_t dev;
 
 	for (dev = 0; dev < 256; ++dev) {
-		uint32_t id = pci_config_readl(dev, 0);
-
-		if ((id & 0xFFFF) == vendor_id && (id >> 16) == device_id)
+		if (pci_config_readw(dev, PCI_VENDOR_ID) == vendor_id &&
+		    pci_config_readw(dev, PCI_DEVICE_ID) == device_id)
 			return dev;
 	}
 
diff --git a/lib/x86/asm/pci.h b/lib/x86/asm/pci.h
index d00438fe91e4..821a2c1e180a 100644
--- a/lib/x86/asm/pci.h
+++ b/lib/x86/asm/pci.h
@@ -9,11 +9,30 @@
 #include "pci.h"
 #include "x86/asm/io.h"
 
+#define PCI_CONF1_ADDRESS(dev, reg)	((0x1 << 31) | (dev << 8) | reg)
+
+static inline uint8_t pci_config_readb(pcidevaddr_t dev, uint8_t reg)
+{
+    outl(PCI_CONF1_ADDRESS(dev, reg), 0xCF8);
+    return inb(0xCFC);
+}
+
+static inline uint16_t pci_config_readw(pcidevaddr_t dev, uint8_t reg)
+{
+    outl(PCI_CONF1_ADDRESS(dev, reg), 0xCF8);
+    return inw(0xCFC);
+}
+
 static inline uint32_t pci_config_readl(pcidevaddr_t dev, uint8_t reg)
 {
-    uint32_t index = reg | (dev << 8) | (0x1 << 31);
-    outl(index, 0xCF8);
+    outl(PCI_CONF1_ADDRESS(dev, reg), 0xCF8);
     return inl(0xCFC);
 }
 
+static inline void pci_config_writel(pcidevaddr_t dev, uint8_t reg, uint32_t val)
+{
+    outl(PCI_CONF1_ADDRESS(dev, reg), 0xCF8);
+    outl(val, 0xCFC);
+}
+
 #endif
-- 
1.8.3.1

[kvm-unit-tests PATCH v5 04/12] pci: Rework pci_bar_addr()

[Alexander Gordeev]

This update makes pci_bar_addr() interface 64 bit BARs aware and
introduces a concept of PCI address translation.

An architecutre should implement pci_translate_addr() interface
in order to provide mapping between PCI bus address and CPU
physical address.

Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
 lib/pci.c         | 76 ++++++++++++++++++++++++++++++++++++++++++++++++++-----
 lib/pci.h         | 16 +++++++++++-
 lib/x86/asm/pci.h |  6 +++++
 3 files changed, 91 insertions(+), 7 deletions(-)

diff --git a/lib/pci.c b/lib/pci.c
index b05ecfa3f3da..e3e8dfda6c87 100644
--- a/lib/pci.c
+++ b/lib/pci.c
@@ -21,14 +21,67 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)
 	return PCIDEVADDR_INVALID;
 }
 
-unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num)
+static uint32_t pci_bar_mask(uint32_t bar)
 {
-	uint32_t bar = pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
+	return (bar & PCI_BASE_ADDRESS_SPACE_IO) ?
+		PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK;
+}
 
-	if (bar & PCI_BASE_ADDRESS_SPACE_IO)
-		return bar & PCI_BASE_ADDRESS_IO_MASK;
-	else
-		return bar & PCI_BASE_ADDRESS_MEM_MASK;
+phys_addr_t pci_bar_addr(pcidevaddr_t dev, int bar_num)
+{
+	int off = PCI_BASE_ADDRESS_0 + bar_num * 4;
+	uint32_t bar = pci_config_readl(dev, off);
+	uint32_t mask = pci_bar_mask(bar);
+	uint64_t addr = bar & mask;
+
+	if (pci_bar_is64(dev, bar_num))
+		addr |= (uint64_t)pci_config_readl(dev, off + 4) << 32;
+
+	return pci_translate_addr(dev, addr);
+}
+
+/*
+ * To determine the amount of address space needed by a PCI device,
+ * one must save the original value of the BAR, write a value of
+ * all 1's to the register, then read it back. The amount of memory
+ * can then be then determined by masking the information bits,
+ * performing a bitwise NOT and incrementing the value by 1.
+ *
+ * The following pci_bar_size_helper() and pci_bar_size() functions do
+ * the described algorithm.
+ */
+static uint32_t pci_bar_size_helper(pcidevaddr_t dev, int bar_num)
+{
+	int off = PCI_BASE_ADDRESS_0 + bar_num * 4;
+	uint32_t bar, size;
+
+	bar = pci_config_readl(dev, off);
+	pci_config_writel(dev, off, ~0u);
+	size = pci_config_readl(dev, off);
+	pci_config_writel(dev, off, bar);
+
+	return size;
+}
+
+phys_addr_t pci_bar_size(pcidevaddr_t dev, int bar_num)
+{
+	uint32_t bar, size;
+
+	size = pci_bar_size_helper(dev, bar_num);
+	if (!size)
+		return 0;
+
+	bar = pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
+	size &= pci_bar_mask(bar);
+
+	if (pci_bar_is64(dev, bar_num)) {
+		phys_addr_t size64 = pci_bar_size_helper(dev, bar_num + 1);
+		size64 = (size64 << 32) | size;
+
+		return ~size64 + 1;
+	} else {
+		return ~size + 1;
+	}
 }
 
 bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num)
@@ -42,3 +95,14 @@ bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num)
 {
 	return pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
 }
+
+bool pci_bar_is64(pcidevaddr_t dev, int bar_num)
+{
+	uint32_t bar = pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
+
+	if (bar & PCI_BASE_ADDRESS_SPACE_IO)
+		return false;
+
+	return (bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
+		      PCI_BASE_ADDRESS_MEM_TYPE_64;
+}
diff --git a/lib/pci.h b/lib/pci.h
index 54fbf22d634a..4d3e8d385eb1 100644
--- a/lib/pci.h
+++ b/lib/pci.h
@@ -16,7 +16,21 @@ enum {
 };
 
 pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);
-unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num);
+
+/*
+ * BAR number in all BAR access functions below is a number of 32-bit
+ * register starting from PCI_BASE_ADDRESS_0 offset.
+ *
+ * In cases BAR size is 64-bit a caller should still provide BAR number
+ * in terms of 32-bit words. For example, if a device has 64-bit BAR#0
+ * and 32-bit BAR#1 the caller should provide 2 to address BAR#1, not 1.
+ *
+ * It is expected the caller is aware of the device BAR layout and never
+ * tries to address in the middle of a 64-bit register.
+ */
+phys_addr_t pci_bar_addr(pcidevaddr_t dev, int bar_num);
+phys_addr_t pci_bar_size(pcidevaddr_t dev, int bar_num);
+bool pci_bar_is64(pcidevaddr_t dev, int bar_num);
 bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num);
 bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num);
 
diff --git a/lib/x86/asm/pci.h b/lib/x86/asm/pci.h
index 821a2c1e180a..7384b91adba1 100644
--- a/lib/x86/asm/pci.h
+++ b/lib/x86/asm/pci.h
@@ -35,4 +35,10 @@ static inline void pci_config_writel(pcidevaddr_t dev, uint8_t reg, uint32_t val
     outl(val, 0xCFC);
 }
 
+static inline
+phys_addr_t pci_translate_addr(pcidevaddr_t dev __unused, uint64_t addr)
+{
+    return addr;
+}
+
 #endif
-- 
1.8.3.1

[kvm-unit-tests PATCH v5 05/12] pci: Factor out pci_bar_get()

[Alexander Gordeev]

Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
 lib/pci.c | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/lib/pci.c b/lib/pci.c
index e3e8dfda6c87..cd8c13e87e3b 100644
--- a/lib/pci.c
+++ b/lib/pci.c
@@ -27,15 +27,19 @@ static uint32_t pci_bar_mask(uint32_t bar)
 		PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK;
 }
 
+static uint32_t pci_bar_get(pcidevaddr_t dev, int bar_num)
+{
+	return pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
+}
+
 phys_addr_t pci_bar_addr(pcidevaddr_t dev, int bar_num)
 {
-	int off = PCI_BASE_ADDRESS_0 + bar_num * 4;
-	uint32_t bar = pci_config_readl(dev, off);
+	uint32_t bar = pci_bar_get(dev, bar_num);
 	uint32_t mask = pci_bar_mask(bar);
 	uint64_t addr = bar & mask;
 
 	if (pci_bar_is64(dev, bar_num))
-		addr |= (uint64_t)pci_config_readl(dev, off + 4) << 32;
+		addr |= (uint64_t)pci_bar_get(dev, bar_num + 1) << 32;
 
 	return pci_translate_addr(dev, addr);
 }
@@ -71,7 +75,7 @@ phys_addr_t pci_bar_size(pcidevaddr_t dev, int bar_num)
 	if (!size)
 		return 0;
 
-	bar = pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
+	bar = pci_bar_get(dev, bar_num);
 	size &= pci_bar_mask(bar);
 
 	if (pci_bar_is64(dev, bar_num)) {
@@ -86,19 +90,19 @@ phys_addr_t pci_bar_size(pcidevaddr_t dev, int bar_num)
 
 bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num)
 {
-	uint32_t bar = pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
+	uint32_t bar = pci_bar_get(dev, bar_num);
 
 	return !(bar & PCI_BASE_ADDRESS_SPACE_IO);
 }
 
 bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num)
 {
-	return pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
+	return pci_bar_get(dev, bar_num);
 }
 
 bool pci_bar_is64(pcidevaddr_t dev, int bar_num)
 {
-	uint32_t bar = pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
+	uint32_t bar = pci_bar_get(dev, bar_num);
 
 	if (bar & PCI_BASE_ADDRESS_SPACE_IO)
 		return false;
-- 
1.8.3.1

[kvm-unit-tests PATCH v5 06/12] pci: Add pci_bar_set_addr()

[Alexander Gordeev]

Because the counterpart to pci_bar_set_addr() setter is
pci_bar_addr() getter, these names become inconsistent.
Rename pci_bar_addr() to pci_bar_get_addr() also to make
the resulting names conform to each other.

Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
 lib/pci.c    | 12 +++++++++++-
 lib/pci.h    |  3 ++-
 x86/vmexit.c |  4 ++--
 3 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/lib/pci.c b/lib/pci.c
index cd8c13e87e3b..bedc388aea25 100644
--- a/lib/pci.c
+++ b/lib/pci.c
@@ -32,7 +32,7 @@ static uint32_t pci_bar_get(pcidevaddr_t dev, int bar_num)
 	return pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
 }
 
-phys_addr_t pci_bar_addr(pcidevaddr_t dev, int bar_num)
+phys_addr_t pci_bar_get_addr(pcidevaddr_t dev, int bar_num)
 {
 	uint32_t bar = pci_bar_get(dev, bar_num);
 	uint32_t mask = pci_bar_mask(bar);
@@ -44,6 +44,16 @@ phys_addr_t pci_bar_addr(pcidevaddr_t dev, int bar_num)
 	return pci_translate_addr(dev, addr);
 }
 
+void pci_bar_set_addr(pcidevaddr_t dev, int bar_num, phys_addr_t addr)
+{
+	int off = PCI_BASE_ADDRESS_0 + bar_num * 4;
+
+	pci_config_writel(dev, off, (uint32_t)addr);
+
+	if (pci_bar_is64(dev, bar_num))
+		pci_config_writel(dev, off + 4, (uint32_t)(addr >> 32));
+}
+
 /*
  * To determine the amount of address space needed by a PCI device,
  * one must save the original value of the BAR, write a value of
diff --git a/lib/pci.h b/lib/pci.h
index 4d3e8d385eb1..9623f21b948b 100644
--- a/lib/pci.h
+++ b/lib/pci.h
@@ -28,7 +28,8 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);
  * It is expected the caller is aware of the device BAR layout and never
  * tries to address in the middle of a 64-bit register.
  */
-phys_addr_t pci_bar_addr(pcidevaddr_t dev, int bar_num);
+phys_addr_t pci_bar_get_addr(pcidevaddr_t dev, int bar_num);
+void pci_bar_set_addr(pcidevaddr_t dev, int bar_num, phys_addr_t addr);
 phys_addr_t pci_bar_size(pcidevaddr_t dev, int bar_num);
 bool pci_bar_is64(pcidevaddr_t dev, int bar_num);
 bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num);
diff --git a/x86/vmexit.c b/x86/vmexit.c
index c2e1e496918d..2d99d5fdf1c2 100644
--- a/x86/vmexit.c
+++ b/x86/vmexit.c
@@ -392,10 +392,10 @@ int main(int ac, char **av)
 				continue;
 			}
 			if (pci_bar_is_memory(pcidev, i)) {
-				membar = pci_bar_addr(pcidev, i);
+				membar = pci_bar_get_addr(pcidev, i);
 				pci_test.memaddr = ioremap(membar, PAGE_SIZE);
 			} else {
-				pci_test.iobar = pci_bar_addr(pcidev, i);
+				pci_test.iobar = pci_bar_get_addr(pcidev, i);
 			}
 		}
 		printf("pci-testdev at 0x%x membar %lx iobar %x\n",
-- 
1.8.3.1

[kvm-unit-tests PATCH v5 07/12] pci: Add pci_dev_exists()

[Alexander Gordeev]

Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
 lib/pci.c | 6 ++++++
 lib/pci.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/lib/pci.c b/lib/pci.c
index bedc388aea25..947bfb2c8f47 100644
--- a/lib/pci.c
+++ b/lib/pci.c
@@ -7,6 +7,12 @@
 #include "pci.h"
 #include "asm/pci.h"
 
+bool pci_dev_exists(pcidevaddr_t dev)
+{
+	return (pci_config_readw(dev, PCI_VENDOR_ID) != 0xffff &&
+		pci_config_readw(dev, PCI_DEVICE_ID) != 0xffff);
+}
+
 /* Scan bus look for a specific device. Only bus 0 scanned for now. */
 pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)
 {
diff --git a/lib/pci.h b/lib/pci.h
index 9623f21b948b..2efb976d13ea 100644
--- a/lib/pci.h
+++ b/lib/pci.h
@@ -15,6 +15,7 @@ enum {
 	PCIDEVADDR_INVALID = 0xffff,
 };
 
+bool pci_dev_exists(pcidevaddr_t dev);
 pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);
 
 /*
-- 
1.8.3.1

[kvm-unit-tests PATCH v5 08/12] pci: Add pci_print()

[Alexander Gordeev]

Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
 lib/pci.c | 78 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 lib/pci.h |  3 +++
 2 files changed, 81 insertions(+)

diff --git a/lib/pci.c b/lib/pci.c
index 947bfb2c8f47..f01a085391f3 100644
--- a/lib/pci.c
+++ b/lib/pci.c
@@ -126,3 +126,81 @@ bool pci_bar_is64(pcidevaddr_t dev, int bar_num)
 	return (bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 		      PCI_BASE_ADDRESS_MEM_TYPE_64;
 }
+
+static void pci_dev_print(pcidevaddr_t dev)
+{
+	uint16_t vendor_id = pci_config_readw(dev, PCI_VENDOR_ID);
+	uint16_t device_id = pci_config_readw(dev, PCI_DEVICE_ID);
+	uint8_t header = pci_config_readb(dev, PCI_HEADER_TYPE);
+	uint8_t progif = pci_config_readb(dev, PCI_CLASS_PROG);
+	uint8_t subclass = pci_config_readb(dev, PCI_CLASS_DEVICE);
+	uint8_t class = pci_config_readb(dev, PCI_CLASS_DEVICE + 1);
+	int i;
+
+	printf("dev %2d fn %d vendor_id %04x device_id %04x type %02x "
+	       "progif %02x class %02x subclass %02x\n",
+	       dev / 8, dev % 8, vendor_id, device_id, header,
+	       progif, class, subclass);
+
+	if ((header & PCI_HEADER_TYPE_MASK) != PCI_HEADER_TYPE_NORMAL)
+		return;
+
+	for (i = 0; i < 6; i++) {
+		phys_addr_t size, start, end;
+		uint32_t bar;
+
+		size = pci_bar_size(dev, i);
+		if (!size)
+			continue;
+
+		start = pci_bar_get_addr(dev, i);
+		end = start + size - 1;
+
+		if (pci_bar_is64(dev, i)) {
+			printf("\tBAR#%d,%d [%" PRIx64 "-%" PRIx64 " ",
+			       i, i + 1, start, end);
+			i++;
+		} else {
+			printf("\tBAR#%d    [%02x-%02x ",
+			       i, (uint32_t)start, (uint32_t)end);
+		}
+
+		bar = pci_bar_get(dev, i);
+
+		if (bar & PCI_BASE_ADDRESS_SPACE_IO) {
+			printf("PIO]\n");
+			continue;
+		}
+
+		printf("MEM");
+
+		switch (bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
+		case PCI_BASE_ADDRESS_MEM_TYPE_32:
+			printf("32");
+			break;
+		case PCI_BASE_ADDRESS_MEM_TYPE_1M:
+			printf("1M");
+			break;
+		case PCI_BASE_ADDRESS_MEM_TYPE_64:
+			printf("64");
+			break;
+		default:
+			assert(0);
+		}
+
+		if (bar & PCI_BASE_ADDRESS_MEM_PREFETCH)
+			printf("/p");
+
+		printf("]\n");
+	}
+}
+
+void pci_print(void)
+{
+	pcidevaddr_t dev;
+
+	for (dev = 0; dev < 256; ++dev) {
+		if (pci_dev_exists(dev))
+			pci_dev_print(dev);
+	}
+}
diff --git a/lib/pci.h b/lib/pci.h
index 2efb976d13ea..ff32ea683c94 100644
--- a/lib/pci.h
+++ b/lib/pci.h
@@ -15,6 +15,7 @@ enum {
 	PCIDEVADDR_INVALID = 0xffff,
 };
 
+void pci_print(void);
 bool pci_dev_exists(pcidevaddr_t dev);
 pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);
 
@@ -56,4 +57,6 @@ struct pci_test_dev_hdr {
 	uint8_t  name[];
 };
 
+#define  PCI_HEADER_TYPE_MASK		0x7f
+
 #endif /* PCI_H */
-- 
1.8.3.1

[kvm-unit-tests PATCH v5 09/12] pci: Add generic ECAM host support

[Alexander Gordeev]

Unlike x86, other architectures using generic ECAM PCI host
do not have a luxury of PCI bus initialized by a BIOS and
ready to use at start. Thus, we need allocate and assign
resources to all devices, much like an architecture's
firmware would do.

There is no any sort of resource management for memory and
io spaces, since only ones-per-BAR allocations are expected
and no deallocations at all.

Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
 lib/asm-generic/pci-host-bridge.h |  26 ++++
 lib/pci-host-generic.c            | 295 ++++++++++++++++++++++++++++++++++++++
 lib/pci-host-generic.h            |  46 ++++++
 lib/pci.c                         |   4 +-
 lib/pci.h                         |   3 +
 5 files changed, 372 insertions(+), 2 deletions(-)
 create mode 100644 lib/asm-generic/pci-host-bridge.h
 create mode 100644 lib/pci-host-generic.c
 create mode 100644 lib/pci-host-generic.h

diff --git a/lib/asm-generic/pci-host-bridge.h b/lib/asm-generic/pci-host-bridge.h
new file mode 100644
index 000000000000..872df3a81310
--- /dev/null
+++ b/lib/asm-generic/pci-host-bridge.h
@@ -0,0 +1,26 @@
+#ifndef _ASM_PCI_HOST_BRIDGE_H_
+#define _ASM_PCI_HOST_BRIDGE_H_
+/*
+ * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ */
+#include "libcflat.h"
+
+phys_addr_t pci_host_bridge_get_paddr(uint64_t addr);
+
+static inline
+phys_addr_t pci_translate_addr(pcidevaddr_t __unused dev, uint64_t addr)
+{
+	/*
+	 * Assume we only have single PCI host bridge in a system.
+	 */
+	return pci_host_bridge_get_paddr(addr);
+}
+
+uint8_t pci_config_readb(pcidevaddr_t dev, uint8_t reg);
+uint16_t pci_config_readw(pcidevaddr_t dev, uint8_t reg);
+uint32_t pci_config_readl(pcidevaddr_t dev, uint8_t reg);
+void pci_config_writel(pcidevaddr_t dev, uint8_t reg, uint32_t val);
+
+#endif
diff --git a/lib/pci-host-generic.c b/lib/pci-host-generic.c
new file mode 100644
index 000000000000..4a2716a33150
--- /dev/null
+++ b/lib/pci-host-generic.c
@@ -0,0 +1,295 @@
+/*
+ * Generic PCI host controller as described in PCI Bus Binding to Open Firmware
+ *
+ * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ */
+#include "libcflat.h"
+#include "devicetree.h"
+#include "alloc.h"
+#include "pci.h"
+#include "asm/pci.h"
+#include "asm/io.h"
+#include "pci-host-generic.h"
+#include <linux/pci_regs.h>
+
+static struct pci_host_bridge *pci_host_bridge;
+
+static int of_flags_to_pci_type(u32 of_flags)
+{
+	static int type_map[] = {
+		[1] = PCI_BASE_ADDRESS_SPACE_IO,
+		[2] = PCI_BASE_ADDRESS_MEM_TYPE_32,
+		[3] = PCI_BASE_ADDRESS_MEM_TYPE_64
+	};
+	int idx = (of_flags >> 24) & 0x03;
+	int res;
+
+	assert(idx > 0);
+	res = type_map[idx];
+
+	if (of_flags & 0x40000000)
+		res |= PCI_BASE_ADDRESS_MEM_PREFETCH;
+
+	return res;
+}
+
+static int pci_bar_type(u32 bar)
+{
+	if (bar & PCI_BASE_ADDRESS_SPACE)
+		return PCI_BASE_ADDRESS_SPACE_IO;
+	else
+		return bar & (PCI_BASE_ADDRESS_MEM_TYPE_MASK |
+			      PCI_BASE_ADDRESS_MEM_PREFETCH);
+}
+
+/*
+ * Probe DT for a generic PCI host controller
+ * See kernel Documentation/devicetree/bindings/pci/host-generic-pci.txt
+ * and function gen_pci_probe() in drivers/pci/host/pci-host-generic.c
+ */
+static struct pci_host_bridge *pci_dt_probe(void)
+{
+	struct pci_host_bridge *host;
+	const void *fdt = dt_fdt();
+	const struct fdt_property *prop;
+	struct dt_pbus_reg base;
+	struct dt_device dt_dev;
+	struct dt_bus dt_bus;
+	struct pci_addr_space *as;
+	fdt32_t *data;
+	u32 bus, bus_max;
+	u32 nac, nsc, nac_root, nsc_root;
+	int nr_range_cells, nr_addr_spaces;
+	int ret, node, len, i;
+
+	if (!dt_available()) {
+		printf("No device tree found\n");
+		return NULL;
+	}
+
+	dt_bus_init_defaults(&dt_bus);
+	dt_device_init(&dt_dev, &dt_bus, NULL);
+
+	node = fdt_path_offset(fdt, "/");
+	assert(node >= 0);
+
+	ret = dt_get_nr_cells(node, &nac_root, &nsc_root);
+	assert(ret == 0);
+	assert(nac_root == 1 || nac_root == 2);
+
+	node = fdt_node_offset_by_compatible(fdt, node,
+					     "pci-host-ecam-generic");
+	if (node == -FDT_ERR_NOTFOUND) {
+		printf("No PCIe ECAM compatible controller found\n");
+		return NULL;
+	}
+	assert(node >= 0);
+
+	prop = fdt_get_property(fdt, node, "device_type", &len);
+	assert(prop && len == 4 && !strcmp((char *)prop->data, "pci"));
+
+	dt_device_bind_node(&dt_dev, node);
+	ret = dt_pbus_get_base(&dt_dev, &base);
+	assert(ret == 0);
+
+	prop = fdt_get_property(fdt, node, "bus-range", &len);
+	if (prop == NULL) {
+		assert(len == -FDT_ERR_NOTFOUND);
+		bus		= 0x00;
+		bus_max		= 0xff;
+	} else {
+		data		= (fdt32_t *)prop->data;
+		bus		= fdt32_to_cpu(data[0]);
+		bus_max		= fdt32_to_cpu(data[1]);
+		assert(bus <= bus_max);
+	}
+	assert(bus_max < base.size / (1 << PCI_ECAM_BUS_SHIFT));
+
+	ret = dt_get_nr_cells(node, &nac, &nsc);
+	assert(ret == 0);
+	assert(nac == 3 && nsc == 2);
+
+	prop = fdt_get_property(fdt, node, "ranges", &len);
+	assert(prop != NULL);
+
+	nr_range_cells = nac + nsc + nac_root;
+	nr_addr_spaces = (len / 4) / nr_range_cells;
+	assert(nr_addr_spaces);
+
+	host = malloc(sizeof(*host) +
+		      sizeof(host->addr_space[0]) * nr_addr_spaces);
+	assert(host != NULL);
+
+	host->start		= base.addr;
+	host->size		= base.size;
+	host->bus		= bus;
+	host->bus_max		= bus_max;
+	host->nr_addr_spaces	= nr_addr_spaces;
+
+	data = (fdt32_t *)prop->data;
+	as = &host->addr_space[0];
+
+	for (i = 0; i < nr_addr_spaces; i++) {
+		/*
+		 * The PCI binding encodes the PCI address with three
+		 * cells as follows:
+		 *
+		 * phys.hi  cell: npt000ss bbbbbbbb dddddfff rrrrrrrr
+		 * phys.mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
+		 * phys.lo  cell: llllllll llllllll llllllll llllllll
+		 *
+		 * PCI device bus address and flags are encoded into phys.high
+		 * PCI 64 bit address is encoded into phys.mid and phys.low
+		 */
+		as->type = of_flags_to_pci_type(fdt32_to_cpu(data[0]));
+		as->pci_start = ((u64)fdt32_to_cpu(data[1]) << 32) |
+				fdt32_to_cpu(data[2]);
+
+		if (nr_range_cells == 6) {
+			as->start = fdt32_to_cpu(data[3]);
+			as->size  = ((u64)fdt32_to_cpu(data[4]) << 32) |
+				    fdt32_to_cpu(data[5]);
+		} else {
+			as->start = ((u64)fdt32_to_cpu(data[3]) << 32) |
+				    fdt32_to_cpu(data[4]);
+			as->size  = ((u64)fdt32_to_cpu(data[5]) << 32) |
+				    fdt32_to_cpu(data[6]);
+		}
+
+		data += nr_range_cells;
+		as++;
+	}
+
+	return host;
+}
+
+static u64 pci_alloc_resource(u32 bar, u64 size)
+{
+	struct pci_host_bridge *host = pci_host_bridge;
+	struct pci_addr_space *as = &host->addr_space[0];
+	phys_addr_t addr;
+	u32 mask;
+	int i;
+
+	for (i = 0; i < host->nr_addr_spaces; i++) {
+		if (as->type == pci_bar_type(bar))
+			break;
+		as++;
+	}
+	if (i >= host->nr_addr_spaces) {
+		printf("No PCI resource found for a device\n");
+		assert(0);
+	}
+
+	mask = pci_bar_mask(bar);
+	size = ALIGN(size, ~mask + 1);
+	assert(as->allocated + size <= as->size);
+
+	addr = as->pci_start + as->allocated;
+	as->allocated += size;
+
+	return addr;
+}
+
+bool pci_probe(void)
+{
+	pcidevaddr_t dev;
+	u8 header;
+	u32 cmd;
+	int i;
+
+	assert(!pci_host_bridge);
+	pci_host_bridge = pci_dt_probe();
+	if (!pci_host_bridge)
+		return false;
+
+	for (dev = 0; dev < 256; dev++) {
+		if (!pci_dev_exists(dev))
+			continue;
+
+		/* We are only interested in normal PCI devices */
+		header = pci_config_readb(dev, PCI_HEADER_TYPE);
+		if ((header & PCI_HEADER_TYPE_MASK) != PCI_HEADER_TYPE_NORMAL)
+			continue;
+
+		cmd = PCI_COMMAND_SERR;
+
+		for (i = 0; i < 6; i++) {
+			u64 addr, size;
+			u32 bar;
+
+			size = pci_bar_size(dev, i);
+			if (!size)
+				continue;
+
+			bar = pci_bar_get(dev, i);
+			addr = pci_alloc_resource(bar, size);
+			pci_bar_set_addr(dev, i, addr);
+
+			if (pci_bar_is_memory(dev, i))
+				cmd |= PCI_COMMAND_MEMORY;
+			else
+				cmd |= PCI_COMMAND_IO;
+
+			if (pci_bar_is64(dev, i))
+				i++;
+		}
+
+		pci_config_writel(dev, PCI_COMMAND, cmd);
+	}
+
+	return true;
+}
+
+/*
+ * This function is to be called from pci_translate_addr() to provide
+ * mapping between this host bridge's PCI busses address and CPU physical
+ * address.
+ */
+phys_addr_t pci_host_bridge_get_paddr(u64 pci_addr)
+{
+	struct pci_host_bridge *host = pci_host_bridge;
+	struct pci_addr_space *as = &host->addr_space[0];
+	int i;
+
+	for (i = 0; i < host->nr_addr_spaces; i++) {
+		if (pci_addr >= as->pci_start &&
+		    pci_addr < as->pci_start + as->size)
+			return as->start + (pci_addr - as->pci_start);
+		as++;
+	}
+
+	return 0;
+}
+
+static void __iomem *pci_get_dev_conf(struct pci_host_bridge *host, int devfn)
+{
+	return (void __iomem *)(unsigned long)
+		host->start + (devfn << PCI_ECAM_DEVFN_SHIFT);
+}
+
+u8 pci_config_readb(pcidevaddr_t dev, u8 off)
+{
+	void __iomem *conf = pci_get_dev_conf(pci_host_bridge, dev);
+	return readb(conf + off);
+}
+
+u16 pci_config_readw(pcidevaddr_t dev, u8 off)
+{
+	void __iomem *conf = pci_get_dev_conf(pci_host_bridge, dev);
+	return readw(conf + off);
+}
+
+u32 pci_config_readl(pcidevaddr_t dev, u8 off)
+{
+	void __iomem *conf = pci_get_dev_conf(pci_host_bridge, dev);
+	return readl(conf + off);
+}
+
+void pci_config_writel(pcidevaddr_t dev, u8 off, u32 val)
+{
+	void __iomem *conf = pci_get_dev_conf(pci_host_bridge, dev);
+	writel(val, conf + off);
+}
diff --git a/lib/pci-host-generic.h b/lib/pci-host-generic.h
new file mode 100644
index 000000000000..fd30e7c74ed8
--- /dev/null
+++ b/lib/pci-host-generic.h
@@ -0,0 +1,46 @@
+#ifndef PCI_HOST_GENERIC_H
+#define PCI_HOST_GENERIC_H
+/*
+ * PCI host bridge supporting structures and constants
+ *
+ * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ */
+#include "libcflat.h"
+
+struct pci_addr_space {
+	phys_addr_t		pci_start;
+	phys_addr_t		start;
+	phys_addr_t		size;
+	phys_addr_t		allocated;
+	int			type;
+};
+
+struct pci_host_bridge {
+	phys_addr_t		start;
+	phys_addr_t		size;
+	int			bus;
+	int			bus_max;
+	int			nr_addr_spaces;
+	struct pci_addr_space	addr_space[];
+};
+
+/*
+ * The following constants are derived from Linux, see this source:
+ *
+ *         drivers/pci/host/pci-host-generic.c
+ *                 struct gen_pci_cfg_bus_ops::bus_shift
+ *                 int gen_pci_parse_map_cfg_windows(struct gen_pci *pci)
+ *
+ * Documentation/devicetree/bindings/pci/host-generic-pci.txt describes
+ * ECAM Configuration Space is be memory-mapped by concatenating the various
+ * components to form an offset:
+ *
+ *	cfg_offset(bus, device, function, register) =
+ *		   bus << 20 | device << 15 | function << 12 | register
+ */
+#define PCI_ECAM_BUS_SHIFT	20
+#define PCI_ECAM_DEVFN_SHIFT	12
+
+#endif
diff --git a/lib/pci.c b/lib/pci.c
index f01a085391f3..46cd39dc9c7e 100644
--- a/lib/pci.c
+++ b/lib/pci.c
@@ -27,13 +27,13 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)
 	return PCIDEVADDR_INVALID;
 }
 
-static uint32_t pci_bar_mask(uint32_t bar)
+uint32_t pci_bar_mask(uint32_t bar)
 {
 	return (bar & PCI_BASE_ADDRESS_SPACE_IO) ?
 		PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK;
 }
 
-static uint32_t pci_bar_get(pcidevaddr_t dev, int bar_num)
+uint32_t pci_bar_get(pcidevaddr_t dev, int bar_num)
 {
 	return pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
 }
diff --git a/lib/pci.h b/lib/pci.h
index ff32ea683c94..e00e1471d80a 100644
--- a/lib/pci.h
+++ b/lib/pci.h
@@ -15,6 +15,7 @@ enum {
 	PCIDEVADDR_INVALID = 0xffff,
 };
 
+bool pci_probe(void);
 void pci_print(void);
 bool pci_dev_exists(pcidevaddr_t dev);
 pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);
@@ -33,6 +34,8 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);
 phys_addr_t pci_bar_get_addr(pcidevaddr_t dev, int bar_num);
 void pci_bar_set_addr(pcidevaddr_t dev, int bar_num, phys_addr_t addr);
 phys_addr_t pci_bar_size(pcidevaddr_t dev, int bar_num);
+uint32_t pci_bar_get(pcidevaddr_t dev, int bar_num);
+uint32_t pci_bar_mask(uint32_t bar);
 bool pci_bar_is64(pcidevaddr_t dev, int bar_num);
 bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num);
 bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num);
-- 
1.8.3.1

[kvm-unit-tests PATCH v5 10/12] arm/arm64: pci: Add PCI bus operation test

[Alexander Gordeev]

Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
 arm/Makefile.common |  5 ++++-
 arm/pci-test.c      | 21 +++++++++++++++++++++
 lib/arm/asm/pci.h   | 11 +++++++++++
 lib/arm64/asm/pci.h |  1 +
 4 files changed, 37 insertions(+), 1 deletion(-)
 create mode 100644 arm/pci-test.c
 create mode 100644 lib/arm/asm/pci.h
 create mode 100644 lib/arm64/asm/pci.h

diff --git a/arm/Makefile.common b/arm/Makefile.common
index ccb554d9251a..97179bbea4e7 100644
--- a/arm/Makefile.common
+++ b/arm/Makefile.common
@@ -11,7 +11,8 @@ endif
 
 tests-common = \
 	$(TEST_DIR)/selftest.flat \
-	$(TEST_DIR)/spinlock-test.flat
+	$(TEST_DIR)/spinlock-test.flat \
+	$(TEST_DIR)/pci-test.flat
 
 all: test_cases
 
@@ -33,6 +34,8 @@ include scripts/asm-offsets.mak
 cflatobjs += lib/util.o
 cflatobjs += lib/alloc.o
 cflatobjs += lib/devicetree.o
+cflatobjs += lib/pci.o
+cflatobjs += lib/pci-host-generic.o
 cflatobjs += lib/virtio.o
 cflatobjs += lib/virtio-mmio.o
 cflatobjs += lib/chr-testdev.o
diff --git a/arm/pci-test.c b/arm/pci-test.c
new file mode 100644
index 000000000000..fde5495dd626
--- /dev/null
+++ b/arm/pci-test.c
@@ -0,0 +1,21 @@
+/*
+ * PCI bus operation test
+ *
+ * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ */
+#include <libcflat.h>
+#include <pci.h>
+
+int main(void)
+{
+	int ret = pci_probe();
+
+	report("PCI bus probing", ret);
+
+	if (ret)
+		pci_print();
+
+	return report_summary();
+}
diff --git a/lib/arm/asm/pci.h b/lib/arm/asm/pci.h
new file mode 100644
index 000000000000..08b0e87d497c
--- /dev/null
+++ b/lib/arm/asm/pci.h
@@ -0,0 +1,11 @@
+#ifndef _ASMARM_PCI_H_
+#define _ASMARM_PCI_H_
+/*
+ * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ */
+#include "libcflat.h"
+#include "asm-generic/pci-host-bridge.h"
+
+#endif
diff --git a/lib/arm64/asm/pci.h b/lib/arm64/asm/pci.h
new file mode 100644
index 000000000000..f70ef560e2ab
--- /dev/null
+++ b/lib/arm64/asm/pci.h
@@ -0,0 +1 @@
+#include "../../arm/asm/pci.h"
-- 
1.8.3.1

[kvm-unit-tests PATCH v5 11/12] pci: Add pci-testdev PCI bus test device

[Alexander Gordeev]

Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
 lib/pci-testdev.c | 188 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 lib/pci.h         |   7 ++
 2 files changed, 195 insertions(+)
 create mode 100644 lib/pci-testdev.c

diff --git a/lib/pci-testdev.c b/lib/pci-testdev.c
new file mode 100644
index 000000000000..1ee4a3ca0df8
--- /dev/null
+++ b/lib/pci-testdev.c
@@ -0,0 +1,188 @@
+/*
+ * QEMU "pci-testdev" PCI test device
+ *
+ * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ */
+#include "pci.h"
+#include "asm/io.h"
+
+struct pci_testdev_ops {
+	u8 (*io_readb)(const volatile void *addr);
+	u16 (*io_readw)(const volatile void *addr);
+	u32 (*io_readl)(const volatile void *addr);
+	void (*io_writeb)(u8 value, volatile void *addr);
+	void (*io_writew)(u16 value, volatile void *addr);
+	void (*io_writel)(u32 value, volatile void *addr);
+};
+
+static u8 pio_readb(const volatile void *addr)
+{
+	return inb((unsigned long)addr);
+}
+
+static u16 pio_readw(const volatile void *addr)
+{
+	return inw((unsigned long)addr);
+}
+
+static u32 pio_readl(const volatile void *addr)
+{
+	return inl((unsigned long)addr);
+}
+
+static void pio_writeb(u8 value, volatile void *addr)
+{
+	outb(value, (unsigned long)addr);
+}
+
+static void pio_writew(u16 value, volatile void *addr)
+{
+	outw(value, (unsigned long)addr);
+}
+
+static void pio_writel(u32 value, volatile void *addr)
+{
+	outl(value, (unsigned long)addr);
+}
+
+static struct pci_testdev_ops pci_testdev_io_ops = {
+	.io_readb	= pio_readb,
+	.io_readw	= pio_readw,
+	.io_readl	= pio_readl,
+	.io_writeb	= pio_writeb,
+	.io_writew	= pio_writew,
+	.io_writel	= pio_writel
+};
+
+static u8 mmio_readb(const volatile void *addr)
+{
+	return *(const volatile u8 __force *)addr;
+}
+
+static u16 mmio_readw(const volatile void *addr)
+{
+	return *(const volatile u16 __force *)addr;
+}
+
+static u32 mmio_readl(const volatile void *addr)
+{
+	return *(const volatile u32 __force *)addr;
+}
+
+static void mmio_writeb(u8 value, volatile void *addr)
+{
+	*(volatile u8 __force *)addr = value;
+}
+
+static void mmio_writew(u16 value, volatile void *addr)
+{
+	*(volatile u16 __force *)addr = value;
+}
+
+static void mmio_writel(u32 value, volatile void *addr)
+{
+	*(volatile u32 __force *)addr = value;
+}
+
+static struct pci_testdev_ops pci_testdev_mem_ops = {
+	.io_readb	= mmio_readb,
+	.io_readw	= mmio_readw,
+	.io_readl	= mmio_readl,
+	.io_writeb	= mmio_writeb,
+	.io_writew	= mmio_writew,
+	.io_writel	= mmio_writel
+};
+
+static bool pci_testdev_one(struct pci_test_dev_hdr *test,
+			    int test_nr,
+			    struct pci_testdev_ops *ops)
+{
+	u8 width;
+	u32 count, sig, off;
+	const int nr_writes = 16;
+	int i;
+
+	ops->io_writeb(test_nr, &test->test);
+	count = ops->io_readl(&test->count);
+	if (count != 0)
+		return false;
+
+	width = ops->io_readb(&test->width);
+	if (width != 1 && width != 2 && width != 4)
+		return false;
+
+	sig = ops->io_readl(&test->data);
+	off = ops->io_readl(&test->offset);
+
+	for (i = 0; i < nr_writes; i++) {
+		switch (width) {
+		case 1: ops->io_writeb(sig, (void *)test + off); break;
+		case 2: ops->io_writew(sig, (void *)test + off); break;
+		case 4: ops->io_writel(sig, (void *)test + off); break;
+		}
+	}
+
+	count = ops->io_readl(&test->count);
+	if (!count)
+		return true;
+
+	return (int)count == nr_writes;
+}
+
+void pci_testdev_print(struct pci_test_dev_hdr *test,
+		       struct pci_testdev_ops *ops)
+{
+	bool io = (ops == &pci_testdev_io_ops);
+	int i;
+
+	printf("pci-testdev %3s: ", io ? "io" : "mem");
+	for (i = 0;; ++i) {
+		char c = ops->io_readb(&test->name[i]);
+		if (!c)
+			break;
+		printf("%c", c);
+	}
+	printf("\n");
+}
+
+static int pci_testdev_all(struct pci_test_dev_hdr *test,
+			   struct pci_testdev_ops *ops)
+{
+	int i;
+
+	for (i = 0;; i++) {
+		if (!pci_testdev_one(test, i, ops))
+			break;
+		pci_testdev_print(test, ops);
+	}
+
+	return i;
+}
+
+int pci_testdev(void)
+{
+	phys_addr_t addr;
+	void __iomem *mem, *io;
+	pcidevaddr_t dev;
+	int nr_tests = 0;
+
+	dev = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST);
+	if (dev == PCIDEVADDR_INVALID)
+		return -1;
+
+	if (!pci_bar_is_valid(dev, 0) || !pci_bar_is_valid(dev, 1))
+		return -1;
+
+	addr = pci_bar_get_addr(dev, 0);
+	mem = ioremap(addr, PAGE_SIZE);
+
+	addr = pci_bar_get_addr(dev, 1);
+	io = (void *)(unsigned long)addr;
+
+	nr_tests += pci_testdev_all(mem, &pci_testdev_mem_ops);
+	nr_tests += pci_testdev_all(io, &pci_testdev_io_ops);
+
+	return nr_tests;
+}
diff --git a/lib/pci.h b/lib/pci.h
index e00e1471d80a..5afe87a66998 100644
--- a/lib/pci.h
+++ b/lib/pci.h
@@ -40,6 +40,8 @@ bool pci_bar_is64(pcidevaddr_t dev, int bar_num);
 bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num);
 bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num);
 
+int pci_testdev(void);
+
 /*
  * pci-testdev is a driver for the pci-testdev qemu pci device. The
  * device enables testing mmio and portio exits, and measuring their
@@ -48,7 +50,12 @@ bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num);
 #define PCI_VENDOR_ID_REDHAT		0x1b36
 #define PCI_DEVICE_ID_REDHAT_TEST	0x0005
 
+/*
+ * pci-testdev supports at least three types of tests (via mmio and
+ * portio BARs): no-eventfd, wildcard-eventfd and datamatch-eventfd
+ */
 #define PCI_TESTDEV_NUM_BARS		2
+#define PCI_TESTDEV_NUM_TESTS		3
 
 struct pci_test_dev_hdr {
 	uint8_t  test;
-- 
1.8.3.1

[kvm-unit-tests PATCH v5 12/12] arm/arm64: pci: Add pci-testdev PCI device operation test

[Alexander Gordeev]

Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
 arm/Makefile.common |  1 +
 arm/pci-test.c      | 14 ++++++++++++--
 arm/run             |  7 ++++++-
 3 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/arm/Makefile.common b/arm/Makefile.common
index 97179bbea4e7..f37b5c2a3de4 100644
--- a/arm/Makefile.common
+++ b/arm/Makefile.common
@@ -36,6 +36,7 @@ cflatobjs += lib/alloc.o
 cflatobjs += lib/devicetree.o
 cflatobjs += lib/pci.o
 cflatobjs += lib/pci-host-generic.o
+cflatobjs += lib/pci-testdev.o
 cflatobjs += lib/virtio.o
 cflatobjs += lib/virtio-mmio.o
 cflatobjs += lib/chr-testdev.o
diff --git a/arm/pci-test.c b/arm/pci-test.c
index fde5495dd626..be228320e8c7 100644
--- a/arm/pci-test.c
+++ b/arm/pci-test.c
@@ -13,9 +13,19 @@ int main(void)
 	int ret = pci_probe();
 
 	report("PCI bus probing", ret);
+	if (!ret)
+		goto done;
 
-	if (ret)
-		pci_print();
+	pci_print();
 
+	if (pci_find_dev(PCI_VENDOR_ID_REDHAT,
+			 PCI_DEVICE_ID_REDHAT_TEST) == PCIDEVADDR_INVALID)
+		goto done;
+
+	ret = pci_testdev();
+	report("PCI test device passed %d tests",
+		ret >= PCI_TESTDEV_NUM_BARS * PCI_TESTDEV_NUM_TESTS, ret);
+
+done:
 	return report_summary();
 }
diff --git a/arm/run b/arm/run
index a2f35ef6a7e6..1ee6231599d6 100755
--- a/arm/run
+++ b/arm/run
@@ -67,8 +67,13 @@ fi
 chr_testdev='-device virtio-serial-device'
 chr_testdev+=' -device virtconsole,chardev=ctd -chardev testdev,id=ctd'
 
+pci_testdev=
+if $qemu $M -device '?' 2>&1 | grep pci-testdev > /dev/null; then
+	pci_testdev="-device pci-testdev"
+fi
+
 M+=",accel=$ACCEL"
-command="$qemu $M -cpu $processor $chr_testdev"
+command="$qemu $M -cpu $processor $chr_testdev $pci_testdev"
 command+=" -display none -serial stdio -kernel"
 command="$(timeout_cmd) $command"
 echo $command "$@"
-- 
1.8.3.1

Re: [kvm-unit-tests PATCH v5 01/12] pci: Fix coding style in generic PCI files

[Andrew Jones]

On Tue, Jul 19, 2016 at 02:52:58PM +0200, Alexander Gordeev wrote:
> Cc: Thomas Huth <thuth@redhat.com>
> Cc: Andrew Jones <drjones@redhat.com>
> Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
> ---
>  lib/pci.c | 38 ++++++++++++++++++++------------------
>  lib/pci.h |  3 ++-
>  2 files changed, 22 insertions(+), 19 deletions(-)

Reviewed-by: Andrew Jones <drjones@redhat.com>

> 
> diff --git a/lib/pci.c b/lib/pci.c
> index 0058d70c888d..43cd0ea4f2fa 100644
> --- a/lib/pci.c
> +++ b/lib/pci.c
> @@ -10,34 +10,36 @@
>  /* Scan bus look for a specific device. Only bus 0 scanned for now. */
>  pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)
>  {
> -    unsigned dev;
> -    for (dev = 0; dev < 256; ++dev) {
> -    uint32_t id = pci_config_read(dev, 0);
> -    if ((id & 0xFFFF) == vendor_id && (id >> 16) == device_id) {
> -        return dev;
> -    }
> -    }
> -    return PCIDEVADDR_INVALID;
> +	pcidevaddr_t dev;
> +
> +	for (dev = 0; dev < 256; ++dev) {
> +		uint32_t id = pci_config_read(dev, 0);
> +
> +		if ((id & 0xFFFF) == vendor_id && (id >> 16) == device_id)
> +			return dev;
> +	}
> +
> +	return PCIDEVADDR_INVALID;
>  }
>  
>  unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num)
>  {
> -    uint32_t bar = pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
> -    if (bar & PCI_BASE_ADDRESS_SPACE_IO) {
> -        return bar & PCI_BASE_ADDRESS_IO_MASK;
> -    } else {
> -        return bar & PCI_BASE_ADDRESS_MEM_MASK;
> -    }
> +	uint32_t bar = pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
> +
> +	if (bar & PCI_BASE_ADDRESS_SPACE_IO)
> +		return bar & PCI_BASE_ADDRESS_IO_MASK;
> +	else
> +		return bar & PCI_BASE_ADDRESS_MEM_MASK;
>  }
>  
>  bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num)
>  {
> -    uint32_t bar = pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
> -    return !(bar & PCI_BASE_ADDRESS_SPACE_IO);
> +	uint32_t bar = pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
> +
> +	return !(bar & PCI_BASE_ADDRESS_SPACE_IO);
>  }
>  
>  bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num)
>  {
> -    uint32_t bar = pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
> -    return bar;
> +	return pci_config_read(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
>  }
> diff --git a/lib/pci.h b/lib/pci.h
> index 9160cfb5950d..54fbf22d634a 100644
> --- a/lib/pci.h
> +++ b/lib/pci.h
> @@ -12,8 +12,9 @@
>  
>  typedef uint16_t pcidevaddr_t;
>  enum {
> -    PCIDEVADDR_INVALID = 0xffff,
> +	PCIDEVADDR_INVALID = 0xffff,
>  };
> +
>  pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);
>  unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num);
>  bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num);
> -- 
> 1.8.3.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe kvm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [kvm-unit-tests PATCH v5 04/12] pci: Rework pci_bar_addr()

[Andrew Jones]

On Tue, Jul 19, 2016 at 02:53:01PM +0200, Alexander Gordeev wrote:
> This update makes pci_bar_addr() interface 64 bit BARs aware and
> introduces a concept of PCI address translation.
> 
> An architecutre should implement pci_translate_addr() interface
> in order to provide mapping between PCI bus address and CPU
> physical address.
> 
> Cc: Thomas Huth <thuth@redhat.com>
> Cc: Andrew Jones <drjones@redhat.com>
> Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
> ---
>  lib/pci.c         | 76 ++++++++++++++++++++++++++++++++++++++++++++++++++-----
>  lib/pci.h         | 16 +++++++++++-
>  lib/x86/asm/pci.h |  6 +++++
>  3 files changed, 91 insertions(+), 7 deletions(-)
> 
> diff --git a/lib/pci.c b/lib/pci.c
> index b05ecfa3f3da..e3e8dfda6c87 100644
> --- a/lib/pci.c
> +++ b/lib/pci.c
> @@ -21,14 +21,67 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)
>  	return PCIDEVADDR_INVALID;
>  }
>  
> -unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num)
> +static uint32_t pci_bar_mask(uint32_t bar)
>  {
> -	uint32_t bar = pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
> +	return (bar & PCI_BASE_ADDRESS_SPACE_IO) ?
> +		PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK;
> +}
>  
> -	if (bar & PCI_BASE_ADDRESS_SPACE_IO)
> -		return bar & PCI_BASE_ADDRESS_IO_MASK;
> -	else
> -		return bar & PCI_BASE_ADDRESS_MEM_MASK;
> +phys_addr_t pci_bar_addr(pcidevaddr_t dev, int bar_num)
> +{
> +	int off = PCI_BASE_ADDRESS_0 + bar_num * 4;
> +	uint32_t bar = pci_config_readl(dev, off);
> +	uint32_t mask = pci_bar_mask(bar);
> +	uint64_t addr = bar & mask;
> +
> +	if (pci_bar_is64(dev, bar_num))
> +		addr |= (uint64_t)pci_config_readl(dev, off + 4) << 32;
> +
> +	return pci_translate_addr(dev, addr);
> +}
> +
> +/*
> + * To determine the amount of address space needed by a PCI device,
> + * one must save the original value of the BAR, write a value of
> + * all 1's to the register, then read it back. The amount of memory
                              ^and
> + * can then be then determined by masking the information bits,
extra 'then'
> + * performing a bitwise NOT and incrementing the value by 1.
                              ^,
> + *
> + * The following pci_bar_size_helper() and pci_bar_size() functions do
> + * the described algorithm.
/do the described/implement the/
> + */
> +static uint32_t pci_bar_size_helper(pcidevaddr_t dev, int bar_num)
> +{
> +	int off = PCI_BASE_ADDRESS_0 + bar_num * 4;
> +	uint32_t bar, size;
> +
> +	bar = pci_config_readl(dev, off);
> +	pci_config_writel(dev, off, ~0u);
> +	size = pci_config_readl(dev, off);
> +	pci_config_writel(dev, off, bar);
> +
> +	return size;
> +}
> +
> +phys_addr_t pci_bar_size(pcidevaddr_t dev, int bar_num)
> +{
> +	uint32_t bar, size;
> +
> +	size = pci_bar_size_helper(dev, bar_num);
> +	if (!size)
> +		return 0;
> +
> +	bar = pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
> +	size &= pci_bar_mask(bar);
> +
> +	if (pci_bar_is64(dev, bar_num)) {
> +		phys_addr_t size64 = pci_bar_size_helper(dev, bar_num + 1);
> +		size64 = (size64 << 32) | size;
> +
> +		return ~size64 + 1;
> +	} else {
> +		return ~size + 1;
> +	}
>  }
>  
>  bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num)
> @@ -42,3 +95,14 @@ bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num)
>  {
>  	return pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
>  }
> +
> +bool pci_bar_is64(pcidevaddr_t dev, int bar_num)
> +{
> +	uint32_t bar = pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
> +
> +	if (bar & PCI_BASE_ADDRESS_SPACE_IO)
> +		return false;
> +
> +	return (bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
> +		      PCI_BASE_ADDRESS_MEM_TYPE_64;
> +}
> diff --git a/lib/pci.h b/lib/pci.h
> index 54fbf22d634a..4d3e8d385eb1 100644
> --- a/lib/pci.h
> +++ b/lib/pci.h
> @@ -16,7 +16,21 @@ enum {
>  };
>  
>  pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);
> -unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num);
> +
> +/*
> + * BAR number in all BAR access functions below is a number of 32-bit
s/BAR number/@bar_num/
s/a number/the index/
s/32-bit/the 32-bit/
> + * register starting from PCI_BASE_ADDRESS_0 offset.
s/PCI_BASE_ADDRESS_0/the PCI_BASE_ADDRESS_0/
> + *
> + * In cases BAR size is 64-bit a caller should still provide BAR number
s/BAR size/where the BAR size/   ^,
s/BAR number/@bar_num/
> + * in terms of 32-bit words. For example, if a device has 64-bit BAR#0
                                                            ^a
> + * and 32-bit BAR#1 the caller should provide 2 to address BAR#1, not 1.
         ^a           ^, then
> + *
> + * It is expected the caller is aware of the device BAR layout and never
> + * tries to address in the middle of a 64-bit register.
remove 'in'
> + */
> +phys_addr_t pci_bar_addr(pcidevaddr_t dev, int bar_num);
> +phys_addr_t pci_bar_size(pcidevaddr_t dev, int bar_num);
> +bool pci_bar_is64(pcidevaddr_t dev, int bar_num);
>  bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num);
>  bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num);
>  
> diff --git a/lib/x86/asm/pci.h b/lib/x86/asm/pci.h
> index 821a2c1e180a..7384b91adba1 100644
> --- a/lib/x86/asm/pci.h
> +++ b/lib/x86/asm/pci.h
> @@ -35,4 +35,10 @@ static inline void pci_config_writel(pcidevaddr_t dev, uint8_t reg, uint32_t val
>      outl(val, 0xCFC);
>  }
>  
> +static inline
> +phys_addr_t pci_translate_addr(pcidevaddr_t dev __unused, uint64_t addr)
> +{
> +    return addr;
> +}
> +
>  #endif
> -- 
> 1.8.3.1
>

Besides the comment edits

Reviewed-by: Andrew Jones <drjones@redhat.com>

Re: [kvm-unit-tests PATCH v5 12/12] arm/arm64: pci: Add pci-testdev PCI device operation test

[Alexander Gordeev]

On Tue, Jul 19, 2016 at 02:53:09PM +0200, Alexander Gordeev wrote:
> Cc: Thomas Huth <thuth@redhat.com>
> Cc: Andrew Jones <drjones@redhat.com>
> Signed-off-by: Alexander Gordeev <agordeev@redhat.com>

This patch already has Andrew's Reviewed-by, I will ropost it with the tag.

[kvm-unit-tests PATCH v6 04/12] pci: Rework pci_bar_addr()

[Alexander Gordeev]

This update makes pci_bar_addr() interface 64 bit BARs aware and
introduces a concept of PCI address translation.

An architecutre should implement pci_translate_addr() interface
in order to provide mapping between PCI bus address and CPU
physical address.

Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
 lib/pci.c         | 76 ++++++++++++++++++++++++++++++++++++++++++++++++++-----
 lib/pci.h         | 17 ++++++++++++-
 lib/x86/asm/pci.h |  6 +++++
 3 files changed, 92 insertions(+), 7 deletions(-)

diff --git a/lib/pci.c b/lib/pci.c
index b05ecfa3f3da..5305fc765f83 100644
--- a/lib/pci.c
+++ b/lib/pci.c
@@ -21,14 +21,67 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)
 	return PCIDEVADDR_INVALID;
 }
 
-unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num)
+static uint32_t pci_bar_mask(uint32_t bar)
 {
-	uint32_t bar = pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
+	return (bar & PCI_BASE_ADDRESS_SPACE_IO) ?
+		PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK;
+}
 
-	if (bar & PCI_BASE_ADDRESS_SPACE_IO)
-		return bar & PCI_BASE_ADDRESS_IO_MASK;
-	else
-		return bar & PCI_BASE_ADDRESS_MEM_MASK;
+phys_addr_t pci_bar_addr(pcidevaddr_t dev, int bar_num)
+{
+	int off = PCI_BASE_ADDRESS_0 + bar_num * 4;
+	uint32_t bar = pci_config_readl(dev, off);
+	uint32_t mask = pci_bar_mask(bar);
+	uint64_t addr = bar & mask;
+
+	if (pci_bar_is64(dev, bar_num))
+		addr |= (uint64_t)pci_config_readl(dev, off + 4) << 32;
+
+	return pci_translate_addr(dev, addr);
+}
+
+/*
+ * To determine the amount of address space needed by a PCI device,
+ * one must save the original value of the BAR, write a value of
+ * all 1's to the register, and then read it back. The amount of
+ * memory can be then determined by masking the information bits,
+ * performing a bitwise NOT, and incrementing the value by 1.
+ *
+ * The following pci_bar_size_helper() and pci_bar_size() functions
+ * implement the algorithm.
+ */
+static uint32_t pci_bar_size_helper(pcidevaddr_t dev, int bar_num)
+{
+	int off = PCI_BASE_ADDRESS_0 + bar_num * 4;
+	uint32_t bar, size;
+
+	bar = pci_config_readl(dev, off);
+	pci_config_writel(dev, off, ~0u);
+	size = pci_config_readl(dev, off);
+	pci_config_writel(dev, off, bar);
+
+	return size;
+}
+
+phys_addr_t pci_bar_size(pcidevaddr_t dev, int bar_num)
+{
+	uint32_t bar, size;
+
+	size = pci_bar_size_helper(dev, bar_num);
+	if (!size)
+		return 0;
+
+	bar = pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
+	size &= pci_bar_mask(bar);
+
+	if (pci_bar_is64(dev, bar_num)) {
+		phys_addr_t size64 = pci_bar_size_helper(dev, bar_num + 1);
+		size64 = (size64 << 32) | size;
+
+		return ~size64 + 1;
+	} else {
+		return ~size + 1;
+	}
 }
 
 bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num)
@@ -42,3 +95,14 @@ bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num)
 {
 	return pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
 }
+
+bool pci_bar_is64(pcidevaddr_t dev, int bar_num)
+{
+	uint32_t bar = pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
+
+	if (bar & PCI_BASE_ADDRESS_SPACE_IO)
+		return false;
+
+	return (bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
+		      PCI_BASE_ADDRESS_MEM_TYPE_64;
+}
diff --git a/lib/pci.h b/lib/pci.h
index 54fbf22d634a..ff666c9a84db 100644
--- a/lib/pci.h
+++ b/lib/pci.h
@@ -16,7 +16,22 @@ enum {
 };
 
 pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);
-unsigned long pci_bar_addr(pcidevaddr_t dev, int bar_num);
+
+/*
+ * @bar_num in all BAR access functions below is the index of the 32-bit
+ * register starting from the PCI_BASE_ADDRESS_0 offset.
+ *
+ * In cases where the BAR size is 64-bit, a caller should still provide
+ * @bar_num in terms of 32-bit words. For example, if a device has a 64-bit
+ * BAR#0 and a 32-bit BAR#1, then caller should provide 2 to address BAR#1,
+ * not 1.
+ *
+ * It is expected the caller is aware of the device BAR layout and never
+ * tries to address the middle of a 64-bit register.
+ */
+phys_addr_t pci_bar_addr(pcidevaddr_t dev, int bar_num);
+phys_addr_t pci_bar_size(pcidevaddr_t dev, int bar_num);
+bool pci_bar_is64(pcidevaddr_t dev, int bar_num);
 bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num);
 bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num);
 
diff --git a/lib/x86/asm/pci.h b/lib/x86/asm/pci.h
index 821a2c1e180a..7384b91adba1 100644
--- a/lib/x86/asm/pci.h
+++ b/lib/x86/asm/pci.h
@@ -35,4 +35,10 @@ static inline void pci_config_writel(pcidevaddr_t dev, uint8_t reg, uint32_t val
     outl(val, 0xCFC);
 }
 
+static inline
+phys_addr_t pci_translate_addr(pcidevaddr_t dev __unused, uint64_t addr)
+{
+    return addr;
+}
+
 #endif
-- 
1.8.3.1

[kvm-unit-tests PATCH v5 12/12] arm/arm64: pci: Add pci-testdev PCI device operation test

[Alexander Gordeev]

Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
 arm/Makefile.common |  1 +
 arm/pci-test.c      | 14 ++++++++++++--
 arm/run             |  7 ++++++-
 3 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/arm/Makefile.common b/arm/Makefile.common
index 97179bbea4e7..f37b5c2a3de4 100644
--- a/arm/Makefile.common
+++ b/arm/Makefile.common
@@ -36,6 +36,7 @@ cflatobjs += lib/alloc.o
 cflatobjs += lib/devicetree.o
 cflatobjs += lib/pci.o
 cflatobjs += lib/pci-host-generic.o
+cflatobjs += lib/pci-testdev.o
 cflatobjs += lib/virtio.o
 cflatobjs += lib/virtio-mmio.o
 cflatobjs += lib/chr-testdev.o
diff --git a/arm/pci-test.c b/arm/pci-test.c
index fde5495dd626..be228320e8c7 100644
--- a/arm/pci-test.c
+++ b/arm/pci-test.c
@@ -13,9 +13,19 @@ int main(void)
 	int ret = pci_probe();
 
 	report("PCI bus probing", ret);
+	if (!ret)
+		goto done;
 
-	if (ret)
-		pci_print();
+	pci_print();
 
+	if (pci_find_dev(PCI_VENDOR_ID_REDHAT,
+			 PCI_DEVICE_ID_REDHAT_TEST) == PCIDEVADDR_INVALID)
+		goto done;
+
+	ret = pci_testdev();
+	report("PCI test device passed %d tests",
+		ret >= PCI_TESTDEV_NUM_BARS * PCI_TESTDEV_NUM_TESTS, ret);
+
+done:
 	return report_summary();
 }
diff --git a/arm/run b/arm/run
index a2f35ef6a7e6..1ee6231599d6 100755
--- a/arm/run
+++ b/arm/run
@@ -67,8 +67,13 @@ fi
 chr_testdev='-device virtio-serial-device'
 chr_testdev+=' -device virtconsole,chardev=ctd -chardev testdev,id=ctd'
 
+pci_testdev=
+if $qemu $M -device '?' 2>&1 | grep pci-testdev > /dev/null; then
+	pci_testdev="-device pci-testdev"
+fi
+
 M+=",accel=$ACCEL"
-command="$qemu $M -cpu $processor $chr_testdev"
+command="$qemu $M -cpu $processor $chr_testdev $pci_testdev"
 command+=" -display none -serial stdio -kernel"
 command="$(timeout_cmd) $command"
 echo $command "$@"
-- 
1.8.3.1

Re: [kvm-unit-tests PATCH v5 05/12] pci: Factor out pci_bar_get()

[Andrew Jones]

Was there a reason we didn't just introduce pci_bar_get a few
patches ago, and then use it from the get-go for all the new
functions? It's not worth respinning for, IMO, but if we do
spin another version, then I think it'd be a nice series cleanup.

Thanks,
drew


On Tue, Jul 19, 2016 at 02:53:02PM +0200, Alexander Gordeev wrote:
> Cc: Thomas Huth <thuth@redhat.com>
> Cc: Andrew Jones <drjones@redhat.com>
> Reviewed-by: Andrew Jones <drjones@redhat.com>
> Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
> ---
>  lib/pci.c | 18 +++++++++++-------
>  1 file changed, 11 insertions(+), 7 deletions(-)
> 
> diff --git a/lib/pci.c b/lib/pci.c
> index e3e8dfda6c87..cd8c13e87e3b 100644
> --- a/lib/pci.c
> +++ b/lib/pci.c
> @@ -27,15 +27,19 @@ static uint32_t pci_bar_mask(uint32_t bar)
>  		PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK;
>  }
>  
> +static uint32_t pci_bar_get(pcidevaddr_t dev, int bar_num)
> +{
> +	return pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
> +}
> +
>  phys_addr_t pci_bar_addr(pcidevaddr_t dev, int bar_num)
>  {
> -	int off = PCI_BASE_ADDRESS_0 + bar_num * 4;
> -	uint32_t bar = pci_config_readl(dev, off);
> +	uint32_t bar = pci_bar_get(dev, bar_num);
>  	uint32_t mask = pci_bar_mask(bar);
>  	uint64_t addr = bar & mask;
>  
>  	if (pci_bar_is64(dev, bar_num))
> -		addr |= (uint64_t)pci_config_readl(dev, off + 4) << 32;
> +		addr |= (uint64_t)pci_bar_get(dev, bar_num + 1) << 32;
>  
>  	return pci_translate_addr(dev, addr);
>  }
> @@ -71,7 +75,7 @@ phys_addr_t pci_bar_size(pcidevaddr_t dev, int bar_num)
>  	if (!size)
>  		return 0;
>  
> -	bar = pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
> +	bar = pci_bar_get(dev, bar_num);
>  	size &= pci_bar_mask(bar);
>  
>  	if (pci_bar_is64(dev, bar_num)) {
> @@ -86,19 +90,19 @@ phys_addr_t pci_bar_size(pcidevaddr_t dev, int bar_num)
>  
>  bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num)
>  {
> -	uint32_t bar = pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
> +	uint32_t bar = pci_bar_get(dev, bar_num);
>  
>  	return !(bar & PCI_BASE_ADDRESS_SPACE_IO);
>  }
>  
>  bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num)
>  {
> -	return pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
> +	return pci_bar_get(dev, bar_num);
>  }
>  
>  bool pci_bar_is64(pcidevaddr_t dev, int bar_num)
>  {
> -	uint32_t bar = pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
> +	uint32_t bar = pci_bar_get(dev, bar_num);
>  
>  	if (bar & PCI_BASE_ADDRESS_SPACE_IO)
>  		return false;
> -- 
> 1.8.3.1
> 

Re: [kvm-unit-tests PATCH v5 11/12] pci: Add pci-testdev PCI bus test device

[Andrew Jones]

On Tue, Jul 19, 2016 at 02:53:08PM +0200, Alexander Gordeev wrote:
> Cc: Thomas Huth <thuth@redhat.com>
> Cc: Andrew Jones <drjones@redhat.com>
> Reviewed-by: Andrew Jones <drjones@redhat.com>
> Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
> ---
>  lib/pci-testdev.c | 188 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  lib/pci.h         |   7 ++
>  2 files changed, 195 insertions(+)
>  create mode 100644 lib/pci-testdev.c
> 
> diff --git a/lib/pci-testdev.c b/lib/pci-testdev.c
> new file mode 100644
> index 000000000000..1ee4a3ca0df8
> --- /dev/null
> +++ b/lib/pci-testdev.c
> @@ -0,0 +1,188 @@
> +/*
> + * QEMU "pci-testdev" PCI test device
> + *
> + * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
> + *
> + * This work is licensed under the terms of the GNU LGPL, version 2.
> + */
> +#include "pci.h"
> +#include "asm/io.h"
> +
> +struct pci_testdev_ops {
> +	u8 (*io_readb)(const volatile void *addr);
> +	u16 (*io_readw)(const volatile void *addr);
> +	u32 (*io_readl)(const volatile void *addr);
> +	void (*io_writeb)(u8 value, volatile void *addr);
> +	void (*io_writew)(u16 value, volatile void *addr);
> +	void (*io_writel)(u32 value, volatile void *addr);
> +};
> +
> +static u8 pio_readb(const volatile void *addr)
> +{
> +	return inb((unsigned long)addr);
> +}
> +
> +static u16 pio_readw(const volatile void *addr)
> +{
> +	return inw((unsigned long)addr);
> +}
> +
> +static u32 pio_readl(const volatile void *addr)
> +{
> +	return inl((unsigned long)addr);
> +}
> +
> +static void pio_writeb(u8 value, volatile void *addr)
> +{
> +	outb(value, (unsigned long)addr);
> +}
> +
> +static void pio_writew(u16 value, volatile void *addr)
> +{
> +	outw(value, (unsigned long)addr);
> +}
> +
> +static void pio_writel(u32 value, volatile void *addr)
> +{
> +	outl(value, (unsigned long)addr);
> +}
> +
> +static struct pci_testdev_ops pci_testdev_io_ops = {
> +	.io_readb	= pio_readb,
> +	.io_readw	= pio_readw,
> +	.io_readl	= pio_readl,
> +	.io_writeb	= pio_writeb,
> +	.io_writew	= pio_writew,
> +	.io_writel	= pio_writel
> +};
> +
> +static u8 mmio_readb(const volatile void *addr)
> +{
> +	return *(const volatile u8 __force *)addr;
> +}
> +
> +static u16 mmio_readw(const volatile void *addr)
> +{
> +	return *(const volatile u16 __force *)addr;
> +}
> +
> +static u32 mmio_readl(const volatile void *addr)
> +{
> +	return *(const volatile u32 __force *)addr;
> +}
> +
> +static void mmio_writeb(u8 value, volatile void *addr)
> +{
> +	*(volatile u8 __force *)addr = value;
> +}
> +
> +static void mmio_writew(u16 value, volatile void *addr)
> +{
> +	*(volatile u16 __force *)addr = value;
> +}
> +
> +static void mmio_writel(u32 value, volatile void *addr)
> +{
> +	*(volatile u32 __force *)addr = value;
> +}
> +
> +static struct pci_testdev_ops pci_testdev_mem_ops = {
> +	.io_readb	= mmio_readb,
> +	.io_readw	= mmio_readw,
> +	.io_readl	= mmio_readl,
> +	.io_writeb	= mmio_writeb,
> +	.io_writew	= mmio_writew,
> +	.io_writel	= mmio_writel
> +};
> +
> +static bool pci_testdev_one(struct pci_test_dev_hdr *test,
> +			    int test_nr,
> +			    struct pci_testdev_ops *ops)
> +{
> +	u8 width;
> +	u32 count, sig, off;
> +	const int nr_writes = 16;
> +	int i;
> +
> +	ops->io_writeb(test_nr, &test->test);
> +	count = ops->io_readl(&test->count);
> +	if (count != 0)
> +		return false;
> +
> +	width = ops->io_readb(&test->width);
> +	if (width != 1 && width != 2 && width != 4)
> +		return false;
> +
> +	sig = ops->io_readl(&test->data);
> +	off = ops->io_readl(&test->offset);
> +
> +	for (i = 0; i < nr_writes; i++) {
> +		switch (width) {
> +		case 1: ops->io_writeb(sig, (void *)test + off); break;
> +		case 2: ops->io_writew(sig, (void *)test + off); break;
> +		case 4: ops->io_writel(sig, (void *)test + off); break;
> +		}
> +	}
> +
> +	count = ops->io_readl(&test->count);
> +	if (!count)
> +		return true;
> +
> +	return (int)count == nr_writes;
> +}
> +
> +void pci_testdev_print(struct pci_test_dev_hdr *test,
> +		       struct pci_testdev_ops *ops)
> +{
> +	bool io = (ops == &pci_testdev_io_ops);
> +	int i;
> +
> +	printf("pci-testdev %3s: ", io ? "io" : "mem");
> +	for (i = 0;; ++i) {
> +		char c = ops->io_readb(&test->name[i]);
> +		if (!c)
> +			break;
> +		printf("%c", c);
> +	}
> +	printf("\n");
> +}
> +
> +static int pci_testdev_all(struct pci_test_dev_hdr *test,
> +			   struct pci_testdev_ops *ops)
> +{
> +	int i;
> +
> +	for (i = 0;; i++) {
> +		if (!pci_testdev_one(test, i, ops))
> +			break;
> +		pci_testdev_print(test, ops);
> +	}
> +
> +	return i;
> +}
> +
> +int pci_testdev(void)
> +{
> +	phys_addr_t addr;
> +	void __iomem *mem, *io;
> +	pcidevaddr_t dev;
> +	int nr_tests = 0;
> +
> +	dev = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST);
> +	if (dev == PCIDEVADDR_INVALID)

You should output an error message here, saying it's not found. You could
suggest how to provide it, i.e. '-device pci-testdev' too.

> +		return -1;
> +
> +	if (!pci_bar_is_valid(dev, 0) || !pci_bar_is_valid(dev, 1))

Needs error message. Actually, why can this happen? Can it? Shouldn't
this just be an assert?

> +		return -1;
> +
> +	addr = pci_bar_get_addr(dev, 0);
> +	mem = ioremap(addr, PAGE_SIZE);
> +
> +	addr = pci_bar_get_addr(dev, 1);
> +	io = (void *)(unsigned long)addr;
> +
> +	nr_tests += pci_testdev_all(mem, &pci_testdev_mem_ops);
> +	nr_tests += pci_testdev_all(io, &pci_testdev_io_ops);
> +
> +	return nr_tests;
> +}
> diff --git a/lib/pci.h b/lib/pci.h
> index e00e1471d80a..5afe87a66998 100644
> --- a/lib/pci.h
> +++ b/lib/pci.h
> @@ -40,6 +40,8 @@ bool pci_bar_is64(pcidevaddr_t dev, int bar_num);
>  bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num);
>  bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num);
>  
> +int pci_testdev(void);
> +
>  /*
>   * pci-testdev is a driver for the pci-testdev qemu pci device. The
>   * device enables testing mmio and portio exits, and measuring their
> @@ -48,7 +50,12 @@ bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num);
>  #define PCI_VENDOR_ID_REDHAT		0x1b36
>  #define PCI_DEVICE_ID_REDHAT_TEST	0x0005
>  
> +/*
> + * pci-testdev supports at least three types of tests (via mmio and
> + * portio BARs): no-eventfd, wildcard-eventfd and datamatch-eventfd
> + */
>  #define PCI_TESTDEV_NUM_BARS		2
> +#define PCI_TESTDEV_NUM_TESTS		3
>  
>  struct pci_test_dev_hdr {
>  	uint8_t  test;
> -- 
> 1.8.3.1
> 
> --
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Re: [kvm-unit-tests PATCH v5 12/12] arm/arm64: pci: Add pci-testdev PCI device operation test

[Andrew Jones]

On Wed, Jul 20, 2016 at 08:23:08PM +0200, Alexander Gordeev wrote:
> Cc: Thomas Huth <thuth@redhat.com>
> Cc: Andrew Jones <drjones@redhat.com>
> Reviewed-by: Andrew Jones <drjones@redhat.com>
> Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
> ---
>  arm/Makefile.common |  1 +
>  arm/pci-test.c      | 14 ++++++++++++--
>  arm/run             |  7 ++++++-
>  3 files changed, 19 insertions(+), 3 deletions(-)
> 
> diff --git a/arm/Makefile.common b/arm/Makefile.common
> index 97179bbea4e7..f37b5c2a3de4 100644
> --- a/arm/Makefile.common
> +++ b/arm/Makefile.common
> @@ -36,6 +36,7 @@ cflatobjs += lib/alloc.o
>  cflatobjs += lib/devicetree.o
>  cflatobjs += lib/pci.o
>  cflatobjs += lib/pci-host-generic.o
> +cflatobjs += lib/pci-testdev.o
>  cflatobjs += lib/virtio.o
>  cflatobjs += lib/virtio-mmio.o
>  cflatobjs += lib/chr-testdev.o
> diff --git a/arm/pci-test.c b/arm/pci-test.c
> index fde5495dd626..be228320e8c7 100644
> --- a/arm/pci-test.c
> +++ b/arm/pci-test.c
> @@ -13,9 +13,19 @@ int main(void)
>  	int ret = pci_probe();
>  
>  	report("PCI bus probing", ret);
> +	if (!ret)
> +		goto done;

I don't think probing should be a test. The only way it can currently
fail is if the DT isn't found, or if the DT doesn't contain the pcie
host bridge. For arm (mach-virt) neither of those should ever happen.
Instead we should complain loudly and abort. Calling abort will allow
you to remove the label and gotos too.

>  
> -	if (ret)
> -		pci_print();
> +	pci_print();
>  
> +	if (pci_find_dev(PCI_VENDOR_ID_REDHAT,
> +			 PCI_DEVICE_ID_REDHAT_TEST) == PCIDEVADDR_INVALID)

If you add the error messages to the previous patch that I suggested,
then you don't need this.

> +		goto done;
> +
> +	ret = pci_testdev();
> +	report("PCI test device passed %d tests",
> +		ret >= PCI_TESTDEV_NUM_BARS * PCI_TESTDEV_NUM_TESTS, ret);

If pci_testdev returns -1 then you'll report that -1 tests passed. We
need to convert that to 0. Also we need know how many tests were attempted
so we can report the more informative ...passed %d/%d tests.

> +
> +done:
>  	return report_summary();

Just to be clear how I think this should look

 #define NR_TESTS (PCI_TESTDEV_NUM_BARS * PCI_TESTDEV_NUM_TESTS)
 main()
 {
   if (!pci_probe()) {
      printf(...);
      abort();
   }

   pci_print();

   ret = pci_testdev();
   report("...%d/%d...", ret >= NR_TESTS, ret > 0 ? ret : 0, NR_TESTS);
   return report_summary();
 }

>  }
> diff --git a/arm/run b/arm/run
> index a2f35ef6a7e6..1ee6231599d6 100755
> --- a/arm/run
> +++ b/arm/run
> @@ -67,8 +67,13 @@ fi
>  chr_testdev='-device virtio-serial-device'
>  chr_testdev+=' -device virtconsole,chardev=ctd -chardev testdev,id=ctd'
>  
> +pci_testdev=
> +if $qemu $M -device '?' 2>&1 | grep pci-testdev > /dev/null; then
> +	pci_testdev="-device pci-testdev"
> +fi
> +
>  M+=",accel=$ACCEL"
> -command="$qemu $M -cpu $processor $chr_testdev"
> +command="$qemu $M -cpu $processor $chr_testdev $pci_testdev"
>  command+=" -display none -serial stdio -kernel"
>  command="$(timeout_cmd) $command"
>  echo $command "$@"
> -- 
> 1.8.3.1
> 
> --
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> the body of a message to majordomo@vger.kernel.org
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Re: [kvm-unit-tests PATCH v5 08/12] pci: Add pci_print()

[Andrew Jones]

On Tue, Jul 19, 2016 at 02:53:05PM +0200, Alexander Gordeev wrote:
> Cc: Thomas Huth <thuth@redhat.com>
> Cc: Andrew Jones <drjones@redhat.com>
> Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
> ---
>  lib/pci.c | 78 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  lib/pci.h |  3 +++
>  2 files changed, 81 insertions(+)


Reviewed-by: Andrew Jones <drjones@redhat.com>

> 
> diff --git a/lib/pci.c b/lib/pci.c
> index 947bfb2c8f47..f01a085391f3 100644
> --- a/lib/pci.c
> +++ b/lib/pci.c
> @@ -126,3 +126,81 @@ bool pci_bar_is64(pcidevaddr_t dev, int bar_num)
>  	return (bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
>  		      PCI_BASE_ADDRESS_MEM_TYPE_64;
>  }
> +
> +static void pci_dev_print(pcidevaddr_t dev)
> +{
> +	uint16_t vendor_id = pci_config_readw(dev, PCI_VENDOR_ID);
> +	uint16_t device_id = pci_config_readw(dev, PCI_DEVICE_ID);
> +	uint8_t header = pci_config_readb(dev, PCI_HEADER_TYPE);
> +	uint8_t progif = pci_config_readb(dev, PCI_CLASS_PROG);
> +	uint8_t subclass = pci_config_readb(dev, PCI_CLASS_DEVICE);
> +	uint8_t class = pci_config_readb(dev, PCI_CLASS_DEVICE + 1);
> +	int i;
> +
> +	printf("dev %2d fn %d vendor_id %04x device_id %04x type %02x "
> +	       "progif %02x class %02x subclass %02x\n",
> +	       dev / 8, dev % 8, vendor_id, device_id, header,
> +	       progif, class, subclass);
> +
> +	if ((header & PCI_HEADER_TYPE_MASK) != PCI_HEADER_TYPE_NORMAL)
> +		return;
> +
> +	for (i = 0; i < 6; i++) {
> +		phys_addr_t size, start, end;
> +		uint32_t bar;
> +
> +		size = pci_bar_size(dev, i);
> +		if (!size)
> +			continue;
> +
> +		start = pci_bar_get_addr(dev, i);
> +		end = start + size - 1;
> +
> +		if (pci_bar_is64(dev, i)) {
> +			printf("\tBAR#%d,%d [%" PRIx64 "-%" PRIx64 " ",
> +			       i, i + 1, start, end);
> +			i++;
> +		} else {
> +			printf("\tBAR#%d    [%02x-%02x ",
> +			       i, (uint32_t)start, (uint32_t)end);
> +		}
> +
> +		bar = pci_bar_get(dev, i);
> +
> +		if (bar & PCI_BASE_ADDRESS_SPACE_IO) {
> +			printf("PIO]\n");
> +			continue;
> +		}
> +
> +		printf("MEM");
> +
> +		switch (bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
> +		case PCI_BASE_ADDRESS_MEM_TYPE_32:
> +			printf("32");
> +			break;
> +		case PCI_BASE_ADDRESS_MEM_TYPE_1M:
> +			printf("1M");
> +			break;
> +		case PCI_BASE_ADDRESS_MEM_TYPE_64:
> +			printf("64");
> +			break;
> +		default:
> +			assert(0);
> +		}
> +
> +		if (bar & PCI_BASE_ADDRESS_MEM_PREFETCH)
> +			printf("/p");
> +
> +		printf("]\n");
> +	}
> +}
> +
> +void pci_print(void)
> +{
> +	pcidevaddr_t dev;
> +
> +	for (dev = 0; dev < 256; ++dev) {
> +		if (pci_dev_exists(dev))
> +			pci_dev_print(dev);
> +	}
> +}
> diff --git a/lib/pci.h b/lib/pci.h
> index 2efb976d13ea..ff32ea683c94 100644
> --- a/lib/pci.h
> +++ b/lib/pci.h
> @@ -15,6 +15,7 @@ enum {
>  	PCIDEVADDR_INVALID = 0xffff,
>  };
>  
> +void pci_print(void);
>  bool pci_dev_exists(pcidevaddr_t dev);
>  pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);
>  
> @@ -56,4 +57,6 @@ struct pci_test_dev_hdr {
>  	uint8_t  name[];
>  };
>  
> +#define  PCI_HEADER_TYPE_MASK		0x7f
> +
>  #endif /* PCI_H */
> -- 
> 1.8.3.1
> 
> --
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Re: [kvm-unit-tests PATCH v5 09/12] pci: Add generic ECAM host support

[Andrew Jones]

On Tue, Jul 19, 2016 at 02:53:06PM +0200, Alexander Gordeev wrote:
> Unlike x86, other architectures using generic ECAM PCI host
> do not have a luxury of PCI bus initialized by a BIOS and
> ready to use at start. Thus, we need allocate and assign
> resources to all devices, much like an architecture's
> firmware would do.
> 
> There is no any sort of resource management for memory and
> io spaces, since only ones-per-BAR allocations are expected
> and no deallocations at all.
> 
> Cc: Thomas Huth <thuth@redhat.com>
> Cc: Andrew Jones <drjones@redhat.com>
> Reviewed-by: Andrew Jones <drjones@redhat.com>
> Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
> ---
>  lib/asm-generic/pci-host-bridge.h |  26 ++++
>  lib/pci-host-generic.c            | 295 ++++++++++++++++++++++++++++++++++++++
>  lib/pci-host-generic.h            |  46 ++++++
>  lib/pci.c                         |   4 +-
>  lib/pci.h                         |   3 +
>  5 files changed, 372 insertions(+), 2 deletions(-)
>  create mode 100644 lib/asm-generic/pci-host-bridge.h
>  create mode 100644 lib/pci-host-generic.c
>  create mode 100644 lib/pci-host-generic.h
> 
> diff --git a/lib/asm-generic/pci-host-bridge.h b/lib/asm-generic/pci-host-bridge.h
> new file mode 100644
> index 000000000000..872df3a81310
> --- /dev/null
> +++ b/lib/asm-generic/pci-host-bridge.h
> @@ -0,0 +1,26 @@
> +#ifndef _ASM_PCI_HOST_BRIDGE_H_
> +#define _ASM_PCI_HOST_BRIDGE_H_
> +/*
> + * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
> + *
> + * This work is licensed under the terms of the GNU LGPL, version 2.
> + */
> +#include "libcflat.h"
> +
> +phys_addr_t pci_host_bridge_get_paddr(uint64_t addr);
> +
> +static inline
> +phys_addr_t pci_translate_addr(pcidevaddr_t __unused dev, uint64_t addr)
> +{
> +	/*
> +	 * Assume we only have single PCI host bridge in a system.
> +	 */
> +	return pci_host_bridge_get_paddr(addr);
> +}
> +
> +uint8_t pci_config_readb(pcidevaddr_t dev, uint8_t reg);
> +uint16_t pci_config_readw(pcidevaddr_t dev, uint8_t reg);
> +uint32_t pci_config_readl(pcidevaddr_t dev, uint8_t reg);
> +void pci_config_writel(pcidevaddr_t dev, uint8_t reg, uint32_t val);
> +
> +#endif
> diff --git a/lib/pci-host-generic.c b/lib/pci-host-generic.c
> new file mode 100644
> index 000000000000..4a2716a33150
> --- /dev/null
> +++ b/lib/pci-host-generic.c
> @@ -0,0 +1,295 @@
> +/*
> + * Generic PCI host controller as described in PCI Bus Binding to Open Firmware
> + *
> + * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
> + *
> + * This work is licensed under the terms of the GNU LGPL, version 2.
> + */
> +#include "libcflat.h"
> +#include "devicetree.h"
> +#include "alloc.h"
> +#include "pci.h"
> +#include "asm/pci.h"
> +#include "asm/io.h"
> +#include "pci-host-generic.h"
> +#include <linux/pci_regs.h>
> +
> +static struct pci_host_bridge *pci_host_bridge;
> +
> +static int of_flags_to_pci_type(u32 of_flags)
> +{
> +	static int type_map[] = {
> +		[1] = PCI_BASE_ADDRESS_SPACE_IO,
> +		[2] = PCI_BASE_ADDRESS_MEM_TYPE_32,
> +		[3] = PCI_BASE_ADDRESS_MEM_TYPE_64
> +	};
> +	int idx = (of_flags >> 24) & 0x03;
> +	int res;
> +
> +	assert(idx > 0);
> +	res = type_map[idx];
> +
> +	if (of_flags & 0x40000000)
> +		res |= PCI_BASE_ADDRESS_MEM_PREFETCH;
> +
> +	return res;
> +}
> +
> +static int pci_bar_type(u32 bar)
> +{
> +	if (bar & PCI_BASE_ADDRESS_SPACE)
> +		return PCI_BASE_ADDRESS_SPACE_IO;
> +	else
> +		return bar & (PCI_BASE_ADDRESS_MEM_TYPE_MASK |
> +			      PCI_BASE_ADDRESS_MEM_PREFETCH);
> +}
> +
> +/*
> + * Probe DT for a generic PCI host controller
> + * See kernel Documentation/devicetree/bindings/pci/host-generic-pci.txt
> + * and function gen_pci_probe() in drivers/pci/host/pci-host-generic.c
> + */
> +static struct pci_host_bridge *pci_dt_probe(void)
> +{
> +	struct pci_host_bridge *host;
> +	const void *fdt = dt_fdt();
> +	const struct fdt_property *prop;
> +	struct dt_pbus_reg base;
> +	struct dt_device dt_dev;
> +	struct dt_bus dt_bus;
> +	struct pci_addr_space *as;
> +	fdt32_t *data;
> +	u32 bus, bus_max;
> +	u32 nac, nsc, nac_root, nsc_root;
> +	int nr_range_cells, nr_addr_spaces;
> +	int ret, node, len, i;
> +
> +	if (!dt_available()) {
> +		printf("No device tree found\n");
> +		return NULL;
> +	}
> +
> +	dt_bus_init_defaults(&dt_bus);
> +	dt_device_init(&dt_dev, &dt_bus, NULL);
> +
> +	node = fdt_path_offset(fdt, "/");
> +	assert(node >= 0);
> +
> +	ret = dt_get_nr_cells(node, &nac_root, &nsc_root);
> +	assert(ret == 0);
> +	assert(nac_root == 1 || nac_root == 2);
> +
> +	node = fdt_node_offset_by_compatible(fdt, node,
> +					     "pci-host-ecam-generic");
> +	if (node == -FDT_ERR_NOTFOUND) {
> +		printf("No PCIe ECAM compatible controller found\n");
> +		return NULL;
> +	}
> +	assert(node >= 0);
> +
> +	prop = fdt_get_property(fdt, node, "device_type", &len);
> +	assert(prop && len == 4 && !strcmp((char *)prop->data, "pci"));
> +
> +	dt_device_bind_node(&dt_dev, node);
> +	ret = dt_pbus_get_base(&dt_dev, &base);
> +	assert(ret == 0);
> +
> +	prop = fdt_get_property(fdt, node, "bus-range", &len);
> +	if (prop == NULL) {
> +		assert(len == -FDT_ERR_NOTFOUND);
> +		bus		= 0x00;
> +		bus_max		= 0xff;
> +	} else {
> +		data		= (fdt32_t *)prop->data;
> +		bus		= fdt32_to_cpu(data[0]);
> +		bus_max		= fdt32_to_cpu(data[1]);
> +		assert(bus <= bus_max);
> +	}
> +	assert(bus_max < base.size / (1 << PCI_ECAM_BUS_SHIFT));

I see you kept the inequality, rather than my suggestion to change it to
assert(bus_max + 1 == base.size / (1 << PCI_ECAM_BUS_SHIFT)) Any reason
why?

I'm not too worried about it though...

> +
> +	ret = dt_get_nr_cells(node, &nac, &nsc);
> +	assert(ret == 0);
> +	assert(nac == 3 && nsc == 2);
> +
> +	prop = fdt_get_property(fdt, node, "ranges", &len);
> +	assert(prop != NULL);
> +
> +	nr_range_cells = nac + nsc + nac_root;
> +	nr_addr_spaces = (len / 4) / nr_range_cells;
> +	assert(nr_addr_spaces);
> +
> +	host = malloc(sizeof(*host) +
> +		      sizeof(host->addr_space[0]) * nr_addr_spaces);
> +	assert(host != NULL);
> +
> +	host->start		= base.addr;
> +	host->size		= base.size;
> +	host->bus		= bus;
> +	host->bus_max		= bus_max;
> +	host->nr_addr_spaces	= nr_addr_spaces;
> +
> +	data = (fdt32_t *)prop->data;
> +	as = &host->addr_space[0];
> +
> +	for (i = 0; i < nr_addr_spaces; i++) {
> +		/*
> +		 * The PCI binding encodes the PCI address with three
> +		 * cells as follows:
> +		 *
> +		 * phys.hi  cell: npt000ss bbbbbbbb dddddfff rrrrrrrr
> +		 * phys.mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
> +		 * phys.lo  cell: llllllll llllllll llllllll llllllll
> +		 *
> +		 * PCI device bus address and flags are encoded into phys.high
> +		 * PCI 64 bit address is encoded into phys.mid and phys.low
> +		 */
> +		as->type = of_flags_to_pci_type(fdt32_to_cpu(data[0]));
> +		as->pci_start = ((u64)fdt32_to_cpu(data[1]) << 32) |
> +				fdt32_to_cpu(data[2]);
> +
> +		if (nr_range_cells == 6) {
> +			as->start = fdt32_to_cpu(data[3]);
> +			as->size  = ((u64)fdt32_to_cpu(data[4]) << 32) |
> +				    fdt32_to_cpu(data[5]);
> +		} else {
> +			as->start = ((u64)fdt32_to_cpu(data[3]) << 32) |
> +				    fdt32_to_cpu(data[4]);
> +			as->size  = ((u64)fdt32_to_cpu(data[5]) << 32) |
> +				    fdt32_to_cpu(data[6]);
> +		}
> +
> +		data += nr_range_cells;
> +		as++;
> +	}
> +
> +	return host;
> +}
> +
> +static u64 pci_alloc_resource(u32 bar, u64 size)
> +{
> +	struct pci_host_bridge *host = pci_host_bridge;
> +	struct pci_addr_space *as = &host->addr_space[0];
> +	phys_addr_t addr;
> +	u32 mask;
> +	int i;
> +
> +	for (i = 0; i < host->nr_addr_spaces; i++) {
> +		if (as->type == pci_bar_type(bar))
> +			break;
> +		as++;
> +	}
> +	if (i >= host->nr_addr_spaces) {
> +		printf("No PCI resource found for a device\n");
> +		assert(0);
> +	}
> +
> +	mask = pci_bar_mask(bar);
> +	size = ALIGN(size, ~mask + 1);
> +	assert(as->allocated + size <= as->size);
> +
> +	addr = as->pci_start + as->allocated;
> +	as->allocated += size;
> +
> +	return addr;
> +}
> +
> +bool pci_probe(void)
> +{
> +	pcidevaddr_t dev;
> +	u8 header;
> +	u32 cmd;
> +	int i;
> +
> +	assert(!pci_host_bridge);
> +	pci_host_bridge = pci_dt_probe();
> +	if (!pci_host_bridge)
> +		return false;
> +
> +	for (dev = 0; dev < 256; dev++) {
> +		if (!pci_dev_exists(dev))
> +			continue;
> +
> +		/* We are only interested in normal PCI devices */
> +		header = pci_config_readb(dev, PCI_HEADER_TYPE);
> +		if ((header & PCI_HEADER_TYPE_MASK) != PCI_HEADER_TYPE_NORMAL)
> +			continue;
> +
> +		cmd = PCI_COMMAND_SERR;
> +
> +		for (i = 0; i < 6; i++) {
> +			u64 addr, size;
> +			u32 bar;
> +
> +			size = pci_bar_size(dev, i);
> +			if (!size)
> +				continue;
> +
> +			bar = pci_bar_get(dev, i);
> +			addr = pci_alloc_resource(bar, size);
> +			pci_bar_set_addr(dev, i, addr);
> +
> +			if (pci_bar_is_memory(dev, i))
> +				cmd |= PCI_COMMAND_MEMORY;
> +			else
> +				cmd |= PCI_COMMAND_IO;
> +
> +			if (pci_bar_is64(dev, i))
> +				i++;
> +		}
> +
> +		pci_config_writel(dev, PCI_COMMAND, cmd);
> +	}
> +
> +	return true;
> +}
> +
> +/*
> + * This function is to be called from pci_translate_addr() to provide
> + * mapping between this host bridge's PCI busses address and CPU physical
> + * address.
> + */
> +phys_addr_t pci_host_bridge_get_paddr(u64 pci_addr)
> +{
> +	struct pci_host_bridge *host = pci_host_bridge;
> +	struct pci_addr_space *as = &host->addr_space[0];
> +	int i;
> +
> +	for (i = 0; i < host->nr_addr_spaces; i++) {
> +		if (pci_addr >= as->pci_start &&
> +		    pci_addr < as->pci_start + as->size)
> +			return as->start + (pci_addr - as->pci_start);
> +		as++;
> +	}
> +
> +	return 0;
> +}
> +
> +static void __iomem *pci_get_dev_conf(struct pci_host_bridge *host, int devfn)
> +{
> +	return (void __iomem *)(unsigned long)
> +		host->start + (devfn << PCI_ECAM_DEVFN_SHIFT);
> +}
> +
> +u8 pci_config_readb(pcidevaddr_t dev, u8 off)
> +{
> +	void __iomem *conf = pci_get_dev_conf(pci_host_bridge, dev);
> +	return readb(conf + off);
> +}
> +
> +u16 pci_config_readw(pcidevaddr_t dev, u8 off)
> +{
> +	void __iomem *conf = pci_get_dev_conf(pci_host_bridge, dev);
> +	return readw(conf + off);
> +}
> +
> +u32 pci_config_readl(pcidevaddr_t dev, u8 off)
> +{
> +	void __iomem *conf = pci_get_dev_conf(pci_host_bridge, dev);
> +	return readl(conf + off);
> +}
> +
> +void pci_config_writel(pcidevaddr_t dev, u8 off, u32 val)
> +{
> +	void __iomem *conf = pci_get_dev_conf(pci_host_bridge, dev);
> +	writel(val, conf + off);
> +}
> diff --git a/lib/pci-host-generic.h b/lib/pci-host-generic.h
> new file mode 100644
> index 000000000000..fd30e7c74ed8
> --- /dev/null
> +++ b/lib/pci-host-generic.h
> @@ -0,0 +1,46 @@
> +#ifndef PCI_HOST_GENERIC_H
> +#define PCI_HOST_GENERIC_H
> +/*
> + * PCI host bridge supporting structures and constants
> + *
> + * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
> + *
> + * This work is licensed under the terms of the GNU LGPL, version 2.
> + */
> +#include "libcflat.h"
> +
> +struct pci_addr_space {
> +	phys_addr_t		pci_start;
> +	phys_addr_t		start;
> +	phys_addr_t		size;
> +	phys_addr_t		allocated;
> +	int			type;
> +};
> +
> +struct pci_host_bridge {
> +	phys_addr_t		start;
> +	phys_addr_t		size;
> +	int			bus;
> +	int			bus_max;
> +	int			nr_addr_spaces;
> +	struct pci_addr_space	addr_space[];
> +};
> +
> +/*
> + * The following constants are derived from Linux, see this source:
> + *
> + *         drivers/pci/host/pci-host-generic.c
> + *                 struct gen_pci_cfg_bus_ops::bus_shift
> + *                 int gen_pci_parse_map_cfg_windows(struct gen_pci *pci)
> + *
> + * Documentation/devicetree/bindings/pci/host-generic-pci.txt describes
> + * ECAM Configuration Space is be memory-mapped by concatenating the various
> + * components to form an offset:
> + *
> + *	cfg_offset(bus, device, function, register) =
> + *		   bus << 20 | device << 15 | function << 12 | register
> + */
> +#define PCI_ECAM_BUS_SHIFT	20
> +#define PCI_ECAM_DEVFN_SHIFT	12
> +
> +#endif
> diff --git a/lib/pci.c b/lib/pci.c
> index f01a085391f3..46cd39dc9c7e 100644
> --- a/lib/pci.c
> +++ b/lib/pci.c
> @@ -27,13 +27,13 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)
>  	return PCIDEVADDR_INVALID;
>  }
>  
> -static uint32_t pci_bar_mask(uint32_t bar)
> +uint32_t pci_bar_mask(uint32_t bar)
>  {
>  	return (bar & PCI_BASE_ADDRESS_SPACE_IO) ?
>  		PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK;
>  }
>  
> -static uint32_t pci_bar_get(pcidevaddr_t dev, int bar_num)
> +uint32_t pci_bar_get(pcidevaddr_t dev, int bar_num)
>  {
>  	return pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
>  }
> diff --git a/lib/pci.h b/lib/pci.h
> index ff32ea683c94..e00e1471d80a 100644
> --- a/lib/pci.h
> +++ b/lib/pci.h
> @@ -15,6 +15,7 @@ enum {
>  	PCIDEVADDR_INVALID = 0xffff,
>  };
>  
> +bool pci_probe(void);
>  void pci_print(void);
>  bool pci_dev_exists(pcidevaddr_t dev);
>  pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);
> @@ -33,6 +34,8 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);
>  phys_addr_t pci_bar_get_addr(pcidevaddr_t dev, int bar_num);
>  void pci_bar_set_addr(pcidevaddr_t dev, int bar_num, phys_addr_t addr);
>  phys_addr_t pci_bar_size(pcidevaddr_t dev, int bar_num);
> +uint32_t pci_bar_get(pcidevaddr_t dev, int bar_num);
> +uint32_t pci_bar_mask(uint32_t bar);
>  bool pci_bar_is64(pcidevaddr_t dev, int bar_num);
>  bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num);
>  bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num);
> -- 
> 1.8.3.1
> 
> --
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Re: [kvm-unit-tests PATCH v5 09/12] pci: Add generic ECAM host support

[Andrew Jones]

On Tue, Jul 19, 2016 at 02:53:06PM +0200, Alexander Gordeev wrote:
> Unlike x86, other architectures using generic ECAM PCI host
> do not have a luxury of PCI bus initialized by a BIOS and
> ready to use at start. Thus, we need allocate and assign
> resources to all devices, much like an architecture's
> firmware would do.
> 
> There is no any sort of resource management for memory and
> io spaces, since only ones-per-BAR allocations are expected
> and no deallocations at all.
> 
> Cc: Thomas Huth <thuth@redhat.com>
> Cc: Andrew Jones <drjones@redhat.com>
> Reviewed-by: Andrew Jones <drjones@redhat.com>
> Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
> ---
>  lib/asm-generic/pci-host-bridge.h |  26 ++++
>  lib/pci-host-generic.c            | 295 ++++++++++++++++++++++++++++++++++++++
>  lib/pci-host-generic.h            |  46 ++++++
>  lib/pci.c                         |   4 +-
>  lib/pci.h                         |   3 +
>  5 files changed, 372 insertions(+), 2 deletions(-)
>  create mode 100644 lib/asm-generic/pci-host-bridge.h
>  create mode 100644 lib/pci-host-generic.c
>  create mode 100644 lib/pci-host-generic.h
> 
> diff --git a/lib/asm-generic/pci-host-bridge.h b/lib/asm-generic/pci-host-bridge.h
> new file mode 100644
> index 000000000000..872df3a81310
> --- /dev/null
> +++ b/lib/asm-generic/pci-host-bridge.h
> @@ -0,0 +1,26 @@
> +#ifndef _ASM_PCI_HOST_BRIDGE_H_
> +#define _ASM_PCI_HOST_BRIDGE_H_
> +/*
> + * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
> + *
> + * This work is licensed under the terms of the GNU LGPL, version 2.
> + */
> +#include "libcflat.h"
> +
> +phys_addr_t pci_host_bridge_get_paddr(uint64_t addr);
> +
> +static inline
> +phys_addr_t pci_translate_addr(pcidevaddr_t __unused dev, uint64_t addr)

__unused should come after dev

> +{
> +	/*
> +	 * Assume we only have single PCI host bridge in a system.
> +	 */
> +	return pci_host_bridge_get_paddr(addr);
> +}
> +
> +uint8_t pci_config_readb(pcidevaddr_t dev, uint8_t reg);
> +uint16_t pci_config_readw(pcidevaddr_t dev, uint8_t reg);
> +uint32_t pci_config_readl(pcidevaddr_t dev, uint8_t reg);
> +void pci_config_writel(pcidevaddr_t dev, uint8_t reg, uint32_t val);
> +
> +#endif
> diff --git a/lib/pci-host-generic.c b/lib/pci-host-generic.c
> new file mode 100644
> index 000000000000..4a2716a33150
> --- /dev/null
> +++ b/lib/pci-host-generic.c
> @@ -0,0 +1,295 @@
> +/*
> + * Generic PCI host controller as described in PCI Bus Binding to Open Firmware
> + *
> + * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
> + *
> + * This work is licensed under the terms of the GNU LGPL, version 2.
> + */
> +#include "libcflat.h"
> +#include "devicetree.h"
> +#include "alloc.h"
> +#include "pci.h"
> +#include "asm/pci.h"
> +#include "asm/io.h"
> +#include "pci-host-generic.h"
> +#include <linux/pci_regs.h>
> +
> +static struct pci_host_bridge *pci_host_bridge;
> +
> +static int of_flags_to_pci_type(u32 of_flags)
> +{
> +	static int type_map[] = {
> +		[1] = PCI_BASE_ADDRESS_SPACE_IO,
> +		[2] = PCI_BASE_ADDRESS_MEM_TYPE_32,
> +		[3] = PCI_BASE_ADDRESS_MEM_TYPE_64
> +	};
> +	int idx = (of_flags >> 24) & 0x03;
> +	int res;
> +
> +	assert(idx > 0);
> +	res = type_map[idx];
> +
> +	if (of_flags & 0x40000000)
> +		res |= PCI_BASE_ADDRESS_MEM_PREFETCH;
> +
> +	return res;
> +}
> +
> +static int pci_bar_type(u32 bar)
> +{
> +	if (bar & PCI_BASE_ADDRESS_SPACE)
> +		return PCI_BASE_ADDRESS_SPACE_IO;
> +	else
> +		return bar & (PCI_BASE_ADDRESS_MEM_TYPE_MASK |
> +			      PCI_BASE_ADDRESS_MEM_PREFETCH);
> +}
> +
> +/*
> + * Probe DT for a generic PCI host controller
> + * See kernel Documentation/devicetree/bindings/pci/host-generic-pci.txt
> + * and function gen_pci_probe() in drivers/pci/host/pci-host-generic.c
> + */
> +static struct pci_host_bridge *pci_dt_probe(void)
> +{
> +	struct pci_host_bridge *host;
> +	const void *fdt = dt_fdt();
> +	const struct fdt_property *prop;
> +	struct dt_pbus_reg base;
> +	struct dt_device dt_dev;
> +	struct dt_bus dt_bus;
> +	struct pci_addr_space *as;
> +	fdt32_t *data;
> +	u32 bus, bus_max;
> +	u32 nac, nsc, nac_root, nsc_root;
> +	int nr_range_cells, nr_addr_spaces;
> +	int ret, node, len, i;
> +
> +	if (!dt_available()) {
> +		printf("No device tree found\n");
> +		return NULL;
> +	}
> +
> +	dt_bus_init_defaults(&dt_bus);
> +	dt_device_init(&dt_dev, &dt_bus, NULL);
> +
> +	node = fdt_path_offset(fdt, "/");
> +	assert(node >= 0);
> +
> +	ret = dt_get_nr_cells(node, &nac_root, &nsc_root);
> +	assert(ret == 0);
> +	assert(nac_root == 1 || nac_root == 2);
> +
> +	node = fdt_node_offset_by_compatible(fdt, node,
> +					     "pci-host-ecam-generic");
> +	if (node == -FDT_ERR_NOTFOUND) {
> +		printf("No PCIe ECAM compatible controller found\n");
> +		return NULL;
> +	}
> +	assert(node >= 0);
> +
> +	prop = fdt_get_property(fdt, node, "device_type", &len);
> +	assert(prop && len == 4 && !strcmp((char *)prop->data, "pci"));
> +
> +	dt_device_bind_node(&dt_dev, node);
> +	ret = dt_pbus_get_base(&dt_dev, &base);
> +	assert(ret == 0);
> +
> +	prop = fdt_get_property(fdt, node, "bus-range", &len);
> +	if (prop == NULL) {
> +		assert(len == -FDT_ERR_NOTFOUND);
> +		bus		= 0x00;
> +		bus_max		= 0xff;
> +	} else {
> +		data		= (fdt32_t *)prop->data;
> +		bus		= fdt32_to_cpu(data[0]);
> +		bus_max		= fdt32_to_cpu(data[1]);
> +		assert(bus <= bus_max);
> +	}
> +	assert(bus_max < base.size / (1 << PCI_ECAM_BUS_SHIFT));
> +
> +	ret = dt_get_nr_cells(node, &nac, &nsc);
> +	assert(ret == 0);
> +	assert(nac == 3 && nsc == 2);
> +
> +	prop = fdt_get_property(fdt, node, "ranges", &len);
> +	assert(prop != NULL);
> +
> +	nr_range_cells = nac + nsc + nac_root;
> +	nr_addr_spaces = (len / 4) / nr_range_cells;
> +	assert(nr_addr_spaces);
> +
> +	host = malloc(sizeof(*host) +
> +		      sizeof(host->addr_space[0]) * nr_addr_spaces);
> +	assert(host != NULL);
> +
> +	host->start		= base.addr;
> +	host->size		= base.size;
> +	host->bus		= bus;
> +	host->bus_max		= bus_max;
> +	host->nr_addr_spaces	= nr_addr_spaces;
> +
> +	data = (fdt32_t *)prop->data;
> +	as = &host->addr_space[0];
> +
> +	for (i = 0; i < nr_addr_spaces; i++) {
> +		/*
> +		 * The PCI binding encodes the PCI address with three
> +		 * cells as follows:
> +		 *
> +		 * phys.hi  cell: npt000ss bbbbbbbb dddddfff rrrrrrrr
> +		 * phys.mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
> +		 * phys.lo  cell: llllllll llllllll llllllll llllllll
> +		 *
> +		 * PCI device bus address and flags are encoded into phys.high
> +		 * PCI 64 bit address is encoded into phys.mid and phys.low
> +		 */
> +		as->type = of_flags_to_pci_type(fdt32_to_cpu(data[0]));
> +		as->pci_start = ((u64)fdt32_to_cpu(data[1]) << 32) |
> +				fdt32_to_cpu(data[2]);
> +
> +		if (nr_range_cells == 6) {
> +			as->start = fdt32_to_cpu(data[3]);
> +			as->size  = ((u64)fdt32_to_cpu(data[4]) << 32) |
> +				    fdt32_to_cpu(data[5]);
> +		} else {
> +			as->start = ((u64)fdt32_to_cpu(data[3]) << 32) |
> +				    fdt32_to_cpu(data[4]);
> +			as->size  = ((u64)fdt32_to_cpu(data[5]) << 32) |
> +				    fdt32_to_cpu(data[6]);
> +		}
> +
> +		data += nr_range_cells;
> +		as++;
> +	}
> +
> +	return host;
> +}
> +
> +static u64 pci_alloc_resource(u32 bar, u64 size)
> +{
> +	struct pci_host_bridge *host = pci_host_bridge;
> +	struct pci_addr_space *as = &host->addr_space[0];
> +	phys_addr_t addr;
> +	u32 mask;
> +	int i;
> +
> +	for (i = 0; i < host->nr_addr_spaces; i++) {
> +		if (as->type == pci_bar_type(bar))
> +			break;
> +		as++;
> +	}
> +	if (i >= host->nr_addr_spaces) {
> +		printf("No PCI resource found for a device\n");
> +		assert(0);
> +	}
> +
> +	mask = pci_bar_mask(bar);
> +	size = ALIGN(size, ~mask + 1);
> +	assert(as->allocated + size <= as->size);
> +
> +	addr = as->pci_start + as->allocated;
> +	as->allocated += size;
> +
> +	return addr;
> +}
> +
> +bool pci_probe(void)
> +{
> +	pcidevaddr_t dev;
> +	u8 header;
> +	u32 cmd;
> +	int i;
> +
> +	assert(!pci_host_bridge);
> +	pci_host_bridge = pci_dt_probe();
> +	if (!pci_host_bridge)
> +		return false;
> +
> +	for (dev = 0; dev < 256; dev++) {
> +		if (!pci_dev_exists(dev))
> +			continue;
> +
> +		/* We are only interested in normal PCI devices */
> +		header = pci_config_readb(dev, PCI_HEADER_TYPE);
> +		if ((header & PCI_HEADER_TYPE_MASK) != PCI_HEADER_TYPE_NORMAL)
> +			continue;
> +
> +		cmd = PCI_COMMAND_SERR;
> +
> +		for (i = 0; i < 6; i++) {
> +			u64 addr, size;
> +			u32 bar;
> +
> +			size = pci_bar_size(dev, i);
> +			if (!size)
> +				continue;
> +
> +			bar = pci_bar_get(dev, i);
> +			addr = pci_alloc_resource(bar, size);
> +			pci_bar_set_addr(dev, i, addr);
> +
> +			if (pci_bar_is_memory(dev, i))
> +				cmd |= PCI_COMMAND_MEMORY;
> +			else
> +				cmd |= PCI_COMMAND_IO;
> +
> +			if (pci_bar_is64(dev, i))
> +				i++;
> +		}
> +
> +		pci_config_writel(dev, PCI_COMMAND, cmd);
> +	}
> +
> +	return true;
> +}
> +
> +/*
> + * This function is to be called from pci_translate_addr() to provide
> + * mapping between this host bridge's PCI busses address and CPU physical
> + * address.
> + */
> +phys_addr_t pci_host_bridge_get_paddr(u64 pci_addr)
> +{
> +	struct pci_host_bridge *host = pci_host_bridge;
> +	struct pci_addr_space *as = &host->addr_space[0];
> +	int i;
> +
> +	for (i = 0; i < host->nr_addr_spaces; i++) {
> +		if (pci_addr >= as->pci_start &&
> +		    pci_addr < as->pci_start + as->size)
> +			return as->start + (pci_addr - as->pci_start);
> +		as++;
> +	}
> +
> +	return 0;
> +}
> +
> +static void __iomem *pci_get_dev_conf(struct pci_host_bridge *host, int devfn)
> +{
> +	return (void __iomem *)(unsigned long)
> +		host->start + (devfn << PCI_ECAM_DEVFN_SHIFT);
> +}
> +
> +u8 pci_config_readb(pcidevaddr_t dev, u8 off)
> +{
> +	void __iomem *conf = pci_get_dev_conf(pci_host_bridge, dev);
> +	return readb(conf + off);
> +}
> +
> +u16 pci_config_readw(pcidevaddr_t dev, u8 off)
> +{
> +	void __iomem *conf = pci_get_dev_conf(pci_host_bridge, dev);
> +	return readw(conf + off);
> +}
> +
> +u32 pci_config_readl(pcidevaddr_t dev, u8 off)
> +{
> +	void __iomem *conf = pci_get_dev_conf(pci_host_bridge, dev);
> +	return readl(conf + off);
> +}
> +
> +void pci_config_writel(pcidevaddr_t dev, u8 off, u32 val)
> +{
> +	void __iomem *conf = pci_get_dev_conf(pci_host_bridge, dev);
> +	writel(val, conf + off);
> +}
> diff --git a/lib/pci-host-generic.h b/lib/pci-host-generic.h
> new file mode 100644
> index 000000000000..fd30e7c74ed8
> --- /dev/null
> +++ b/lib/pci-host-generic.h
> @@ -0,0 +1,46 @@
> +#ifndef PCI_HOST_GENERIC_H
> +#define PCI_HOST_GENERIC_H
> +/*
> + * PCI host bridge supporting structures and constants
> + *
> + * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
> + *
> + * This work is licensed under the terms of the GNU LGPL, version 2.
> + */
> +#include "libcflat.h"
> +
> +struct pci_addr_space {
> +	phys_addr_t		pci_start;
> +	phys_addr_t		start;
> +	phys_addr_t		size;
> +	phys_addr_t		allocated;
> +	int			type;
> +};
> +
> +struct pci_host_bridge {
> +	phys_addr_t		start;
> +	phys_addr_t		size;
> +	int			bus;
> +	int			bus_max;
> +	int			nr_addr_spaces;
> +	struct pci_addr_space	addr_space[];
> +};
> +
> +/*
> + * The following constants are derived from Linux, see this source:
> + *
> + *         drivers/pci/host/pci-host-generic.c
> + *                 struct gen_pci_cfg_bus_ops::bus_shift
> + *                 int gen_pci_parse_map_cfg_windows(struct gen_pci *pci)
> + *
> + * Documentation/devicetree/bindings/pci/host-generic-pci.txt describes
> + * ECAM Configuration Space is be memory-mapped by concatenating the various
> + * components to form an offset:
> + *
> + *	cfg_offset(bus, device, function, register) =
> + *		   bus << 20 | device << 15 | function << 12 | register
> + */
> +#define PCI_ECAM_BUS_SHIFT	20
> +#define PCI_ECAM_DEVFN_SHIFT	12
> +
> +#endif
> diff --git a/lib/pci.c b/lib/pci.c
> index f01a085391f3..46cd39dc9c7e 100644
> --- a/lib/pci.c
> +++ b/lib/pci.c
> @@ -27,13 +27,13 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)
>  	return PCIDEVADDR_INVALID;
>  }
>  
> -static uint32_t pci_bar_mask(uint32_t bar)
> +uint32_t pci_bar_mask(uint32_t bar)
>  {
>  	return (bar & PCI_BASE_ADDRESS_SPACE_IO) ?
>  		PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK;
>  }
>  
> -static uint32_t pci_bar_get(pcidevaddr_t dev, int bar_num)
> +uint32_t pci_bar_get(pcidevaddr_t dev, int bar_num)
>  {
>  	return pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
>  }
> diff --git a/lib/pci.h b/lib/pci.h
> index ff32ea683c94..e00e1471d80a 100644
> --- a/lib/pci.h
> +++ b/lib/pci.h
> @@ -15,6 +15,7 @@ enum {
>  	PCIDEVADDR_INVALID = 0xffff,
>  };
>  
> +bool pci_probe(void);
>  void pci_print(void);
>  bool pci_dev_exists(pcidevaddr_t dev);
>  pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);
> @@ -33,6 +34,8 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);
>  phys_addr_t pci_bar_get_addr(pcidevaddr_t dev, int bar_num);
>  void pci_bar_set_addr(pcidevaddr_t dev, int bar_num, phys_addr_t addr);
>  phys_addr_t pci_bar_size(pcidevaddr_t dev, int bar_num);
> +uint32_t pci_bar_get(pcidevaddr_t dev, int bar_num);
> +uint32_t pci_bar_mask(uint32_t bar);
>  bool pci_bar_is64(pcidevaddr_t dev, int bar_num);
>  bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num);
>  bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num);
> -- 
> 1.8.3.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe kvm" in
> the body of a message to majordomo@vger.kernel.org
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Re: [kvm-unit-tests PATCH v5 10/12] arm/arm64: pci: Add PCI bus operation test

[Andrew Jones]

On Tue, Jul 19, 2016 at 02:53:07PM +0200, Alexander Gordeev wrote:
> Cc: Thomas Huth <thuth@redhat.com>
> Cc: Andrew Jones <drjones@redhat.com>
> Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
> ---
>  arm/Makefile.common |  5 ++++-
>  arm/pci-test.c      | 21 +++++++++++++++++++++
>  lib/arm/asm/pci.h   | 11 +++++++++++
>  lib/arm64/asm/pci.h |  1 +
>  4 files changed, 37 insertions(+), 1 deletion(-)
>  create mode 100644 arm/pci-test.c
>  create mode 100644 lib/arm/asm/pci.h
>  create mode 100644 lib/arm64/asm/pci.h
> 
> diff --git a/arm/Makefile.common b/arm/Makefile.common
> index ccb554d9251a..97179bbea4e7 100644
> --- a/arm/Makefile.common
> +++ b/arm/Makefile.common
> @@ -11,7 +11,8 @@ endif
>  
>  tests-common = \
>  	$(TEST_DIR)/selftest.flat \
> -	$(TEST_DIR)/spinlock-test.flat
> +	$(TEST_DIR)/spinlock-test.flat \
> +	$(TEST_DIR)/pci-test.flat
>  
>  all: test_cases
>  
> @@ -33,6 +34,8 @@ include scripts/asm-offsets.mak
>  cflatobjs += lib/util.o
>  cflatobjs += lib/alloc.o
>  cflatobjs += lib/devicetree.o
> +cflatobjs += lib/pci.o
> +cflatobjs += lib/pci-host-generic.o
>  cflatobjs += lib/virtio.o
>  cflatobjs += lib/virtio-mmio.o
>  cflatobjs += lib/chr-testdev.o
> diff --git a/arm/pci-test.c b/arm/pci-test.c
> new file mode 100644
> index 000000000000..fde5495dd626
> --- /dev/null
> +++ b/arm/pci-test.c
> @@ -0,0 +1,21 @@
> +/*
> + * PCI bus operation test
> + *
> + * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
> + *
> + * This work is licensed under the terms of the GNU LGPL, version 2.
> + */
> +#include <libcflat.h>
> +#include <pci.h>
> +
> +int main(void)
> +{
> +	int ret = pci_probe();
> +
> +	report("PCI bus probing", ret);

See other patch were I state pci_probe doesn't need to be a test.

> +
> +	if (ret)
> +		pci_print();
> +
> +	return report_summary();
> +}
> diff --git a/lib/arm/asm/pci.h b/lib/arm/asm/pci.h
> new file mode 100644
> index 000000000000..08b0e87d497c
> --- /dev/null
> +++ b/lib/arm/asm/pci.h
> @@ -0,0 +1,11 @@
> +#ifndef _ASMARM_PCI_H_
> +#define _ASMARM_PCI_H_
> +/*
> + * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
> + *
> + * This work is licensed under the terms of the GNU LGPL, version 2.
> + */
> +#include "libcflat.h"

no need to include libcflat.h

> +#include "asm-generic/pci-host-bridge.h"

Actually there's no point in having a full file with GPL header here.
Just this one #include line is enough.

> +
> +#endif
> diff --git a/lib/arm64/asm/pci.h b/lib/arm64/asm/pci.h
> new file mode 100644
> index 000000000000..f70ef560e2ab
> --- /dev/null
> +++ b/lib/arm64/asm/pci.h
> @@ -0,0 +1 @@
> +#include "../../arm/asm/pci.h"
> -- 
> 1.8.3.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe kvm" in
> the body of a message to majordomo@vger.kernel.org
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Re: [kvm-unit-tests PATCH v5 09/12] pci: Add generic ECAM host support

[Alexander Gordeev]

On Thu, Jul 21, 2016 at 11:26:55AM +0200, Andrew Jones wrote:
> On Tue, Jul 19, 2016 at 02:53:06PM +0200, Alexander Gordeev wrote:
> > Unlike x86, other architectures using generic ECAM PCI host
> > do not have a luxury of PCI bus initialized by a BIOS and
> > ready to use at start. Thus, we need allocate and assign
> > resources to all devices, much like an architecture's
> > firmware would do.
> > 
> > There is no any sort of resource management for memory and
> > io spaces, since only ones-per-BAR allocations are expected
> > and no deallocations at all.
> > 
> > Cc: Thomas Huth <thuth@redhat.com>
> > Cc: Andrew Jones <drjones@redhat.com>
> > Reviewed-by: Andrew Jones <drjones@redhat.com>
> > Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
> > ---
> >  lib/asm-generic/pci-host-bridge.h |  26 ++++
> >  lib/pci-host-generic.c            | 295 ++++++++++++++++++++++++++++++++++++++
> >  lib/pci-host-generic.h            |  46 ++++++
> >  lib/pci.c                         |   4 +-
> >  lib/pci.h                         |   3 +
> >  5 files changed, 372 insertions(+), 2 deletions(-)
> >  create mode 100644 lib/asm-generic/pci-host-bridge.h
> >  create mode 100644 lib/pci-host-generic.c
> >  create mode 100644 lib/pci-host-generic.h
> > 
> > diff --git a/lib/asm-generic/pci-host-bridge.h b/lib/asm-generic/pci-host-bridge.h
> > new file mode 100644
> > index 000000000000..872df3a81310
> > --- /dev/null
> > +++ b/lib/asm-generic/pci-host-bridge.h
> > @@ -0,0 +1,26 @@
> > +#ifndef _ASM_PCI_HOST_BRIDGE_H_
> > +#define _ASM_PCI_HOST_BRIDGE_H_
> > +/*
> > + * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
> > + *
> > + * This work is licensed under the terms of the GNU LGPL, version 2.
> > + */
> > +#include "libcflat.h"
> > +
> > +phys_addr_t pci_host_bridge_get_paddr(uint64_t addr);
> > +
> > +static inline
> > +phys_addr_t pci_translate_addr(pcidevaddr_t __unused dev, uint64_t addr)
> > +{
> > +	/*
> > +	 * Assume we only have single PCI host bridge in a system.
> > +	 */
> > +	return pci_host_bridge_get_paddr(addr);
> > +}
> > +
> > +uint8_t pci_config_readb(pcidevaddr_t dev, uint8_t reg);
> > +uint16_t pci_config_readw(pcidevaddr_t dev, uint8_t reg);
> > +uint32_t pci_config_readl(pcidevaddr_t dev, uint8_t reg);
> > +void pci_config_writel(pcidevaddr_t dev, uint8_t reg, uint32_t val);
> > +
> > +#endif
> > diff --git a/lib/pci-host-generic.c b/lib/pci-host-generic.c
> > new file mode 100644
> > index 000000000000..4a2716a33150
> > --- /dev/null
> > +++ b/lib/pci-host-generic.c
> > @@ -0,0 +1,295 @@
> > +/*
> > + * Generic PCI host controller as described in PCI Bus Binding to Open Firmware
> > + *
> > + * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
> > + *
> > + * This work is licensed under the terms of the GNU LGPL, version 2.
> > + */
> > +#include "libcflat.h"
> > +#include "devicetree.h"
> > +#include "alloc.h"
> > +#include "pci.h"
> > +#include "asm/pci.h"
> > +#include "asm/io.h"
> > +#include "pci-host-generic.h"
> > +#include <linux/pci_regs.h>
> > +
> > +static struct pci_host_bridge *pci_host_bridge;
> > +
> > +static int of_flags_to_pci_type(u32 of_flags)
> > +{
> > +	static int type_map[] = {
> > +		[1] = PCI_BASE_ADDRESS_SPACE_IO,
> > +		[2] = PCI_BASE_ADDRESS_MEM_TYPE_32,
> > +		[3] = PCI_BASE_ADDRESS_MEM_TYPE_64
> > +	};
> > +	int idx = (of_flags >> 24) & 0x03;
> > +	int res;
> > +
> > +	assert(idx > 0);
> > +	res = type_map[idx];
> > +
> > +	if (of_flags & 0x40000000)
> > +		res |= PCI_BASE_ADDRESS_MEM_PREFETCH;
> > +
> > +	return res;
> > +}
> > +
> > +static int pci_bar_type(u32 bar)
> > +{
> > +	if (bar & PCI_BASE_ADDRESS_SPACE)
> > +		return PCI_BASE_ADDRESS_SPACE_IO;
> > +	else
> > +		return bar & (PCI_BASE_ADDRESS_MEM_TYPE_MASK |
> > +			      PCI_BASE_ADDRESS_MEM_PREFETCH);
> > +}
> > +
> > +/*
> > + * Probe DT for a generic PCI host controller
> > + * See kernel Documentation/devicetree/bindings/pci/host-generic-pci.txt
> > + * and function gen_pci_probe() in drivers/pci/host/pci-host-generic.c
> > + */
> > +static struct pci_host_bridge *pci_dt_probe(void)
> > +{
> > +	struct pci_host_bridge *host;
> > +	const void *fdt = dt_fdt();
> > +	const struct fdt_property *prop;
> > +	struct dt_pbus_reg base;
> > +	struct dt_device dt_dev;
> > +	struct dt_bus dt_bus;
> > +	struct pci_addr_space *as;
> > +	fdt32_t *data;
> > +	u32 bus, bus_max;
> > +	u32 nac, nsc, nac_root, nsc_root;
> > +	int nr_range_cells, nr_addr_spaces;
> > +	int ret, node, len, i;
> > +
> > +	if (!dt_available()) {
> > +		printf("No device tree found\n");
> > +		return NULL;
> > +	}
> > +
> > +	dt_bus_init_defaults(&dt_bus);
> > +	dt_device_init(&dt_dev, &dt_bus, NULL);
> > +
> > +	node = fdt_path_offset(fdt, "/");
> > +	assert(node >= 0);
> > +
> > +	ret = dt_get_nr_cells(node, &nac_root, &nsc_root);
> > +	assert(ret == 0);
> > +	assert(nac_root == 1 || nac_root == 2);
> > +
> > +	node = fdt_node_offset_by_compatible(fdt, node,
> > +					     "pci-host-ecam-generic");
> > +	if (node == -FDT_ERR_NOTFOUND) {
> > +		printf("No PCIe ECAM compatible controller found\n");
> > +		return NULL;
> > +	}
> > +	assert(node >= 0);
> > +
> > +	prop = fdt_get_property(fdt, node, "device_type", &len);
> > +	assert(prop && len == 4 && !strcmp((char *)prop->data, "pci"));
> > +
> > +	dt_device_bind_node(&dt_dev, node);
> > +	ret = dt_pbus_get_base(&dt_dev, &base);
> > +	assert(ret == 0);
> > +
> > +	prop = fdt_get_property(fdt, node, "bus-range", &len);
> > +	if (prop == NULL) {
> > +		assert(len == -FDT_ERR_NOTFOUND);
> > +		bus		= 0x00;
> > +		bus_max		= 0xff;
> > +	} else {
> > +		data		= (fdt32_t *)prop->data;
> > +		bus		= fdt32_to_cpu(data[0]);
> > +		bus_max		= fdt32_to_cpu(data[1]);
> > +		assert(bus <= bus_max);
> > +	}
> > +	assert(bus_max < base.size / (1 << PCI_ECAM_BUS_SHIFT));
> 
> I see you kept the inequality, rather than my suggestion to change it to
> assert(bus_max + 1 == base.size / (1 << PCI_ECAM_BUS_SHIFT)) Any reason
> why?

Because I do not read "bus-range" property description as it should
match the host address space size. IOW, number of implemented busses
which is less than host address space does not appear as a failure.

> I'm not too worried about it though...

Re: [kvm-unit-tests PATCH v5 11/12] pci: Add pci-testdev PCI bus test device

[Alexander Gordeev]

On Thu, Jul 21, 2016 at 10:17:48AM +0200, Andrew Jones wrote:
> On Tue, Jul 19, 2016 at 02:53:08PM +0200, Alexander Gordeev wrote:
> > Cc: Thomas Huth <thuth@redhat.com>
> > Cc: Andrew Jones <drjones@redhat.com>
> > Reviewed-by: Andrew Jones <drjones@redhat.com>
> > Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
> > ---
> >  lib/pci-testdev.c | 188 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
> >  lib/pci.h         |   7 ++
> >  2 files changed, 195 insertions(+)
> >  create mode 100644 lib/pci-testdev.c
> > 
> > diff --git a/lib/pci-testdev.c b/lib/pci-testdev.c
> > new file mode 100644
> > index 000000000000..1ee4a3ca0df8
> > --- /dev/null
> > +++ b/lib/pci-testdev.c
> > @@ -0,0 +1,188 @@
> > +/*
> > + * QEMU "pci-testdev" PCI test device
> > + *
> > + * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
> > + *
> > + * This work is licensed under the terms of the GNU LGPL, version 2.
> > + */
> > +#include "pci.h"
> > +#include "asm/io.h"
> > +
> > +struct pci_testdev_ops {
> > +	u8 (*io_readb)(const volatile void *addr);
> > +	u16 (*io_readw)(const volatile void *addr);
> > +	u32 (*io_readl)(const volatile void *addr);
> > +	void (*io_writeb)(u8 value, volatile void *addr);
> > +	void (*io_writew)(u16 value, volatile void *addr);
> > +	void (*io_writel)(u32 value, volatile void *addr);
> > +};
> > +
> > +static u8 pio_readb(const volatile void *addr)
> > +{
> > +	return inb((unsigned long)addr);
> > +}
> > +
> > +static u16 pio_readw(const volatile void *addr)
> > +{
> > +	return inw((unsigned long)addr);
> > +}
> > +
> > +static u32 pio_readl(const volatile void *addr)
> > +{
> > +	return inl((unsigned long)addr);
> > +}
> > +
> > +static void pio_writeb(u8 value, volatile void *addr)
> > +{
> > +	outb(value, (unsigned long)addr);
> > +}
> > +
> > +static void pio_writew(u16 value, volatile void *addr)
> > +{
> > +	outw(value, (unsigned long)addr);
> > +}
> > +
> > +static void pio_writel(u32 value, volatile void *addr)
> > +{
> > +	outl(value, (unsigned long)addr);
> > +}
> > +
> > +static struct pci_testdev_ops pci_testdev_io_ops = {
> > +	.io_readb	= pio_readb,
> > +	.io_readw	= pio_readw,
> > +	.io_readl	= pio_readl,
> > +	.io_writeb	= pio_writeb,
> > +	.io_writew	= pio_writew,
> > +	.io_writel	= pio_writel
> > +};
> > +
> > +static u8 mmio_readb(const volatile void *addr)
> > +{
> > +	return *(const volatile u8 __force *)addr;
> > +}
> > +
> > +static u16 mmio_readw(const volatile void *addr)
> > +{
> > +	return *(const volatile u16 __force *)addr;
> > +}
> > +
> > +static u32 mmio_readl(const volatile void *addr)
> > +{
> > +	return *(const volatile u32 __force *)addr;
> > +}
> > +
> > +static void mmio_writeb(u8 value, volatile void *addr)
> > +{
> > +	*(volatile u8 __force *)addr = value;
> > +}
> > +
> > +static void mmio_writew(u16 value, volatile void *addr)
> > +{
> > +	*(volatile u16 __force *)addr = value;
> > +}
> > +
> > +static void mmio_writel(u32 value, volatile void *addr)
> > +{
> > +	*(volatile u32 __force *)addr = value;
> > +}
> > +
> > +static struct pci_testdev_ops pci_testdev_mem_ops = {
> > +	.io_readb	= mmio_readb,
> > +	.io_readw	= mmio_readw,
> > +	.io_readl	= mmio_readl,
> > +	.io_writeb	= mmio_writeb,
> > +	.io_writew	= mmio_writew,
> > +	.io_writel	= mmio_writel
> > +};
> > +
> > +static bool pci_testdev_one(struct pci_test_dev_hdr *test,
> > +			    int test_nr,
> > +			    struct pci_testdev_ops *ops)
> > +{
> > +	u8 width;
> > +	u32 count, sig, off;
> > +	const int nr_writes = 16;
> > +	int i;
> > +
> > +	ops->io_writeb(test_nr, &test->test);
> > +	count = ops->io_readl(&test->count);
> > +	if (count != 0)
> > +		return false;
> > +
> > +	width = ops->io_readb(&test->width);
> > +	if (width != 1 && width != 2 && width != 4)
> > +		return false;
> > +
> > +	sig = ops->io_readl(&test->data);
> > +	off = ops->io_readl(&test->offset);
> > +
> > +	for (i = 0; i < nr_writes; i++) {
> > +		switch (width) {
> > +		case 1: ops->io_writeb(sig, (void *)test + off); break;
> > +		case 2: ops->io_writew(sig, (void *)test + off); break;
> > +		case 4: ops->io_writel(sig, (void *)test + off); break;
> > +		}
> > +	}
> > +
> > +	count = ops->io_readl(&test->count);
> > +	if (!count)
> > +		return true;
> > +
> > +	return (int)count == nr_writes;
> > +}
> > +
> > +void pci_testdev_print(struct pci_test_dev_hdr *test,
> > +		       struct pci_testdev_ops *ops)
> > +{
> > +	bool io = (ops == &pci_testdev_io_ops);
> > +	int i;
> > +
> > +	printf("pci-testdev %3s: ", io ? "io" : "mem");
> > +	for (i = 0;; ++i) {
> > +		char c = ops->io_readb(&test->name[i]);
> > +		if (!c)
> > +			break;
> > +		printf("%c", c);
> > +	}
> > +	printf("\n");
> > +}
> > +
> > +static int pci_testdev_all(struct pci_test_dev_hdr *test,
> > +			   struct pci_testdev_ops *ops)
> > +{
> > +	int i;
> > +
> > +	for (i = 0;; i++) {
> > +		if (!pci_testdev_one(test, i, ops))
> > +			break;
> > +		pci_testdev_print(test, ops);
> > +	}
> > +
> > +	return i;
> > +}
> > +
> > +int pci_testdev(void)
> > +{
> > +	phys_addr_t addr;
> > +	void __iomem *mem, *io;
> > +	pcidevaddr_t dev;
> > +	int nr_tests = 0;
> > +
> > +	dev = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST);
> > +	if (dev == PCIDEVADDR_INVALID)
> 
> You should output an error message here, saying it's not found. You could
> suggest how to provide it, i.e. '-device pci-testdev' too.
> 
> > +		return -1;
> > +
> > +	if (!pci_bar_is_valid(dev, 0) || !pci_bar_is_valid(dev, 1))
> 
> Needs error message. Actually, why can this happen? Can it? Shouldn't
> this just be an assert?

I think it is a matter of interpretation. If the device does exist,
but does not report these BARs it could mean (a) device layout failure
or (b) device/PCI misoperation. The latter is a test failure while
the former could be both a test failure and a fatal failure. I tend
treating is as (b).

> > +		return -1;
> > +
> > +	addr = pci_bar_get_addr(dev, 0);
> > +	mem = ioremap(addr, PAGE_SIZE);
> > +
> > +	addr = pci_bar_get_addr(dev, 1);
> > +	io = (void *)(unsigned long)addr;
> > +
> > +	nr_tests += pci_testdev_all(mem, &pci_testdev_mem_ops);
> > +	nr_tests += pci_testdev_all(io, &pci_testdev_io_ops);
> > +
> > +	return nr_tests;
> > +}
> > diff --git a/lib/pci.h b/lib/pci.h
> > index e00e1471d80a..5afe87a66998 100644
> > --- a/lib/pci.h
> > +++ b/lib/pci.h
> > @@ -40,6 +40,8 @@ bool pci_bar_is64(pcidevaddr_t dev, int bar_num);
> >  bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num);
> >  bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num);
> >  
> > +int pci_testdev(void);
> > +
> >  /*
> >   * pci-testdev is a driver for the pci-testdev qemu pci device. The
> >   * device enables testing mmio and portio exits, and measuring their
> > @@ -48,7 +50,12 @@ bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num);
> >  #define PCI_VENDOR_ID_REDHAT		0x1b36
> >  #define PCI_DEVICE_ID_REDHAT_TEST	0x0005
> >  
> > +/*
> > + * pci-testdev supports at least three types of tests (via mmio and
> > + * portio BARs): no-eventfd, wildcard-eventfd and datamatch-eventfd
> > + */
> >  #define PCI_TESTDEV_NUM_BARS		2
> > +#define PCI_TESTDEV_NUM_TESTS		3
> >  
> >  struct pci_test_dev_hdr {
> >  	uint8_t  test;
> > -- 
> > 1.8.3.1
> > 
> > --
> > To unsubscribe from this list: send the line "unsubscribe kvm" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [kvm-unit-tests PATCH v5 11/12] pci: Add pci-testdev PCI bus test device

[Andrew Jones]

On Thu, Jul 28, 2016 at 12:30:43PM +0200, Alexander Gordeev wrote:
> On Thu, Jul 21, 2016 at 10:17:48AM +0200, Andrew Jones wrote:
> > On Tue, Jul 19, 2016 at 02:53:08PM +0200, Alexander Gordeev wrote:
> > > Cc: Thomas Huth <thuth@redhat.com>
> > > Cc: Andrew Jones <drjones@redhat.com>
> > > Reviewed-by: Andrew Jones <drjones@redhat.com>
> > > Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
> > > ---
> > >  lib/pci-testdev.c | 188 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
> > >  lib/pci.h         |   7 ++
> > >  2 files changed, 195 insertions(+)
> > >  create mode 100644 lib/pci-testdev.c
> > > 
> > > diff --git a/lib/pci-testdev.c b/lib/pci-testdev.c
> > > new file mode 100644
> > > index 000000000000..1ee4a3ca0df8
> > > --- /dev/null
> > > +++ b/lib/pci-testdev.c
> > > @@ -0,0 +1,188 @@
> > > +/*
> > > + * QEMU "pci-testdev" PCI test device
> > > + *
> > > + * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
> > > + *
> > > + * This work is licensed under the terms of the GNU LGPL, version 2.
> > > + */
> > > +#include "pci.h"
> > > +#include "asm/io.h"
> > > +
> > > +struct pci_testdev_ops {
> > > +	u8 (*io_readb)(const volatile void *addr);
> > > +	u16 (*io_readw)(const volatile void *addr);
> > > +	u32 (*io_readl)(const volatile void *addr);
> > > +	void (*io_writeb)(u8 value, volatile void *addr);
> > > +	void (*io_writew)(u16 value, volatile void *addr);
> > > +	void (*io_writel)(u32 value, volatile void *addr);
> > > +};
> > > +
> > > +static u8 pio_readb(const volatile void *addr)
> > > +{
> > > +	return inb((unsigned long)addr);
> > > +}
> > > +
> > > +static u16 pio_readw(const volatile void *addr)
> > > +{
> > > +	return inw((unsigned long)addr);
> > > +}
> > > +
> > > +static u32 pio_readl(const volatile void *addr)
> > > +{
> > > +	return inl((unsigned long)addr);
> > > +}
> > > +
> > > +static void pio_writeb(u8 value, volatile void *addr)
> > > +{
> > > +	outb(value, (unsigned long)addr);
> > > +}
> > > +
> > > +static void pio_writew(u16 value, volatile void *addr)
> > > +{
> > > +	outw(value, (unsigned long)addr);
> > > +}
> > > +
> > > +static void pio_writel(u32 value, volatile void *addr)
> > > +{
> > > +	outl(value, (unsigned long)addr);
> > > +}
> > > +
> > > +static struct pci_testdev_ops pci_testdev_io_ops = {
> > > +	.io_readb	= pio_readb,
> > > +	.io_readw	= pio_readw,
> > > +	.io_readl	= pio_readl,
> > > +	.io_writeb	= pio_writeb,
> > > +	.io_writew	= pio_writew,
> > > +	.io_writel	= pio_writel
> > > +};
> > > +
> > > +static u8 mmio_readb(const volatile void *addr)
> > > +{
> > > +	return *(const volatile u8 __force *)addr;
> > > +}
> > > +
> > > +static u16 mmio_readw(const volatile void *addr)
> > > +{
> > > +	return *(const volatile u16 __force *)addr;
> > > +}
> > > +
> > > +static u32 mmio_readl(const volatile void *addr)
> > > +{
> > > +	return *(const volatile u32 __force *)addr;
> > > +}
> > > +
> > > +static void mmio_writeb(u8 value, volatile void *addr)
> > > +{
> > > +	*(volatile u8 __force *)addr = value;
> > > +}
> > > +
> > > +static void mmio_writew(u16 value, volatile void *addr)
> > > +{
> > > +	*(volatile u16 __force *)addr = value;
> > > +}
> > > +
> > > +static void mmio_writel(u32 value, volatile void *addr)
> > > +{
> > > +	*(volatile u32 __force *)addr = value;
> > > +}
> > > +
> > > +static struct pci_testdev_ops pci_testdev_mem_ops = {
> > > +	.io_readb	= mmio_readb,
> > > +	.io_readw	= mmio_readw,
> > > +	.io_readl	= mmio_readl,
> > > +	.io_writeb	= mmio_writeb,
> > > +	.io_writew	= mmio_writew,
> > > +	.io_writel	= mmio_writel
> > > +};
> > > +
> > > +static bool pci_testdev_one(struct pci_test_dev_hdr *test,
> > > +			    int test_nr,
> > > +			    struct pci_testdev_ops *ops)
> > > +{
> > > +	u8 width;
> > > +	u32 count, sig, off;
> > > +	const int nr_writes = 16;
> > > +	int i;
> > > +
> > > +	ops->io_writeb(test_nr, &test->test);
> > > +	count = ops->io_readl(&test->count);
> > > +	if (count != 0)
> > > +		return false;
> > > +
> > > +	width = ops->io_readb(&test->width);
> > > +	if (width != 1 && width != 2 && width != 4)
> > > +		return false;
> > > +
> > > +	sig = ops->io_readl(&test->data);
> > > +	off = ops->io_readl(&test->offset);
> > > +
> > > +	for (i = 0; i < nr_writes; i++) {
> > > +		switch (width) {
> > > +		case 1: ops->io_writeb(sig, (void *)test + off); break;
> > > +		case 2: ops->io_writew(sig, (void *)test + off); break;
> > > +		case 4: ops->io_writel(sig, (void *)test + off); break;
> > > +		}
> > > +	}
> > > +
> > > +	count = ops->io_readl(&test->count);
> > > +	if (!count)
> > > +		return true;
> > > +
> > > +	return (int)count == nr_writes;
> > > +}
> > > +
> > > +void pci_testdev_print(struct pci_test_dev_hdr *test,
> > > +		       struct pci_testdev_ops *ops)
> > > +{
> > > +	bool io = (ops == &pci_testdev_io_ops);
> > > +	int i;
> > > +
> > > +	printf("pci-testdev %3s: ", io ? "io" : "mem");
> > > +	for (i = 0;; ++i) {
> > > +		char c = ops->io_readb(&test->name[i]);
> > > +		if (!c)
> > > +			break;
> > > +		printf("%c", c);
> > > +	}
> > > +	printf("\n");
> > > +}
> > > +
> > > +static int pci_testdev_all(struct pci_test_dev_hdr *test,
> > > +			   struct pci_testdev_ops *ops)
> > > +{
> > > +	int i;
> > > +
> > > +	for (i = 0;; i++) {
> > > +		if (!pci_testdev_one(test, i, ops))
> > > +			break;
> > > +		pci_testdev_print(test, ops);
> > > +	}
> > > +
> > > +	return i;
> > > +}
> > > +
> > > +int pci_testdev(void)
> > > +{
> > > +	phys_addr_t addr;
> > > +	void __iomem *mem, *io;
> > > +	pcidevaddr_t dev;
> > > +	int nr_tests = 0;
> > > +
> > > +	dev = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST);
> > > +	if (dev == PCIDEVADDR_INVALID)
> > 
> > You should output an error message here, saying it's not found. You could
> > suggest how to provide it, i.e. '-device pci-testdev' too.
> > 
> > > +		return -1;
> > > +
> > > +	if (!pci_bar_is_valid(dev, 0) || !pci_bar_is_valid(dev, 1))
> > 
> > Needs error message. Actually, why can this happen? Can it? Shouldn't
> > this just be an assert?
> 
> I think it is a matter of interpretation. If the device does exist,
> but does not report these BARs it could mean (a) device layout failure
> or (b) device/PCI misoperation. The latter is a test failure while
> the former could be both a test failure and a fatal failure. I tend
> treating is as (b).

A single test function (pci_testdev) with multiple failures needs multiple
exit codes. If -1 means unexpected failure, and is used for multiple
conditions, then it's not useful for unit testing. You should create
more exit codes and check them; e.g.

 ret = pci_testdev();
 report("TEST1", ret != ERROR1);
 report("TEST2", ret != ERROR2);
 ...

But, if this test is quite unlikely to fail, and most likely only to fail
if the QEMU pci-testdev code breaks, then I think an assert() is the most
appropriate action.

Thanks,
drew

[kvm-unit-tests PATCH v6 09/12] pci: Add generic ECAM host support

[Alexander Gordeev]

Unlike x86, other architectures using generic ECAM PCI host
do not have a luxury of PCI bus initialized by a BIOS and
ready to use at start. Thus, we need allocate and assign
resources to all devices, much like an architecture's
firmware would do.

There is no any sort of resource management for memory and
io spaces, since only ones-per-BAR allocations are expected
and no deallocations at all.

Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
 lib/asm-generic/pci-host-bridge.h |  26 ++++
 lib/pci-host-generic.c            | 295 ++++++++++++++++++++++++++++++++++++++
 lib/pci-host-generic.h            |  46 ++++++
 lib/pci.c                         |   4 +-
 lib/pci.h                         |   3 +
 5 files changed, 372 insertions(+), 2 deletions(-)
 create mode 100644 lib/asm-generic/pci-host-bridge.h
 create mode 100644 lib/pci-host-generic.c
 create mode 100644 lib/pci-host-generic.h

diff --git a/lib/asm-generic/pci-host-bridge.h b/lib/asm-generic/pci-host-bridge.h
new file mode 100644
index 000000000000..ac32b85198e9
--- /dev/null
+++ b/lib/asm-generic/pci-host-bridge.h
@@ -0,0 +1,26 @@
+#ifndef _ASM_PCI_HOST_BRIDGE_H_
+#define _ASM_PCI_HOST_BRIDGE_H_
+/*
+ * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ */
+#include "libcflat.h"
+
+phys_addr_t pci_host_bridge_get_paddr(uint64_t addr);
+
+static inline
+phys_addr_t pci_translate_addr(pcidevaddr_t dev __unused, uint64_t addr)
+{
+	/*
+	 * Assume we only have single PCI host bridge in a system.
+	 */
+	return pci_host_bridge_get_paddr(addr);
+}
+
+uint8_t pci_config_readb(pcidevaddr_t dev, uint8_t reg);
+uint16_t pci_config_readw(pcidevaddr_t dev, uint8_t reg);
+uint32_t pci_config_readl(pcidevaddr_t dev, uint8_t reg);
+void pci_config_writel(pcidevaddr_t dev, uint8_t reg, uint32_t val);
+
+#endif
diff --git a/lib/pci-host-generic.c b/lib/pci-host-generic.c
new file mode 100644
index 000000000000..4a2716a33150
--- /dev/null
+++ b/lib/pci-host-generic.c
@@ -0,0 +1,295 @@
+/*
+ * Generic PCI host controller as described in PCI Bus Binding to Open Firmware
+ *
+ * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ */
+#include "libcflat.h"
+#include "devicetree.h"
+#include "alloc.h"
+#include "pci.h"
+#include "asm/pci.h"
+#include "asm/io.h"
+#include "pci-host-generic.h"
+#include <linux/pci_regs.h>
+
+static struct pci_host_bridge *pci_host_bridge;
+
+static int of_flags_to_pci_type(u32 of_flags)
+{
+	static int type_map[] = {
+		[1] = PCI_BASE_ADDRESS_SPACE_IO,
+		[2] = PCI_BASE_ADDRESS_MEM_TYPE_32,
+		[3] = PCI_BASE_ADDRESS_MEM_TYPE_64
+	};
+	int idx = (of_flags >> 24) & 0x03;
+	int res;
+
+	assert(idx > 0);
+	res = type_map[idx];
+
+	if (of_flags & 0x40000000)
+		res |= PCI_BASE_ADDRESS_MEM_PREFETCH;
+
+	return res;
+}
+
+static int pci_bar_type(u32 bar)
+{
+	if (bar & PCI_BASE_ADDRESS_SPACE)
+		return PCI_BASE_ADDRESS_SPACE_IO;
+	else
+		return bar & (PCI_BASE_ADDRESS_MEM_TYPE_MASK |
+			      PCI_BASE_ADDRESS_MEM_PREFETCH);
+}
+
+/*
+ * Probe DT for a generic PCI host controller
+ * See kernel Documentation/devicetree/bindings/pci/host-generic-pci.txt
+ * and function gen_pci_probe() in drivers/pci/host/pci-host-generic.c
+ */
+static struct pci_host_bridge *pci_dt_probe(void)
+{
+	struct pci_host_bridge *host;
+	const void *fdt = dt_fdt();
+	const struct fdt_property *prop;
+	struct dt_pbus_reg base;
+	struct dt_device dt_dev;
+	struct dt_bus dt_bus;
+	struct pci_addr_space *as;
+	fdt32_t *data;
+	u32 bus, bus_max;
+	u32 nac, nsc, nac_root, nsc_root;
+	int nr_range_cells, nr_addr_spaces;
+	int ret, node, len, i;
+
+	if (!dt_available()) {
+		printf("No device tree found\n");
+		return NULL;
+	}
+
+	dt_bus_init_defaults(&dt_bus);
+	dt_device_init(&dt_dev, &dt_bus, NULL);
+
+	node = fdt_path_offset(fdt, "/");
+	assert(node >= 0);
+
+	ret = dt_get_nr_cells(node, &nac_root, &nsc_root);
+	assert(ret == 0);
+	assert(nac_root == 1 || nac_root == 2);
+
+	node = fdt_node_offset_by_compatible(fdt, node,
+					     "pci-host-ecam-generic");
+	if (node == -FDT_ERR_NOTFOUND) {
+		printf("No PCIe ECAM compatible controller found\n");
+		return NULL;
+	}
+	assert(node >= 0);
+
+	prop = fdt_get_property(fdt, node, "device_type", &len);
+	assert(prop && len == 4 && !strcmp((char *)prop->data, "pci"));
+
+	dt_device_bind_node(&dt_dev, node);
+	ret = dt_pbus_get_base(&dt_dev, &base);
+	assert(ret == 0);
+
+	prop = fdt_get_property(fdt, node, "bus-range", &len);
+	if (prop == NULL) {
+		assert(len == -FDT_ERR_NOTFOUND);
+		bus		= 0x00;
+		bus_max		= 0xff;
+	} else {
+		data		= (fdt32_t *)prop->data;
+		bus		= fdt32_to_cpu(data[0]);
+		bus_max		= fdt32_to_cpu(data[1]);
+		assert(bus <= bus_max);
+	}
+	assert(bus_max < base.size / (1 << PCI_ECAM_BUS_SHIFT));
+
+	ret = dt_get_nr_cells(node, &nac, &nsc);
+	assert(ret == 0);
+	assert(nac == 3 && nsc == 2);
+
+	prop = fdt_get_property(fdt, node, "ranges", &len);
+	assert(prop != NULL);
+
+	nr_range_cells = nac + nsc + nac_root;
+	nr_addr_spaces = (len / 4) / nr_range_cells;
+	assert(nr_addr_spaces);
+
+	host = malloc(sizeof(*host) +
+		      sizeof(host->addr_space[0]) * nr_addr_spaces);
+	assert(host != NULL);
+
+	host->start		= base.addr;
+	host->size		= base.size;
+	host->bus		= bus;
+	host->bus_max		= bus_max;
+	host->nr_addr_spaces	= nr_addr_spaces;
+
+	data = (fdt32_t *)prop->data;
+	as = &host->addr_space[0];
+
+	for (i = 0; i < nr_addr_spaces; i++) {
+		/*
+		 * The PCI binding encodes the PCI address with three
+		 * cells as follows:
+		 *
+		 * phys.hi  cell: npt000ss bbbbbbbb dddddfff rrrrrrrr
+		 * phys.mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
+		 * phys.lo  cell: llllllll llllllll llllllll llllllll
+		 *
+		 * PCI device bus address and flags are encoded into phys.high
+		 * PCI 64 bit address is encoded into phys.mid and phys.low
+		 */
+		as->type = of_flags_to_pci_type(fdt32_to_cpu(data[0]));
+		as->pci_start = ((u64)fdt32_to_cpu(data[1]) << 32) |
+				fdt32_to_cpu(data[2]);
+
+		if (nr_range_cells == 6) {
+			as->start = fdt32_to_cpu(data[3]);
+			as->size  = ((u64)fdt32_to_cpu(data[4]) << 32) |
+				    fdt32_to_cpu(data[5]);
+		} else {
+			as->start = ((u64)fdt32_to_cpu(data[3]) << 32) |
+				    fdt32_to_cpu(data[4]);
+			as->size  = ((u64)fdt32_to_cpu(data[5]) << 32) |
+				    fdt32_to_cpu(data[6]);
+		}
+
+		data += nr_range_cells;
+		as++;
+	}
+
+	return host;
+}
+
+static u64 pci_alloc_resource(u32 bar, u64 size)
+{
+	struct pci_host_bridge *host = pci_host_bridge;
+	struct pci_addr_space *as = &host->addr_space[0];
+	phys_addr_t addr;
+	u32 mask;
+	int i;
+
+	for (i = 0; i < host->nr_addr_spaces; i++) {
+		if (as->type == pci_bar_type(bar))
+			break;
+		as++;
+	}
+	if (i >= host->nr_addr_spaces) {
+		printf("No PCI resource found for a device\n");
+		assert(0);
+	}
+
+	mask = pci_bar_mask(bar);
+	size = ALIGN(size, ~mask + 1);
+	assert(as->allocated + size <= as->size);
+
+	addr = as->pci_start + as->allocated;
+	as->allocated += size;
+
+	return addr;
+}
+
+bool pci_probe(void)
+{
+	pcidevaddr_t dev;
+	u8 header;
+	u32 cmd;
+	int i;
+
+	assert(!pci_host_bridge);
+	pci_host_bridge = pci_dt_probe();
+	if (!pci_host_bridge)
+		return false;
+
+	for (dev = 0; dev < 256; dev++) {
+		if (!pci_dev_exists(dev))
+			continue;
+
+		/* We are only interested in normal PCI devices */
+		header = pci_config_readb(dev, PCI_HEADER_TYPE);
+		if ((header & PCI_HEADER_TYPE_MASK) != PCI_HEADER_TYPE_NORMAL)
+			continue;
+
+		cmd = PCI_COMMAND_SERR;
+
+		for (i = 0; i < 6; i++) {
+			u64 addr, size;
+			u32 bar;
+
+			size = pci_bar_size(dev, i);
+			if (!size)
+				continue;
+
+			bar = pci_bar_get(dev, i);
+			addr = pci_alloc_resource(bar, size);
+			pci_bar_set_addr(dev, i, addr);
+
+			if (pci_bar_is_memory(dev, i))
+				cmd |= PCI_COMMAND_MEMORY;
+			else
+				cmd |= PCI_COMMAND_IO;
+
+			if (pci_bar_is64(dev, i))
+				i++;
+		}
+
+		pci_config_writel(dev, PCI_COMMAND, cmd);
+	}
+
+	return true;
+}
+
+/*
+ * This function is to be called from pci_translate_addr() to provide
+ * mapping between this host bridge's PCI busses address and CPU physical
+ * address.
+ */
+phys_addr_t pci_host_bridge_get_paddr(u64 pci_addr)
+{
+	struct pci_host_bridge *host = pci_host_bridge;
+	struct pci_addr_space *as = &host->addr_space[0];
+	int i;
+
+	for (i = 0; i < host->nr_addr_spaces; i++) {
+		if (pci_addr >= as->pci_start &&
+		    pci_addr < as->pci_start + as->size)
+			return as->start + (pci_addr - as->pci_start);
+		as++;
+	}
+
+	return 0;
+}
+
+static void __iomem *pci_get_dev_conf(struct pci_host_bridge *host, int devfn)
+{
+	return (void __iomem *)(unsigned long)
+		host->start + (devfn << PCI_ECAM_DEVFN_SHIFT);
+}
+
+u8 pci_config_readb(pcidevaddr_t dev, u8 off)
+{
+	void __iomem *conf = pci_get_dev_conf(pci_host_bridge, dev);
+	return readb(conf + off);
+}
+
+u16 pci_config_readw(pcidevaddr_t dev, u8 off)
+{
+	void __iomem *conf = pci_get_dev_conf(pci_host_bridge, dev);
+	return readw(conf + off);
+}
+
+u32 pci_config_readl(pcidevaddr_t dev, u8 off)
+{
+	void __iomem *conf = pci_get_dev_conf(pci_host_bridge, dev);
+	return readl(conf + off);
+}
+
+void pci_config_writel(pcidevaddr_t dev, u8 off, u32 val)
+{
+	void __iomem *conf = pci_get_dev_conf(pci_host_bridge, dev);
+	writel(val, conf + off);
+}
diff --git a/lib/pci-host-generic.h b/lib/pci-host-generic.h
new file mode 100644
index 000000000000..fd30e7c74ed8
--- /dev/null
+++ b/lib/pci-host-generic.h
@@ -0,0 +1,46 @@
+#ifndef PCI_HOST_GENERIC_H
+#define PCI_HOST_GENERIC_H
+/*
+ * PCI host bridge supporting structures and constants
+ *
+ * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ */
+#include "libcflat.h"
+
+struct pci_addr_space {
+	phys_addr_t		pci_start;
+	phys_addr_t		start;
+	phys_addr_t		size;
+	phys_addr_t		allocated;
+	int			type;
+};
+
+struct pci_host_bridge {
+	phys_addr_t		start;
+	phys_addr_t		size;
+	int			bus;
+	int			bus_max;
+	int			nr_addr_spaces;
+	struct pci_addr_space	addr_space[];
+};
+
+/*
+ * The following constants are derived from Linux, see this source:
+ *
+ *         drivers/pci/host/pci-host-generic.c
+ *                 struct gen_pci_cfg_bus_ops::bus_shift
+ *                 int gen_pci_parse_map_cfg_windows(struct gen_pci *pci)
+ *
+ * Documentation/devicetree/bindings/pci/host-generic-pci.txt describes
+ * ECAM Configuration Space is be memory-mapped by concatenating the various
+ * components to form an offset:
+ *
+ *	cfg_offset(bus, device, function, register) =
+ *		   bus << 20 | device << 15 | function << 12 | register
+ */
+#define PCI_ECAM_BUS_SHIFT	20
+#define PCI_ECAM_DEVFN_SHIFT	12
+
+#endif
diff --git a/lib/pci.c b/lib/pci.c
index 4271ae5b528e..4bdfd803fd80 100644
--- a/lib/pci.c
+++ b/lib/pci.c
@@ -27,13 +27,13 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)
 	return PCIDEVADDR_INVALID;
 }
 
-static uint32_t pci_bar_mask(uint32_t bar)
+uint32_t pci_bar_mask(uint32_t bar)
 {
 	return (bar & PCI_BASE_ADDRESS_SPACE_IO) ?
 		PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK;
 }
 
-static uint32_t pci_bar_get(pcidevaddr_t dev, int bar_num)
+uint32_t pci_bar_get(pcidevaddr_t dev, int bar_num)
 {
 	return pci_config_readl(dev, PCI_BASE_ADDRESS_0 + bar_num * 4);
 }
diff --git a/lib/pci.h b/lib/pci.h
index 5038a0c8cbb4..d0585a0451c2 100644
--- a/lib/pci.h
+++ b/lib/pci.h
@@ -15,6 +15,7 @@ enum {
 	PCIDEVADDR_INVALID = 0xffff,
 };
 
+bool pci_probe(void);
 void pci_print(void);
 bool pci_dev_exists(pcidevaddr_t dev);
 pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);
@@ -34,6 +35,8 @@ pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id);
 phys_addr_t pci_bar_get_addr(pcidevaddr_t dev, int bar_num);
 void pci_bar_set_addr(pcidevaddr_t dev, int bar_num, phys_addr_t addr);
 phys_addr_t pci_bar_size(pcidevaddr_t dev, int bar_num);
+uint32_t pci_bar_get(pcidevaddr_t dev, int bar_num);
+uint32_t pci_bar_mask(uint32_t bar);
 bool pci_bar_is64(pcidevaddr_t dev, int bar_num);
 bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num);
 bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num);
-- 
1.8.3.1

[kvm-unit-tests PATCH v6 10/12] arm/arm64: pci: Add PCI bus operation test

[Alexander Gordeev]

Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
 arm/Makefile.common |  5 ++++-
 arm/pci-test.c      | 21 +++++++++++++++++++++
 lib/arm/asm/pci.h   |  4 ++++
 lib/arm64/asm/pci.h |  1 +
 4 files changed, 30 insertions(+), 1 deletion(-)
 create mode 100644 arm/pci-test.c
 create mode 100644 lib/arm/asm/pci.h
 create mode 100644 lib/arm64/asm/pci.h

diff --git a/arm/Makefile.common b/arm/Makefile.common
index ccb554d9251a..97179bbea4e7 100644
--- a/arm/Makefile.common
+++ b/arm/Makefile.common
@@ -11,7 +11,8 @@ endif
 
 tests-common = \
 	$(TEST_DIR)/selftest.flat \
-	$(TEST_DIR)/spinlock-test.flat
+	$(TEST_DIR)/spinlock-test.flat \
+	$(TEST_DIR)/pci-test.flat
 
 all: test_cases
 
@@ -33,6 +34,8 @@ include scripts/asm-offsets.mak
 cflatobjs += lib/util.o
 cflatobjs += lib/alloc.o
 cflatobjs += lib/devicetree.o
+cflatobjs += lib/pci.o
+cflatobjs += lib/pci-host-generic.o
 cflatobjs += lib/virtio.o
 cflatobjs += lib/virtio-mmio.o
 cflatobjs += lib/chr-testdev.o
diff --git a/arm/pci-test.c b/arm/pci-test.c
new file mode 100644
index 000000000000..315a4e5e986c
--- /dev/null
+++ b/arm/pci-test.c
@@ -0,0 +1,21 @@
+/*
+ * PCI bus operation test
+ *
+ * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ */
+#include <libcflat.h>
+#include <pci.h>
+
+int main(void)
+{
+	if (!pci_probe()) {
+		printf("PCI bus probing failed\n");
+		abort();
+	}
+
+	pci_print();
+
+	return report_summary();
+}
diff --git a/lib/arm/asm/pci.h b/lib/arm/asm/pci.h
new file mode 100644
index 000000000000..c6467496614b
--- /dev/null
+++ b/lib/arm/asm/pci.h
@@ -0,0 +1,4 @@
+#ifndef _ASMARM_PCI_H_
+#define _ASMARM_PCI_H_
+#include "asm-generic/pci-host-bridge.h"
+#endif
diff --git a/lib/arm64/asm/pci.h b/lib/arm64/asm/pci.h
new file mode 100644
index 000000000000..f70ef560e2ab
--- /dev/null
+++ b/lib/arm64/asm/pci.h
@@ -0,0 +1 @@
+#include "../../arm/asm/pci.h"
-- 
1.8.3.1

[kvm-unit-tests PATCH v6 11/12] pci: Add pci-testdev PCI bus test device

[Alexander Gordeev]

Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
 lib/pci-testdev.c | 192 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 lib/pci.h         |   7 ++
 2 files changed, 199 insertions(+)
 create mode 100644 lib/pci-testdev.c

diff --git a/lib/pci-testdev.c b/lib/pci-testdev.c
new file mode 100644
index 000000000000..ad482d3291c7
--- /dev/null
+++ b/lib/pci-testdev.c
@@ -0,0 +1,192 @@
+/*
+ * QEMU "pci-testdev" PCI test device
+ *
+ * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.
+ */
+#include "pci.h"
+#include "asm/io.h"
+
+struct pci_testdev_ops {
+	u8 (*io_readb)(const volatile void *addr);
+	u16 (*io_readw)(const volatile void *addr);
+	u32 (*io_readl)(const volatile void *addr);
+	void (*io_writeb)(u8 value, volatile void *addr);
+	void (*io_writew)(u16 value, volatile void *addr);
+	void (*io_writel)(u32 value, volatile void *addr);
+};
+
+static u8 pio_readb(const volatile void *addr)
+{
+	return inb((unsigned long)addr);
+}
+
+static u16 pio_readw(const volatile void *addr)
+{
+	return inw((unsigned long)addr);
+}
+
+static u32 pio_readl(const volatile void *addr)
+{
+	return inl((unsigned long)addr);
+}
+
+static void pio_writeb(u8 value, volatile void *addr)
+{
+	outb(value, (unsigned long)addr);
+}
+
+static void pio_writew(u16 value, volatile void *addr)
+{
+	outw(value, (unsigned long)addr);
+}
+
+static void pio_writel(u32 value, volatile void *addr)
+{
+	outl(value, (unsigned long)addr);
+}
+
+static struct pci_testdev_ops pci_testdev_io_ops = {
+	.io_readb	= pio_readb,
+	.io_readw	= pio_readw,
+	.io_readl	= pio_readl,
+	.io_writeb	= pio_writeb,
+	.io_writew	= pio_writew,
+	.io_writel	= pio_writel
+};
+
+static u8 mmio_readb(const volatile void *addr)
+{
+	return *(const volatile u8 __force *)addr;
+}
+
+static u16 mmio_readw(const volatile void *addr)
+{
+	return *(const volatile u16 __force *)addr;
+}
+
+static u32 mmio_readl(const volatile void *addr)
+{
+	return *(const volatile u32 __force *)addr;
+}
+
+static void mmio_writeb(u8 value, volatile void *addr)
+{
+	*(volatile u8 __force *)addr = value;
+}
+
+static void mmio_writew(u16 value, volatile void *addr)
+{
+	*(volatile u16 __force *)addr = value;
+}
+
+static void mmio_writel(u32 value, volatile void *addr)
+{
+	*(volatile u32 __force *)addr = value;
+}
+
+static struct pci_testdev_ops pci_testdev_mem_ops = {
+	.io_readb	= mmio_readb,
+	.io_readw	= mmio_readw,
+	.io_readl	= mmio_readl,
+	.io_writeb	= mmio_writeb,
+	.io_writew	= mmio_writew,
+	.io_writel	= mmio_writel
+};
+
+static bool pci_testdev_one(struct pci_test_dev_hdr *test,
+			    int test_nr,
+			    struct pci_testdev_ops *ops)
+{
+	u8 width;
+	u32 count, sig, off;
+	const int nr_writes = 16;
+	int i;
+
+	ops->io_writeb(test_nr, &test->test);
+	count = ops->io_readl(&test->count);
+	if (count != 0)
+		return false;
+
+	width = ops->io_readb(&test->width);
+	if (width != 1 && width != 2 && width != 4)
+		return false;
+
+	sig = ops->io_readl(&test->data);
+	off = ops->io_readl(&test->offset);
+
+	for (i = 0; i < nr_writes; i++) {
+		switch (width) {
+		case 1: ops->io_writeb(sig, (void *)test + off); break;
+		case 2: ops->io_writew(sig, (void *)test + off); break;
+		case 4: ops->io_writel(sig, (void *)test + off); break;
+		}
+	}
+
+	count = ops->io_readl(&test->count);
+	if (!count)
+		return true;
+
+	return (int)count == nr_writes;
+}
+
+void pci_testdev_print(struct pci_test_dev_hdr *test,
+		       struct pci_testdev_ops *ops)
+{
+	bool io = (ops == &pci_testdev_io_ops);
+	int i;
+
+	printf("pci-testdev %3s: ", io ? "io" : "mem");
+	for (i = 0;; ++i) {
+		char c = ops->io_readb(&test->name[i]);
+		if (!c)
+			break;
+		printf("%c", c);
+	}
+	printf("\n");
+}
+
+static int pci_testdev_all(struct pci_test_dev_hdr *test,
+			   struct pci_testdev_ops *ops)
+{
+	int i;
+
+	for (i = 0;; i++) {
+		if (!pci_testdev_one(test, i, ops))
+			break;
+		pci_testdev_print(test, ops);
+	}
+
+	return i;
+}
+
+int pci_testdev(void)
+{
+	phys_addr_t addr;
+	void __iomem *mem, *io;
+	pcidevaddr_t dev;
+	int nr_tests = 0;
+	bool ret;
+
+	dev = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST);
+	if (dev == PCIDEVADDR_INVALID) {
+		printf("'pci-testdev' device is not found, "
+		       "check QEMU '-device pci-testdev' parameter\n");
+		return -1;
+	}
+
+	ret = pci_bar_is_valid(dev, 0) && pci_bar_is_valid(dev, 1);
+	assert(ret);
+
+	addr = pci_bar_get_addr(dev, 0);
+	mem = ioremap(addr, PAGE_SIZE);
+
+	addr = pci_bar_get_addr(dev, 1);
+	io = (void *)(unsigned long)addr;
+
+	nr_tests += pci_testdev_all(mem, &pci_testdev_mem_ops);
+	nr_tests += pci_testdev_all(io, &pci_testdev_io_ops);
+
+	return nr_tests;
+}
diff --git a/lib/pci.h b/lib/pci.h
index d0585a0451c2..a0187fed96b0 100644
--- a/lib/pci.h
+++ b/lib/pci.h
@@ -41,6 +41,8 @@ bool pci_bar_is64(pcidevaddr_t dev, int bar_num);
 bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num);
 bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num);
 
+int pci_testdev(void);
+
 /*
  * pci-testdev is a driver for the pci-testdev qemu pci device. The
  * device enables testing mmio and portio exits, and measuring their
@@ -49,7 +51,12 @@ bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num);
 #define PCI_VENDOR_ID_REDHAT		0x1b36
 #define PCI_DEVICE_ID_REDHAT_TEST	0x0005
 
+/*
+ * pci-testdev supports at least three types of tests (via mmio and
+ * portio BARs): no-eventfd, wildcard-eventfd and datamatch-eventfd
+ */
 #define PCI_TESTDEV_NUM_BARS		2
+#define PCI_TESTDEV_NUM_TESTS		3
 
 struct pci_test_dev_hdr {
 	uint8_t  test;
-- 
1.8.3.1

[kvm-unit-tests PATCH v6 12/12] arm/arm64: pci: Add pci-testdev PCI device operation test

[Alexander Gordeev]

Suggested-by: Andrew Jones <drjones@redhat.com>
Cc: Thomas Huth <thuth@redhat.com>
Cc: Andrew Jones <drjones@redhat.com>
Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
---
 arm/Makefile.common | 1 +
 arm/pci-test.c      | 8 ++++++++
 arm/run             | 7 ++++++-
 3 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/arm/Makefile.common b/arm/Makefile.common
index 97179bbea4e7..f37b5c2a3de4 100644
--- a/arm/Makefile.common
+++ b/arm/Makefile.common
@@ -36,6 +36,7 @@ cflatobjs += lib/alloc.o
 cflatobjs += lib/devicetree.o
 cflatobjs += lib/pci.o
 cflatobjs += lib/pci-host-generic.o
+cflatobjs += lib/pci-testdev.o
 cflatobjs += lib/virtio.o
 cflatobjs += lib/virtio-mmio.o
 cflatobjs += lib/chr-testdev.o
diff --git a/arm/pci-test.c b/arm/pci-test.c
index 315a4e5e986c..3030f2cfaf59 100644
--- a/arm/pci-test.c
+++ b/arm/pci-test.c
@@ -8,8 +8,12 @@
 #include <libcflat.h>
 #include <pci.h>
 
+#define NR_TESTS (PCI_TESTDEV_NUM_BARS * PCI_TESTDEV_NUM_TESTS)
+
 int main(void)
 {
+	int ret;
+
 	if (!pci_probe()) {
 		printf("PCI bus probing failed\n");
 		abort();
@@ -17,5 +21,9 @@ int main(void)
 
 	pci_print();
 
+	ret = pci_testdev();
+	report("PCI test device passed %d/%d tests",
+		ret >= NR_TESTS, ret > 0 ? ret : 0, NR_TESTS);
+
 	return report_summary();
 }
diff --git a/arm/run b/arm/run
index a2f35ef6a7e6..1ee6231599d6 100755
--- a/arm/run
+++ b/arm/run
@@ -67,8 +67,13 @@ fi
 chr_testdev='-device virtio-serial-device'
 chr_testdev+=' -device virtconsole,chardev=ctd -chardev testdev,id=ctd'
 
+pci_testdev=
+if $qemu $M -device '?' 2>&1 | grep pci-testdev > /dev/null; then
+	pci_testdev="-device pci-testdev"
+fi
+
 M+=",accel=$ACCEL"
-command="$qemu $M -cpu $processor $chr_testdev"
+command="$qemu $M -cpu $processor $chr_testdev $pci_testdev"
 command+=" -display none -serial stdio -kernel"
 command="$(timeout_cmd) $command"
 echo $command "$@"
-- 
1.8.3.1

Re: [kvm-unit-tests PATCH v6 10/12] arm/arm64: pci: Add PCI bus operation test

[Andrew Jones]

On Fri, Jul 29, 2016 at 02:00:01PM +0200, Alexander Gordeev wrote:
> Cc: Thomas Huth <thuth@redhat.com>
> Cc: Andrew Jones <drjones@redhat.com>
> Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
> ---
>  arm/Makefile.common |  5 ++++-
>  arm/pci-test.c      | 21 +++++++++++++++++++++
>  lib/arm/asm/pci.h   |  4 ++++
>  lib/arm64/asm/pci.h |  1 +
>  4 files changed, 30 insertions(+), 1 deletion(-)
>  create mode 100644 arm/pci-test.c
>  create mode 100644 lib/arm/asm/pci.h
>  create mode 100644 lib/arm64/asm/pci.h
> 
> diff --git a/arm/Makefile.common b/arm/Makefile.common
> index ccb554d9251a..97179bbea4e7 100644
> --- a/arm/Makefile.common
> +++ b/arm/Makefile.common
> @@ -11,7 +11,8 @@ endif
>  
>  tests-common = \
>  	$(TEST_DIR)/selftest.flat \
> -	$(TEST_DIR)/spinlock-test.flat
> +	$(TEST_DIR)/spinlock-test.flat \
> +	$(TEST_DIR)/pci-test.flat
>  
>  all: test_cases
>  
> @@ -33,6 +34,8 @@ include scripts/asm-offsets.mak
>  cflatobjs += lib/util.o
>  cflatobjs += lib/alloc.o
>  cflatobjs += lib/devicetree.o
> +cflatobjs += lib/pci.o
> +cflatobjs += lib/pci-host-generic.o
>  cflatobjs += lib/virtio.o
>  cflatobjs += lib/virtio-mmio.o
>  cflatobjs += lib/chr-testdev.o
> diff --git a/arm/pci-test.c b/arm/pci-test.c
> new file mode 100644
> index 000000000000..315a4e5e986c
> --- /dev/null
> +++ b/arm/pci-test.c
> @@ -0,0 +1,21 @@
> +/*
> + * PCI bus operation test
> + *
> + * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
> + *
> + * This work is licensed under the terms of the GNU LGPL, version 2.
> + */
> +#include <libcflat.h>
> +#include <pci.h>
> +
> +int main(void)
> +{
> +	if (!pci_probe()) {
> +		printf("PCI bus probing failed\n");
> +		abort();

report_abort("PCI bus probing failed");

> +	}
> +
> +	pci_print();
> +
> +	return report_summary();
> +}
> diff --git a/lib/arm/asm/pci.h b/lib/arm/asm/pci.h
> new file mode 100644
> index 000000000000..c6467496614b
> --- /dev/null
> +++ b/lib/arm/asm/pci.h
> @@ -0,0 +1,4 @@
> +#ifndef _ASMARM_PCI_H_
> +#define _ASMARM_PCI_H_

You don't need the #ifndef, asm-generic/pci-host-bridge.h has it's own
guard.

> +#include "asm-generic/pci-host-bridge.h"
> +#endif
> diff --git a/lib/arm64/asm/pci.h b/lib/arm64/asm/pci.h
> new file mode 100644
> index 000000000000..f70ef560e2ab
> --- /dev/null
> +++ b/lib/arm64/asm/pci.h
> @@ -0,0 +1 @@
> +#include "../../arm/asm/pci.h"
> -- 
> 1.8.3.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe kvm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [kvm-unit-tests PATCH v6 11/12] pci: Add pci-testdev PCI bus test device

[Andrew Jones]

On Fri, Jul 29, 2016 at 02:01:05PM +0200, Alexander Gordeev wrote:
> Cc: Thomas Huth <thuth@redhat.com>
> Cc: Andrew Jones <drjones@redhat.com>
> Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
> ---
>  lib/pci-testdev.c | 192 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  lib/pci.h         |   7 ++
>  2 files changed, 199 insertions(+)
>  create mode 100644 lib/pci-testdev.c

Reviewed-by: Andrew Jones <drjones@redhat.com>

Also a series-wide comment below though.

> 
> diff --git a/lib/pci-testdev.c b/lib/pci-testdev.c
> new file mode 100644
> index 000000000000..ad482d3291c7
> --- /dev/null
> +++ b/lib/pci-testdev.c
> @@ -0,0 +1,192 @@
> +/*
> + * QEMU "pci-testdev" PCI test device
> + *
> + * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
> + *
> + * This work is licensed under the terms of the GNU LGPL, version 2.
> + */
> +#include "pci.h"
> +#include "asm/io.h"
> +
> +struct pci_testdev_ops {
> +	u8 (*io_readb)(const volatile void *addr);
> +	u16 (*io_readw)(const volatile void *addr);
> +	u32 (*io_readl)(const volatile void *addr);
> +	void (*io_writeb)(u8 value, volatile void *addr);
> +	void (*io_writew)(u16 value, volatile void *addr);
> +	void (*io_writel)(u32 value, volatile void *addr);
> +};
> +
> +static u8 pio_readb(const volatile void *addr)
> +{
> +	return inb((unsigned long)addr);
> +}
> +
> +static u16 pio_readw(const volatile void *addr)
> +{
> +	return inw((unsigned long)addr);
> +}
> +
> +static u32 pio_readl(const volatile void *addr)
> +{
> +	return inl((unsigned long)addr);
> +}
> +
> +static void pio_writeb(u8 value, volatile void *addr)
> +{
> +	outb(value, (unsigned long)addr);
> +}
> +
> +static void pio_writew(u16 value, volatile void *addr)
> +{
> +	outw(value, (unsigned long)addr);
> +}
> +
> +static void pio_writel(u32 value, volatile void *addr)
> +{
> +	outl(value, (unsigned long)addr);
> +}
> +
> +static struct pci_testdev_ops pci_testdev_io_ops = {
> +	.io_readb	= pio_readb,
> +	.io_readw	= pio_readw,
> +	.io_readl	= pio_readl,
> +	.io_writeb	= pio_writeb,
> +	.io_writew	= pio_writew,
> +	.io_writel	= pio_writel
> +};
> +
> +static u8 mmio_readb(const volatile void *addr)
> +{
> +	return *(const volatile u8 __force *)addr;
> +}
> +
> +static u16 mmio_readw(const volatile void *addr)
> +{
> +	return *(const volatile u16 __force *)addr;
> +}
> +
> +static u32 mmio_readl(const volatile void *addr)
> +{
> +	return *(const volatile u32 __force *)addr;
> +}
> +
> +static void mmio_writeb(u8 value, volatile void *addr)
> +{
> +	*(volatile u8 __force *)addr = value;
> +}
> +
> +static void mmio_writew(u16 value, volatile void *addr)
> +{
> +	*(volatile u16 __force *)addr = value;
> +}
> +
> +static void mmio_writel(u32 value, volatile void *addr)
> +{
> +	*(volatile u32 __force *)addr = value;
> +}
> +
> +static struct pci_testdev_ops pci_testdev_mem_ops = {
> +	.io_readb	= mmio_readb,
> +	.io_readw	= mmio_readw,
> +	.io_readl	= mmio_readl,
> +	.io_writeb	= mmio_writeb,
> +	.io_writew	= mmio_writew,
> +	.io_writel	= mmio_writel
> +};
> +
> +static bool pci_testdev_one(struct pci_test_dev_hdr *test,
> +			    int test_nr,
> +			    struct pci_testdev_ops *ops)
> +{
> +	u8 width;
> +	u32 count, sig, off;
> +	const int nr_writes = 16;
> +	int i;
> +
> +	ops->io_writeb(test_nr, &test->test);
> +	count = ops->io_readl(&test->count);
> +	if (count != 0)
> +		return false;
> +
> +	width = ops->io_readb(&test->width);
> +	if (width != 1 && width != 2 && width != 4)
> +		return false;
> +
> +	sig = ops->io_readl(&test->data);
> +	off = ops->io_readl(&test->offset);
> +
> +	for (i = 0; i < nr_writes; i++) {
> +		switch (width) {
> +		case 1: ops->io_writeb(sig, (void *)test + off); break;
> +		case 2: ops->io_writew(sig, (void *)test + off); break;
> +		case 4: ops->io_writel(sig, (void *)test + off); break;
> +		}
> +	}
> +
> +	count = ops->io_readl(&test->count);
> +	if (!count)
> +		return true;
> +
> +	return (int)count == nr_writes;
> +}
> +
> +void pci_testdev_print(struct pci_test_dev_hdr *test,
> +		       struct pci_testdev_ops *ops)
> +{
> +	bool io = (ops == &pci_testdev_io_ops);
> +	int i;
> +
> +	printf("pci-testdev %3s: ", io ? "io" : "mem");
> +	for (i = 0;; ++i) {
> +		char c = ops->io_readb(&test->name[i]);
> +		if (!c)
> +			break;
> +		printf("%c", c);
> +	}
> +	printf("\n");
> +}
> +
> +static int pci_testdev_all(struct pci_test_dev_hdr *test,
> +			   struct pci_testdev_ops *ops)
> +{
> +	int i;
> +
> +	for (i = 0;; i++) {
> +		if (!pci_testdev_one(test, i, ops))
> +			break;
> +		pci_testdev_print(test, ops);
> +	}
> +
> +	return i;
> +}
> +
> +int pci_testdev(void)
> +{
> +	phys_addr_t addr;
> +	void __iomem *mem, *io;
> +	pcidevaddr_t dev;
> +	int nr_tests = 0;
> +	bool ret;
> +
> +	dev = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST);
> +	if (dev == PCIDEVADDR_INVALID) {
> +		printf("'pci-testdev' device is not found, "
> +		       "check QEMU '-device pci-testdev' parameter\n");
> +		return -1;
> +	}
> +
> +	ret = pci_bar_is_valid(dev, 0) && pci_bar_is_valid(dev, 1);
> +	assert(ret);
> +
> +	addr = pci_bar_get_addr(dev, 0);
> +	mem = ioremap(addr, PAGE_SIZE);
> +
> +	addr = pci_bar_get_addr(dev, 1);
> +	io = (void *)(unsigned long)addr;
> +
> +	nr_tests += pci_testdev_all(mem, &pci_testdev_mem_ops);
> +	nr_tests += pci_testdev_all(io, &pci_testdev_io_ops);
> +
> +	return nr_tests;
> +}
> diff --git a/lib/pci.h b/lib/pci.h
> index d0585a0451c2..a0187fed96b0 100644
> --- a/lib/pci.h
> +++ b/lib/pci.h
> @@ -41,6 +41,8 @@ bool pci_bar_is64(pcidevaddr_t dev, int bar_num);
>  bool pci_bar_is_memory(pcidevaddr_t dev, int bar_num);
>  bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num);

I just noticed that lib/pci.h function declarations are missing 'extern'.
It's sort of annoying that we have extern everywhere, but we do, and I
prefer consistency. Can you please fix that with a cleanup patch and
make sure all new function declarations added with this series also
have extern?

Thanks,
drew

>  
> +int pci_testdev(void);
> +
>  /*
>   * pci-testdev is a driver for the pci-testdev qemu pci device. The
>   * device enables testing mmio and portio exits, and measuring their
> @@ -49,7 +51,12 @@ bool pci_bar_is_valid(pcidevaddr_t dev, int bar_num);
>  #define PCI_VENDOR_ID_REDHAT		0x1b36
>  #define PCI_DEVICE_ID_REDHAT_TEST	0x0005
>  
> +/*
> + * pci-testdev supports at least three types of tests (via mmio and
> + * portio BARs): no-eventfd, wildcard-eventfd and datamatch-eventfd
> + */
>  #define PCI_TESTDEV_NUM_BARS		2
> +#define PCI_TESTDEV_NUM_TESTS		3
>  
>  struct pci_test_dev_hdr {
>  	uint8_t  test;
> -- 
> 1.8.3.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe kvm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [kvm-unit-tests PATCH v6 12/12] arm/arm64: pci: Add pci-testdev PCI device operation test

[Andrew Jones]

On Fri, Jul 29, 2016 at 02:01:43PM +0200, Alexander Gordeev wrote:
> Suggested-by: Andrew Jones <drjones@redhat.com>
> Cc: Thomas Huth <thuth@redhat.com>
> Cc: Andrew Jones <drjones@redhat.com>
> Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
> ---
>  arm/Makefile.common | 1 +
>  arm/pci-test.c      | 8 ++++++++
>  arm/run             | 7 ++++++-
>  3 files changed, 15 insertions(+), 1 deletion(-)

Reviewed-by: Andrew Jones <drjones@redhat.com>

> 
> diff --git a/arm/Makefile.common b/arm/Makefile.common
> index 97179bbea4e7..f37b5c2a3de4 100644
> --- a/arm/Makefile.common
> +++ b/arm/Makefile.common
> @@ -36,6 +36,7 @@ cflatobjs += lib/alloc.o
>  cflatobjs += lib/devicetree.o
>  cflatobjs += lib/pci.o
>  cflatobjs += lib/pci-host-generic.o
> +cflatobjs += lib/pci-testdev.o
>  cflatobjs += lib/virtio.o
>  cflatobjs += lib/virtio-mmio.o
>  cflatobjs += lib/chr-testdev.o
> diff --git a/arm/pci-test.c b/arm/pci-test.c
> index 315a4e5e986c..3030f2cfaf59 100644
> --- a/arm/pci-test.c
> +++ b/arm/pci-test.c
> @@ -8,8 +8,12 @@
>  #include <libcflat.h>
>  #include <pci.h>
>  
> +#define NR_TESTS (PCI_TESTDEV_NUM_BARS * PCI_TESTDEV_NUM_TESTS)
> +
>  int main(void)
>  {
> +	int ret;
> +
>  	if (!pci_probe()) {
>  		printf("PCI bus probing failed\n");
>  		abort();
> @@ -17,5 +21,9 @@ int main(void)
>  
>  	pci_print();
>  
> +	ret = pci_testdev();
> +	report("PCI test device passed %d/%d tests",
> +		ret >= NR_TESTS, ret > 0 ? ret : 0, NR_TESTS);
> +
>  	return report_summary();
>  }
> diff --git a/arm/run b/arm/run
> index a2f35ef6a7e6..1ee6231599d6 100755
> --- a/arm/run
> +++ b/arm/run
> @@ -67,8 +67,13 @@ fi
>  chr_testdev='-device virtio-serial-device'
>  chr_testdev+=' -device virtconsole,chardev=ctd -chardev testdev,id=ctd'
>  
> +pci_testdev=
> +if $qemu $M -device '?' 2>&1 | grep pci-testdev > /dev/null; then
> +	pci_testdev="-device pci-testdev"
> +fi
> +
>  M+=",accel=$ACCEL"
> -command="$qemu $M -cpu $processor $chr_testdev"
> +command="$qemu $M -cpu $processor $chr_testdev $pci_testdev"
>  command+=" -display none -serial stdio -kernel"
>  command="$(timeout_cmd) $command"
>  echo $command "$@"
> -- 
> 1.8.3.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe kvm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [kvm-unit-tests PATCH v5 00/12] PCI bus support

[Andrew Jones]

Hi Alex,

For v7 (which I'm sure will be the last :-) please repost the whole
series and, if you have a publicly accessible git tree, provide me a
branch from which I can pull it from. If you don't have a tree, it's
no biggy, I'll just grab the patches from mutt.

Thanks,
drew


On Tue, Jul 19, 2016 at 02:52:57PM +0200, Alexander Gordeev wrote:
> Hi Andrew,
> 
> This is 5th version of PCI support. Changes since v4 are mainly addressing
> nits and a rework of pci_bar_addr() function. The biggest change - the PCI
> test succeeds on arm, aarch64, i386 and x86_64 (I am not posting pci-testdev
> enablement for x86 though).
> 
> There are few changes (some of them to already Reviewed-by patches) worth
> a notice - here are the interdiffs commented:
> 
> [08/12] pci: Add pci_print(); pci_print() function:
>   - possibile devices with unimplemented gap BARs are printed correctly;
>   - pci_bar_size() is called once;
> 
> diff -u b/lib/pci.c b/lib/pci.c
> --- b/lib/pci.c
> +++ b/lib/pci.c
> @@ -146,14 +146,15 @@
>  		return;
>  
>  	for (i = 0; i < 6; i++) {
> -		phys_addr_t start, end;
> +		phys_addr_t size, start, end;
>  		uint32_t bar;
>  
> -		if (!pci_bar_is_valid(dev, i))
> -			break;
> +		size = pci_bar_size(dev, i);
> +		if (!size)
> +			continue;
>  
>  		start = pci_bar_get_addr(dev, i);
> -		end = start + pci_bar_size(dev, i) - 1;
> +		end = start + size - 1;
>  
>  		if (pci_bar_is64(dev, i)) {
>  			printf("\tBAR#%d,%d [%" PRIx64 "-%" PRIx64 " ",
> 
> [09/12] pci: Add generic ECAM host support; pci_probe() function:
>   - possibile devices with unimplemented gap BARs are scanned correctly;
> 
> @@ -276,7 +290,7 @@
>  +
>  +			size = pci_bar_size(dev, i);
>  +			if (!size)
> -+				break;
> ++				continue;
>  +
>  +			bar = pci_bar_get(dev, i);
>  +			addr = pci_alloc_resource(bar, size);
> 
> [11/12] pci: Add pci-testdev PCI bus test device; pci_testdev_one() function:
>   - no-eventfd vs eventfd accesses (clarified by Paolo on qemu-devel list)
>     are handled now;
> 
> @@ -124,7 +124,11 @@
>  		}
>  	}
>  
> -	return (int)ops->io_readl(&test->count) == nr_writes;
> +	count = ops->io_readl(&test->count);
> +	if (!count)
> +		return true;
> +
> +	return (int)count == nr_writes;
>  }
>  
>  void pci_testdev_print(struct pci_test_dev_hdr *test,
> 
> 
> Alexander Gordeev (12):
>   [01/12] pci: Fix coding style in generic PCI files
>   [02/12] pci: x86: Rename pci_config_read() to pci_config_readl()
>   [03/12] pci: x86: Add remaining PCI configuration space accessors
>   [04/12] pci: Rework pci_bar_addr()
>   [05/12] pci: Factor out pci_bar_get()
>   [06/12] pci: Add pci_bar_set_addr()
>   [07/12] pci: Add pci_dev_exists()
>   [08/12] pci: Add pci_print()
>   [09/12] pci: Add generic ECAM host support
>   [10/12] arm/arm64: pci: Add PCI bus operation test
>   [11/12] pci: Add pci-testdev PCI bus test device
>   [12/12] arm/arm64: pci: Add pci-testdev PCI device operation test
> 
>  arm/Makefile.common               |   6 +-
>  arm/pci-test.c                    |  31 ++++
>  arm/run                           |   7 +-
>  lib/arm/asm/pci.h                 |  11 ++
>  lib/arm64/asm/pci.h               |   1 +
>  lib/asm-generic/pci-host-bridge.h |  26 ++++
>  lib/pci-host-generic.c            | 295 ++++++++++++++++++++++++++++++++++++++
>  lib/pci-host-generic.h            |  46 ++++++
>  lib/pci-testdev.c                 | 188 ++++++++++++++++++++++++
>  lib/pci.c                         | 201 +++++++++++++++++++++++---
>  lib/pci.h                         |  34 ++++-
>  lib/x86/asm/pci.h                 |  31 +++-
>  x86/vmexit.c                      |   4 +-
>  13 files changed, 853 insertions(+), 28 deletions(-)
>  create mode 100644 arm/pci-test.c
>  create mode 100644 lib/arm/asm/pci.h
>  create mode 100644 lib/arm64/asm/pci.h
>  create mode 100644 lib/asm-generic/pci-host-bridge.h
>  create mode 100644 lib/pci-host-generic.c
>  create mode 100644 lib/pci-host-generic.h
>  create mode 100644 lib/pci-testdev.c
> 
> -- 
> 1.8.3.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe kvm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [kvm-unit-tests PATCH v6 10/12] arm/arm64: pci: Add PCI bus operation test

[Andrew Jones]

Forgot to say in last reply,

Otherwise

Reviewed-by: Andrew Jones <drjones@redhat.com>

On Fri, Jul 29, 2016 at 03:06:40PM +0200, Andrew Jones wrote:
> On Fri, Jul 29, 2016 at 02:00:01PM +0200, Alexander Gordeev wrote:
> > Cc: Thomas Huth <thuth@redhat.com>
> > Cc: Andrew Jones <drjones@redhat.com>
> > Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
> > ---
> >  arm/Makefile.common |  5 ++++-
> >  arm/pci-test.c      | 21 +++++++++++++++++++++
> >  lib/arm/asm/pci.h   |  4 ++++
> >  lib/arm64/asm/pci.h |  1 +
> >  4 files changed, 30 insertions(+), 1 deletion(-)
> >  create mode 100644 arm/pci-test.c
> >  create mode 100644 lib/arm/asm/pci.h
> >  create mode 100644 lib/arm64/asm/pci.h
> > 
> > diff --git a/arm/Makefile.common b/arm/Makefile.common
> > index ccb554d9251a..97179bbea4e7 100644
> > --- a/arm/Makefile.common
> > +++ b/arm/Makefile.common
> > @@ -11,7 +11,8 @@ endif
> >  
> >  tests-common = \
> >  	$(TEST_DIR)/selftest.flat \
> > -	$(TEST_DIR)/spinlock-test.flat
> > +	$(TEST_DIR)/spinlock-test.flat \
> > +	$(TEST_DIR)/pci-test.flat
> >  
> >  all: test_cases
> >  
> > @@ -33,6 +34,8 @@ include scripts/asm-offsets.mak
> >  cflatobjs += lib/util.o
> >  cflatobjs += lib/alloc.o
> >  cflatobjs += lib/devicetree.o
> > +cflatobjs += lib/pci.o
> > +cflatobjs += lib/pci-host-generic.o
> >  cflatobjs += lib/virtio.o
> >  cflatobjs += lib/virtio-mmio.o
> >  cflatobjs += lib/chr-testdev.o
> > diff --git a/arm/pci-test.c b/arm/pci-test.c
> > new file mode 100644
> > index 000000000000..315a4e5e986c
> > --- /dev/null
> > +++ b/arm/pci-test.c
> > @@ -0,0 +1,21 @@
> > +/*
> > + * PCI bus operation test
> > + *
> > + * Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
> > + *
> > + * This work is licensed under the terms of the GNU LGPL, version 2.
> > + */
> > +#include <libcflat.h>
> > +#include <pci.h>
> > +
> > +int main(void)
> > +{
> > +	if (!pci_probe()) {
> > +		printf("PCI bus probing failed\n");
> > +		abort();
> 
> report_abort("PCI bus probing failed");
> 
> > +	}
> > +
> > +	pci_print();
> > +
> > +	return report_summary();
> > +}
> > diff --git a/lib/arm/asm/pci.h b/lib/arm/asm/pci.h
> > new file mode 100644
> > index 000000000000..c6467496614b
> > --- /dev/null
> > +++ b/lib/arm/asm/pci.h
> > @@ -0,0 +1,4 @@
> > +#ifndef _ASMARM_PCI_H_
> > +#define _ASMARM_PCI_H_
> 
> You don't need the #ifndef, asm-generic/pci-host-bridge.h has it's own
> guard.
> 
> > +#include "asm-generic/pci-host-bridge.h"
> > +#endif
> > diff --git a/lib/arm64/asm/pci.h b/lib/arm64/asm/pci.h
> > new file mode 100644
> > index 000000000000..f70ef560e2ab
> > --- /dev/null
> > +++ b/lib/arm64/asm/pci.h
> > @@ -0,0 +1 @@
> > +#include "../../arm/asm/pci.h"
> > -- 
> > 1.8.3.1
> > 
> > --
> > To unsubscribe from this list: send the line "unsubscribe kvm" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
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Re: [kvm-unit-tests PATCH v6 12/12] arm/arm64: pci: Add pci-testdev PCI device operation test

[Andrew Jones]

This patch is missing the arm/unittests.cfg test addition.
Please add for v7.

Thanks,
drew


On Fri, Jul 29, 2016 at 02:01:43PM +0200, Alexander Gordeev wrote:
> Suggested-by: Andrew Jones <drjones@redhat.com>
> Cc: Thomas Huth <thuth@redhat.com>
> Cc: Andrew Jones <drjones@redhat.com>
> Signed-off-by: Alexander Gordeev <agordeev@redhat.com>
> ---
>  arm/Makefile.common | 1 +
>  arm/pci-test.c      | 8 ++++++++
>  arm/run             | 7 ++++++-
>  3 files changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/arm/Makefile.common b/arm/Makefile.common
> index 97179bbea4e7..f37b5c2a3de4 100644
> --- a/arm/Makefile.common
> +++ b/arm/Makefile.common
> @@ -36,6 +36,7 @@ cflatobjs += lib/alloc.o
>  cflatobjs += lib/devicetree.o
>  cflatobjs += lib/pci.o
>  cflatobjs += lib/pci-host-generic.o
> +cflatobjs += lib/pci-testdev.o
>  cflatobjs += lib/virtio.o
>  cflatobjs += lib/virtio-mmio.o
>  cflatobjs += lib/chr-testdev.o
> diff --git a/arm/pci-test.c b/arm/pci-test.c
> index 315a4e5e986c..3030f2cfaf59 100644
> --- a/arm/pci-test.c
> +++ b/arm/pci-test.c
> @@ -8,8 +8,12 @@
>  #include <libcflat.h>
>  #include <pci.h>
>  
> +#define NR_TESTS (PCI_TESTDEV_NUM_BARS * PCI_TESTDEV_NUM_TESTS)
> +
>  int main(void)
>  {
> +	int ret;
> +
>  	if (!pci_probe()) {
>  		printf("PCI bus probing failed\n");
>  		abort();
> @@ -17,5 +21,9 @@ int main(void)
>  
>  	pci_print();
>  
> +	ret = pci_testdev();
> +	report("PCI test device passed %d/%d tests",
> +		ret >= NR_TESTS, ret > 0 ? ret : 0, NR_TESTS);
> +
>  	return report_summary();
>  }
> diff --git a/arm/run b/arm/run
> index a2f35ef6a7e6..1ee6231599d6 100755
> --- a/arm/run
> +++ b/arm/run
> @@ -67,8 +67,13 @@ fi
>  chr_testdev='-device virtio-serial-device'
>  chr_testdev+=' -device virtconsole,chardev=ctd -chardev testdev,id=ctd'
>  
> +pci_testdev=
> +if $qemu $M -device '?' 2>&1 | grep pci-testdev > /dev/null; then
> +	pci_testdev="-device pci-testdev"
> +fi
> +
>  M+=",accel=$ACCEL"
> -command="$qemu $M -cpu $processor $chr_testdev"
> +command="$qemu $M -cpu $processor $chr_testdev $pci_testdev"
>  command+=" -display none -serial stdio -kernel"
>  command="$(timeout_cmd) $command"
>  echo $command "$@"
> -- 
> 1.8.3.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe kvm" in
> the body of a message to majordomo@vger.kernel.org
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Re: [kvm-unit-tests PATCH v6 12/12] arm/arm64: pci: Add pci-testdev PCI device operation test

[Alexander Gordeev]

On Fri, Jul 29, 2016 at 03:40:36PM +0200, Andrew Jones wrote:
> 
> This patch is missing the arm/unittests.cfg test addition.
> Please add for v7.

If such one is okay?

[pci-test]
file = pci-test.flat
groups = pci

> Thanks,
> drew

Re: [kvm-unit-tests PATCH v6 12/12] arm/arm64: pci: Add pci-testdev PCI device operation test

[Andrew Jones]

On Tue, Aug 16, 2016 at 05:27:21PM +0200, Alexander Gordeev wrote:
> On Fri, Jul 29, 2016 at 03:40:36PM +0200, Andrew Jones wrote:
> > 
> > This patch is missing the arm/unittests.cfg test addition.
> > Please add for v7.
> 
> If such one is okay?
> 
> [pci-test]
> file = pci-test.flat
> groups = pci

yup. that's it

thanks,
drew