Re: [PATCH v2] mmc: sunxi: Handle the 'New Timings'

Re: [PATCH v2] mmc: sunxi: Handle the 'New Timings'

[Mark Rutland]

On Mon, Aug 01, 2016 at 03:10:29PM +0200, Jean-Francois Moine wrote:
> Some MMC devices as mmc2 in the A83T or mmc1 and mmc2 in the H3 have
> a 'New Timings' mode.
> Set this capacity in the DT and use it when possible.

What exactly is this "New Timings" mode?

Why do we wnat to set it? Improved performance, power?

Is it *necessary* to use it?

> Signed-off-by: Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>
> ---
> I don't know if this mode works or is needed at 25MHz.
> ---
>  Documentation/devicetree/bindings/mmc/sunxi-mmc.txt |  1 +
>  drivers/mmc/host/sunxi-mmc.c                        | 21 +++++++++++++++++++--
>  2 files changed, 20 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> index 4bf41d8..a541bf4 100644
> --- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> +++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> @@ -19,6 +19,7 @@ Optional properties:
>   - reset-names : must contain "ahb"
>   - for cd, bus-width and additional generic mmc parameters
>     please refer to mmc.txt within this directory
> + - allwinner,new-timings: the controller may accept the "New Timings" mode

It's not at all clear to me what this means. This needs a better
description.

Which devices have this? Can we determine this based on compatible
string?

Mark.

[PATCH v2] mmc: sunxi: Handle the 'New Timings'

[Mark Rutland]

On Mon, Aug 01, 2016 at 03:10:29PM +0200, Jean-Francois Moine wrote:
> Some MMC devices as mmc2 in the A83T or mmc1 and mmc2 in the H3 have
> a 'New Timings' mode.
> Set this capacity in the DT and use it when possible.

What exactly is this "New Timings" mode?

Why do we wnat to set it? Improved performance, power?

Is it *necessary* to use it?

> Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
> ---
> I don't know if this mode works or is needed at 25MHz.
> ---
>  Documentation/devicetree/bindings/mmc/sunxi-mmc.txt |  1 +
>  drivers/mmc/host/sunxi-mmc.c                        | 21 +++++++++++++++++++--
>  2 files changed, 20 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> index 4bf41d8..a541bf4 100644
> --- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> +++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> @@ -19,6 +19,7 @@ Optional properties:
>   - reset-names : must contain "ahb"
>   - for cd, bus-width and additional generic mmc parameters
>     please refer to mmc.txt within this directory
> + - allwinner,new-timings: the controller may accept the "New Timings" mode

It's not at all clear to me what this means. This needs a better
description.

Which devices have this? Can we determine this based on compatible
string?

Mark.

Re: [PATCH v2] mmc: sunxi: Handle the 'New Timings'

[Jean-Francois Moine]

On Mon, 1 Aug 2016 16:30:19 +0100
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> wrote:

> On Mon, Aug 01, 2016 at 03:10:29PM +0200, Jean-Francois Moine wrote:
> > Some MMC devices as mmc2 in the A83T or mmc1 and mmc2 in the H3 have
> > a 'New Timings' mode.
> > Set this capacity in the DT and use it when possible.
> 
> What exactly is this "New Timings" mode?
> 
> Why do we wnat to set it? Improved performance, power?
> 
> Is it *necessary* to use it?

This mode is described at least in the Allwinner's documentation of the
A83T, A64 and H3.
>From my tests, it is required to access the eMMC of the Banana Pi M3
(mmc2).

> > Signed-off-by: Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>
> > ---
> > I don't know if this mode works or is needed at 25MHz.
> > ---
> >  Documentation/devicetree/bindings/mmc/sunxi-mmc.txt |  1 +
> >  drivers/mmc/host/sunxi-mmc.c                        | 21 +++++++++++++++++++--
> >  2 files changed, 20 insertions(+), 2 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> > index 4bf41d8..a541bf4 100644
> > --- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> > +++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> > @@ -19,6 +19,7 @@ Optional properties:
> >   - reset-names : must contain "ahb"
> >   - for cd, bus-width and additional generic mmc parameters
> >     please refer to mmc.txt within this directory
> > + - allwinner,new-timings: the controller may accept the "New Timings" mode
> 
> It's not at all clear to me what this means. This needs a better
> description.
> 
> Which devices have this? Can we determine this based on compatible
> string?

No, only some devices of the SoCs have this capability: the mmc2 of the
A83T, the smhc0 and smhc1 of the A64, and the mmc1 and mmc2 of the H3.

-- 
Ken ar c'hentañ	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/

-- 
You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
For more options, visit https://groups.google.com/d/optout.

[PATCH v2] mmc: sunxi: Handle the 'New Timings'

[Jean-Francois Moine]

On Mon, 1 Aug 2016 16:30:19 +0100
Mark Rutland <mark.rutland@arm.com> wrote:

> On Mon, Aug 01, 2016 at 03:10:29PM +0200, Jean-Francois Moine wrote:
> > Some MMC devices as mmc2 in the A83T or mmc1 and mmc2 in the H3 have
> > a 'New Timings' mode.
> > Set this capacity in the DT and use it when possible.
> 
> What exactly is this "New Timings" mode?
> 
> Why do we wnat to set it? Improved performance, power?
> 
> Is it *necessary* to use it?

This mode is described at least in the Allwinner's documentation of the
A83T, A64 and H3.
>From my tests, it is required to access the eMMC of the Banana Pi M3
(mmc2).

> > Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
> > ---
> > I don't know if this mode works or is needed at 25MHz.
> > ---
> >  Documentation/devicetree/bindings/mmc/sunxi-mmc.txt |  1 +
> >  drivers/mmc/host/sunxi-mmc.c                        | 21 +++++++++++++++++++--
> >  2 files changed, 20 insertions(+), 2 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> > index 4bf41d8..a541bf4 100644
> > --- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> > +++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> > @@ -19,6 +19,7 @@ Optional properties:
> >   - reset-names : must contain "ahb"
> >   - for cd, bus-width and additional generic mmc parameters
> >     please refer to mmc.txt within this directory
> > + - allwinner,new-timings: the controller may accept the "New Timings" mode
> 
> It's not at all clear to me what this means. This needs a better
> description.
> 
> Which devices have this? Can we determine this based on compatible
> string?

No, only some devices of the SoCs have this capability: the mmc2 of the
A83T, the smhc0 and smhc1 of the A64, and the mmc1 and mmc2 of the H3.

-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/

Re: [PATCH v2] mmc: sunxi: Handle the 'New Timings'

[Mark Rutland]

On Mon, Aug 01, 2016 at 06:26:03PM +0200, Jean-Francois Moine wrote:
> On Mon, 1 Aug 2016 16:30:19 +0100
> Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> wrote:
> 
> > On Mon, Aug 01, 2016 at 03:10:29PM +0200, Jean-Francois Moine wrote:
> > > Some MMC devices as mmc2 in the A83T or mmc1 and mmc2 in the H3 have
> > > a 'New Timings' mode.
> > > Set this capacity in the DT and use it when possible.
> > 
> > What exactly is this "New Timings" mode?
> > 
> > Why do we wnat to set it? Improved performance, power?
> > 
> > Is it *necessary* to use it?
> 
> This mode is described at least in the Allwinner's documentation of the
> A83T, A64 and H3.

Is this publicly available? If not, can the gist of it be described?

> From my tests, it is required to access the eMMC of the Banana Pi M3
> (mmc2).

Ok.

> > > Signed-off-by: Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>
> > > ---
> > > I don't know if this mode works or is needed at 25MHz.
> > > ---
> > >  Documentation/devicetree/bindings/mmc/sunxi-mmc.txt |  1 +
> > >  drivers/mmc/host/sunxi-mmc.c                        | 21 +++++++++++++++++++--
> > >  2 files changed, 20 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> > > index 4bf41d8..a541bf4 100644
> > > --- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> > > +++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> > > @@ -19,6 +19,7 @@ Optional properties:
> > >   - reset-names : must contain "ahb"
> > >   - for cd, bus-width and additional generic mmc parameters
> > >     please refer to mmc.txt within this directory
> > > + - allwinner,new-timings: the controller may accept the "New Timings" mode
> > 
> > It's not at all clear to me what this means. This needs a better
> > description.
> > 
> > Which devices have this? Can we determine this based on compatible
> > string?
> 
> No, only some devices of the SoCs have this capability: the mmc2 of the
> A83T, the smhc0 and smhc1 of the A64, and the mmc1 and mmc2 of the H3.

Ok.

Thanks,
Mark.

[PATCH v2] mmc: sunxi: Handle the 'New Timings'

[Mark Rutland]

On Mon, Aug 01, 2016 at 06:26:03PM +0200, Jean-Francois Moine wrote:
> On Mon, 1 Aug 2016 16:30:19 +0100
> Mark Rutland <mark.rutland@arm.com> wrote:
> 
> > On Mon, Aug 01, 2016 at 03:10:29PM +0200, Jean-Francois Moine wrote:
> > > Some MMC devices as mmc2 in the A83T or mmc1 and mmc2 in the H3 have
> > > a 'New Timings' mode.
> > > Set this capacity in the DT and use it when possible.
> > 
> > What exactly is this "New Timings" mode?
> > 
> > Why do we wnat to set it? Improved performance, power?
> > 
> > Is it *necessary* to use it?
> 
> This mode is described at least in the Allwinner's documentation of the
> A83T, A64 and H3.

Is this publicly available? If not, can the gist of it be described?

> From my tests, it is required to access the eMMC of the Banana Pi M3
> (mmc2).

Ok.

> > > Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
> > > ---
> > > I don't know if this mode works or is needed at 25MHz.
> > > ---
> > >  Documentation/devicetree/bindings/mmc/sunxi-mmc.txt |  1 +
> > >  drivers/mmc/host/sunxi-mmc.c                        | 21 +++++++++++++++++++--
> > >  2 files changed, 20 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> > > index 4bf41d8..a541bf4 100644
> > > --- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> > > +++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> > > @@ -19,6 +19,7 @@ Optional properties:
> > >   - reset-names : must contain "ahb"
> > >   - for cd, bus-width and additional generic mmc parameters
> > >     please refer to mmc.txt within this directory
> > > + - allwinner,new-timings: the controller may accept the "New Timings" mode
> > 
> > It's not at all clear to me what this means. This needs a better
> > description.
> > 
> > Which devices have this? Can we determine this based on compatible
> > string?
> 
> No, only some devices of the SoCs have this capability: the mmc2 of the
> A83T, the smhc0 and smhc1 of the A64, and the mmc1 and mmc2 of the H3.

Ok.

Thanks,
Mark.

Re: [PATCH v2] mmc: sunxi: Handle the 'New Timings'

[Jean-Francois Moine]

On Tue, 2 Aug 2016 12:20:48 +0100
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> wrote:

> > This mode is described at least in the Allwinner's documentation of the
> > A83T, A64 and H3.
> 
> Is this publicly available? If not, can the gist of it be described?

The links are in the kernel Documentation/arm/sunxi/README

-- 
Ken ar c'hentañ	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/

-- 
You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
For more options, visit https://groups.google.com/d/optout.

[PATCH v2] mmc: sunxi: Handle the 'New Timings'

[Jean-Francois Moine]

On Tue, 2 Aug 2016 12:20:48 +0100
Mark Rutland <mark.rutland@arm.com> wrote:

> > This mode is described at least in the Allwinner's documentation of the
> > A83T, A64 and H3.
> 
> Is this publicly available? If not, can the gist of it be described?

The links are in the kernel Documentation/arm/sunxi/README

-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/

Re: [PATCH v2] mmc: sunxi: Handle the 'New Timings'

[Icenowy Zheng]

02.08.2016, 19:48, "Jean-Francois Moine" <moinejf-GANU6spQydw@public.gmane.org>:
> On Tue, 2 Aug 2016 12:20:48 +0100
> Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> wrote:
>
>>  > This mode is described at least in the Allwinner's documentation of the
>>  > A83T, A64 and H3.
>>
>>  Is this publicly available? If not, can the gist of it be described?
>
> The links are in the kernel Documentation/arm/sunxi/README

All the SoCs you mentioned here have no data sheet link in the file.
I may submit a patch to fix this.

>
> --
> Ken ar c'hentañ | ** Breizh ha Linux atav! **
> Jef | http://moinejf.free.fr/
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
For more options, visit https://groups.google.com/d/optout.

[PATCH v2] mmc: sunxi: Handle the 'New Timings'

[Icenowy Zheng]

02.08.2016, 19:48, "Jean-Francois Moine" <moinejf@free.fr>:
> On Tue, 2 Aug 2016 12:20:48 +0100
> Mark Rutland <mark.rutland@arm.com> wrote:
>
>> ?> This mode is described at least in the Allwinner's documentation of the
>> ?> A83T, A64 and H3.
>>
>> ?Is this publicly available? If not, can the gist of it be described?
>
> The links are in the kernel Documentation/arm/sunxi/README

All the SoCs you mentioned here have no data sheet link in the file.
I may submit a patch to fix this.

>
> --
> Ken ar c'henta? | ** Breizh ha Linux atav! **
> Jef | http://moinejf.free.fr/
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v2] mmc: sunxi: Handle the 'New Timings'

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 2733 bytes --]

Hi Mark,

On Mon, Aug 01, 2016 at 04:30:19PM +0100, Mark Rutland wrote:
> On Mon, Aug 01, 2016 at 03:10:29PM +0200, Jean-Francois Moine wrote:
> > Some MMC devices as mmc2 in the A83T or mmc1 and mmc2 in the H3 have
> > a 'New Timings' mode.
> > Set this capacity in the DT and use it when possible.
> 
> What exactly is this "New Timings" mode?
> 
> Why do we wnat to set it? Improved performance, power?

Allwinner calls it under a rather generic name: "new mode" (which is
of course the opposite of the old mode).

In the old mode, the rate and phase controls were all handled by the
functional clock feeding the MMC controller.

In the new mode, the MMC controller itself is able to do some sort of
auto-calibration to adjust the rate and phase of the clock output on
the MMC bus.

> Is it *necessary* to use it?

Yes. Allwinner recommends to use it to enhance the compatibility with
MMC cards, and they say that it also improves the performances, even
though no one really checked. The main point for us at the moment is
that some eMMCs at least require the new mode to operate properly.

> > Signed-off-by: Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>
> > ---
> > I don't know if this mode works or is needed at 25MHz.
> > ---
> >  Documentation/devicetree/bindings/mmc/sunxi-mmc.txt |  1 +
> >  drivers/mmc/host/sunxi-mmc.c                        | 21 +++++++++++++++++++--
> >  2 files changed, 20 insertions(+), 2 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> > index 4bf41d8..a541bf4 100644
> > --- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> > +++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> > @@ -19,6 +19,7 @@ Optional properties:
> >   - reset-names : must contain "ahb"
> >   - for cd, bus-width and additional generic mmc parameters
> >     please refer to mmc.txt within this directory
> > + - allwinner,new-timings: the controller may accept the "New Timings" mode
> 
> It's not at all clear to me what this means. This needs a better
> description.
> 
> Which devices have this? Can we determine this based on compatible
> string?

On some SoCs, yes, on some, no.

The older SoCs (everything up to A80) only have the old mode, so the
compatible works there. The newer SoCs (H3, A64) support the new mode
on all their MMC controllers, so the compatible works too. However, in
the SoC Jean-Francois is currently working on, the A83T, the new mode
is only found in one (over three) controller.

So I really think we need a property to express this, at least in the
A83T case.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[PATCH v2] mmc: sunxi: Handle the 'New Timings'

[Maxime Ripard]

Hi Mark,

On Mon, Aug 01, 2016 at 04:30:19PM +0100, Mark Rutland wrote:
> On Mon, Aug 01, 2016 at 03:10:29PM +0200, Jean-Francois Moine wrote:
> > Some MMC devices as mmc2 in the A83T or mmc1 and mmc2 in the H3 have
> > a 'New Timings' mode.
> > Set this capacity in the DT and use it when possible.
> 
> What exactly is this "New Timings" mode?
> 
> Why do we wnat to set it? Improved performance, power?

Allwinner calls it under a rather generic name: "new mode" (which is
of course the opposite of the old mode).

In the old mode, the rate and phase controls were all handled by the
functional clock feeding the MMC controller.

In the new mode, the MMC controller itself is able to do some sort of
auto-calibration to adjust the rate and phase of the clock output on
the MMC bus.

> Is it *necessary* to use it?

Yes. Allwinner recommends to use it to enhance the compatibility with
MMC cards, and they say that it also improves the performances, even
though no one really checked. The main point for us at the moment is
that some eMMCs at least require the new mode to operate properly.

> > Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
> > ---
> > I don't know if this mode works or is needed at 25MHz.
> > ---
> >  Documentation/devicetree/bindings/mmc/sunxi-mmc.txt |  1 +
> >  drivers/mmc/host/sunxi-mmc.c                        | 21 +++++++++++++++++++--
> >  2 files changed, 20 insertions(+), 2 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> > index 4bf41d8..a541bf4 100644
> > --- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> > +++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> > @@ -19,6 +19,7 @@ Optional properties:
> >   - reset-names : must contain "ahb"
> >   - for cd, bus-width and additional generic mmc parameters
> >     please refer to mmc.txt within this directory
> > + - allwinner,new-timings: the controller may accept the "New Timings" mode
> 
> It's not at all clear to me what this means. This needs a better
> description.
> 
> Which devices have this? Can we determine this based on compatible
> string?

On some SoCs, yes, on some, no.

The older SoCs (everything up to A80) only have the old mode, so the
compatible works there. The newer SoCs (H3, A64) support the new mode
on all their MMC controllers, so the compatible works too. However, in
the SoC Jean-Francois is currently working on, the A83T, the new mode
is only found in one (over three) controller.

So I really think we need a property to express this, at least in the
A83T case.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160823/43972904/attachment.sig>

Re: [PATCH v2] mmc: sunxi: Handle the 'New Timings'

[Jean-Francois Moine]

Hi Chen-Yu,

On Mon, 1 Aug 2016 21:52:48 +0800
Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> wrote:

> On Mon, Aug 1, 2016 at 9:10 PM, Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org> wrote:
> > Some MMC devices as mmc2 in the A83T or mmc1 and mmc2 in the H3 have
> > a 'New Timings' mode.
> > Set this capacity in the DT and use it when possible.
> 
>            ^^ capability?
> 
> Also, in this patch you are adding support for a DT boolean flag
> property, not adding stuff to the DT.

Sorry, forgotten.

> >
> > Signed-off-by: Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>
> > ---
> 
> I got 3 copies of the same patch...

Maybe because I sent it to you, and to the mmc and sunxi lists.

> > I don't know if this mode works or is needed at 25MHz.
> 
> Could you test it? You can change mmc->f_max in the probe function
> to limit it to 25 MHz.
> 
> I'm more interested in the throughput you get after applying this
> patch though.

I did a test on a BPI-M2+ (H3). The new timings don't work at 25MHz,
neither for mmc1 (wifi) - nor for mmc2 (eMMC).

-- 
Ken ar c'hentañ	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/

-- 
You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
For more options, visit https://groups.google.com/d/optout.

[PATCH v2] mmc: sunxi: Handle the 'New Timings'

[Jean-Francois Moine]

Hi Chen-Yu,

On Mon, 1 Aug 2016 21:52:48 +0800
Chen-Yu Tsai <wens@csie.org> wrote:

> On Mon, Aug 1, 2016 at 9:10 PM, Jean-Francois Moine <moinejf@free.fr> wrote:
> > Some MMC devices as mmc2 in the A83T or mmc1 and mmc2 in the H3 have
> > a 'New Timings' mode.
> > Set this capacity in the DT and use it when possible.
> 
>            ^^ capability?
> 
> Also, in this patch you are adding support for a DT boolean flag
> property, not adding stuff to the DT.

Sorry, forgotten.

> >
> > Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
> > ---
> 
> I got 3 copies of the same patch...

Maybe because I sent it to you, and to the mmc and sunxi lists.

> > I don't know if this mode works or is needed at 25MHz.
> 
> Could you test it? You can change mmc->f_max in the probe function
> to limit it to 25 MHz.
> 
> I'm more interested in the throughput you get after applying this
> patch though.

I did a test on a BPI-M2+ (H3). The new timings don't work at 25MHz,
neither for mmc1 (wifi) - nor for mmc2 (eMMC).

-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/

Re: [PATCH v2] mmc: sunxi: Handle the 'New Timings'

[Chen-Yu Tsai]

Hi,

On Mon, Aug 1, 2016 at 9:10 PM, Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org> wrote:
> Some MMC devices as mmc2 in the A83T or mmc1 and mmc2 in the H3 have
> a 'New Timings' mode.
> Set this capacity in the DT and use it when possible.

           ^^ capability?

Also, in this patch you are adding support for a DT boolean flag
property, not adding stuff to the DT.

>
> Signed-off-by: Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>
> ---

I got 3 copies of the same patch...

> I don't know if this mode works or is needed at 25MHz.

Could you test it? You can change mmc->f_max in the probe function
to limit it to 25 MHz.

I'm more interested in the throughput you get after applying this
patch though.

> ---
>  Documentation/devicetree/bindings/mmc/sunxi-mmc.txt |  1 +
>  drivers/mmc/host/sunxi-mmc.c                        | 21 +++++++++++++++++++--
>  2 files changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> index 4bf41d8..a541bf4 100644
> --- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> +++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> @@ -19,6 +19,7 @@ Optional properties:
>   - reset-names : must contain "ahb"
>   - for cd, bus-width and additional generic mmc parameters
>     please refer to mmc.txt within this directory
> + - allwinner,new-timings: the controller may accept the "New Timings" mode
>
>  Examples:
>         - Within .dtsi:
> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
> index 2ee4c21..98922b5 100644
> --- a/drivers/mmc/host/sunxi-mmc.c
> +++ b/drivers/mmc/host/sunxi-mmc.c
> @@ -64,6 +64,7 @@
>  #define SDXC_REG_CBCR  (0x48) /* SMC CIU Byte Count Register */
>  #define SDXC_REG_BBCR  (0x4C) /* SMC BIU Byte Count Register */
>  #define SDXC_REG_DBGC  (0x50) /* SMC Debug Enable Register */
> +#define SDXC_REG_NTSR  (0x5c) /* SMC NewTiming Set Register */
>  #define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */
>  #define SDXC_REG_DMAC  (0x80) /* SMC IDMAC Control Register */
>  #define SDXC_REG_DLBA  (0x84) /* SMC IDMAC Descriptor List Base Addre */
> @@ -171,6 +172,9 @@
>  #define SDXC_SEND_AUTO_STOPCCSD                BIT(9)
>  #define SDXC_CEATA_DEV_IRQ_ENABLE      BIT(10)
>
> +/* NewTiming Set Register */
> +#define SDXC_NEWMODE_ENABLE            BIT(31)
> +
>  /* IDMA controller bus mod bit field */
>  #define SDXC_IDMAC_SOFT_RESET          BIT(0)
>  #define SDXC_IDMAC_FIX_BURST           BIT(1)
> @@ -261,6 +265,9 @@ struct sunxi_mmc_host {
>
>         /* vqmmc */
>         bool            vqmmc_enabled;
> +
> +       /* misc */
> +       bool            new_timings;    /* new timings capable */
>  };
>
>  static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
> @@ -715,8 +722,13 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
>                 return -EINVAL;
>         }
>
> -       clk_set_phase(host->clk_sample, sclk_dly);
> -       clk_set_phase(host->clk_output, oclk_dly);
> +       if (host->new_timings && rate >= 50000000) {
> +               mmc_writel(host, REG_NTSR,
> +                       mmc_readl(host, REG_NTSR) | SDXC_NEWMODE_ENABLE);
> +       } else {
> +               clk_set_phase(host->clk_sample, sclk_dly);
> +               clk_set_phase(host->clk_output, oclk_dly);
> +       }

Does this mean the old phase clock stuff will still be used for slower cards?
You should probably mention this in the commit log.

>
>         return sunxi_mmc_oclk_onoff(host, 1);
>  }
> @@ -1133,12 +1145,17 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
>         if (ret)
>                 goto error_free_dma;
>
> +       if (pdev->dev.of_node &&
> +           of_property_read_bool(pdev->dev.of_node, "allwinner,new-timings"))
> +               host->new_timings = true;
> +
>         ret = mmc_add_host(mmc);
>         if (ret)
>                 goto error_free_dma;
>
>         dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
>         platform_set_drvdata(pdev, mmc);
> +

This doesn't belong.

Regards
ChenYu

>         return 0;
>
>  error_free_dma:
> --
> 2.9.2
>

[PATCH v2] mmc: sunxi: Handle the 'New Timings'

[Chen-Yu Tsai]

Hi,

On Mon, Aug 1, 2016 at 9:10 PM, Jean-Francois Moine <moinejf@free.fr> wrote:
> Some MMC devices as mmc2 in the A83T or mmc1 and mmc2 in the H3 have
> a 'New Timings' mode.
> Set this capacity in the DT and use it when possible.

           ^^ capability?

Also, in this patch you are adding support for a DT boolean flag
property, not adding stuff to the DT.

>
> Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
> ---

I got 3 copies of the same patch...

> I don't know if this mode works or is needed at 25MHz.

Could you test it? You can change mmc->f_max in the probe function
to limit it to 25 MHz.

I'm more interested in the throughput you get after applying this
patch though.

> ---
>  Documentation/devicetree/bindings/mmc/sunxi-mmc.txt |  1 +
>  drivers/mmc/host/sunxi-mmc.c                        | 21 +++++++++++++++++++--
>  2 files changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> index 4bf41d8..a541bf4 100644
> --- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> +++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
> @@ -19,6 +19,7 @@ Optional properties:
>   - reset-names : must contain "ahb"
>   - for cd, bus-width and additional generic mmc parameters
>     please refer to mmc.txt within this directory
> + - allwinner,new-timings: the controller may accept the "New Timings" mode
>
>  Examples:
>         - Within .dtsi:
> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
> index 2ee4c21..98922b5 100644
> --- a/drivers/mmc/host/sunxi-mmc.c
> +++ b/drivers/mmc/host/sunxi-mmc.c
> @@ -64,6 +64,7 @@
>  #define SDXC_REG_CBCR  (0x48) /* SMC CIU Byte Count Register */
>  #define SDXC_REG_BBCR  (0x4C) /* SMC BIU Byte Count Register */
>  #define SDXC_REG_DBGC  (0x50) /* SMC Debug Enable Register */
> +#define SDXC_REG_NTSR  (0x5c) /* SMC NewTiming Set Register */
>  #define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */
>  #define SDXC_REG_DMAC  (0x80) /* SMC IDMAC Control Register */
>  #define SDXC_REG_DLBA  (0x84) /* SMC IDMAC Descriptor List Base Addre */
> @@ -171,6 +172,9 @@
>  #define SDXC_SEND_AUTO_STOPCCSD                BIT(9)
>  #define SDXC_CEATA_DEV_IRQ_ENABLE      BIT(10)
>
> +/* NewTiming Set Register */
> +#define SDXC_NEWMODE_ENABLE            BIT(31)
> +
>  /* IDMA controller bus mod bit field */
>  #define SDXC_IDMAC_SOFT_RESET          BIT(0)
>  #define SDXC_IDMAC_FIX_BURST           BIT(1)
> @@ -261,6 +265,9 @@ struct sunxi_mmc_host {
>
>         /* vqmmc */
>         bool            vqmmc_enabled;
> +
> +       /* misc */
> +       bool            new_timings;    /* new timings capable */
>  };
>
>  static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
> @@ -715,8 +722,13 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
>                 return -EINVAL;
>         }
>
> -       clk_set_phase(host->clk_sample, sclk_dly);
> -       clk_set_phase(host->clk_output, oclk_dly);
> +       if (host->new_timings && rate >= 50000000) {
> +               mmc_writel(host, REG_NTSR,
> +                       mmc_readl(host, REG_NTSR) | SDXC_NEWMODE_ENABLE);
> +       } else {
> +               clk_set_phase(host->clk_sample, sclk_dly);
> +               clk_set_phase(host->clk_output, oclk_dly);
> +       }

Does this mean the old phase clock stuff will still be used for slower cards?
You should probably mention this in the commit log.

>
>         return sunxi_mmc_oclk_onoff(host, 1);
>  }
> @@ -1133,12 +1145,17 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
>         if (ret)
>                 goto error_free_dma;
>
> +       if (pdev->dev.of_node &&
> +           of_property_read_bool(pdev->dev.of_node, "allwinner,new-timings"))
> +               host->new_timings = true;
> +
>         ret = mmc_add_host(mmc);
>         if (ret)
>                 goto error_free_dma;
>
>         dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
>         platform_set_drvdata(pdev, mmc);
> +

This doesn't belong.

Regards
ChenYu

>         return 0;
>
>  error_free_dma:
> --
> 2.9.2
>

[PATCH v2] mmc: sunxi: Handle the 'New Timings'

[Jean-Francois Moine]

Some MMC devices as mmc2 in the A83T or mmc1 and mmc2 in the H3 have
a 'New Timings' mode.
Set this capacity in the DT and use it when possible.

Signed-off-by: Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>
---
I don't know if this mode works or is needed at 25MHz.
---
 Documentation/devicetree/bindings/mmc/sunxi-mmc.txt |  1 +
 drivers/mmc/host/sunxi-mmc.c                        | 21 +++++++++++++++++++--
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
index 4bf41d8..a541bf4 100644
--- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
@@ -19,6 +19,7 @@ Optional properties:
  - reset-names : must contain "ahb"
  - for cd, bus-width and additional generic mmc parameters
    please refer to mmc.txt within this directory
+ - allwinner,new-timings: the controller may accept the "New Timings" mode
 
 Examples:
 	- Within .dtsi:
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 2ee4c21..98922b5 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -64,6 +64,7 @@
 #define SDXC_REG_CBCR	(0x48) /* SMC CIU Byte Count Register */
 #define SDXC_REG_BBCR	(0x4C) /* SMC BIU Byte Count Register */
 #define SDXC_REG_DBGC	(0x50) /* SMC Debug Enable Register */
+#define SDXC_REG_NTSR	(0x5c) /* SMC NewTiming Set Register */
 #define SDXC_REG_HWRST	(0x78) /* SMC Card Hardware Reset for Register */
 #define SDXC_REG_DMAC	(0x80) /* SMC IDMAC Control Register */
 #define SDXC_REG_DLBA	(0x84) /* SMC IDMAC Descriptor List Base Addre */
@@ -171,6 +172,9 @@
 #define SDXC_SEND_AUTO_STOPCCSD		BIT(9)
 #define SDXC_CEATA_DEV_IRQ_ENABLE	BIT(10)
 
+/* NewTiming Set Register */
+#define SDXC_NEWMODE_ENABLE		BIT(31)
+
 /* IDMA controller bus mod bit field */
 #define SDXC_IDMAC_SOFT_RESET		BIT(0)
 #define SDXC_IDMAC_FIX_BURST		BIT(1)
@@ -261,6 +265,9 @@ struct sunxi_mmc_host {
 
 	/* vqmmc */
 	bool		vqmmc_enabled;
+
+	/* misc */
+	bool		new_timings;	/* new timings capable */
 };
 
 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
@@ -715,8 +722,13 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
 		return -EINVAL;
 	}
 
-	clk_set_phase(host->clk_sample, sclk_dly);
-	clk_set_phase(host->clk_output, oclk_dly);
+	if (host->new_timings && rate >= 50000000) {
+		mmc_writel(host, REG_NTSR,
+			mmc_readl(host, REG_NTSR) | SDXC_NEWMODE_ENABLE);
+	} else {
+		clk_set_phase(host->clk_sample, sclk_dly);
+		clk_set_phase(host->clk_output, oclk_dly);
+	}
 
 	return sunxi_mmc_oclk_onoff(host, 1);
 }
@@ -1133,12 +1145,17 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
 	if (ret)
 		goto error_free_dma;
 
+	if (pdev->dev.of_node &&
+	    of_property_read_bool(pdev->dev.of_node, "allwinner,new-timings"))
+		host->new_timings = true;
+
 	ret = mmc_add_host(mmc);
 	if (ret)
 		goto error_free_dma;
 
 	dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
 	platform_set_drvdata(pdev, mmc);
+
 	return 0;
 
 error_free_dma:
-- 
2.9.2

[PATCH v2] mmc: sunxi: Handle the 'New Timings'

[Jean-Francois Moine]

Some MMC devices as mmc2 in the A83T or mmc1 and mmc2 in the H3 have
a 'New Timings' mode.
Set this capacity in the DT and use it when possible.

Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
---
I don't know if this mode works or is needed at 25MHz.
---
 Documentation/devicetree/bindings/mmc/sunxi-mmc.txt |  1 +
 drivers/mmc/host/sunxi-mmc.c                        | 21 +++++++++++++++++++--
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
index 4bf41d8..a541bf4 100644
--- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
@@ -19,6 +19,7 @@ Optional properties:
  - reset-names : must contain "ahb"
  - for cd, bus-width and additional generic mmc parameters
    please refer to mmc.txt within this directory
+ - allwinner,new-timings: the controller may accept the "New Timings" mode
 
 Examples:
 	- Within .dtsi:
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 2ee4c21..98922b5 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -64,6 +64,7 @@
 #define SDXC_REG_CBCR	(0x48) /* SMC CIU Byte Count Register */
 #define SDXC_REG_BBCR	(0x4C) /* SMC BIU Byte Count Register */
 #define SDXC_REG_DBGC	(0x50) /* SMC Debug Enable Register */
+#define SDXC_REG_NTSR	(0x5c) /* SMC NewTiming Set Register */
 #define SDXC_REG_HWRST	(0x78) /* SMC Card Hardware Reset for Register */
 #define SDXC_REG_DMAC	(0x80) /* SMC IDMAC Control Register */
 #define SDXC_REG_DLBA	(0x84) /* SMC IDMAC Descriptor List Base Addre */
@@ -171,6 +172,9 @@
 #define SDXC_SEND_AUTO_STOPCCSD		BIT(9)
 #define SDXC_CEATA_DEV_IRQ_ENABLE	BIT(10)
 
+/* NewTiming Set Register */
+#define SDXC_NEWMODE_ENABLE		BIT(31)
+
 /* IDMA controller bus mod bit field */
 #define SDXC_IDMAC_SOFT_RESET		BIT(0)
 #define SDXC_IDMAC_FIX_BURST		BIT(1)
@@ -261,6 +265,9 @@ struct sunxi_mmc_host {
 
 	/* vqmmc */
 	bool		vqmmc_enabled;
+
+	/* misc */
+	bool		new_timings;	/* new timings capable */
 };
 
 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
@@ -715,8 +722,13 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
 		return -EINVAL;
 	}
 
-	clk_set_phase(host->clk_sample, sclk_dly);
-	clk_set_phase(host->clk_output, oclk_dly);
+	if (host->new_timings && rate >= 50000000) {
+		mmc_writel(host, REG_NTSR,
+			mmc_readl(host, REG_NTSR) | SDXC_NEWMODE_ENABLE);
+	} else {
+		clk_set_phase(host->clk_sample, sclk_dly);
+		clk_set_phase(host->clk_output, oclk_dly);
+	}
 
 	return sunxi_mmc_oclk_onoff(host, 1);
 }
@@ -1133,12 +1145,17 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
 	if (ret)
 		goto error_free_dma;
 
+	if (pdev->dev.of_node &&
+	    of_property_read_bool(pdev->dev.of_node, "allwinner,new-timings"))
+		host->new_timings = true;
+
 	ret = mmc_add_host(mmc);
 	if (ret)
 		goto error_free_dma;
 
 	dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
 	platform_set_drvdata(pdev, mmc);
+
 	return 0;
 
 error_free_dma:
-- 
2.9.2

[PATCH v2] mmc: sunxi: Handle the 'New Timings'

[Jean-Francois Moine]

Some MMC devices as mmc2 in the A83T or mmc1 and mmc2 in the H3 have
a 'New Timings' mode.
Set this capacity in the DT and use it when possible.

Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
---
I don't know if this mode works or is needed at 25MHz.
---
 Documentation/devicetree/bindings/mmc/sunxi-mmc.txt |  1 +
 drivers/mmc/host/sunxi-mmc.c                        | 21 +++++++++++++++++++--
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
index 4bf41d8..a541bf4 100644
--- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
@@ -19,6 +19,7 @@ Optional properties:
  - reset-names : must contain "ahb"
  - for cd, bus-width and additional generic mmc parameters
    please refer to mmc.txt within this directory
+ - allwinner,new-timings: the controller may accept the "New Timings" mode
 
 Examples:
 	- Within .dtsi:
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 2ee4c21..98922b5 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -64,6 +64,7 @@
 #define SDXC_REG_CBCR	(0x48) /* SMC CIU Byte Count Register */
 #define SDXC_REG_BBCR	(0x4C) /* SMC BIU Byte Count Register */
 #define SDXC_REG_DBGC	(0x50) /* SMC Debug Enable Register */
+#define SDXC_REG_NTSR	(0x5c) /* SMC NewTiming Set Register */
 #define SDXC_REG_HWRST	(0x78) /* SMC Card Hardware Reset for Register */
 #define SDXC_REG_DMAC	(0x80) /* SMC IDMAC Control Register */
 #define SDXC_REG_DLBA	(0x84) /* SMC IDMAC Descriptor List Base Addre */
@@ -171,6 +172,9 @@
 #define SDXC_SEND_AUTO_STOPCCSD		BIT(9)
 #define SDXC_CEATA_DEV_IRQ_ENABLE	BIT(10)
 
+/* NewTiming Set Register */
+#define SDXC_NEWMODE_ENABLE		BIT(31)
+
 /* IDMA controller bus mod bit field */
 #define SDXC_IDMAC_SOFT_RESET		BIT(0)
 #define SDXC_IDMAC_FIX_BURST		BIT(1)
@@ -261,6 +265,9 @@ struct sunxi_mmc_host {
 
 	/* vqmmc */
 	bool		vqmmc_enabled;
+
+	/* misc */
+	bool		new_timings;	/* new timings capable */
 };
 
 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
@@ -715,8 +722,13 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
 		return -EINVAL;
 	}
 
-	clk_set_phase(host->clk_sample, sclk_dly);
-	clk_set_phase(host->clk_output, oclk_dly);
+	if (host->new_timings && rate >= 50000000) {
+		mmc_writel(host, REG_NTSR,
+			mmc_readl(host, REG_NTSR) | SDXC_NEWMODE_ENABLE);
+	} else {
+		clk_set_phase(host->clk_sample, sclk_dly);
+		clk_set_phase(host->clk_output, oclk_dly);
+	}
 
 	return sunxi_mmc_oclk_onoff(host, 1);
 }
@@ -1133,12 +1145,17 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
 	if (ret)
 		goto error_free_dma;
 
+	if (pdev->dev.of_node &&
+	    of_property_read_bool(pdev->dev.of_node, "allwinner,new-timings"))
+		host->new_timings = true;
+
 	ret = mmc_add_host(mmc);
 	if (ret)
 		goto error_free_dma;
 
 	dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
 	platform_set_drvdata(pdev, mmc);
+
 	return 0;
 
 error_free_dma:
-- 
2.9.2

[PATCH v2] mmc: sunxi: Handle the 'New Timings'

[Jean-Francois Moine]

Some MMC devices as mmc2 in the A83T or mmc1 and mmc2 in the H3 have
a 'New Timings' mode.
Set this capacity in the DT and use it when possible.

Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
---
I don't know if this mode works or is needed at 25MHz.
---
 Documentation/devicetree/bindings/mmc/sunxi-mmc.txt |  1 +
 drivers/mmc/host/sunxi-mmc.c                        | 21 +++++++++++++++++++--
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
index 4bf41d8..a541bf4 100644
--- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
@@ -19,6 +19,7 @@ Optional properties:
  - reset-names : must contain "ahb"
  - for cd, bus-width and additional generic mmc parameters
    please refer to mmc.txt within this directory
+ - allwinner,new-timings: the controller may accept the "New Timings" mode
 
 Examples:
 	- Within .dtsi:
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 2ee4c21..98922b5 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -64,6 +64,7 @@
 #define SDXC_REG_CBCR	(0x48) /* SMC CIU Byte Count Register */
 #define SDXC_REG_BBCR	(0x4C) /* SMC BIU Byte Count Register */
 #define SDXC_REG_DBGC	(0x50) /* SMC Debug Enable Register */
+#define SDXC_REG_NTSR	(0x5c) /* SMC NewTiming Set Register */
 #define SDXC_REG_HWRST	(0x78) /* SMC Card Hardware Reset for Register */
 #define SDXC_REG_DMAC	(0x80) /* SMC IDMAC Control Register */
 #define SDXC_REG_DLBA	(0x84) /* SMC IDMAC Descriptor List Base Addre */
@@ -171,6 +172,9 @@
 #define SDXC_SEND_AUTO_STOPCCSD		BIT(9)
 #define SDXC_CEATA_DEV_IRQ_ENABLE	BIT(10)
 
+/* NewTiming Set Register */
+#define SDXC_NEWMODE_ENABLE		BIT(31)
+
 /* IDMA controller bus mod bit field */
 #define SDXC_IDMAC_SOFT_RESET		BIT(0)
 #define SDXC_IDMAC_FIX_BURST		BIT(1)
@@ -261,6 +265,9 @@ struct sunxi_mmc_host {
 
 	/* vqmmc */
 	bool		vqmmc_enabled;
+
+	/* misc */
+	bool		new_timings;	/* new timings capable */
 };
 
 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
@@ -715,8 +722,13 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
 		return -EINVAL;
 	}
 
-	clk_set_phase(host->clk_sample, sclk_dly);
-	clk_set_phase(host->clk_output, oclk_dly);
+	if (host->new_timings && rate >= 50000000) {
+		mmc_writel(host, REG_NTSR,
+			mmc_readl(host, REG_NTSR) | SDXC_NEWMODE_ENABLE);
+	} else {
+		clk_set_phase(host->clk_sample, sclk_dly);
+		clk_set_phase(host->clk_output, oclk_dly);
+	}
 
 	return sunxi_mmc_oclk_onoff(host, 1);
 }
@@ -1133,12 +1145,17 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
 	if (ret)
 		goto error_free_dma;
 
+	if (pdev->dev.of_node &&
+	    of_property_read_bool(pdev->dev.of_node, "allwinner,new-timings"))
+		host->new_timings = true;
+
 	ret = mmc_add_host(mmc);
 	if (ret)
 		goto error_free_dma;
 
 	dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
 	platform_set_drvdata(pdev, mmc);
+
 	return 0;
 
 error_free_dma:
-- 
2.9.2