* [PATCH 0/4] SKL turbo part 1
@ 2015-01-16 18:07 Damien Lespiau
2015-01-16 18:07 ` [PATCH 1/4] drm/i915/skl: add turbo support Damien Lespiau
` (4 more replies)
0 siblings, 5 replies; 18+ messages in thread
From: Damien Lespiau @ 2015-01-16 18:07 UTC (permalink / raw)
To: intel-gfx
The turbo work is not quite complete with those patches, but it's a big step
forward. The missing bit is that the granularity of frequency the GPU supports
has changed.
For this reason, I left in the code disabling gen6_rps_irq_handler() for gen9+
in until we have a proper implementation.
--
Damien
Akash Goel (1):
drm/i915/skl: Updated the RC6/Forcewake related debugfs interface for
Gen9
Damien Lespiau (1):
drm/i915/skl: Retrieve the frequency limits
Jesse Barnes (1):
drm/i915/skl: add turbo support
Zhe Wang (1):
drm/i915/skl: Gen9 coarse power gating
drivers/gpu/drm/i915/i915_debugfs.c | 44 +++++++++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 6 +++++
drivers/gpu/drm/i915/intel_pm.c | 40 +++++++++++++++++++++++++++++++++
3 files changed, 88 insertions(+), 2 deletions(-)
--
1.8.3.1
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 1/4] drm/i915/skl: add turbo support
2015-01-16 18:07 [PATCH 0/4] SKL turbo part 1 Damien Lespiau
@ 2015-01-16 18:07 ` Damien Lespiau
2015-01-19 10:02 ` Mika Kuoppala
2015-01-16 18:07 ` [PATCH 2/4] drm/i915/skl: Retrieve the frequency limits Damien Lespiau
` (3 subsequent siblings)
4 siblings, 1 reply; 18+ messages in thread
From: Damien Lespiau @ 2015-01-16 18:07 UTC (permalink / raw)
To: intel-gfx
From: Jesse Barnes <jbarnes@virtuousgeek.org>
Per latest PM programming guide.
v2: the wrong flavour of the function updating the ring frequency was
called, leading to dead locks (Tvrtko)
v3: Add GEN6_RP_MEDIA_IS_GFX to RP_CONTROL (Imre, done by Damien)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 03fc7f2..3a0aec0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4025,9 +4025,37 @@ static void gen6_init_rps_frequencies(struct drm_device *dev)
}
}
+/* See the Gen9_GT_PM_Programming_Guide doc for the below */
static void gen9_enable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+
+ gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+
+ I915_WRITE(GEN6_RPNSWREQ, 0xc800000);
+ I915_WRITE(GEN6_RC_VIDEO_FREQ, 0xc800000);
+
+ I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
+ I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 0x12060000);
+ I915_WRITE(GEN6_RP_UP_THRESHOLD, 0xe808);
+ I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 0x3bd08);
+ I915_WRITE(GEN6_RP_UP_EI, 0x101d0);
+ I915_WRITE(GEN6_RP_DOWN_EI, 0x55730);
+ I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
+ I915_WRITE(GEN6_PMINTRMSK, 0x6);
+ I915_WRITE(GEN6_RP_CONTROL, GEN6_RP_MEDIA_TURBO |
+ GEN6_RP_MEDIA_HW_MODE | GEN6_RP_MEDIA_IS_GFX |
+ GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG |
+ GEN6_RP_DOWN_IDLE_AVG);
+
+ gen6_enable_rps_interrupts(dev);
+
+ gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
+}
+
+static void gen9_enable_rc6(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_engine_cs *ring;
uint32_t rc6_mask = 0;
int unused;
@@ -5527,7 +5555,9 @@ static void intel_gen6_powersave_work(struct work_struct *work)
} else if (IS_VALLEYVIEW(dev)) {
valleyview_enable_rps(dev);
} else if (INTEL_INFO(dev)->gen >= 9) {
+ gen9_enable_rc6(dev);
gen9_enable_rps(dev);
+ __gen6_update_ring_freq(dev);
} else if (IS_BROADWELL(dev)) {
gen8_enable_rps(dev);
__gen6_update_ring_freq(dev);
--
1.8.3.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 2/4] drm/i915/skl: Retrieve the frequency limits
2015-01-16 18:07 [PATCH 0/4] SKL turbo part 1 Damien Lespiau
2015-01-16 18:07 ` [PATCH 1/4] drm/i915/skl: add turbo support Damien Lespiau
@ 2015-01-16 18:07 ` Damien Lespiau
2015-01-20 10:14 ` Daniel Vetter
2015-01-16 18:07 ` [PATCH 3/4] drm/i915/skl: Gen9 coarse power gating Damien Lespiau
` (2 subsequent siblings)
4 siblings, 1 reply; 18+ messages in thread
From: Damien Lespiau @ 2015-01-16 18:07 UTC (permalink / raw)
To: intel-gfx
v2: Use the new function, gen6_init_rps_frequencies() (Damien)
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> (v1)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3a0aec0..f40b8f2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4032,6 +4032,8 @@ static void gen9_enable_rps(struct drm_device *dev)
gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+ gen6_init_rps_frequencies(dev);
+
I915_WRITE(GEN6_RPNSWREQ, 0xc800000);
I915_WRITE(GEN6_RC_VIDEO_FREQ, 0xc800000);
--
1.8.3.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 3/4] drm/i915/skl: Gen9 coarse power gating
2015-01-16 18:07 [PATCH 0/4] SKL turbo part 1 Damien Lespiau
2015-01-16 18:07 ` [PATCH 1/4] drm/i915/skl: add turbo support Damien Lespiau
2015-01-16 18:07 ` [PATCH 2/4] drm/i915/skl: Retrieve the frequency limits Damien Lespiau
@ 2015-01-16 18:07 ` Damien Lespiau
2015-01-19 15:39 ` Damien Lespiau
2015-01-16 18:07 ` [PATCH 4/4] drm/i915/skl: Updated the RC6/Forcewake related debugfs interface for Gen9 Damien Lespiau
2016-06-27 14:52 ` ✗ Ro.CI.BAT: warning for " Patchwork
4 siblings, 1 reply; 18+ messages in thread
From: Damien Lespiau @ 2015-01-16 18:07 UTC (permalink / raw)
To: intel-gfx
From: Zhe Wang <zhe1.wang@intel.com>
Enable coarse power gating for Gen9. This feature allows render and
media engine to enter RC6 independently. Policies are configured
together with RC6. This feature will only be enabled when RC6 is
enabled.
Signed-off-by: Zhe Wang <zhe1.wang@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cb96041..3d08f9d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6065,6 +6065,9 @@ enum skl_disp_power_wells {
#define GEN6_PMINTRMSK 0xA168
#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31)
#define VLV_PWRDWNUPCTL 0xA294
+#define GEN9_MEDIA_PG_IDLE_HYSTERESIS 0xA0C4
+#define GEN9_RENDER_PG_IDLE_HYSTERESIS 0xA0C8
+#define GEN9_PG_ENABLE 0xA210
#define VLV_CHICKEN_3 (VLV_DISPLAY_BASE + 0x7040C)
#define PIXEL_OVERLAP_CNT_MASK (3 << 30)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f40b8f2..71bf4f4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3892,6 +3892,7 @@ static void gen9_disable_rps(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
I915_WRITE(GEN6_RC_CONTROL, 0);
+ I915_WRITE(GEN9_PG_ENABLE, 0);
}
static void gen6_disable_rps(struct drm_device *dev)
@@ -4081,6 +4082,10 @@ static void gen9_enable_rc6(struct drm_device *dev)
I915_WRITE(GEN6_RC_SLEEP, 0);
I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
+ /* 2c: Program Coarse Power Gating Policies. */
+ I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
+ I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
+
/* 3a: Enable RC6 */
if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
@@ -4090,6 +4095,9 @@ static void gen9_enable_rc6(struct drm_device *dev)
GEN6_RC_CTL_EI_MODE(1) |
rc6_mask);
+ /* 3b: Enable Coarse Power Gating only when RC6 is enabled */
+ I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 3 : 0);
+
gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
}
--
1.8.3.1
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 4/4] drm/i915/skl: Updated the RC6/Forcewake related debugfs interface for Gen9
2015-01-16 18:07 [PATCH 0/4] SKL turbo part 1 Damien Lespiau
` (2 preceding siblings ...)
2015-01-16 18:07 ` [PATCH 3/4] drm/i915/skl: Gen9 coarse power gating Damien Lespiau
@ 2015-01-16 18:07 ` Damien Lespiau
2015-01-17 10:59 ` shuang.he
` (2 more replies)
2016-06-27 14:52 ` ✗ Ro.CI.BAT: warning for " Patchwork
4 siblings, 3 replies; 18+ messages in thread
From: Damien Lespiau @ 2015-01-16 18:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Akash Goel
From: Akash Goel <akash.goel@intel.com>
Updated the i915_drpc_info & i915_gen6_forcewake_count debugfs interface
v2: Change all IS_GEN9() by gen >= 9 (Damien)
Change-Id: Ibed2fb71b233a369e69278bc96298df82d032a47
Signed-off-by: Akash Goel <akash.goel@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 44 +++++++++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 45 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index aac6126..b0a142d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1347,8 +1347,10 @@ static int gen6_drpc_info(struct seq_file *m)
struct drm_device *dev = node->minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
+ u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
unsigned forcewake_count;
int count = 0, ret;
+ u32 fw_rendercount = 0, fw_mediacount = 0, fw_blittercount = 0;
ret = mutex_lock_interruptible(&dev->struct_mutex);
if (ret)
@@ -1374,6 +1376,10 @@ static int gen6_drpc_info(struct seq_file *m)
rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
rcctl1 = I915_READ(GEN6_RC_CONTROL);
+ if (INTEL_INFO(dev)->gen >= 9) {
+ gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
+ gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
+ }
mutex_unlock(&dev->struct_mutex);
mutex_lock(&dev_priv->rps.hw_lock);
sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
@@ -1392,6 +1398,12 @@ static int gen6_drpc_info(struct seq_file *m)
yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
seq_printf(m, "RC6 Enabled: %s\n",
yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
+ if (INTEL_INFO(dev)->gen >= 9) {
+ seq_printf(m, "Render Well Gating Enabled: %s\n",
+ yesno(gen9_powergate_enable & 0x1));
+ seq_printf(m, "Media Well Gating Enabled: %s\n",
+ yesno(gen9_powergate_enable & 0x2));
+ }
seq_printf(m, "Deep RC6 Enabled: %s\n",
yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
seq_printf(m, "Deepest RC6 Enabled: %s\n",
@@ -1420,6 +1432,14 @@ static int gen6_drpc_info(struct seq_file *m)
seq_printf(m, "Core Power Down: %s\n",
yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
+ if (INTEL_INFO(dev)->gen >= 9) {
+ seq_printf(m, "Render Power Well: %s\n",
+ (gen9_powergate_status &
+ GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
+ seq_printf(m, "Media Power Well: %s\n",
+ (gen9_powergate_status &
+ GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
+ }
/* Not exactly sure what this is */
seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
@@ -1437,6 +1457,20 @@ static int gen6_drpc_info(struct seq_file *m)
GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
seq_printf(m, "RC6++ voltage: %dmV\n",
GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
+
+ if (INTEL_INFO(dev)->gen >= 9) {
+ spin_lock_irq(&dev_priv->uncore.lock);
+ fw_rendercount = dev_priv->uncore.fw_rendercount;
+ fw_mediacount = dev_priv->uncore.fw_mediacount;
+ fw_blittercount = dev_priv->uncore.fw_blittercount;
+ spin_unlock_irq(&dev_priv->uncore.lock);
+
+ seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
+ seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
+ seq_printf(m, "Forcewake Blitter Count = %u\n",
+ fw_blittercount);
+ }
+
return 0;
}
@@ -1990,18 +2024,24 @@ static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
struct drm_device *dev = node->minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
+ unsigned fw_blittercount = 0;
spin_lock_irq(&dev_priv->uncore.lock);
- if (IS_VALLEYVIEW(dev)) {
+ if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen >= 9) {
fw_rendercount = dev_priv->uncore.fw_rendercount;
fw_mediacount = dev_priv->uncore.fw_mediacount;
+ if (INTEL_INFO(dev)->gen >= 9)
+ fw_blittercount = dev_priv->uncore.fw_blittercount;
} else
forcewake_count = dev_priv->uncore.forcewake_count;
+
spin_unlock_irq(&dev_priv->uncore.lock);
- if (IS_VALLEYVIEW(dev)) {
+ if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen >= 9) {
seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
+ if (INTEL_INFO(dev)->gen >= 9)
+ seq_printf(m, "fw_blittercount = %u\n", fw_blittercount);
} else
seq_printf(m, "forcewake count = %u\n", forcewake_count);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3d08f9d..81538c7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5945,6 +5945,9 @@ enum skl_disp_power_wells {
#define FORCEWAKE_ACK_MEDIA_GEN9 0x0D88
#define FORCEWAKE_ACK_RENDER_GEN9 0x0D84
#define FORCEWAKE_ACK_BLITTER_GEN9 0x130044
+#define GEN9_PWRGT_DOMAIN_STATUS 0xA2A0
+#define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
+#define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1)
#define FORCEWAKE_KERNEL 0x1
#define FORCEWAKE_USER 0x2
#define FORCEWAKE_MT_ACK 0x130040
--
1.8.3.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 4/4] drm/i915/skl: Updated the RC6/Forcewake related debugfs interface for Gen9
2015-01-16 18:07 ` [PATCH 4/4] drm/i915/skl: Updated the RC6/Forcewake related debugfs interface for Gen9 Damien Lespiau
@ 2015-01-17 10:59 ` shuang.he
2015-01-19 15:50 ` Damien Lespiau
2016-06-27 14:40 ` [PATCH v3] drm/i915/gen9: Update i915_drpc_info debugfs for coarse pg & forcewake info akash.goel
2 siblings, 0 replies; 18+ messages in thread
From: shuang.he @ 2015-01-17 10:59 UTC (permalink / raw)
To: shuang.he, ethan.gao, intel-gfx, damien.lespiau
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5596
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 353/353 353/353
ILK 200/200 200/200
SNB -1 400/422 399/422
IVB 487/487 487/487
BYT 296/296 296/296
HSW -1 487/508 486/508
BDW 401/402 401/402
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*SNB igt_kms_flip_modeset-vs-vblank-race PASS(2, M35M22) NSPT(1, M22)
HSW igt_kms_flip_event_leak NSPT(5, M19)PASS(1, M19) NSPT(1, M19)
Note: You need to pay more attention to line start with '*'
_______________________________________________
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/4] drm/i915/skl: add turbo support
2015-01-16 18:07 ` [PATCH 1/4] drm/i915/skl: add turbo support Damien Lespiau
@ 2015-01-19 10:02 ` Mika Kuoppala
0 siblings, 0 replies; 18+ messages in thread
From: Mika Kuoppala @ 2015-01-19 10:02 UTC (permalink / raw)
To: Damien Lespiau, intel-gfx
Damien Lespiau <damien.lespiau@intel.com> writes:
> From: Jesse Barnes <jbarnes@virtuousgeek.org>
>
> Per latest PM programming guide.
>
> v2: the wrong flavour of the function updating the ring frequency was
> called, leading to dead locks (Tvrtko)
>
> v3: Add GEN6_RP_MEDIA_IS_GFX to RP_CONTROL (Imre, done by Damien)
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 03fc7f2..3a0aec0 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4025,9 +4025,37 @@ static void gen6_init_rps_frequencies(struct drm_device *dev)
> }
> }
>
> +/* See the Gen9_GT_PM_Programming_Guide doc for the below */
> static void gen9_enable_rps(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
> +
> + I915_WRITE(GEN6_RPNSWREQ, 0xc800000);
> + I915_WRITE(GEN6_RC_VIDEO_FREQ, 0xc800000);
> +
> + I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
> + I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 0x12060000);
> + I915_WRITE(GEN6_RP_UP_THRESHOLD, 0xe808);
> + I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 0x3bd08);
> + I915_WRITE(GEN6_RP_UP_EI, 0x101d0);
> + I915_WRITE(GEN6_RP_DOWN_EI, 0x55730);
> + I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
> + I915_WRITE(GEN6_PMINTRMSK, 0x6);
> + I915_WRITE(GEN6_RP_CONTROL, GEN6_RP_MEDIA_TURBO |
> + GEN6_RP_MEDIA_HW_MODE | GEN6_RP_MEDIA_IS_GFX |
> + GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG |
> + GEN6_RP_DOWN_IDLE_AVG);
> +
> + gen6_enable_rps_interrupts(dev);
> +
> + gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
> +}
> +
> +static void gen9_enable_rc6(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_engine_cs *ring;
> uint32_t rc6_mask = 0;
> int unused;
> @@ -5527,7 +5555,9 @@ static void intel_gen6_powersave_work(struct work_struct *work)
> } else if (IS_VALLEYVIEW(dev)) {
> valleyview_enable_rps(dev);
> } else if (INTEL_INFO(dev)->gen >= 9) {
> + gen9_enable_rc6(dev);
> gen9_enable_rps(dev);
> + __gen6_update_ring_freq(dev);
> } else if (IS_BROADWELL(dev)) {
> gen8_enable_rps(dev);
> __gen6_update_ring_freq(dev);
> --
> 1.8.3.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/4] drm/i915/skl: Gen9 coarse power gating
2015-01-16 18:07 ` [PATCH 3/4] drm/i915/skl: Gen9 coarse power gating Damien Lespiau
@ 2015-01-19 15:39 ` Damien Lespiau
0 siblings, 0 replies; 18+ messages in thread
From: Damien Lespiau @ 2015-01-19 15:39 UTC (permalink / raw)
To: intel-gfx
On Fri, Jan 16, 2015 at 06:07:27PM +0000, Damien Lespiau wrote:
> From: Zhe Wang <zhe1.wang@intel.com>
>
> Enable coarse power gating for Gen9. This feature allows render and
> media engine to enter RC6 independently. Policies are configured
> together with RC6. This feature will only be enabled when RC6 is
> enabled.
>
> Signed-off-by: Zhe Wang <zhe1.wang@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++
> 2 files changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index cb96041..3d08f9d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6065,6 +6065,9 @@ enum skl_disp_power_wells {
> #define GEN6_PMINTRMSK 0xA168
> #define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31)
> #define VLV_PWRDWNUPCTL 0xA294
> +#define GEN9_MEDIA_PG_IDLE_HYSTERESIS 0xA0C4
> +#define GEN9_RENDER_PG_IDLE_HYSTERESIS 0xA0C8
> +#define GEN9_PG_ENABLE 0xA210
>
> #define VLV_CHICKEN_3 (VLV_DISPLAY_BASE + 0x7040C)
> #define PIXEL_OVERLAP_CNT_MASK (3 << 30)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f40b8f2..71bf4f4 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3892,6 +3892,7 @@ static void gen9_disable_rps(struct drm_device *dev)
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> I915_WRITE(GEN6_RC_CONTROL, 0);
> + I915_WRITE(GEN9_PG_ENABLE, 0);
> }
>
> static void gen6_disable_rps(struct drm_device *dev)
> @@ -4081,6 +4082,10 @@ static void gen9_enable_rc6(struct drm_device *dev)
> I915_WRITE(GEN6_RC_SLEEP, 0);
> I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
>
> + /* 2c: Program Coarse Power Gating Policies. */
> + I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
> + I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
> +
> /* 3a: Enable RC6 */
> if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
> rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
> @@ -4090,6 +4095,9 @@ static void gen9_enable_rc6(struct drm_device *dev)
> GEN6_RC_CTL_EI_MODE(1) |
> rc6_mask);
>
> + /* 3b: Enable Coarse Power Gating only when RC6 is enabled */
> + I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 3 : 0);
> +
> gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
>
> }
> --
> 1.8.3.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 4/4] drm/i915/skl: Updated the RC6/Forcewake related debugfs interface for Gen9
2015-01-16 18:07 ` [PATCH 4/4] drm/i915/skl: Updated the RC6/Forcewake related debugfs interface for Gen9 Damien Lespiau
2015-01-17 10:59 ` shuang.he
@ 2015-01-19 15:50 ` Damien Lespiau
2016-06-27 14:40 ` [PATCH v3] drm/i915/gen9: Update i915_drpc_info debugfs for coarse pg & forcewake info akash.goel
2 siblings, 0 replies; 18+ messages in thread
From: Damien Lespiau @ 2015-01-19 15:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Akash Goel
On Fri, Jan 16, 2015 at 06:07:28PM +0000, Damien Lespiau wrote:
> From: Akash Goel <akash.goel@intel.com>
>
> Updated the i915_drpc_info & i915_gen6_forcewake_count debugfs interface
>
> v2: Change all IS_GEN9() by gen >= 9 (Damien)
>
> Change-Id: Ibed2fb71b233a369e69278bc96298df82d032a47
> Signed-off-by: Akash Goel <akash.goel@intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 44 +++++++++++++++++++++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 2 files changed, 45 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index aac6126..b0a142d 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1347,8 +1347,10 @@ static int gen6_drpc_info(struct seq_file *m)
> struct drm_device *dev = node->minor->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
> + u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
> unsigned forcewake_count;
> int count = 0, ret;
> + u32 fw_rendercount = 0, fw_mediacount = 0, fw_blittercount = 0;
>
> ret = mutex_lock_interruptible(&dev->struct_mutex);
> if (ret)
> @@ -1374,6 +1376,10 @@ static int gen6_drpc_info(struct seq_file *m)
>
> rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
> rcctl1 = I915_READ(GEN6_RC_CONTROL);
> + if (INTEL_INFO(dev)->gen >= 9) {
> + gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
> + gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
> + }
> mutex_unlock(&dev->struct_mutex);
> mutex_lock(&dev_priv->rps.hw_lock);
> sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
> @@ -1392,6 +1398,12 @@ static int gen6_drpc_info(struct seq_file *m)
> yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
> seq_printf(m, "RC6 Enabled: %s\n",
> yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
> + if (INTEL_INFO(dev)->gen >= 9) {
> + seq_printf(m, "Render Well Gating Enabled: %s\n",
> + yesno(gen9_powergate_enable & 0x1));
> + seq_printf(m, "Media Well Gating Enabled: %s\n",
> + yesno(gen9_powergate_enable & 0x2));
> + }
> seq_printf(m, "Deep RC6 Enabled: %s\n",
> yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
> seq_printf(m, "Deepest RC6 Enabled: %s\n",
> @@ -1420,6 +1432,14 @@ static int gen6_drpc_info(struct seq_file *m)
>
> seq_printf(m, "Core Power Down: %s\n",
> yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
> + if (INTEL_INFO(dev)->gen >= 9) {
> + seq_printf(m, "Render Power Well: %s\n",
> + (gen9_powergate_status &
> + GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
> + seq_printf(m, "Media Power Well: %s\n",
> + (gen9_powergate_status &
> + GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
> + }
>
> /* Not exactly sure what this is */
> seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
> @@ -1437,6 +1457,20 @@ static int gen6_drpc_info(struct seq_file *m)
> GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
> seq_printf(m, "RC6++ voltage: %dmV\n",
> GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
> +
> + if (INTEL_INFO(dev)->gen >= 9) {
> + spin_lock_irq(&dev_priv->uncore.lock);
> + fw_rendercount = dev_priv->uncore.fw_rendercount;
> + fw_mediacount = dev_priv->uncore.fw_mediacount;
> + fw_blittercount = dev_priv->uncore.fw_blittercount;
> + spin_unlock_irq(&dev_priv->uncore.lock);
> +
> + seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
> + seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
> + seq_printf(m, "Forcewake Blitter Count = %u\n",
> + fw_blittercount);
> + }
> +
> return 0;
> }
>
> @@ -1990,18 +2024,24 @@ static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
> struct drm_device *dev = node->minor->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
> + unsigned fw_blittercount = 0;
>
> spin_lock_irq(&dev_priv->uncore.lock);
> - if (IS_VALLEYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen >= 9) {
> fw_rendercount = dev_priv->uncore.fw_rendercount;
> fw_mediacount = dev_priv->uncore.fw_mediacount;
> + if (INTEL_INFO(dev)->gen >= 9)
> + fw_blittercount = dev_priv->uncore.fw_blittercount;
> } else
> forcewake_count = dev_priv->uncore.forcewake_count;
> +
> spin_unlock_irq(&dev_priv->uncore.lock);
>
> - if (IS_VALLEYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen >= 9) {
> seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
> seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
> + if (INTEL_INFO(dev)->gen >= 9)
> + seq_printf(m, "fw_blittercount = %u\n", fw_blittercount);
> } else
> seq_printf(m, "forcewake count = %u\n", forcewake_count);
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3d08f9d..81538c7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5945,6 +5945,9 @@ enum skl_disp_power_wells {
> #define FORCEWAKE_ACK_MEDIA_GEN9 0x0D88
> #define FORCEWAKE_ACK_RENDER_GEN9 0x0D84
> #define FORCEWAKE_ACK_BLITTER_GEN9 0x130044
> +#define GEN9_PWRGT_DOMAIN_STATUS 0xA2A0
> +#define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
> +#define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1)
> #define FORCEWAKE_KERNEL 0x1
> #define FORCEWAKE_USER 0x2
> #define FORCEWAKE_MT_ACK 0x130040
> --
> 1.8.3.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/4] drm/i915/skl: Retrieve the frequency limits
2015-01-16 18:07 ` [PATCH 2/4] drm/i915/skl: Retrieve the frequency limits Damien Lespiau
@ 2015-01-20 10:14 ` Daniel Vetter
2015-01-20 11:45 ` Damien Lespiau
0 siblings, 1 reply; 18+ messages in thread
From: Daniel Vetter @ 2015-01-20 10:14 UTC (permalink / raw)
To: Damien Lespiau; +Cc: intel-gfx
On Fri, Jan 16, 2015 at 06:07:26PM +0000, Damien Lespiau wrote:
> v2: Use the new function, gen6_init_rps_frequencies() (Damien)
>
> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> (v1)
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
First two patches merged, later two have conflicts. Can you please rebase?
Also the big rework from Mika to support forcewake domains generically has
landed, I hope that unblocks skl rps support?
Thanks, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/4] drm/i915/skl: Retrieve the frequency limits
2015-01-20 10:14 ` Daniel Vetter
@ 2015-01-20 11:45 ` Damien Lespiau
0 siblings, 0 replies; 18+ messages in thread
From: Damien Lespiau @ 2015-01-20 11:45 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Tue, Jan 20, 2015 at 11:14:22AM +0100, Daniel Vetter wrote:
> On Fri, Jan 16, 2015 at 06:07:26PM +0000, Damien Lespiau wrote:
> > v2: Use the new function, gen6_init_rps_frequencies() (Damien)
> >
> > Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> (v1)
> > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
>
> First two patches merged, later two have conflicts. Can you please rebase?
>
> Also the big rework from Mika to support forcewake domains generically has
> landed, I hope that unblocks skl rps support?
Actually the whole series needs rebasing (doesn't compile with
Mika's/Chris rework). Let me do that.
It doesn't quite unblock the rps support, we still need some work as it
has been identified that the frequency granularity has changed on SKL
(as always with PM, we know about things super late and by chance)
--
Damien
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3] drm/i915/gen9: Update i915_drpc_info debugfs for coarse pg & forcewake info
2015-01-16 18:07 ` [PATCH 4/4] drm/i915/skl: Updated the RC6/Forcewake related debugfs interface for Gen9 Damien Lespiau
2015-01-17 10:59 ` shuang.he
2015-01-19 15:50 ` Damien Lespiau
@ 2016-06-27 14:40 ` akash.goel
2016-08-01 17:48 ` Kamble, Sagar A
2 siblings, 1 reply; 18+ messages in thread
From: akash.goel @ 2016-06-27 14:40 UTC (permalink / raw)
To: intel-gfx; +Cc: Akash Goel
From: Akash Goel <akash.goel@intel.com>
Updated the i915_drpc_info debugfs with coarse power gating & forcewake
info for Gen9.
v2: Change all IS_GEN9() by gen >= 9 (Damien)
v3: Rebase
Cc: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Akash Goel <akash.goel@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 21 ++++++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index f664884..5185e02 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1588,6 +1588,7 @@ static int gen6_drpc_info(struct seq_file *m)
struct drm_device *dev = node->minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
+ u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
unsigned forcewake_count;
int count = 0, ret;
@@ -1615,6 +1616,10 @@ static int gen6_drpc_info(struct seq_file *m)
rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
rcctl1 = I915_READ(GEN6_RC_CONTROL);
+ if (INTEL_INFO(dev)->gen >= 9) {
+ gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
+ gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
+ }
mutex_unlock(&dev->struct_mutex);
mutex_lock(&dev_priv->rps.hw_lock);
sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
@@ -1633,6 +1638,12 @@ static int gen6_drpc_info(struct seq_file *m)
yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
seq_printf(m, "RC6 Enabled: %s\n",
yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
+ if (INTEL_INFO(dev)->gen >= 9) {
+ seq_printf(m, "Render Well Gating Enabled: %s\n",
+ yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
+ seq_printf(m, "Media Well Gating Enabled: %s\n",
+ yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
+ }
seq_printf(m, "Deep RC6 Enabled: %s\n",
yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
seq_printf(m, "Deepest RC6 Enabled: %s\n",
@@ -1661,6 +1672,14 @@ static int gen6_drpc_info(struct seq_file *m)
seq_printf(m, "Core Power Down: %s\n",
yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
+ if (INTEL_INFO(dev)->gen >= 9) {
+ seq_printf(m, "Render Power Well: %s\n",
+ (gen9_powergate_status &
+ GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
+ seq_printf(m, "Media Power Well: %s\n",
+ (gen9_powergate_status &
+ GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
+ }
/* Not exactly sure what this is */
seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
@@ -1678,7 +1697,7 @@ static int gen6_drpc_info(struct seq_file *m)
GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
seq_printf(m, "RC6++ voltage: %dmV\n",
GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
- return 0;
+ return i915_forcewake_domains(m, NULL);
}
static int i915_drpc_info(struct seq_file *m, void *unused)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c6bfbf8..1c8d029 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6955,6 +6955,9 @@ enum {
#define ECOBUS _MMIO(0xa180)
#define FORCEWAKE_MT_ENABLE (1<<5)
#define VLV_SPAREG2H _MMIO(0xA194)
+#define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0)
+#define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
+#define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1)
#define GTFIFODBG _MMIO(0x120000)
#define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
--
1.9.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* ✗ Ro.CI.BAT: warning for drm/i915/gen9: Update i915_drpc_info debugfs for coarse pg & forcewake info
2015-01-16 18:07 [PATCH 0/4] SKL turbo part 1 Damien Lespiau
` (3 preceding siblings ...)
2015-01-16 18:07 ` [PATCH 4/4] drm/i915/skl: Updated the RC6/Forcewake related debugfs interface for Gen9 Damien Lespiau
@ 2016-06-27 14:52 ` Patchwork
4 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2016-06-27 14:52 UTC (permalink / raw)
To: Akash Goel; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gen9: Update i915_drpc_info debugfs for coarse pg & forcewake info
URL : https://patchwork.freedesktop.org/series/9192/
State : warning
== Summary ==
Series 9192v1 drm/i915/gen9: Update i915_drpc_info debugfs for coarse pg & forcewake info
http://patchwork.freedesktop.org/api/1.0/series/9192/revisions/1/mbox
Test gem_exec_flush:
Subgroup basic-batch-kernel-default-cmd:
fail -> PASS (ro-byt-n2820)
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-c-frame-sequence:
pass -> DMESG-WARN (fi-hsw-i7-4770k)
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> SKIP (ro-bdw-i5-5250u)
fi-hsw-i7-4770k total:229 pass:193 dwarn:1 dfail:0 fail:2 skip:33
fi-kbl-qkkr total:229 pass:160 dwarn:29 dfail:0 fail:0 skip:40
fi-skl-i5-6260u total:229 pass:202 dwarn:0 dfail:0 fail:2 skip:25
fi-skl-i7-6700k total:229 pass:188 dwarn:0 dfail:0 fail:2 skip:39
fi-snb-i7-2600 total:229 pass:174 dwarn:0 dfail:0 fail:2 skip:53
ro-bdw-i5-5250u total:229 pass:202 dwarn:1 dfail:1 fail:2 skip:23
ro-bdw-i7-5600u total:229 pass:190 dwarn:0 dfail:1 fail:0 skip:38
ro-byt-n2820 total:229 pass:179 dwarn:0 dfail:1 fail:4 skip:45
ro-hsw-i3-4010u total:229 pass:195 dwarn:0 dfail:1 fail:2 skip:31
ro-hsw-i7-4770r total:229 pass:195 dwarn:0 dfail:1 fail:2 skip:31
ro-ilk-i7-620lm total:229 pass:155 dwarn:0 dfail:1 fail:3 skip:70
ro-ilk1-i5-650 total:224 pass:155 dwarn:0 dfail:1 fail:3 skip:65
ro-ivb-i7-3770 total:229 pass:186 dwarn:0 dfail:1 fail:2 skip:40
ro-ivb2-i7-3770 total:229 pass:190 dwarn:0 dfail:1 fail:2 skip:36
ro-skl3-i5-6260u total:229 pass:206 dwarn:1 dfail:1 fail:2 skip:19
ro-snb-i7-2620M total:229 pass:179 dwarn:0 dfail:1 fail:1 skip:48
ro-bdw-i7-5557U failed to connect after reboot
Results at /archive/results/CI_IGT_test/RO_Patchwork_1314/
892ee30 drm-intel-nightly: 2016y-06m-27d-13h-05m-35s UTC integration manifest
2f23cc7 drm/i915/gen9: Update i915_drpc_info debugfs for coarse pg & forcewake info
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3] drm/i915/gen9: Update i915_drpc_info debugfs for coarse pg & forcewake info
2016-06-27 14:40 ` [PATCH v3] drm/i915/gen9: Update i915_drpc_info debugfs for coarse pg & forcewake info akash.goel
@ 2016-08-01 17:48 ` Kamble, Sagar A
2016-08-02 14:09 ` Daniel Vetter
0 siblings, 1 reply; 18+ messages in thread
From: Kamble, Sagar A @ 2016-08-01 17:48 UTC (permalink / raw)
To: akash.goel, intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 3882 bytes --]
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com
<mailto:sagar.a.kamble@intel.com>>
On 6/27/2016 8:10 PM, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
>
> Updated the i915_drpc_info debugfs with coarse power gating & forcewake
> info for Gen9.
>
> v2: Change all IS_GEN9() by gen >= 9 (Damien)
>
> v3: Rebase
>
> Cc: Damien Lespiau <damien.lespiau@intel.com>
> Signed-off-by: Akash Goel <akash.goel@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 21 ++++++++++++++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 2 files changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index f664884..5185e02 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1588,6 +1588,7 @@ static int gen6_drpc_info(struct seq_file *m)
> struct drm_device *dev = node->minor->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
> + u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
> unsigned forcewake_count;
> int count = 0, ret;
>
> @@ -1615,6 +1616,10 @@ static int gen6_drpc_info(struct seq_file *m)
>
> rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
> rcctl1 = I915_READ(GEN6_RC_CONTROL);
> + if (INTEL_INFO(dev)->gen >= 9) {
> + gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
> + gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
> + }
> mutex_unlock(&dev->struct_mutex);
> mutex_lock(&dev_priv->rps.hw_lock);
> sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
> @@ -1633,6 +1638,12 @@ static int gen6_drpc_info(struct seq_file *m)
> yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
> seq_printf(m, "RC6 Enabled: %s\n",
> yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
> + if (INTEL_INFO(dev)->gen >= 9) {
> + seq_printf(m, "Render Well Gating Enabled: %s\n",
> + yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
> + seq_printf(m, "Media Well Gating Enabled: %s\n",
> + yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
> + }
> seq_printf(m, "Deep RC6 Enabled: %s\n",
> yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
> seq_printf(m, "Deepest RC6 Enabled: %s\n",
> @@ -1661,6 +1672,14 @@ static int gen6_drpc_info(struct seq_file *m)
>
> seq_printf(m, "Core Power Down: %s\n",
> yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
> + if (INTEL_INFO(dev)->gen >= 9) {
> + seq_printf(m, "Render Power Well: %s\n",
> + (gen9_powergate_status &
> + GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
> + seq_printf(m, "Media Power Well: %s\n",
> + (gen9_powergate_status &
> + GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
> + }
>
> /* Not exactly sure what this is */
> seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
> @@ -1678,7 +1697,7 @@ static int gen6_drpc_info(struct seq_file *m)
> GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
> seq_printf(m, "RC6++ voltage: %dmV\n",
> GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
> - return 0;
> + return i915_forcewake_domains(m, NULL);
> }
>
> static int i915_drpc_info(struct seq_file *m, void *unused)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c6bfbf8..1c8d029 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6955,6 +6955,9 @@ enum {
> #define ECOBUS _MMIO(0xa180)
> #define FORCEWAKE_MT_ENABLE (1<<5)
> #define VLV_SPAREG2H _MMIO(0xA194)
> +#define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0)
> +#define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
> +#define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1)
>
> #define GTFIFODBG _MMIO(0x120000)
> #define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
[-- Attachment #1.2: Type: text/html, Size: 42842 bytes --]
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3] drm/i915/gen9: Update i915_drpc_info debugfs for coarse pg & forcewake info
2016-08-01 17:48 ` Kamble, Sagar A
@ 2016-08-02 14:09 ` Daniel Vetter
2016-08-04 18:31 ` David Weinehall
0 siblings, 1 reply; 18+ messages in thread
From: Daniel Vetter @ 2016-08-02 14:09 UTC (permalink / raw)
To: Kamble, Sagar A; +Cc: akash.goel, intel-gfx
On Mon, Aug 01, 2016 at 11:18:15PM +0530, Kamble, Sagar A wrote:
> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com
> <mailto:sagar.a.kamble@intel.com>>
You're mailer wreaks havoc with your reviewed-by tags. Pleas fix this.
> On 6/27/2016 8:10 PM, akash.goel@intel.com wrote:
> > From: Akash Goel <akash.goel@intel.com>
> >
> > Updated the i915_drpc_info debugfs with coarse power gating & forcewake
> > info for Gen9.
> >
> > v2: Change all IS_GEN9() by gen >= 9 (Damien)
> >
> > v3: Rebase
> >
> > Cc: Damien Lespiau <damien.lespiau@intel.com>
> > Signed-off-by: Akash Goel <akash.goel@intel.com>
Queued for -next, thanks for the patch.
-Daniel
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 21 ++++++++++++++++++++-
> > drivers/gpu/drm/i915/i915_reg.h | 3 +++
> > 2 files changed, 23 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index f664884..5185e02 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -1588,6 +1588,7 @@ static int gen6_drpc_info(struct seq_file *m)
> > struct drm_device *dev = node->minor->dev;
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
> > + u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
> > unsigned forcewake_count;
> > int count = 0, ret;
> > @@ -1615,6 +1616,10 @@ static int gen6_drpc_info(struct seq_file *m)
> > rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
> > rcctl1 = I915_READ(GEN6_RC_CONTROL);
> > + if (INTEL_INFO(dev)->gen >= 9) {
> > + gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
> > + gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
> > + }
> > mutex_unlock(&dev->struct_mutex);
> > mutex_lock(&dev_priv->rps.hw_lock);
> > sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
> > @@ -1633,6 +1638,12 @@ static int gen6_drpc_info(struct seq_file *m)
> > yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
> > seq_printf(m, "RC6 Enabled: %s\n",
> > yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
> > + if (INTEL_INFO(dev)->gen >= 9) {
> > + seq_printf(m, "Render Well Gating Enabled: %s\n",
> > + yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
> > + seq_printf(m, "Media Well Gating Enabled: %s\n",
> > + yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
> > + }
> > seq_printf(m, "Deep RC6 Enabled: %s\n",
> > yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
> > seq_printf(m, "Deepest RC6 Enabled: %s\n",
> > @@ -1661,6 +1672,14 @@ static int gen6_drpc_info(struct seq_file *m)
> > seq_printf(m, "Core Power Down: %s\n",
> > yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
> > + if (INTEL_INFO(dev)->gen >= 9) {
> > + seq_printf(m, "Render Power Well: %s\n",
> > + (gen9_powergate_status &
> > + GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
> > + seq_printf(m, "Media Power Well: %s\n",
> > + (gen9_powergate_status &
> > + GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
> > + }
> > /* Not exactly sure what this is */
> > seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
> > @@ -1678,7 +1697,7 @@ static int gen6_drpc_info(struct seq_file *m)
> > GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
> > seq_printf(m, "RC6++ voltage: %dmV\n",
> > GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
> > - return 0;
> > + return i915_forcewake_domains(m, NULL);
> > }
> > static int i915_drpc_info(struct seq_file *m, void *unused)
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index c6bfbf8..1c8d029 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6955,6 +6955,9 @@ enum {
> > #define ECOBUS _MMIO(0xa180)
> > #define FORCEWAKE_MT_ENABLE (1<<5)
> > #define VLV_SPAREG2H _MMIO(0xA194)
> > +#define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0)
> > +#define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
> > +#define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1)
> > #define GTFIFODBG _MMIO(0x120000)
> > #define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3] drm/i915/gen9: Update i915_drpc_info debugfs for coarse pg & forcewake info
2016-08-02 14:09 ` Daniel Vetter
@ 2016-08-04 18:31 ` David Weinehall
2016-08-05 8:24 ` Jani Nikula
0 siblings, 1 reply; 18+ messages in thread
From: David Weinehall @ 2016-08-04 18:31 UTC (permalink / raw)
To: Daniel Vetter; +Cc: akash.goel, intel-gfx
On Tue, Aug 02, 2016 at 04:09:49PM +0200, Daniel Vetter wrote:
> On Mon, Aug 01, 2016 at 11:18:15PM +0530, Kamble, Sagar A wrote:
> > Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com
> > <mailto:sagar.a.kamble@intel.com>>
>
> You're mailer wreaks havoc with your reviewed-by tags. Pleas fix this.
>
>
> > On 6/27/2016 8:10 PM, akash.goel@intel.com wrote:
> > > From: Akash Goel <akash.goel@intel.com>
> > >
> > > Updated the i915_drpc_info debugfs with coarse power gating & forcewake
> > > info for Gen9.
> > >
> > > v2: Change all IS_GEN9() by gen >= 9 (Damien)
For future reference, please use IS_GEN(dev_priv) >= 9 for expressions
such as this. My bad for not spotting this until the patch got merged.
Fret not, however, I've got a few patches that'll clean this up :)
Regards, David Weinehall
_______________________________________________
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3] drm/i915/gen9: Update i915_drpc_info debugfs for coarse pg & forcewake info
2016-08-04 18:31 ` David Weinehall
@ 2016-08-05 8:24 ` Jani Nikula
2016-08-08 11:10 ` David Weinehall
0 siblings, 1 reply; 18+ messages in thread
From: Jani Nikula @ 2016-08-05 8:24 UTC (permalink / raw)
To: David Weinehall, Daniel Vetter; +Cc: akash.goel, intel-gfx
On Thu, 04 Aug 2016, David Weinehall <david.weinehall@linux.intel.com> wrote:
> On Tue, Aug 02, 2016 at 04:09:49PM +0200, Daniel Vetter wrote:
>> On Mon, Aug 01, 2016 at 11:18:15PM +0530, Kamble, Sagar A wrote:
>> > Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com
>> > <mailto:sagar.a.kamble@intel.com>>
>>
>> You're mailer wreaks havoc with your reviewed-by tags. Pleas fix this.
>>
>>
>> > On 6/27/2016 8:10 PM, akash.goel@intel.com wrote:
>> > > From: Akash Goel <akash.goel@intel.com>
>> > >
>> > > Updated the i915_drpc_info debugfs with coarse power gating & forcewake
>> > > info for Gen9.
>> > >
>> > > v2: Change all IS_GEN9() by gen >= 9 (Damien)
>
> For future reference, please use IS_GEN(dev_priv) >= 9 for expressions
> such as this. My bad for not spotting this until the patch got merged.
> Fret not, however, I've got a few patches that'll clean this up :)
David means INTEL_GEN(), not IS_GEN(). ;)
BR,
Jani.
>
>
> Regards, David Weinehall
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3] drm/i915/gen9: Update i915_drpc_info debugfs for coarse pg & forcewake info
2016-08-05 8:24 ` Jani Nikula
@ 2016-08-08 11:10 ` David Weinehall
0 siblings, 0 replies; 18+ messages in thread
From: David Weinehall @ 2016-08-08 11:10 UTC (permalink / raw)
To: Jani Nikula; +Cc: akash.goel, intel-gfx
On Fri, Aug 05, 2016 at 11:24:12AM +0300, Jani Nikula wrote:
> On Thu, 04 Aug 2016, David Weinehall <david.weinehall@linux.intel.com> wrote:
> > On Tue, Aug 02, 2016 at 04:09:49PM +0200, Daniel Vetter wrote:
> >> On Mon, Aug 01, 2016 at 11:18:15PM +0530, Kamble, Sagar A wrote:
> >> > Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com
> >> > <mailto:sagar.a.kamble@intel.com>>
> >>
> >> You're mailer wreaks havoc with your reviewed-by tags. Pleas fix this.
> >>
> >>
> >> > On 6/27/2016 8:10 PM, akash.goel@intel.com wrote:
> >> > > From: Akash Goel <akash.goel@intel.com>
> >> > >
> >> > > Updated the i915_drpc_info debugfs with coarse power gating & forcewake
> >> > > info for Gen9.
> >> > >
> >> > > v2: Change all IS_GEN9() by gen >= 9 (Damien)
> >
> > For future reference, please use IS_GEN(dev_priv) >= 9 for expressions
> > such as this. My bad for not spotting this until the patch got merged.
> > Fret not, however, I've got a few patches that'll clean this up :)
>
> David means INTEL_GEN(), not IS_GEN(). ;)
David indeed means INTEL_GEN(). Brainfart. :(
Kind regards, David
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^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2016-08-08 11:10 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-01-16 18:07 [PATCH 0/4] SKL turbo part 1 Damien Lespiau
2015-01-16 18:07 ` [PATCH 1/4] drm/i915/skl: add turbo support Damien Lespiau
2015-01-19 10:02 ` Mika Kuoppala
2015-01-16 18:07 ` [PATCH 2/4] drm/i915/skl: Retrieve the frequency limits Damien Lespiau
2015-01-20 10:14 ` Daniel Vetter
2015-01-20 11:45 ` Damien Lespiau
2015-01-16 18:07 ` [PATCH 3/4] drm/i915/skl: Gen9 coarse power gating Damien Lespiau
2015-01-19 15:39 ` Damien Lespiau
2015-01-16 18:07 ` [PATCH 4/4] drm/i915/skl: Updated the RC6/Forcewake related debugfs interface for Gen9 Damien Lespiau
2015-01-17 10:59 ` shuang.he
2015-01-19 15:50 ` Damien Lespiau
2016-06-27 14:40 ` [PATCH v3] drm/i915/gen9: Update i915_drpc_info debugfs for coarse pg & forcewake info akash.goel
2016-08-01 17:48 ` Kamble, Sagar A
2016-08-02 14:09 ` Daniel Vetter
2016-08-04 18:31 ` David Weinehall
2016-08-05 8:24 ` Jani Nikula
2016-08-08 11:10 ` David Weinehall
2016-06-27 14:52 ` ✗ Ro.CI.BAT: warning for " Patchwork
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