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From: Peter Zijlstra <peterz@infradead.org>
To: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Cc: linux-mm@kvack.org, linux-kernel@vger.kernel.org, x86@kernel.org,
	Borislav Petkov <bp@suse.de>, Andy Lutomirski <luto@kernel.org>,
	Rik van Riel <riel@redhat.com>, Mel Gorman <mgorman@suse.de>
Subject: Re: [PATCH] x86/mm: disable preemption during CR3 read+write
Date: Fri, 5 Aug 2016 15:53:08 +0200	[thread overview]
Message-ID: <20160805135308.GT6879@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <1470404259-26290-1-git-send-email-bigeasy@linutronix.de>

On Fri, Aug 05, 2016 at 03:37:39PM +0200, Sebastian Andrzej Siewior wrote:
> diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
> index 4e5be94e079a..1ee065954e24 100644
> --- a/arch/x86/include/asm/tlbflush.h
> +++ b/arch/x86/include/asm/tlbflush.h
> @@ -135,7 +135,14 @@ static inline void cr4_set_bits_and_update_boot(unsigned long mask)
>  
>  static inline void __native_flush_tlb(void)
>  {
> +	/*
> +	 * if current->mm == NULL then we borrow a mm which may change during a
> +	 * task switch and therefore we must not be preempted while we write CR3
> +	 * back.
> +	 */
> +	preempt_disable();
>  	native_write_cr3(native_read_cr3());
> +	preempt_enable();
>  }

Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>

WARNING: multiple messages have this Message-ID (diff)
From: Peter Zijlstra <peterz@infradead.org>
To: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Cc: linux-mm@kvack.org, linux-kernel@vger.kernel.org, x86@kernel.org,
	Borislav Petkov <bp@suse.de>, Andy Lutomirski <luto@kernel.org>,
	Rik van Riel <riel@redhat.com>, Mel Gorman <mgorman@suse.de>
Subject: Re: [PATCH] x86/mm: disable preemption during CR3 read+write
Date: Fri, 5 Aug 2016 15:53:08 +0200	[thread overview]
Message-ID: <20160805135308.GT6879@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <1470404259-26290-1-git-send-email-bigeasy@linutronix.de>

On Fri, Aug 05, 2016 at 03:37:39PM +0200, Sebastian Andrzej Siewior wrote:
> diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
> index 4e5be94e079a..1ee065954e24 100644
> --- a/arch/x86/include/asm/tlbflush.h
> +++ b/arch/x86/include/asm/tlbflush.h
> @@ -135,7 +135,14 @@ static inline void cr4_set_bits_and_update_boot(unsigned long mask)
>  
>  static inline void __native_flush_tlb(void)
>  {
> +	/*
> +	 * if current->mm == NULL then we borrow a mm which may change during a
> +	 * task switch and therefore we must not be preempted while we write CR3
> +	 * back.
> +	 */
> +	preempt_disable();
>  	native_write_cr3(native_read_cr3());
> +	preempt_enable();
>  }

Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>

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  reply	other threads:[~2016-08-05 13:53 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-05 13:37 [PATCH] x86/mm: disable preemption during CR3 read+write Sebastian Andrzej Siewior
2016-08-05 13:37 ` Sebastian Andrzej Siewior
2016-08-05 13:53 ` Peter Zijlstra [this message]
2016-08-05 13:53   ` Peter Zijlstra
2016-08-05 14:38 ` Rik van Riel
2016-08-05 15:42 ` Andy Lutomirski
2016-08-05 15:42   ` Andy Lutomirski
2016-08-05 15:52   ` Sebastian Andrzej Siewior
2016-08-05 15:52     ` Sebastian Andrzej Siewior
2016-08-10 18:10 ` [tip:x86/urgent] x86/mm: Disable " tip-bot for Sebastian Andrzej Siewior
2017-10-17 15:57 [PATCH] " Sebastian Andrzej Siewior
2017-10-18 15:01 ` Bernhard Kaindl
2017-10-18 16:51   ` Greg KH

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