* [PATCH v2 1/6] drm/dp: Add drm_dp_psr_setup_time()
2016-05-31 15:50 [PATCH 0/6] drm/i915: Remaining PSR fixes ville.syrjala
@ 2016-05-31 15:50 ` ville.syrjala
2016-05-31 15:50 ` [PATCH v2 2/6] drm/dp: Add drm_dp_psr_need_train_on_exit() ville.syrjala
` (8 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: ville.syrjala @ 2016-05-31 15:50 UTC (permalink / raw)
To: dri-devel; +Cc: Daniel Vetter, intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add a small helper to parse the PSR setup time from the DPCD PSR
capabilities and return the value in microseconds.
v2: Don't waste so many bytes on the psr_setup_time_us[] table
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 32 ++++++++++++++++++++++++++++++++
include/drm/drm_dp_helper.h | 2 ++
2 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index eeaf5a7c3aa7..1f914629031e 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -822,3 +822,35 @@ void drm_dp_aux_unregister(struct drm_dp_aux *aux)
i2c_del_adapter(&aux->ddc);
}
EXPORT_SYMBOL(drm_dp_aux_unregister);
+
+#define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x)
+
+/**
+ * drm_dp_psr_setup_time() - PSR setup in time usec
+ * @psr_cap: PSR capabilities from DPCD
+ *
+ * Returns:
+ * PSR setup time for the panel in microseconds, negative
+ * error code on failure.
+ */
+int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
+{
+ static const u16 psr_setup_time_us[] = {
+ PSR_SETUP_TIME(330),
+ PSR_SETUP_TIME(275),
+ PSR_SETUP_TIME(165),
+ PSR_SETUP_TIME(110),
+ PSR_SETUP_TIME(55),
+ PSR_SETUP_TIME(0),
+ };
+ int i;
+
+ i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT;
+ if (i >= ARRAY_SIZE(psr_setup_time_us))
+ return -EINVAL;
+
+ return psr_setup_time_us[i];
+}
+EXPORT_SYMBOL(drm_dp_psr_setup_time);
+
+#undef PSR_SETUP_TIME
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 5a848e734422..6aa74f7d45b4 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -657,6 +657,8 @@ struct edp_vsc_psr {
#define EDP_VSC_PSR_UPDATE_RFB (1<<1)
#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
+int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
+
static inline int
drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
{
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 2/6] drm/dp: Add drm_dp_psr_need_train_on_exit()
2016-05-31 15:50 [PATCH 0/6] drm/i915: Remaining PSR fixes ville.syrjala
2016-05-31 15:50 ` [PATCH v2 1/6] drm/dp: Add drm_dp_psr_setup_time() ville.syrjala
@ 2016-05-31 15:50 ` ville.syrjala
2016-05-31 15:50 ` [PATCH 3/6] drm/i915: Check PSR setup time vs. vblank length ville.syrjala
` (7 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: ville.syrjala @ 2016-05-31 15:50 UTC (permalink / raw)
To: dri-devel; +Cc: Daniel Vetter, intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add a small helper to parse from the DPCD whether link training
is required when exiting PSR main-link off mode.
v2: Rebased
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 14 ++++++++++++++
include/drm/drm_dp_helper.h | 1 +
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 1f914629031e..cc7b55a695b5 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -854,3 +854,17 @@ int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
EXPORT_SYMBOL(drm_dp_psr_setup_time);
#undef PSR_SETUP_TIME
+
+/**
+ * drm_dp_psr_need_train_on_exit() - Indicate whether link training is needed on PSR exit
+ * @psr_cap: PSR capabilities from DPCD
+ *
+ * Returns:
+ * Whether link training is required when exiting PSR main-link off mode.
+ */
+bool drm_dp_psr_need_train_on_exit(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
+{
+ /* DP_PSR_NO_TRAIN_ON_EXIT is "don't care" for PSR2 capable devices */
+ return psr_cap[0] < 0x2 && (psr_cap[1] & DP_PSR_NO_TRAIN_ON_EXIT) == 0;
+}
+EXPORT_SYMBOL(drm_dp_psr_need_train_on_exit);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 6aa74f7d45b4..2437f1b6e776 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -658,6 +658,7 @@ struct edp_vsc_psr {
#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
+bool drm_dp_psr_need_train_on_exit(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
static inline int
drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
--
2.7.4
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 3/6] drm/i915: Check PSR setup time vs. vblank length
2016-05-31 15:50 [PATCH 0/6] drm/i915: Remaining PSR fixes ville.syrjala
2016-05-31 15:50 ` [PATCH v2 1/6] drm/dp: Add drm_dp_psr_setup_time() ville.syrjala
2016-05-31 15:50 ` [PATCH v2 2/6] drm/dp: Add drm_dp_psr_need_train_on_exit() ville.syrjala
@ 2016-05-31 15:50 ` ville.syrjala
2016-08-05 22:10 ` [Intel-gfx] " Rodrigo Vivi
2016-05-31 15:50 ` [PATCH 4/6] drm/i915/psr: Skip aux handeshake if the vbt tells us to ville.syrjala
` (6 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: ville.syrjala @ 2016-05-31 15:50 UTC (permalink / raw)
To: dri-devel; +Cc: Daniel Vetter, intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Bspec says:
"Restriction : SRD must not be enabled when the PSR Setup time from DPCD
00071h is greater than the time for vertical blank minus one line."
Let's check for that and disallow PSR if we exceed the limit.
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/drm/i915/intel_psr.c | 19 ++++++++++++++++++-
drivers/gpu/drm/i915/intel_sprite.c | 6 +++---
3 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9b5f6634c558..56ae3b78e25e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1672,6 +1672,8 @@ bool intel_sdvo_init(struct drm_device *dev,
/* intel_sprite.c */
+int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
+ int usecs);
int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
struct drm_file *file_priv);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 29a09bf6bd18..aacd8d1767f2 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -327,6 +327,9 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_crtc *crtc = dig_port->base.base.crtc;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ const struct drm_display_mode *adjusted_mode =
+ &intel_crtc->config->base.adjusted_mode;
+ int psr_setup_time;
lockdep_assert_held(&dev_priv->psr.lock);
WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
@@ -365,11 +368,25 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
}
if (IS_HASWELL(dev) &&
- intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+ adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
return false;
}
+ psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
+ if (psr_setup_time < 0) {
+ DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n",
+ intel_dp->psr_dpcd[1]);
+ return false;
+ }
+
+ if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
+ adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
+ DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n",
+ psr_setup_time);
+ return false;
+ }
+
dev_priv->psr.source_ok = true;
return true;
}
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 324ccb06397d..293b48007006 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -53,8 +53,8 @@ format_is_yuv(uint32_t format)
}
}
-static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
- int usecs)
+int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
+ int usecs)
{
/* paranoia */
if (!adjusted_mode->crtc_htotal)
@@ -91,7 +91,7 @@ void intel_pipe_update_start(struct intel_crtc *crtc)
vblank_start = DIV_ROUND_UP(vblank_start, 2);
/* FIXME needs to be calibrated sensibly */
- min = vblank_start - usecs_to_scanlines(adjusted_mode, 100);
+ min = vblank_start - intel_usecs_to_scanlines(adjusted_mode, 100);
max = vblank_start - 1;
local_irq_disable();
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [Intel-gfx] [PATCH 3/6] drm/i915: Check PSR setup time vs. vblank length
2016-05-31 15:50 ` [PATCH 3/6] drm/i915: Check PSR setup time vs. vblank length ville.syrjala
@ 2016-08-05 22:10 ` Rodrigo Vivi
2016-08-08 7:38 ` Ville Syrjälä
2016-08-08 8:33 ` Jani Nikula
0 siblings, 2 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2016-08-05 22:10 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Daniel Vetter, intel-gfx, DRI mailing list
This patch is blocking PSR on panels that we know that our hardware support.
I wonder if:
1. This restrictions was for older platforms and spec is out dated
2. Or Spec is not documenting the restriction properly
3. Or we have some issue with out setup time calculation.
On Tue, May 31, 2016 at 8:50 AM, <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Bspec says:
> "Restriction : SRD must not be enabled when the PSR Setup time from DPCD
> 00071h is greater than the time for vertical blank minus one line."
>
> Let's check for that and disallow PSR if we exceed the limit.
>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> drivers/gpu/drm/i915/intel_psr.c | 19 ++++++++++++++++++-
> drivers/gpu/drm/i915/intel_sprite.c | 6 +++---
> 3 files changed, 23 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 9b5f6634c558..56ae3b78e25e 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1672,6 +1672,8 @@ bool intel_sdvo_init(struct drm_device *dev,
>
>
> /* intel_sprite.c */
> +int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
> + int usecs);
> int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
> int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
> struct drm_file *file_priv);
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 29a09bf6bd18..aacd8d1767f2 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -327,6 +327,9 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct drm_crtc *crtc = dig_port->base.base.crtc;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> + const struct drm_display_mode *adjusted_mode =
> + &intel_crtc->config->base.adjusted_mode;
> + int psr_setup_time;
>
> lockdep_assert_held(&dev_priv->psr.lock);
> WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
> @@ -365,11 +368,25 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
> }
>
> if (IS_HASWELL(dev) &&
> - intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> + adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
> return false;
> }
>
> + psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
> + if (psr_setup_time < 0) {
> + DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n",
> + intel_dp->psr_dpcd[1]);
> + return false;
> + }
> +
> + if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
> + adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
> + DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n",
> + psr_setup_time);
> + return false;
> + }
> +
> dev_priv->psr.source_ok = true;
> return true;
> }
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 324ccb06397d..293b48007006 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -53,8 +53,8 @@ format_is_yuv(uint32_t format)
> }
> }
>
> -static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
> - int usecs)
> +int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
> + int usecs)
> {
> /* paranoia */
> if (!adjusted_mode->crtc_htotal)
> @@ -91,7 +91,7 @@ void intel_pipe_update_start(struct intel_crtc *crtc)
> vblank_start = DIV_ROUND_UP(vblank_start, 2);
>
> /* FIXME needs to be calibrated sensibly */
> - min = vblank_start - usecs_to_scanlines(adjusted_mode, 100);
> + min = vblank_start - intel_usecs_to_scanlines(adjusted_mode, 100);
> max = vblank_start - 1;
>
> local_irq_disable();
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
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^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 3/6] drm/i915: Check PSR setup time vs. vblank length
2016-08-05 22:10 ` [Intel-gfx] " Rodrigo Vivi
@ 2016-08-08 7:38 ` Ville Syrjälä
2016-08-08 8:33 ` Jani Nikula
1 sibling, 0 replies; 17+ messages in thread
From: Ville Syrjälä @ 2016-08-08 7:38 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: Daniel Vetter, intel-gfx, Runyan, Arthur J, DRI mailing list
On Fri, Aug 05, 2016 at 03:10:51PM -0700, Rodrigo Vivi wrote:
> This patch is blocking PSR on panels that we know that our hardware support.
How do we know that?
> I wonder if:
> 1. This restrictions was for older platforms and spec is out dated
> 2. Or Spec is not documenting the restriction properly
I doubt it. AFAICS the only way that restriction could be lifted is by
adding support for the "Frame Capture Indication" bit in the PSR DPCD
register 0x170. That would cause the panel to wait one extra frame
between receiving the PSR entry indication and capturing the last
active frame. But I see no knob in Bspec that would allow us to tell
the source to send out that one extra active frame.
But maybe I've missed something. Art?
> 3. Or we have some issue with out setup time calculation.
I don't think so. Well, unless the panel is crap and reports a
totally bogus setup time.
I did notice that my SKL RVP stops trying to do PSR with this patch.
The EDID specifies two modes: 3200x1800@60Hz with 146us vblank,
and 3200x1800@48Hz with with ~2.5ms vblank. The setup time is
declared as 330us, so with the default mode we won't use PSR. We
could use the other timings I suppose, but I'm not sure everyone
would be happy with a 48Hz refresh rate. This is really a question
policy that shouldn't be handled in the kernel. What we could do is
expose both 60Hz and 48Hz modes, and let userspace choose the
refresh rate.
> On Tue, May 31, 2016 at 8:50 AM, <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Bspec says:
> > "Restriction : SRD must not be enabled when the PSR Setup time from DPCD
> > 00071h is greater than the time for vertical blank minus one line."
> >
> > Let's check for that and disallow PSR if we exceed the limit.
> >
> > Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> > Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_drv.h | 2 ++
> > drivers/gpu/drm/i915/intel_psr.c | 19 ++++++++++++++++++-
> > drivers/gpu/drm/i915/intel_sprite.c | 6 +++---
> > 3 files changed, 23 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 9b5f6634c558..56ae3b78e25e 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1672,6 +1672,8 @@ bool intel_sdvo_init(struct drm_device *dev,
> >
> >
> > /* intel_sprite.c */
> > +int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
> > + int usecs);
> > int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
> > int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
> > struct drm_file *file_priv);
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> > index 29a09bf6bd18..aacd8d1767f2 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -327,6 +327,9 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > struct drm_crtc *crtc = dig_port->base.base.crtc;
> > struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > + const struct drm_display_mode *adjusted_mode =
> > + &intel_crtc->config->base.adjusted_mode;
> > + int psr_setup_time;
> >
> > lockdep_assert_held(&dev_priv->psr.lock);
> > WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
> > @@ -365,11 +368,25 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
> > }
> >
> > if (IS_HASWELL(dev) &&
> > - intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> > + adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> > DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
> > return false;
> > }
> >
> > + psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
> > + if (psr_setup_time < 0) {
> > + DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n",
> > + intel_dp->psr_dpcd[1]);
> > + return false;
> > + }
> > +
> > + if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
> > + adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
> > + DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n",
> > + psr_setup_time);
> > + return false;
> > + }
> > +
> > dev_priv->psr.source_ok = true;
> > return true;
> > }
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > index 324ccb06397d..293b48007006 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -53,8 +53,8 @@ format_is_yuv(uint32_t format)
> > }
> > }
> >
> > -static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
> > - int usecs)
> > +int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
> > + int usecs)
> > {
> > /* paranoia */
> > if (!adjusted_mode->crtc_htotal)
> > @@ -91,7 +91,7 @@ void intel_pipe_update_start(struct intel_crtc *crtc)
> > vblank_start = DIV_ROUND_UP(vblank_start, 2);
> >
> > /* FIXME needs to be calibrated sensibly */
> > - min = vblank_start - usecs_to_scanlines(adjusted_mode, 100);
> > + min = vblank_start - intel_usecs_to_scanlines(adjusted_mode, 100);
> > max = vblank_start - 1;
> >
> > local_irq_disable();
> > --
> > 2.7.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 3/6] drm/i915: Check PSR setup time vs. vblank length
2016-08-05 22:10 ` [Intel-gfx] " Rodrigo Vivi
2016-08-08 7:38 ` Ville Syrjälä
@ 2016-08-08 8:33 ` Jani Nikula
2016-08-25 21:39 ` [Intel-gfx] " Rodrigo Vivi
1 sibling, 1 reply; 17+ messages in thread
From: Jani Nikula @ 2016-08-08 8:33 UTC (permalink / raw)
To: Rodrigo Vivi, Ville Syrjälä
Cc: Daniel Vetter, intel-gfx, DRI mailing list
On Sat, 06 Aug 2016, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
> This patch is blocking PSR on panels that we know that our hardware support.
And it also fixes a regression on Linus' laptop, and it's been merged
upstream...
BR,
Jani.
>
> I wonder if:
> 1. This restrictions was for older platforms and spec is out dated
> 2. Or Spec is not documenting the restriction properly
> 3. Or we have some issue with out setup time calculation.
>
>
> On Tue, May 31, 2016 at 8:50 AM, <ville.syrjala@linux.intel.com> wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Bspec says:
>> "Restriction : SRD must not be enabled when the PSR Setup time from DPCD
>> 00071h is greater than the time for vertical blank minus one line."
>>
>> Let's check for that and disallow PSR if we exceed the limit.
>>
>> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
>> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_drv.h | 2 ++
>> drivers/gpu/drm/i915/intel_psr.c | 19 ++++++++++++++++++-
>> drivers/gpu/drm/i915/intel_sprite.c | 6 +++---
>> 3 files changed, 23 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index 9b5f6634c558..56ae3b78e25e 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -1672,6 +1672,8 @@ bool intel_sdvo_init(struct drm_device *dev,
>>
>>
>> /* intel_sprite.c */
>> +int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
>> + int usecs);
>> int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
>> int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
>> struct drm_file *file_priv);
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>> index 29a09bf6bd18..aacd8d1767f2 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -327,6 +327,9 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> struct drm_crtc *crtc = dig_port->base.base.crtc;
>> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>> + const struct drm_display_mode *adjusted_mode =
>> + &intel_crtc->config->base.adjusted_mode;
>> + int psr_setup_time;
>>
>> lockdep_assert_held(&dev_priv->psr.lock);
>> WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
>> @@ -365,11 +368,25 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
>> }
>>
>> if (IS_HASWELL(dev) &&
>> - intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
>> + adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
>> DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
>> return false;
>> }
>>
>> + psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
>> + if (psr_setup_time < 0) {
>> + DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n",
>> + intel_dp->psr_dpcd[1]);
>> + return false;
>> + }
>> +
>> + if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
>> + adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
>> + DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n",
>> + psr_setup_time);
>> + return false;
>> + }
>> +
>> dev_priv->psr.source_ok = true;
>> return true;
>> }
>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
>> index 324ccb06397d..293b48007006 100644
>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>> @@ -53,8 +53,8 @@ format_is_yuv(uint32_t format)
>> }
>> }
>>
>> -static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
>> - int usecs)
>> +int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
>> + int usecs)
>> {
>> /* paranoia */
>> if (!adjusted_mode->crtc_htotal)
>> @@ -91,7 +91,7 @@ void intel_pipe_update_start(struct intel_crtc *crtc)
>> vblank_start = DIV_ROUND_UP(vblank_start, 2);
>>
>> /* FIXME needs to be calibrated sensibly */
>> - min = vblank_start - usecs_to_scanlines(adjusted_mode, 100);
>> + min = vblank_start - intel_usecs_to_scanlines(adjusted_mode, 100);
>> max = vblank_start - 1;
>>
>> local_irq_disable();
>> --
>> 2.7.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [Intel-gfx] [PATCH 3/6] drm/i915: Check PSR setup time vs. vblank length
2016-08-08 8:33 ` Jani Nikula
@ 2016-08-25 21:39 ` Rodrigo Vivi
0 siblings, 0 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2016-08-25 21:39 UTC (permalink / raw)
To: Jani Nikula; +Cc: Daniel Vetter, intel-gfx, DRI mailing list
On Mon, Aug 8, 2016 at 1:33 AM, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Sat, 06 Aug 2016, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
>> This patch is blocking PSR on panels that we know that our hardware support.
>
> And it also fixes a regression on Linus' laptop, and it's been merged
> upstream...
yeap, this patch is like setting i915.enable_psr=0...
I still believe we have an error somewhere else.
With this patch in place there is no panel out there with PSR
supported with preferred mode.
Maybe this ultra fast vblank is confusing this PSR blocks if this are
the expected timings...
>
> BR,
> Jani.
>
>>
>> I wonder if:
>> 1. This restrictions was for older platforms and spec is out dated
>> 2. Or Spec is not documenting the restriction properly
>> 3. Or we have some issue with out setup time calculation.
>>
>>
>> On Tue, May 31, 2016 at 8:50 AM, <ville.syrjala@linux.intel.com> wrote:
>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>
>>> Bspec says:
>>> "Restriction : SRD must not be enabled when the PSR Setup time from DPCD
>>> 00071h is greater than the time for vertical blank minus one line."
>>>
>>> Let's check for that and disallow PSR if we exceed the limit.
>>>
>>> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
>>> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> ---
>>> drivers/gpu/drm/i915/intel_drv.h | 2 ++
>>> drivers/gpu/drm/i915/intel_psr.c | 19 ++++++++++++++++++-
>>> drivers/gpu/drm/i915/intel_sprite.c | 6 +++---
>>> 3 files changed, 23 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>>> index 9b5f6634c558..56ae3b78e25e 100644
>>> --- a/drivers/gpu/drm/i915/intel_drv.h
>>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>>> @@ -1672,6 +1672,8 @@ bool intel_sdvo_init(struct drm_device *dev,
>>>
>>>
>>> /* intel_sprite.c */
>>> +int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
>>> + int usecs);
>>> int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
>>> int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
>>> struct drm_file *file_priv);
>>> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>>> index 29a09bf6bd18..aacd8d1767f2 100644
>>> --- a/drivers/gpu/drm/i915/intel_psr.c
>>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>>> @@ -327,6 +327,9 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
>>> struct drm_i915_private *dev_priv = dev->dev_private;
>>> struct drm_crtc *crtc = dig_port->base.base.crtc;
>>> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>>> + const struct drm_display_mode *adjusted_mode =
>>> + &intel_crtc->config->base.adjusted_mode;
>>> + int psr_setup_time;
>>>
>>> lockdep_assert_held(&dev_priv->psr.lock);
>>> WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
>>> @@ -365,11 +368,25 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
>>> }
>>>
>>> if (IS_HASWELL(dev) &&
>>> - intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
>>> + adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
>>> DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
>>> return false;
>>> }
>>>
>>> + psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
>>> + if (psr_setup_time < 0) {
>>> + DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n",
>>> + intel_dp->psr_dpcd[1]);
>>> + return false;
>>> + }
>>> +
>>> + if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
>>> + adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
>>> + DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n",
>>> + psr_setup_time);
>>> + return false;
>>> + }
>>> +
>>> dev_priv->psr.source_ok = true;
>>> return true;
>>> }
>>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
>>> index 324ccb06397d..293b48007006 100644
>>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>>> @@ -53,8 +53,8 @@ format_is_yuv(uint32_t format)
>>> }
>>> }
>>>
>>> -static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
>>> - int usecs)
>>> +int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
>>> + int usecs)
>>> {
>>> /* paranoia */
>>> if (!adjusted_mode->crtc_htotal)
>>> @@ -91,7 +91,7 @@ void intel_pipe_update_start(struct intel_crtc *crtc)
>>> vblank_start = DIV_ROUND_UP(vblank_start, 2);
>>>
>>> /* FIXME needs to be calibrated sensibly */
>>> - min = vblank_start - usecs_to_scanlines(adjusted_mode, 100);
>>> + min = vblank_start - intel_usecs_to_scanlines(adjusted_mode, 100);
>>> max = vblank_start - 1;
>>>
>>> local_irq_disable();
>>> --
>>> 2.7.4
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Jani Nikula, Intel Open Source Technology Center
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 4/6] drm/i915/psr: Skip aux handeshake if the vbt tells us to
2016-05-31 15:50 [PATCH 0/6] drm/i915: Remaining PSR fixes ville.syrjala
` (2 preceding siblings ...)
2016-05-31 15:50 ` [PATCH 3/6] drm/i915: Check PSR setup time vs. vblank length ville.syrjala
@ 2016-05-31 15:50 ` ville.syrjala
2016-05-31 15:50 ` [PATCH 5/6] drm/i915: Ask the sink whether training is required when exiting PSR main-link off mode ville.syrjala
` (5 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: ville.syrjala @ 2016-05-31 15:50 UTC (permalink / raw)
To: dri-devel; +Cc: intel-gfx, Rodrigo Vivi
From: Daniel Vetter <daniel.vetter@ffwll.ch>
Not sure we can trust VBT on this one, but let's try.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Sonika Jindal <sonika.jindal@intel.com>
Cc: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_psr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index aacd8d1767f2..c073cbbf1b91 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -298,6 +298,9 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
else
val |= EDP_PSR_TP1_TP2_SEL;
+ if (!dev_priv->vbt.psr.require_aux_wakeup)
+ val |= EDP_PSR_SKIP_AUX_EXIT;
+
I915_WRITE(EDP_PSR_CTL, val);
if (!dev_priv->psr.psr2_support)
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 5/6] drm/i915: Ask the sink whether training is required when exiting PSR main-link off mode
2016-05-31 15:50 [PATCH 0/6] drm/i915: Remaining PSR fixes ville.syrjala
` (3 preceding siblings ...)
2016-05-31 15:50 ` [PATCH 4/6] drm/i915/psr: Skip aux handeshake if the vbt tells us to ville.syrjala
@ 2016-05-31 15:50 ` ville.syrjala
2016-05-31 15:50 ` [PATCH 6/6] drm/i915: Move psr.link_standby setup to intel_psr_match_conditions() ville.syrjala
` (4 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: ville.syrjala @ 2016-05-31 15:50 UTC (permalink / raw)
To: dri-devel; +Cc: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The sink can tell us if link training needs to be performed when
exiting PSR main-link off mode. Currently we get that information
from the VBT, but at least on my HSW the VBT says one thing, the sink
another. And in practice the sink doesn't seem to notice any screen
updates unless we do the training.
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_psr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index c073cbbf1b91..4db9c26fb970 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -298,7 +298,8 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
else
val |= EDP_PSR_TP1_TP2_SEL;
- if (!dev_priv->vbt.psr.require_aux_wakeup)
+ if (!dev_priv->vbt.psr.require_aux_wakeup &&
+ !drm_dp_psr_need_train_on_exit(intel_dp->psr_dpcd))
val |= EDP_PSR_SKIP_AUX_EXIT;
I915_WRITE(EDP_PSR_CTL, val);
--
2.7.4
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 6/6] drm/i915: Move psr.link_standby setup to intel_psr_match_conditions()
2016-05-31 15:50 [PATCH 0/6] drm/i915: Remaining PSR fixes ville.syrjala
` (4 preceding siblings ...)
2016-05-31 15:50 ` [PATCH 5/6] drm/i915: Ask the sink whether training is required when exiting PSR main-link off mode ville.syrjala
@ 2016-05-31 15:50 ` ville.syrjala
2016-05-31 16:17 ` ✗ Ro.CI.BAT: failure for drm/i915: Remaining PSR fixes Patchwork
` (3 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: ville.syrjala @ 2016-05-31 15:50 UTC (permalink / raw)
To: dri-devel; +Cc: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Determine the value of psr.link_standby at runtime rather than at init
time. This helps in testing since you can change between link-off and
link-standby at runtime.
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_psr.c | 41 ++++++++++++++++++++--------------------
1 file changed, 21 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 4db9c26fb970..8c70420cc6db 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -339,6 +339,27 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
+ /* Set link_standby x link_off defaults */
+ if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+ /* HSW and BDW require workarounds that we don't implement. */
+ dev_priv->psr.link_standby = false;
+ else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+ /* On VLV and CHV only standby mode is supported. */
+ dev_priv->psr.link_standby = true;
+ else
+ /* For new platforms let's respect VBT back again */
+ dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
+
+ /* Override link_standby x link_off defaults */
+ if (i915.enable_psr == 2 && !dev_priv->psr.link_standby) {
+ DRM_DEBUG_KMS("PSR: Forcing link standby\n");
+ dev_priv->psr.link_standby = true;
+ }
+ if (i915.enable_psr == 3 && dev_priv->psr.link_standby) {
+ DRM_DEBUG_KMS("PSR: Forcing main link off\n");
+ dev_priv->psr.link_standby = false;
+ }
+
dev_priv->psr.source_ok = false;
/*
@@ -830,26 +851,6 @@ void intel_psr_init(struct drm_device *dev)
i915.enable_psr = 0;
}
- /* Set link_standby x link_off defaults */
- if (IS_HASWELL(dev) || IS_BROADWELL(dev))
- /* HSW and BDW require workarounds that we don't implement. */
- dev_priv->psr.link_standby = false;
- else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
- /* On VLV and CHV only standby mode is supported. */
- dev_priv->psr.link_standby = true;
- else
- /* For new platforms let's respect VBT back again */
- dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
-
- /* Override link_standby x link_off defaults */
- if (i915.enable_psr == 2 && !dev_priv->psr.link_standby) {
- DRM_DEBUG_KMS("PSR: Forcing link standby\n");
- dev_priv->psr.link_standby = true;
- }
- if (i915.enable_psr == 3 && dev_priv->psr.link_standby) {
- DRM_DEBUG_KMS("PSR: Forcing main link off\n");
- dev_priv->psr.link_standby = false;
- }
INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
mutex_init(&dev_priv->psr.lock);
--
2.7.4
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 17+ messages in thread* ✗ Ro.CI.BAT: failure for drm/i915: Remaining PSR fixes
2016-05-31 15:50 [PATCH 0/6] drm/i915: Remaining PSR fixes ville.syrjala
` (5 preceding siblings ...)
2016-05-31 15:50 ` [PATCH 6/6] drm/i915: Move psr.link_standby setup to intel_psr_match_conditions() ville.syrjala
@ 2016-05-31 16:17 ` Patchwork
2016-06-02 18:28 ` Ville Syrjälä
2016-05-31 19:07 ` [PATCH 0/6] " Daniel Vetter
` (2 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: Patchwork @ 2016-05-31 16:17 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Remaining PSR fixes
URL : https://patchwork.freedesktop.org/series/8046/
State : failure
== Summary ==
Series 8046v1 drm/i915: Remaining PSR fixes
http://patchwork.freedesktop.org/api/1.0/series/8046/revisions/1/mbox
Test gem_close_race:
Subgroup basic-process:
dmesg-warn -> PASS (ro-ivb2-i7-3770)
Test gem_cpu_reloc:
Subgroup basic:
dmesg-warn -> PASS (ro-ivb2-i7-3770)
Test gem_ctx_param:
Subgroup basic:
pass -> DMESG-WARN (ro-ivb2-i7-3770)
Test gem_exec_basic:
Subgroup gtt-default:
dmesg-warn -> PASS (ro-skl-i7-6700hq)
Subgroup gtt-vebox:
dmesg-warn -> PASS (ro-skl-i7-6700hq)
Subgroup readonly-bsd:
dmesg-warn -> PASS (ro-ivb2-i7-3770)
Test gem_exec_flush:
Subgroup basic-uc-pro-default:
pass -> DMESG-WARN (ro-skl-i7-6700hq)
Subgroup basic-uc-rw-default:
dmesg-warn -> PASS (ro-skl-i7-6700hq)
Subgroup basic-wb-rw-default:
pass -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_exec_parallel:
Subgroup basic:
dmesg-warn -> PASS (ro-ivb2-i7-3770)
Test gem_exec_store:
Subgroup basic-render:
dmesg-warn -> PASS (ro-ivb2-i7-3770)
Test gem_mmap_gtt:
Subgroup basic-write-gtt-no-prefault:
dmesg-warn -> PASS (ro-skl-i7-6700hq)
Subgroup basic-write-no-prefault:
pass -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_pread:
Subgroup basic:
dmesg-warn -> PASS (ro-skl-i7-6700hq)
Test gem_pwrite:
Subgroup basic:
pass -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_tiled_fence_blits:
Subgroup basic:
dmesg-warn -> PASS (ro-ivb2-i7-3770)
Test kms_addfb_basic:
Subgroup addfb25-yf-tiled:
pass -> DMESG-WARN (ro-skl-i7-6700hq)
Subgroup basic-y-tiled:
pass -> DMESG-WARN (ro-skl-i7-6700hq)
Subgroup framebuffer-vs-set-tiling:
dmesg-warn -> PASS (ro-skl-i7-6700hq)
Subgroup too-high:
dmesg-warn -> PASS (ro-skl-i7-6700hq)
Test kms_force_connector_basic:
Subgroup force-edid:
dmesg-warn -> PASS (ro-ivb2-i7-3770)
Test kms_frontbuffer_tracking:
Subgroup basic:
pass -> DMESG-FAIL (ro-skl-i7-6700hq)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass -> INCOMPLETE (fi-hsw-i7-4770k)
Test kms_sink_crc_basic:
pass -> SKIP (ro-bdw-i7-5600u)
pass -> SKIP (ro-skl-i7-6700hq)
fi-byt-n2820 total:209 pass:168 dwarn:0 dfail:0 fail:3 skip:38
fi-hsw-i7-4770k total:184 pass:166 dwarn:0 dfail:0 fail:0 skip:17
fi-hsw-i7-4770r total:209 pass:186 dwarn:0 dfail:0 fail:0 skip:23
fi-skl-i5-6260u total:209 pass:198 dwarn:0 dfail:0 fail:0 skip:11
fi-skl-i7-6700k total:209 pass:184 dwarn:0 dfail:0 fail:0 skip:25
fi-snb-i7-2600 total:209 pass:170 dwarn:0 dfail:0 fail:0 skip:39
ro-bdw-i5-5250u total:102 pass:93 dwarn:0 dfail:0 fail:0 skip:8
ro-bdw-i7-5600u total:102 pass:74 dwarn:0 dfail:0 fail:0 skip:27
ro-bsw-n3050 total:209 pass:168 dwarn:0 dfail:0 fail:2 skip:39
ro-byt-n2820 total:209 pass:169 dwarn:0 dfail:0 fail:3 skip:37
ro-hsw-i3-4010u total:209 pass:186 dwarn:0 dfail:0 fail:0 skip:23
ro-hsw-i7-4770r total:102 pass:82 dwarn:0 dfail:0 fail:0 skip:19
ro-ilk1-i5-650 total:204 pass:146 dwarn:0 dfail:0 fail:1 skip:57
ro-ivb2-i7-3770 total:102 pass:47 dwarn:32 dfail:0 fail:0 skip:22
ro-skl-i7-6700hq total:204 pass:172 dwarn:9 dfail:1 fail:0 skip:22
fi-bdw-i7-5557u failed to connect after reboot
fi-bsw-n3050 failed to connect after reboot
ro-bdw-i7-5557U failed to connect after reboot
ro-ilk-i7-620lm failed to connect after reboot
ro-ivb-i7-3770 failed to connect after reboot
ro-snb-i7-2620M failed to connect after reboot
Results at /archive/results/CI_IGT_test/RO_Patchwork_1068/
877a1d2 drm-intel-nightly: 2016y-05m-31d-14h-57m-44s UTC integration manifest
8238bdb drm/i915: Move psr.link_standby setup to intel_psr_match_conditions()
58ee76a drm/i915: Ask the sink whether training is required when exiting PSR main-link off mode
5fe07aa drm/i915/psr: Skip aux handeshake if the vbt tells us to
6e98304 drm/i915: Check PSR setup time vs. vblank length
2a67384 drm/dp: Add drm_dp_psr_need_train_on_exit()
3ad03bc drm/dp: Add drm_dp_psr_setup_time()
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: ✗ Ro.CI.BAT: failure for drm/i915: Remaining PSR fixes
2016-05-31 16:17 ` ✗ Ro.CI.BAT: failure for drm/i915: Remaining PSR fixes Patchwork
@ 2016-06-02 18:28 ` Ville Syrjälä
0 siblings, 0 replies; 17+ messages in thread
From: Ville Syrjälä @ 2016-06-02 18:28 UTC (permalink / raw)
To: intel-gfx
On Tue, May 31, 2016 at 04:17:00PM -0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Remaining PSR fixes
> URL : https://patchwork.freedesktop.org/series/8046/
> State : failure
>
> == Summary ==
>
> Series 8046v1 drm/i915: Remaining PSR fixes
> http://patchwork.freedesktop.org/api/1.0/series/8046/revisions/1/mbox
>
> Test gem_close_race:
> Subgroup basic-process:
> dmesg-warn -> PASS (ro-ivb2-i7-3770)
ivb fails are
[ 176.194435] BUG: using smp_processor_id() in preemptible [00000000] code: usb-storage/216
https://bugs.freedesktop.org/show_bug.cgi?id=96293
> Test gem_cpu_reloc:
> Subgroup basic:
> dmesg-warn -> PASS (ro-ivb2-i7-3770)
> Test gem_ctx_param:
> Subgroup basic:
> pass -> DMESG-WARN (ro-ivb2-i7-3770)
> Test gem_exec_basic:
> Subgroup gtt-default:
> dmesg-warn -> PASS (ro-skl-i7-6700hq)
> Subgroup gtt-vebox:
> dmesg-warn -> PASS (ro-skl-i7-6700hq)
> Subgroup readonly-bsd:
> dmesg-warn -> PASS (ro-ivb2-i7-3770)
> Test gem_exec_flush:
> Subgroup basic-uc-pro-default:
> pass -> DMESG-WARN (ro-skl-i7-6700hq)
skl fails are
[ 360.358514] [drm:intel_pipe_update_start [i915]] *ERROR* Potential atomic update failure on pipe A
https://bugs.freedesktop.org/show_bug.cgi?id=95632
> Test kms_pipe_crc_basic:
> Subgroup suspend-read-crc-pipe-a:
> pass -> INCOMPLETE (fi-hsw-i7-4770k)
Hmm. Nothing in dmesg after
[ 403.811416] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-A
so no clue what happened.
> Test kms_sink_crc_basic:
> pass -> SKIP (ro-bdw-i7-5600u)
> pass -> SKIP (ro-skl-i7-6700hq)
[ 114.613007] [drm:intel_dp_sink_crc [i915]] *ERROR* Panel is unable to calculate any CRC after 6 vblanks
Hmm. This could actually have something to with the patch set.
Looking at the long term CI results, at least the bdw seems to have
been rather solid since RO_CI_DRM_419 which included [1]. The skl
has been fluctuating until ~RO_CI_DRM_453, but I see no PSR related
changes around that time so I'm going to assume the apparent recent
stability was more of a fluke.
[1]
dc00b6a drm/i915/psr: Implement PSR2 w/a for gen9
d4dcbdc drm/i915/psr: Use ->get_aux_send_ctl functions
6f32ea7 drm/i915/psr: Order DP aux transactions correctly
1c80c25 drm/i915/psr: Make idle_frames sensible again
50db139 drm/i915/psr: Try to program link training times correctly
>
> fi-byt-n2820 total:209 pass:168 dwarn:0 dfail:0 fail:3 skip:38
> fi-hsw-i7-4770k total:184 pass:166 dwarn:0 dfail:0 fail:0 skip:17
> fi-hsw-i7-4770r total:209 pass:186 dwarn:0 dfail:0 fail:0 skip:23
> fi-skl-i5-6260u total:209 pass:198 dwarn:0 dfail:0 fail:0 skip:11
> fi-skl-i7-6700k total:209 pass:184 dwarn:0 dfail:0 fail:0 skip:25
> fi-snb-i7-2600 total:209 pass:170 dwarn:0 dfail:0 fail:0 skip:39
> ro-bdw-i5-5250u total:102 pass:93 dwarn:0 dfail:0 fail:0 skip:8
> ro-bdw-i7-5600u total:102 pass:74 dwarn:0 dfail:0 fail:0 skip:27
> ro-bsw-n3050 total:209 pass:168 dwarn:0 dfail:0 fail:2 skip:39
> ro-byt-n2820 total:209 pass:169 dwarn:0 dfail:0 fail:3 skip:37
> ro-hsw-i3-4010u total:209 pass:186 dwarn:0 dfail:0 fail:0 skip:23
> ro-hsw-i7-4770r total:102 pass:82 dwarn:0 dfail:0 fail:0 skip:19
> ro-ilk1-i5-650 total:204 pass:146 dwarn:0 dfail:0 fail:1 skip:57
> ro-ivb2-i7-3770 total:102 pass:47 dwarn:32 dfail:0 fail:0 skip:22
> ro-skl-i7-6700hq total:204 pass:172 dwarn:9 dfail:1 fail:0 skip:22
> fi-bdw-i7-5557u failed to connect after reboot
> fi-bsw-n3050 failed to connect after reboot
> ro-bdw-i7-5557U failed to connect after reboot
> ro-ilk-i7-620lm failed to connect after reboot
> ro-ivb-i7-3770 failed to connect after reboot
> ro-snb-i7-2620M failed to connect after reboot
>
> Results at /archive/results/CI_IGT_test/RO_Patchwork_1068/
>
> 877a1d2 drm-intel-nightly: 2016y-05m-31d-14h-57m-44s UTC integration manifest
> 8238bdb drm/i915: Move psr.link_standby setup to intel_psr_match_conditions()
> 58ee76a drm/i915: Ask the sink whether training is required when exiting PSR main-link off mode
> 5fe07aa drm/i915/psr: Skip aux handeshake if the vbt tells us to
> 6e98304 drm/i915: Check PSR setup time vs. vblank length
> 2a67384 drm/dp: Add drm_dp_psr_need_train_on_exit()
> 3ad03bc drm/dp: Add drm_dp_psr_setup_time()
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 0/6] drm/i915: Remaining PSR fixes
2016-05-31 15:50 [PATCH 0/6] drm/i915: Remaining PSR fixes ville.syrjala
` (6 preceding siblings ...)
2016-05-31 16:17 ` ✗ Ro.CI.BAT: failure for drm/i915: Remaining PSR fixes Patchwork
@ 2016-05-31 19:07 ` Daniel Vetter
2016-05-31 19:16 ` Ville Syrjälä
2016-06-08 14:34 ` ✗ Ro.CI.BAT: warning for " Patchwork
2016-06-10 15:20 ` Patchwork
9 siblings, 1 reply; 17+ messages in thread
From: Daniel Vetter @ 2016-05-31 19:07 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx, dri-devel
On Tue, May 31, 2016 at 06:50:24PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Here's a repost of my PSR fixes, and one straggler from Daniel.
>
> One interesting thing I noticed is that my SKL actually hits the PSR setup
> time vs. vblank length check, so after these patches that machine won't
> actually use PSR. The panel does support a lower refresh rate timing as well
> though which doesn't suffer from this limitation, so I hacked the code to
> use that mode instead, and PSR did seem to work without problems. With the
> original mode I had some screen stalls while running xonotic, which I'm
> going to assume were due to the setup time exceeding the safe limit.
Hm, is there a way to make that hack less hackish and merge it? Selecting
a mode with slightly different timings (but same resolution ofc) to make
PSR possible seems like a very sensible idea. Or is this a 60Hz vs 30Hz
kind of thing?
Scrolled through patches, still lgtm.
-Daniel
>
> I also hooked up the PSR interrupts for BDW+ and pushed the patches to [1],
> but I'm not including those patches here since the PSR interrupts don't
> seem to gain us anything useful in practice.
>
> [1] git://github.com/vsyrjala/linux.git psr_interrupts
>
> Daniel Vetter (1):
> drm/i915/psr: Skip aux handeshake if the vbt tells us to
>
> Ville Syrjälä (5):
> drm/dp: Add drm_dp_psr_setup_time()
> drm/dp: Add drm_dp_psr_need_train_on_exit()
> drm/i915: Check PSR setup time vs. vblank length
> drm/i915: Ask the sink whether training is required when exiting PSR
> main-link off mode
> drm/i915: Move psr.link_standby setup to intel_psr_match_conditions()
>
> drivers/gpu/drm/drm_dp_helper.c | 46 ++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> drivers/gpu/drm/i915/intel_psr.c | 64 +++++++++++++++++++++++++------------
> drivers/gpu/drm/i915/intel_sprite.c | 6 ++--
> include/drm/drm_dp_helper.h | 3 ++
> 5 files changed, 97 insertions(+), 24 deletions(-)
>
> --
> 2.7.4
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 0/6] drm/i915: Remaining PSR fixes
2016-05-31 19:07 ` [PATCH 0/6] " Daniel Vetter
@ 2016-05-31 19:16 ` Ville Syrjälä
0 siblings, 0 replies; 17+ messages in thread
From: Ville Syrjälä @ 2016-05-31 19:16 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx, dri-devel
On Tue, May 31, 2016 at 09:07:49PM +0200, Daniel Vetter wrote:
> On Tue, May 31, 2016 at 06:50:24PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Here's a repost of my PSR fixes, and one straggler from Daniel.
> >
> > One interesting thing I noticed is that my SKL actually hits the PSR setup
> > time vs. vblank length check, so after these patches that machine won't
> > actually use PSR. The panel does support a lower refresh rate timing as well
> > though which doesn't suffer from this limitation, so I hacked the code to
> > use that mode instead, and PSR did seem to work without problems. With the
> > original mode I had some screen stalls while running xonotic, which I'm
> > going to assume were due to the setup time exceeding the safe limit.
>
> Hm, is there a way to make that hack less hackish and merge it? Selecting
> a mode with slightly different timings (but same resolution ofc) to make
> PSR possible seems like a very sensible idea. Or is this a 60Hz vs 30Hz
> kind of thing?
60 vs. 48 in this case, so might not want it as a default. However
this is not a production machine anyway, so I wouldn't worry about
it too much unless someone comes across a real machine with a
similar setup.
>
> Scrolled through patches, still lgtm.
> -Daniel
>
> >
> > I also hooked up the PSR interrupts for BDW+ and pushed the patches to [1],
> > but I'm not including those patches here since the PSR interrupts don't
> > seem to gain us anything useful in practice.
> >
> > [1] git://github.com/vsyrjala/linux.git psr_interrupts
> >
> > Daniel Vetter (1):
> > drm/i915/psr: Skip aux handeshake if the vbt tells us to
> >
> > Ville Syrjälä (5):
> > drm/dp: Add drm_dp_psr_setup_time()
> > drm/dp: Add drm_dp_psr_need_train_on_exit()
> > drm/i915: Check PSR setup time vs. vblank length
> > drm/i915: Ask the sink whether training is required when exiting PSR
> > main-link off mode
> > drm/i915: Move psr.link_standby setup to intel_psr_match_conditions()
> >
> > drivers/gpu/drm/drm_dp_helper.c | 46 ++++++++++++++++++++++++++
> > drivers/gpu/drm/i915/intel_drv.h | 2 ++
> > drivers/gpu/drm/i915/intel_psr.c | 64 +++++++++++++++++++++++++------------
> > drivers/gpu/drm/i915/intel_sprite.c | 6 ++--
> > include/drm/drm_dp_helper.h | 3 ++
> > 5 files changed, 97 insertions(+), 24 deletions(-)
> >
> > --
> > 2.7.4
> >
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* ✗ Ro.CI.BAT: warning for drm/i915: Remaining PSR fixes
2016-05-31 15:50 [PATCH 0/6] drm/i915: Remaining PSR fixes ville.syrjala
` (7 preceding siblings ...)
2016-05-31 19:07 ` [PATCH 0/6] " Daniel Vetter
@ 2016-06-08 14:34 ` Patchwork
2016-06-10 15:20 ` Patchwork
9 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2016-06-08 14:34 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Remaining PSR fixes
URL : https://patchwork.freedesktop.org/series/8046/
State : warning
== Summary ==
Series 8046v1 drm/i915: Remaining PSR fixes
http://patchwork.freedesktop.org/api/1.0/series/8046/revisions/1/mbox
Test kms_sink_crc_basic:
pass -> SKIP (ro-bdw-i7-5600u)
fi-bdw-i7-5557u total:102 pass:93 dwarn:0 dfail:0 fail:0 skip:8
fi-skl-i5-6260u total:209 pass:198 dwarn:0 dfail:0 fail:0 skip:11
fi-skl-i7-6700k total:209 pass:184 dwarn:0 dfail:0 fail:0 skip:25
fi-snb-i7-2600 total:209 pass:170 dwarn:0 dfail:0 fail:0 skip:39
ro-bdw-i5-5250u total:183 pass:172 dwarn:0 dfail:0 fail:0 skip:10
ro-bdw-i7-5600u total:183 pass:153 dwarn:0 dfail:0 fail:0 skip:29
ro-bsw-n3050 total:208 pass:167 dwarn:0 dfail:0 fail:2 skip:39
ro-byt-n2820 total:208 pass:168 dwarn:0 dfail:0 fail:3 skip:37
ro-hsw-i3-4010u total:208 pass:185 dwarn:0 dfail:0 fail:0 skip:23
ro-hsw-i7-4770r total:183 pass:161 dwarn:0 dfail:0 fail:0 skip:21
ro-ilk1-i5-650 total:204 pass:146 dwarn:0 dfail:0 fail:1 skip:57
ro-ivb-i7-3770 total:183 pass:154 dwarn:0 dfail:0 fail:0 skip:28
ro-ivb2-i7-3770 total:183 pass:158 dwarn:0 dfail:0 fail:0 skip:24
ro-snb-i7-2620M total:183 pass:151 dwarn:0 dfail:0 fail:0 skip:31
fi-hsw-i7-4770k failed to connect after reboot
ro-bdw-i7-5557U failed to connect after reboot
Results at /archive/results/CI_IGT_test/RO_Patchwork_1140/
131a54b drm-intel-nightly: 2016y-06m-07d-19h-46m-33s UTC integration manifest
7308d82 drm/i915: Move psr.link_standby setup to intel_psr_match_conditions()
1ab6761 drm/i915: Ask the sink whether training is required when exiting PSR main-link off mode
21ec657 drm/i915/psr: Skip aux handeshake if the vbt tells us to
0c49a1e drm/i915: Check PSR setup time vs. vblank length
fedc8d8 drm/dp: Add drm_dp_psr_need_train_on_exit()
a3c27c1 drm/dp: Add drm_dp_psr_setup_time()
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* ✗ Ro.CI.BAT: warning for drm/i915: Remaining PSR fixes
2016-05-31 15:50 [PATCH 0/6] drm/i915: Remaining PSR fixes ville.syrjala
` (8 preceding siblings ...)
2016-06-08 14:34 ` ✗ Ro.CI.BAT: warning for " Patchwork
@ 2016-06-10 15:20 ` Patchwork
9 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2016-06-10 15:20 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Remaining PSR fixes
URL : https://patchwork.freedesktop.org/series/8046/
State : warning
== Summary ==
Series 8046v1 drm/i915: Remaining PSR fixes
http://patchwork.freedesktop.org/api/1.0/series/8046/revisions/1/mbox
Test drv_module_reload_basic:
skip -> PASS (ro-ivb-i7-3770)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b:
pass -> SKIP (fi-skl-i5-6260u)
Subgroup read-crc-pipe-b-frame-sequence:
skip -> PASS (fi-skl-i5-6260u)
Test kms_sink_crc_basic:
pass -> SKIP (ro-bdw-i7-5600u)
fi-bdw-i7-5557u total:213 pass:201 dwarn:0 dfail:0 fail:0 skip:12
fi-skl-i5-6260u total:213 pass:201 dwarn:0 dfail:0 fail:0 skip:12
fi-skl-i7-6700k total:213 pass:188 dwarn:0 dfail:0 fail:0 skip:25
fi-snb-i7-2600 total:213 pass:174 dwarn:0 dfail:0 fail:0 skip:39
ro-bdw-i5-5250u total:213 pass:197 dwarn:1 dfail:0 fail:0 skip:15
ro-bdw-i7-5557U total:213 pass:197 dwarn:1 dfail:0 fail:0 skip:15
ro-bdw-i7-5600u total:213 pass:184 dwarn:0 dfail:0 fail:0 skip:29
ro-bsw-n3050 total:213 pass:172 dwarn:0 dfail:0 fail:2 skip:39
ro-hsw-i3-4010u total:213 pass:190 dwarn:0 dfail:0 fail:0 skip:23
ro-hsw-i7-4770r total:213 pass:190 dwarn:0 dfail:0 fail:0 skip:23
ro-ilk-i7-620lm total:213 pass:150 dwarn:0 dfail:0 fail:1 skip:62
ro-ilk1-i5-650 total:208 pass:150 dwarn:0 dfail:0 fail:1 skip:57
ro-ivb-i7-3770 total:213 pass:181 dwarn:0 dfail:0 fail:0 skip:32
ro-ivb2-i7-3770 total:213 pass:185 dwarn:0 dfail:0 fail:0 skip:28
ro-skl3-i5-6260u total:213 pass:201 dwarn:1 dfail:0 fail:0 skip:11
ro-snb-i7-2620M total:213 pass:174 dwarn:0 dfail:0 fail:1 skip:38
fi-hsw-i7-4770k failed to connect after reboot
ro-byt-n2820 failed to connect after reboot
Results at /archive/results/CI_IGT_test/RO_Patchwork_1159/
1723c64 drm-intel-nightly: 2016y-06m-10d-14h-36m-05s UTC integration manifest
77cd5c6 drm/i915: Move psr.link_standby setup to intel_psr_match_conditions()
c16c581 drm/i915: Ask the sink whether training is required when exiting PSR main-link off mode
1bb3ecf drm/i915/psr: Skip aux handeshake if the vbt tells us to
6e94f00 drm/i915: Check PSR setup time vs. vblank length
1b495b8 drm/dp: Add drm_dp_psr_need_train_on_exit()
4ab36fd drm/dp: Add drm_dp_psr_setup_time()
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