[PATCH v3 0/6] Accommodate multiple GuC submission clients

[PATCH v3 0/6] Accommodate multiple GuC submission clients

[Dave Gordon]

This patchset is essentially preparation for using multiple clients
for GuC submission (probably one per engine, to reduce contention).
We accommodate association of each client with one or more engines,
although for now we still use only one client for all engines.
Switching over to one client per engine is left for a subsequent
patch after the next release of GuC firmware is available.

Dave Gordon (6):
  drm/i915/guc: doorbell reset should avoid used doorbells
  drm/i915/guc: refactor guc_init_doorbell_hw()
  drm/i915/guc: add engine mask to GuC client & pass to GuC
  drm/i915/guc: use for_each_engine_id() where appropriate
  drm/i915/guc: re-optimise i915_guc_client layout
  drm/i915/guc: re-enable GuC loading and submission by default

 drivers/gpu/drm/i915/i915_debugfs.c        | 19 +++----
 drivers/gpu/drm/i915/i915_guc_submission.c | 80 ++++++++++++++++++------------
 drivers/gpu/drm/i915/i915_params.c         |  4 +-
 drivers/gpu/drm/i915/intel_guc.h           |  9 ++--
 4 files changed, 65 insertions(+), 47 deletions(-)

-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 1/6] drm/i915/guc: doorbell reset should avoid used doorbells

[Dave Gordon]

guc_init_doorbell_hw() borrows the (currently single) GuC client to use
in reinitialising ALL the doorbell registers (as the hardware doesn't
reset them when the GuC is reset). As a prerequisite for accommodating
multiple clients, it should only reset doorbells that are supposed to be
disabled, avoiding those that are marked as in use by any client.

Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 03a5cef..d5db0d1 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -697,7 +697,7 @@ static void gem_release_guc_obj(struct drm_i915_gem_object *obj)
 }
 
 /*
- * Borrow the first client to set up & tear down every doorbell
+ * Borrow the first client to set up & tear down each unused doorbell
  * in turn, to ensure that all doorbell h/w is (re)initialised.
  */
 static void guc_init_doorbell_hw(struct intel_guc *guc)
@@ -713,6 +713,9 @@ static void guc_init_doorbell_hw(struct intel_guc *guc)
 		i915_reg_t drbreg = GEN8_DRBREGL(i);
 		u32 value = I915_READ(drbreg);
 
+		if (test_bit(i, guc->doorbell_bitmap))
+			continue;
+
 		err = guc_update_doorbell_id(guc, client, i);
 
 		/* Report update failure or unexpectedly active doorbell */
@@ -731,6 +734,9 @@ static void guc_init_doorbell_hw(struct intel_guc *guc)
 		i915_reg_t drbreg = GEN8_DRBREGL(i);
 		u32 value = I915_READ(drbreg);
 
+		if (test_bit(i, guc->doorbell_bitmap))
+			continue;
+
 		if (i != db_id && (value & GUC_DOORBELL_ENABLED))
 			DRM_DEBUG_DRIVER("Doorbell %d (reg 0x%x) finally 0x%x\n",
 					  i, drbreg.reg, value);
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 2/6] drm/i915/guc: refactor guc_init_doorbell_hw()

[Dave Gordon]

We have essentially the same code in each of two different
loops, so we can refactor it into a little helper function.

This also reduces the amount of work done during startup,
as we now only reprogram h/w found to be in a state other
than that expected, and so avoid the overhead of setting
doorbell registers to the state they're already in.

Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 54 +++++++++++++++++-------------
 1 file changed, 30 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index d5db0d1..af5c4cf 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -696,32 +696,47 @@ static void gem_release_guc_obj(struct drm_i915_gem_object *obj)
 	kfree(client);
 }
 
+/* Check that a doorbell register is in the expected state */
+static bool guc_doorbell_check(struct intel_guc *guc, uint16_t db_id)
+{
+	struct drm_i915_private *dev_priv = guc_to_i915(guc);
+	i915_reg_t drbreg = GEN8_DRBREGL(db_id);
+	uint32_t value = I915_READ(drbreg);
+	bool enabled = (value & GUC_DOORBELL_ENABLED) != 0;
+	bool expected = test_bit(db_id, guc->doorbell_bitmap);
+
+	if (enabled == expected)
+		return true;
+
+	DRM_DEBUG_DRIVER("Doorbell %d (reg 0x%x) 0x%x, should be %s\n",
+			 db_id, drbreg.reg, value,
+			 expected ? "active" : "inactive");
+
+	return false;
+}
+
 /*
  * Borrow the first client to set up & tear down each unused doorbell
  * in turn, to ensure that all doorbell h/w is (re)initialised.
  */
 static void guc_init_doorbell_hw(struct intel_guc *guc)
 {
-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
 	struct i915_guc_client *client = guc->execbuf_client;
-	uint16_t db_id, i;
-	int err;
+	uint16_t db_id;
+	int i, err;
 
+	/* Save client's original doorbell selection */
 	db_id = client->doorbell_id;
 
 	for (i = 0; i < GUC_MAX_DOORBELLS; ++i) {
-		i915_reg_t drbreg = GEN8_DRBREGL(i);
-		u32 value = I915_READ(drbreg);
-
-		if (test_bit(i, guc->doorbell_bitmap))
+		/* Skip if doorbell is OK */
+		if (guc_doorbell_check(guc, i))
 			continue;
 
 		err = guc_update_doorbell_id(guc, client, i);
-
-		/* Report update failure or unexpectedly active doorbell */
-		if (err || (i != db_id && (value & GUC_DOORBELL_ENABLED)))
-			DRM_DEBUG_DRIVER("Doorbell %d (reg 0x%x) was 0x%x, err %d\n",
-					  i, drbreg.reg, value, err);
+		if (err)
+			DRM_DEBUG_DRIVER("Doorbell %d update failed, err %d\n",
+					i, err);
 	}
 
 	/* Restore to original value */
@@ -730,18 +745,9 @@ static void guc_init_doorbell_hw(struct intel_guc *guc)
 		DRM_ERROR("Failed to restore doorbell to %d, err %d\n",
 			db_id, err);
 
-	for (i = 0; i < GUC_MAX_DOORBELLS; ++i) {
-		i915_reg_t drbreg = GEN8_DRBREGL(i);
-		u32 value = I915_READ(drbreg);
-
-		if (test_bit(i, guc->doorbell_bitmap))
-			continue;
-
-		if (i != db_id && (value & GUC_DOORBELL_ENABLED))
-			DRM_DEBUG_DRIVER("Doorbell %d (reg 0x%x) finally 0x%x\n",
-					  i, drbreg.reg, value);
-
-	}
+	/* Read back & verify all doorbell registers */
+	for (i = 0; i < GUC_MAX_DOORBELLS; ++i)
+		(void)guc_doorbell_check(guc, i);
 }
 
 /**
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 3/6] drm/i915/guc: add engine mask to GuC client & pass to GuC

[Dave Gordon]

The Context Descriptor passed by the kernel to the GuC contains a field
specifying which engine(s) the context will use. Historically, this was
always set to "all of them", but if we had a separate client for each
engine, we could be more precise, and set only the bit for the engine
that the client was associated with. So this patch enables this usage,
in preparation for having multiple clients, though at this point there
is still only a single client used for all supported engines.

Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 15 ++++++++++-----
 drivers/gpu/drm/i915/intel_guc.h           |  3 ++-
 2 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index af5c4cf..405e445 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -340,7 +340,7 @@ static void guc_init_ctx_desc(struct intel_guc *guc,
 	desc.priority = client->priority;
 	desc.db_id = client->doorbell_id;
 
-	for_each_engine(engine, dev_priv) {
+	for_each_engine_masked(engine, dev_priv, client->engines) {
 		struct intel_context *ce = &ctx->engine[engine->id];
 		struct guc_execlist_context *lrc = &desc.lrc[engine->guc_id];
 		struct drm_i915_gem_object *obj;
@@ -374,6 +374,8 @@ static void guc_init_ctx_desc(struct intel_guc *guc,
 		desc.engines_used |= (1 << engine->guc_id);
 	}
 
+	DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n",
+			client->engines, desc.engines_used);
 	WARN_ON(desc.engines_used == 0);
 
 	/*
@@ -764,6 +766,7 @@ static void guc_init_doorbell_hw(struct intel_guc *guc)
  */
 static struct i915_guc_client *
 guc_client_alloc(struct drm_i915_private *dev_priv,
+		 uint32_t engines,
 		 uint32_t priority,
 		 struct i915_gem_context *ctx)
 {
@@ -776,10 +779,11 @@ static void guc_init_doorbell_hw(struct intel_guc *guc)
 	if (!client)
 		return NULL;
 
-	client->doorbell_id = GUC_INVALID_DOORBELL_ID;
-	client->priority = priority;
 	client->owner = ctx;
 	client->guc = guc;
+	client->engines = engines;
+	client->priority = priority;
+	client->doorbell_id = GUC_INVALID_DOORBELL_ID;
 
 	client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0,
 			GUC_MAX_GPU_CONTEXTS, GFP_KERNEL);
@@ -821,8 +825,8 @@ static void guc_init_doorbell_hw(struct intel_guc *guc)
 	if (guc_init_doorbell(guc, client, db_id))
 		goto err;
 
-	DRM_DEBUG_DRIVER("new priority %u client %p: ctx_index %u\n",
-		priority, client, client->ctx_index);
+	DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: ctx_index %u\n",
+		priority, client, client->engines, client->ctx_index);
 	DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%x\n",
 		client->doorbell_id, client->doorbell_offset);
 
@@ -1006,6 +1010,7 @@ int i915_guc_submission_enable(struct drm_i915_private *dev_priv)
 
 	/* client for execbuf submission */
 	client = guc_client_alloc(dev_priv,
+				  INTEL_INFO(dev_priv)->ring_mask,
 				  GUC_CTX_PRIORITY_KMD_NORMAL,
 				  dev_priv->kernel_context);
 	if (!client) {
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 623cf26..e57661f 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -67,6 +67,8 @@ struct i915_guc_client {
 	void *client_base;		/* first page (only) of above	*/
 	struct i915_gem_context *owner;
 	struct intel_guc *guc;
+
+	uint32_t engines;		/* bitmap of (host) engine ids	*/
 	uint32_t priority;
 	uint32_t ctx_index;
 
@@ -79,7 +81,6 @@ struct i915_guc_client {
 	uint32_t wq_offset;
 	uint32_t wq_size;
 	uint32_t wq_tail;
-	uint32_t unused;		/* Was 'wq_head'		*/
 
 	uint32_t no_wq_space;
 	uint32_t q_fail;		/* No longer used		*/
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 4/6] drm/i915/guc: use for_each_engine_id() where appropriate

[Dave Gordon]

Now that host structures are indexed by host engine-id rather than
guc_id, we can usefully convert some for_each_engine() loops to use
for_each_engine_id() and avoid multiple dereferences of engine->id.

Also a few related tweaks to cache structure members locally wherever
they're used more than once or twice, hopefully eliminating memory
references.

Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c        | 18 ++++++++++--------
 drivers/gpu/drm/i915/i915_guc_submission.c | 13 +++++++------
 2 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index f62285c..15c5b4e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2547,6 +2547,7 @@ static void i915_guc_client_info(struct seq_file *m,
 				 struct i915_guc_client *client)
 {
 	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
 	uint64_t tot = 0;
 
 	seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
@@ -2561,11 +2562,11 @@ static void i915_guc_client_info(struct seq_file *m,
 	seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
 	seq_printf(m, "\tLast submission result: %d\n", client->retcode);
 
-	for_each_engine(engine, dev_priv) {
+	for_each_engine_id(engine, dev_priv, id) {
+		u64 submissions = client->submissions[id];
+		tot += submissions;
 		seq_printf(m, "\tSubmissions: %llu %s\n",
-				client->submissions[engine->id],
-				engine->name);
-		tot += client->submissions[engine->id];
+				submissions, engine->name);
 	}
 	seq_printf(m, "\tTotal: %llu\n", tot);
 }
@@ -2578,6 +2579,7 @@ static int i915_guc_info(struct seq_file *m, void *data)
 	struct intel_guc guc;
 	struct i915_guc_client client = {};
 	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
 	u64 total = 0;
 
 	if (!HAS_GUC_SCHED(dev_priv))
@@ -2604,11 +2606,11 @@ static int i915_guc_info(struct seq_file *m, void *data)
 	seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
 
 	seq_printf(m, "\nGuC submissions:\n");
-	for_each_engine(engine, dev_priv) {
+	for_each_engine_id(engine, dev_priv, id) {
+		u64 submissions = guc.submissions[id];
+		total += submissions;
 		seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
-			engine->name, guc.submissions[engine->id],
-			guc.last_seqno[engine->id]);
-		total += guc.submissions[engine->id];
+			engine->name, submissions, guc.last_seqno[id]);
 	}
 	seq_printf(m, "\t%s: %llu\n", "Total", total);
 
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 405e445..6831321 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -342,7 +342,8 @@ static void guc_init_ctx_desc(struct intel_guc *guc,
 
 	for_each_engine_masked(engine, dev_priv, client->engines) {
 		struct intel_context *ce = &ctx->engine[engine->id];
-		struct guc_execlist_context *lrc = &desc.lrc[engine->guc_id];
+		uint32_t guc_engine_id = engine->guc_id;
+		struct guc_execlist_context *lrc = &desc.lrc[guc_engine_id];
 		struct drm_i915_gem_object *obj;
 
 		/* TODO: We have a design issue to be solved here. Only when we
@@ -361,7 +362,7 @@ static void guc_init_ctx_desc(struct intel_guc *guc,
 		gfx_addr = i915_gem_obj_ggtt_offset(ce->state);
 		lrc->ring_lcra = gfx_addr + LRC_STATE_PN * PAGE_SIZE;
 		lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) |
-				(engine->guc_id << GUC_ELC_ENGINE_OFFSET);
+				(guc_engine_id << GUC_ELC_ENGINE_OFFSET);
 
 		obj = ce->ring->obj;
 		gfx_addr = i915_gem_obj_ggtt_offset(obj);
@@ -371,7 +372,7 @@ static void guc_init_ctx_desc(struct intel_guc *guc,
 		lrc->ring_next_free_location = gfx_addr;
 		lrc->ring_current_tail_pointer_value = 0;
 
-		desc.engines_used |= (1 << engine->guc_id);
+		desc.engines_used |= (1 << guc_engine_id);
 	}
 
 	DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n",
@@ -459,6 +460,7 @@ static void guc_add_workqueue_item(struct i915_guc_client *gc,
 	/* wqi_len is in DWords, and does not include the one-word header */
 	const size_t wqi_size = sizeof(struct guc_wq_item);
 	const u32 wqi_len = wqi_size/sizeof(u32) - 1;
+	struct intel_engine_cs *engine = rq->engine;
 	struct guc_process_desc *desc;
 	struct guc_wq_item *wqi;
 	void *base;
@@ -500,12 +502,11 @@ static void guc_add_workqueue_item(struct i915_guc_client *gc,
 	/* Now fill in the 4-word work queue item */
 	wqi->header = WQ_TYPE_INORDER |
 			(wqi_len << WQ_LEN_SHIFT) |
-			(rq->engine->guc_id << WQ_TARGET_SHIFT) |
+			(engine->guc_id << WQ_TARGET_SHIFT) |
 			WQ_NO_WCFLUSH_WAIT;
 
 	/* The GuC wants only the low-order word of the context descriptor */
-	wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx,
-							     rq->engine);
+	wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, engine);
 
 	wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT;
 	wqi->fence_id = rq->fence.seqno;
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 5/6] drm/i915/guc: re-optimise i915_guc_client layout

[Dave Gordon]

As we're tweaking the GuC-related code in debugfs, we can
drop the no-longer-used 'q_fail' and repack the structure.

Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 1 -
 drivers/gpu/drm/i915/intel_guc.h    | 6 ++----
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 15c5b4e..9170854 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2558,7 +2558,6 @@ static void i915_guc_client_info(struct seq_file *m,
 		client->wq_size, client->wq_offset, client->wq_tail);
 
 	seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
-	seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
 	seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
 	seq_printf(m, "\tLast submission result: %d\n", client->retcode);
 
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index e57661f..26f3d9c 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -71,19 +71,17 @@ struct i915_guc_client {
 	uint32_t engines;		/* bitmap of (host) engine ids	*/
 	uint32_t priority;
 	uint32_t ctx_index;
-
 	uint32_t proc_desc_offset;
+
 	uint32_t doorbell_offset;
 	uint32_t cookie;
 	uint16_t doorbell_id;
-	uint16_t padding;		/* Maintain alignment		*/
+	uint16_t padding[3];		/* Maintain alignment		*/
 
 	uint32_t wq_offset;
 	uint32_t wq_size;
 	uint32_t wq_tail;
-
 	uint32_t no_wq_space;
-	uint32_t q_fail;		/* No longer used		*/
 	uint32_t b_fail;
 	int retcode;
 
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v3 6/6] NOMERGE: re-enable GuC loading and submission by default

[Dave Gordon]

Re-enables GuC loading and submission by default on suitable
platforms, since it's Intel's Plan of Record that GuC submission
shall be used where available.

Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
---
 drivers/gpu/drm/i915/i915_params.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index b6e404c..682d0ec 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -54,8 +54,8 @@ struct i915_params i915 __read_mostly = {
 	.verbose_state_checks = 1,
 	.nuclear_pageflip = 0,
 	.edp_vswing = 0,
-	.enable_guc_loading = 0,
-	.enable_guc_submission = 0,
+	.enable_guc_loading = -1,
+	.enable_guc_submission = -1,
 	.guc_log_level = -1,
 	.enable_dp_mst = true,
 	.inject_load_failure = 0,
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Ro.CI.BAT: failure for Accommodate multiple GuC submission clients

[Patchwork]

== Series Details ==

Series: Accommodate multiple GuC submission clients
URL   : https://patchwork.freedesktop.org/series/10847/
State : failure

== Summary ==

Series 10847v1 Accommodate multiple GuC submission clients
http://patchwork.freedesktop.org/api/1.0/series/10847/revisions/1/mbox

Test drv_module_reload_basic:
                pass       -> DMESG-WARN (ro-skl3-i5-6260u)
Test kms_flip:
        Subgroup basic-flip-vs-wf_vblank:
                pass       -> FAIL       (ro-byt-n2820)

fi-hsw-i7-4770k  total:107  pass:91   dwarn:0   dfail:0   fail:0   skip:15 
fi-kbl-qkkr      total:107  pass:83   dwarn:0   dfail:0   fail:0   skip:23 
fi-skl-i5-6260u  total:107  pass:98   dwarn:0   dfail:0   fail:0   skip:8  
fi-skl-i7-6700k  total:107  pass:84   dwarn:0   dfail:0   fail:0   skip:22 
fi-snb-i7-2600   total:107  pass:77   dwarn:0   dfail:0   fail:0   skip:29 
ro-bdw-i5-5250u  total:107  pass:97   dwarn:0   dfail:0   fail:0   skip:9  
ro-bdw-i7-5600u  total:107  pass:79   dwarn:0   dfail:0   fail:0   skip:27 
ro-bsw-n3050     total:240  pass:194  dwarn:0   dfail:0   fail:4   skip:42 
ro-byt-n2820     total:240  pass:196  dwarn:0   dfail:0   fail:4   skip:40 
ro-hsw-i3-4010u  total:107  pass:87   dwarn:0   dfail:0   fail:0   skip:19 
ro-ilk1-i5-650   total:235  pass:173  dwarn:0   dfail:0   fail:2   skip:60 
ro-ivb-i7-3770   total:107  pass:80   dwarn:0   dfail:0   fail:0   skip:26 
ro-skl3-i5-6260u total:107  pass:97   dwarn:1   dfail:0   fail:0   skip:8  
ro-bdw-i7-5557U failed to connect after reboot
ro-hsw-i7-4770r failed to connect after reboot
ro-ivb2-i7-3770 failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1785/

e220d47 drm-intel-nightly: 2016y-08m-09d-09h-18m-12s UTC integration manifest
f93075d NOMERGE: re-enable GuC loading and submission by default
9fba995 drm/i915/guc: re-optimise i915_guc_client layout
64c9f76 drm/i915/guc: use for_each_engine_id() where appropriate
550dfa4 drm/i915/guc: add engine mask to GuC client & pass to GuC
fa78cb8 drm/i915/guc: refactor guc_init_doorbell_hw()
b194fc6 drm/i915/guc: doorbell reset should avoid used doorbells

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: ✗ Ro.CI.BAT: failure for Accommodate multiple GuC submission clients

[Dave Gordon]

On 09/08/16 15:55, Patchwork wrote:
> == Series Details ==
>
> Series: Accommodate multiple GuC submission clients
> URL   : https://patchwork.freedesktop.org/series/10847/
> State : failure
>
> == Summary ==
>
> Series 10847v1 Accommodate multiple GuC submission clients
> http://patchwork.freedesktop.org/api/1.0/series/10847/revisions/1/mbox
>
> Test drv_module_reload_basic:
>                 pass       -> DMESG-WARN (ro-skl3-i5-6260u)

This machine is missing (the correct version of) the GuC firmware!

> Test kms_flip:
>         Subgroup basic-flip-vs-wf_vblank:
>                 pass       -> FAIL       (ro-byt-n2820)

Bug 95236 - [BAT various] kms_flip fails with "inter-flip ts jitter: 0s, 
183334usec" or similar time around 180msec

.Dave.

> fi-hsw-i7-4770k  total:107  pass:91   dwarn:0   dfail:0   fail:0   skip:15
> fi-kbl-qkkr      total:107  pass:83   dwarn:0   dfail:0   fail:0   skip:23
> fi-skl-i5-6260u  total:107  pass:98   dwarn:0   dfail:0   fail:0   skip:8
> fi-skl-i7-6700k  total:107  pass:84   dwarn:0   dfail:0   fail:0   skip:22
> fi-snb-i7-2600   total:107  pass:77   dwarn:0   dfail:0   fail:0   skip:29
> ro-bdw-i5-5250u  total:107  pass:97   dwarn:0   dfail:0   fail:0   skip:9
> ro-bdw-i7-5600u  total:107  pass:79   dwarn:0   dfail:0   fail:0   skip:27
> ro-bsw-n3050     total:240  pass:194  dwarn:0   dfail:0   fail:4   skip:42
> ro-byt-n2820     total:240  pass:196  dwarn:0   dfail:0   fail:4   skip:40
> ro-hsw-i3-4010u  total:107  pass:87   dwarn:0   dfail:0   fail:0   skip:19
> ro-ilk1-i5-650   total:235  pass:173  dwarn:0   dfail:0   fail:2   skip:60
> ro-ivb-i7-3770   total:107  pass:80   dwarn:0   dfail:0   fail:0   skip:26
> ro-skl3-i5-6260u total:107  pass:97   dwarn:1   dfail:0   fail:0   skip:8
> ro-bdw-i7-5557U failed to connect after reboot
> ro-hsw-i7-4770r failed to connect after reboot
> ro-ivb2-i7-3770 failed to connect after reboot
>
> Results at /archive/results/CI_IGT_test/RO_Patchwork_1785/
>
> e220d47 drm-intel-nightly: 2016y-08m-09d-09h-18m-12s UTC integration manifest
> f93075d NOMERGE: re-enable GuC loading and submission by default
> 9fba995 drm/i915/guc: re-optimise i915_guc_client layout
> 64c9f76 drm/i915/guc: use for_each_engine_id() where appropriate
> 550dfa4 drm/i915/guc: add engine mask to GuC client & pass to GuC
> fa78cb8 drm/i915/guc: refactor guc_init_doorbell_hw()
> b194fc6 drm/i915/guc: doorbell reset should avoid used doorbells
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Ro.CI.BAT: failure for Accommodate multiple GuC submission clients

[Patchwork]

== Series Details ==

Series: Accommodate multiple GuC submission clients
URL   : https://patchwork.freedesktop.org/series/10847/
State : failure

== Summary ==

Series 10847v1 Accommodate multiple GuC submission clients
http://patchwork.freedesktop.org/api/1.0/series/10847/revisions/1/mbox

Test drv_module_reload_basic:
                pass       -> DMESG-WARN (ro-skl3-i5-6260u)
                pass       -> SKIP       (fi-skl-i5-6260u)
Test kms_cursor_legacy:
        Subgroup basic-cursor-vs-flip-varying-size:
                fail       -> PASS       (ro-ilk1-i5-650)
        Subgroup basic-flip-vs-cursor-legacy:
                pass       -> FAIL       (ro-hsw-i7-4770r)
                pass       -> FAIL       (ro-byt-n2820)
                pass       -> FAIL       (ro-skl3-i5-6260u)
        Subgroup basic-flip-vs-cursor-varying-size:
                pass       -> FAIL       (ro-skl3-i5-6260u)
Test kms_pipe_crc_basic:
        Subgroup read-crc-pipe-c-frame-sequence:
                fail       -> PASS       (ro-ivb-i7-3770)
        Subgroup suspend-read-crc-pipe-a:
                incomplete -> PASS       (fi-hsw-i7-4770k)
                skip       -> DMESG-WARN (ro-bdw-i5-5250u)
        Subgroup suspend-read-crc-pipe-b:
                skip       -> DMESG-WARN (ro-bdw-i5-5250u)
        Subgroup suspend-read-crc-pipe-c:
                dmesg-warn -> PASS       (ro-bdw-i7-5600u)
                dmesg-warn -> SKIP       (ro-bdw-i5-5250u)

fi-hsw-i7-4770k  total:213  pass:192  dwarn:0   dfail:0   fail:0   skip:20 
fi-kbl-qkkr      total:244  pass:186  dwarn:29  dfail:0   fail:3   skip:26 
fi-skl-i5-6260u  total:244  pass:223  dwarn:4   dfail:0   fail:2   skip:15 
fi-skl-i7-6700k  total:107  pass:84   dwarn:0   dfail:0   fail:0   skip:22 
ro-bdw-i5-5250u  total:240  pass:220  dwarn:3   dfail:0   fail:0   skip:17 
ro-bdw-i7-5557U  total:240  pass:220  dwarn:1   dfail:0   fail:0   skip:19 
ro-bdw-i7-5600u  total:240  pass:207  dwarn:0   dfail:0   fail:1   skip:32 
ro-bsw-n3050     total:240  pass:194  dwarn:0   dfail:0   fail:4   skip:42 
ro-byt-n2820     total:240  pass:197  dwarn:0   dfail:0   fail:3   skip:40 
ro-hsw-i3-4010u  total:240  pass:214  dwarn:0   dfail:0   fail:0   skip:26 
ro-hsw-i7-4770r  total:240  pass:213  dwarn:0   dfail:0   fail:1   skip:26 
ro-ilk1-i5-650   total:235  pass:174  dwarn:0   dfail:0   fail:1   skip:60 
ro-ivb-i7-3770   total:240  pass:205  dwarn:0   dfail:0   fail:0   skip:35 
ro-ivb2-i7-3770  total:240  pass:209  dwarn:0   dfail:0   fail:0   skip:31 
ro-skl3-i5-6260u total:240  pass:221  dwarn:1   dfail:0   fail:4   skip:14 

Results at /archive/results/CI_IGT_test/RO_Patchwork_1795/

d0e3a4b drm-intel-nightly: 2016y-08m-09d-20h-18m-38s UTC integration manifest
e083d03 NOMERGE: re-enable GuC loading and submission by default
8b23a18 drm/i915/guc: re-optimise i915_guc_client layout
60e9f50 drm/i915/guc: use for_each_engine_id() where appropriate
5d72f27 drm/i915/guc: add engine mask to GuC client & pass to GuC
33fc708 drm/i915/guc: refactor guc_init_doorbell_hw()
df6d716 drm/i915/guc: doorbell reset should avoid used doorbells

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: ✗ Ro.CI.BAT: failure for Accommodate multiple GuC submission clients

[Tvrtko Ursulin]

On 09/08/16 16:48, Dave Gordon wrote:
> On 09/08/16 15:55, Patchwork wrote:
>> == Series Details ==
>>
>> Series: Accommodate multiple GuC submission clients
>> URL   : https://patchwork.freedesktop.org/series/10847/
>> State : failure
>>
>> == Summary ==
>>
>> Series 10847v1 Accommodate multiple GuC submission clients
>> http://patchwork.freedesktop.org/api/1.0/series/10847/revisions/1/mbox
>>
>> Test drv_module_reload_basic:
>>                 pass       -> DMESG-WARN (ro-skl3-i5-6260u)
>
> This machine is missing (the correct version of) the GuC firmware!
>
>> Test kms_flip:
>>         Subgroup basic-flip-vs-wf_vblank:
>>                 pass       -> FAIL       (ro-byt-n2820)
>
> Bug 95236 - [BAT various] kms_flip fails with "inter-flip ts jitter: 0s,
> 183334usec" or similar time around 180msec
>
> .Dave.
>
>> fi-hsw-i7-4770k  total:107  pass:91   dwarn:0   dfail:0   fail:0
>> skip:15
>> fi-kbl-qkkr      total:107  pass:83   dwarn:0   dfail:0   fail:0
>> skip:23
>> fi-skl-i5-6260u  total:107  pass:98   dwarn:0   dfail:0   fail:0   skip:8
>> fi-skl-i7-6700k  total:107  pass:84   dwarn:0   dfail:0   fail:0
>> skip:22
>> fi-snb-i7-2600   total:107  pass:77   dwarn:0   dfail:0   fail:0
>> skip:29
>> ro-bdw-i5-5250u  total:107  pass:97   dwarn:0   dfail:0   fail:0   skip:9
>> ro-bdw-i7-5600u  total:107  pass:79   dwarn:0   dfail:0   fail:0
>> skip:27
>> ro-bsw-n3050     total:240  pass:194  dwarn:0   dfail:0   fail:4
>> skip:42
>> ro-byt-n2820     total:240  pass:196  dwarn:0   dfail:0   fail:4
>> skip:40
>> ro-hsw-i3-4010u  total:107  pass:87   dwarn:0   dfail:0   fail:0
>> skip:19
>> ro-ilk1-i5-650   total:235  pass:173  dwarn:0   dfail:0   fail:2
>> skip:60
>> ro-ivb-i7-3770   total:107  pass:80   dwarn:0   dfail:0   fail:0
>> skip:26
>> ro-skl3-i5-6260u total:107  pass:97   dwarn:1   dfail:0   fail:0   skip:8
>> ro-bdw-i7-5557U failed to connect after reboot
>> ro-hsw-i7-4770r failed to connect after reboot
>> ro-ivb2-i7-3770 failed to connect after reboot
>>
>> Results at /archive/results/CI_IGT_test/RO_Patchwork_1785/
>>
>> e220d47 drm-intel-nightly: 2016y-08m-09d-09h-18m-12s UTC integration
>> manifest
>> f93075d NOMERGE: re-enable GuC loading and submission by default
>> 9fba995 drm/i915/guc: re-optimise i915_guc_client layout
>> 64c9f76 drm/i915/guc: use for_each_engine_id() where appropriate
>> 550dfa4 drm/i915/guc: add engine mask to GuC client & pass to GuC
>> fa78cb8 drm/i915/guc: refactor guc_init_doorbell_hw()
>> b194fc6 drm/i915/guc: doorbell reset should avoid used doorbells

Merged to dinq, thanks for the patches and review!

Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx