* [PATCH] drm/i915: Don't mark PCH underrun reporting as diasabled for transcoder B/C on LPT-H
@ 2016-08-05 17:00 ville.syrjala
2016-08-05 20:22 ` Daniel Vetter
2016-08-06 7:16 ` ✗ Ro.CI.BAT: failure for " Patchwork
0 siblings, 2 replies; 5+ messages in thread
From: ville.syrjala @ 2016-08-05 17:00 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Marking PCH transcoder FIFO underrun reporting as disabled for
transcoder B/C on LPT-H will block us from enabling the south error
interrupt. So let's only mark transcoder A underrun reporting as
disabled initially.
This is a little tricky to hit since you need a machine with LPT-H, and
the BIOS must enable either pipe B or C at boot. Then i915 would mark
the "transcoder B/C" underrun reporting as disabled and never enable it
again, meaning south interrupts would never get enabled either. The only
other interrupt in there is actually the poison interrupt which, if we
could ever trigger it, would just result in a little error in dmesg.
Here's the resulting change in SDEIMR on my HSW when I boot it with
multiple displays attached:
- (0x000c4004): 0xf115ffff
+ (0x000c4004): 0xf114ffff
My previous attempt [1] tried to fix this a little differently, but
Daniel requested I do this instead.
[1] https://lists.freedesktop.org/archives/intel-gfx/2015-November/081420.html
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9cbf5431c1e3..888a52c64a26 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15771,6 +15771,13 @@ static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
return false;
}
+static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
+ enum transcoder pch_transcoder)
+{
+ return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
+ (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
+}
+
static void intel_sanitize_crtc(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
@@ -15849,7 +15856,17 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
* worst a fifo underrun happens which also sets this to false.
*/
crtc->cpu_fifo_underrun_disabled = true;
- crtc->pch_fifo_underrun_disabled = true;
+ /*
+ * We track the PCH trancoder underrun reporting state
+ * within the crtc. With crtc for pipe A housing the underrun
+ * reporting state for PCH transcoder A, crtc for pipe B housing
+ * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
+ * and marking underrun reporting as disabled for the non-existing
+ * PCH transcoders B and C would prevent enabling the south
+ * error interrupt (see cpt_can_enable_serr_int()).
+ */
+ if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
+ crtc->pch_fifo_underrun_disabled = true;
}
}
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915: Don't mark PCH underrun reporting as diasabled for transcoder B/C on LPT-H
2016-08-05 17:00 [PATCH] drm/i915: Don't mark PCH underrun reporting as diasabled for transcoder B/C on LPT-H ville.syrjala
@ 2016-08-05 20:22 ` Daniel Vetter
2016-08-09 15:04 ` Ville Syrjälä
2016-08-06 7:16 ` ✗ Ro.CI.BAT: failure for " Patchwork
1 sibling, 1 reply; 5+ messages in thread
From: Daniel Vetter @ 2016-08-05 20:22 UTC (permalink / raw)
To: ville.syrjala; +Cc: Daniel Vetter, intel-gfx
On Fri, Aug 05, 2016 at 08:00:17PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Marking PCH transcoder FIFO underrun reporting as disabled for
> transcoder B/C on LPT-H will block us from enabling the south error
> interrupt. So let's only mark transcoder A underrun reporting as
> disabled initially.
>
> This is a little tricky to hit since you need a machine with LPT-H, and
> the BIOS must enable either pipe B or C at boot. Then i915 would mark
> the "transcoder B/C" underrun reporting as disabled and never enable it
> again, meaning south interrupts would never get enabled either. The only
> other interrupt in there is actually the poison interrupt which, if we
> could ever trigger it, would just result in a little error in dmesg.
>
> Here's the resulting change in SDEIMR on my HSW when I boot it with
> multiple displays attached:
> - (0x000c4004): 0xf115ffff
> + (0x000c4004): 0xf114ffff
>
> My previous attempt [1] tried to fix this a little differently, but
> Daniel requested I do this instead.
>
> [1] https://lists.freedesktop.org/archives/intel-gfx/2015-November/081420.html
>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/intel_display.c | 19 ++++++++++++++++++-
> 1 file changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9cbf5431c1e3..888a52c64a26 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -15771,6 +15771,13 @@ static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
> return false;
> }
>
> +static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
> + enum transcoder pch_transcoder)
> +{
> + return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
> + (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
> +}
> +
> static void intel_sanitize_crtc(struct intel_crtc *crtc)
> {
> struct drm_device *dev = crtc->base.dev;
> @@ -15849,7 +15856,17 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
> * worst a fifo underrun happens which also sets this to false.
> */
> crtc->cpu_fifo_underrun_disabled = true;
> - crtc->pch_fifo_underrun_disabled = true;
> + /*
> + * We track the PCH trancoder underrun reporting state
> + * within the crtc. With crtc for pipe A housing the underrun
> + * reporting state for PCH transcoder A, crtc for pipe B housing
> + * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
> + * and marking underrun reporting as disabled for the non-existing
> + * PCH transcoders B and C would prevent enabling the south
> + * error interrupt (see cpt_can_enable_serr_int()).
> + */
> + if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
> + crtc->pch_fifo_underrun_disabled = true;
> }
> }
>
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* ✗ Ro.CI.BAT: failure for drm/i915: Don't mark PCH underrun reporting as diasabled for transcoder B/C on LPT-H
2016-08-05 17:00 [PATCH] drm/i915: Don't mark PCH underrun reporting as diasabled for transcoder B/C on LPT-H ville.syrjala
2016-08-05 20:22 ` Daniel Vetter
@ 2016-08-06 7:16 ` Patchwork
2016-08-09 14:45 ` Ville Syrjälä
1 sibling, 1 reply; 5+ messages in thread
From: Patchwork @ 2016-08-06 7:16 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Don't mark PCH underrun reporting as diasabled for transcoder B/C on LPT-H
URL : https://patchwork.freedesktop.org/series/10726/
State : failure
== Summary ==
Series 10726v1 drm/i915: Don't mark PCH underrun reporting as diasabled for transcoder B/C on LPT-H
http://patchwork.freedesktop.org/api/1.0/series/10726/revisions/1/mbox
Test drv_module_reload_basic:
pass -> DMESG-WARN (ro-hsw-i7-4770r)
Test kms_cursor_legacy:
Subgroup basic-cursor-vs-flip-varying-size:
pass -> FAIL (ro-ilk1-i5-650)
Subgroup basic-flip-vs-cursor-legacy:
fail -> PASS (ro-byt-n2820)
fail -> PASS (ro-bdw-i5-5250u)
pass -> FAIL (ro-skl3-i5-6260u)
Subgroup basic-flip-vs-cursor-varying-size:
pass -> FAIL (ro-snb-i7-2620M)
fail -> PASS (ro-bdw-i5-5250u)
fi-kbl-qkkr total:244 pass:185 dwarn:29 dfail:0 fail:3 skip:27
ro-bdw-i5-5250u total:240 pass:220 dwarn:4 dfail:0 fail:0 skip:16
ro-bdw-i7-5557U total:240 pass:224 dwarn:0 dfail:0 fail:0 skip:16
ro-bdw-i7-5600u total:240 pass:207 dwarn:0 dfail:0 fail:1 skip:32
ro-bsw-n3050 total:240 pass:194 dwarn:0 dfail:0 fail:4 skip:42
ro-byt-n2820 total:240 pass:198 dwarn:0 dfail:0 fail:2 skip:40
ro-hsw-i3-4010u total:240 pass:214 dwarn:0 dfail:0 fail:0 skip:26
ro-hsw-i7-4770r total:240 pass:213 dwarn:1 dfail:0 fail:0 skip:26
ro-ilk-i7-620lm total:240 pass:173 dwarn:1 dfail:0 fail:1 skip:65
ro-ilk1-i5-650 total:235 pass:173 dwarn:0 dfail:0 fail:2 skip:60
ro-ivb-i7-3770 total:240 pass:205 dwarn:0 dfail:0 fail:0 skip:35
ro-ivb2-i7-3770 total:240 pass:209 dwarn:0 dfail:0 fail:0 skip:31
ro-skl3-i5-6260u total:240 pass:222 dwarn:0 dfail:0 fail:4 skip:14
ro-snb-i7-2620M total:240 pass:197 dwarn:0 dfail:0 fail:2 skip:41
Results at /archive/results/CI_IGT_test/RO_Patchwork_1736/
b834992 drm-intel-nightly: 2016y-08m-05d-20h-40m-44s UTC integration manifest
d24b0aa drm/i915: Don't mark PCH underrun reporting as diasabled for transcoder B/C on LPT-H
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: ✗ Ro.CI.BAT: failure for drm/i915: Don't mark PCH underrun reporting as diasabled for transcoder B/C on LPT-H
2016-08-06 7:16 ` ✗ Ro.CI.BAT: failure for " Patchwork
@ 2016-08-09 14:45 ` Ville Syrjälä
0 siblings, 0 replies; 5+ messages in thread
From: Ville Syrjälä @ 2016-08-09 14:45 UTC (permalink / raw)
To: intel-gfx
On Sat, Aug 06, 2016 at 07:16:09AM -0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Don't mark PCH underrun reporting as diasabled for transcoder B/C on LPT-H
> URL : https://patchwork.freedesktop.org/series/10726/
> State : failure
>
> == Summary ==
>
> Series 10726v1 drm/i915: Don't mark PCH underrun reporting as diasabled for transcoder B/C on LPT-H
> http://patchwork.freedesktop.org/api/1.0/series/10726/revisions/1/mbox
>
> Test drv_module_reload_basic:
> pass -> DMESG-WARN (ro-hsw-i7-4770r)
[ 134.371594] =============================================
[ 134.371596] [ INFO: possible recursive locking detected ]
[ 134.371599] 4.7.0-gfxbench-RO_Patchwork_1736+ #1 Tainted: G U
[ 134.371601] ---------------------------------------------
[ 134.371604] rmmod/6305 is trying to acquire lock:
[ 134.371607] (&(&n->list_lock)->rlock){-.-...}, at: [<ffffffff811ca177>] get_partial_node.isra.23+0x47/0x430
[ 134.371617]
but task is already holding lock:
[ 134.371619] (&(&n->list_lock)->rlock){-.-...}, at: [<ffffffff811cd56c>] __kmem_cache_shutdown+0x5c/0x360
[ 134.371636]
other info that might help us debug this:
[ 134.371638] Possible unsafe locking scenario:
[ 134.371652] CPU0
[ 134.371653] ----
[ 134.371654] lock(&(&n->list_lock)->rlock);
[ 134.371656] lock(&(&n->list_lock)->rlock);
[ 134.371658]
*** DEADLOCK ***
[ 134.371662] May be due to missing lock nesting notation
[ 134.371666] 5 locks held by rmmod/6305:
[ 134.371668] #0: (&dev->mutex){......}, at: [<ffffffff8152d9c2>] driver_detach+0x42/0xc0
[ 134.371676] #1: (&dev->mutex){......}, at: [<ffffffff8152d9d0>] driver_detach+0x50/0xc0
[ 134.371682] #2: (cpu_hotplug.dep_map){++++++}, at: [<ffffffff8107e0cd>] get_online_cpus+0x2d/0x80
[ 134.371689] #3: (slab_mutex){+.+.+.}, at: [<ffffffff81197c0c>] kmem_cache_destroy+0x3c/0x220
[ 134.371696] #4: (&(&n->list_lock)->rlock){-.-...}, at: [<ffffffff811cd56c>] __kmem_cache_shutdown+0x5c/0x360
[ 134.371702]
stack backtrace:
[ 134.371705] CPU: 1 PID: 6305 Comm: rmmod Tainted: G U 4.7.0-gfxbench-RO_Patchwork_1736+ #1
[ 134.371710] Hardware name: GIGABYTE M4HM87P-00/M4HM87P-00, BIOS F6 12/10/2014
[ 134.371713] 0000000000000000 ffff8802057137f0 ffffffff8141c765 ffffffff82596890
[ 134.371718] ffffffff82596890 ffff8802057138b0 ffffffff810d5914 ffff8801e5ac4eb8
[ 134.371722] 000000001480ef00 ffff88021483c240 ffff880200000005 ffffffff0000b700
[ 134.371727] Call Trace:
[ 134.371731] [<ffffffff8141c765>] dump_stack+0x67/0x92
[ 134.371735] [<ffffffff810d5914>] __lock_acquire+0x1544/0x1930
[ 134.371763] [<ffffffffa03c58ba>] ? i915_exit+0x1a/0x1ec [i915]
[ 134.371780] [<ffffffffa03c58ba>] ? i915_exit+0x1a/0x1ec [i915]
[ 134.371785] [<ffffffff810ea570>] ? rcu_read_lock_sched_held+0x70/0x80
[ 134.371789] [<ffffffff810ea4fd>] ? debug_lockdep_rcu_enabled+0x1d/0x20
[ 134.371793] [<ffffffff810d6122>] lock_acquire+0xb2/0x200
[ 134.371797] [<ffffffff811ca177>] ? get_partial_node.isra.23+0x47/0x430
[ 134.371801] [<ffffffff817c4566>] _raw_spin_lock+0x36/0x50
[ 134.371805] [<ffffffff811ca177>] ? get_partial_node.isra.23+0x47/0x430
[ 134.371808] [<ffffffff811ca177>] get_partial_node.isra.23+0x47/0x430
[ 134.371813] [<ffffffff8110f837>] ? __module_address+0x27/0xf0
[ 134.371829] [<ffffffffa03c58ba>] ? i915_exit+0x1a/0x1ec [i915]
[ 134.371833] [<ffffffff8110f90d>] ? __module_text_address+0xd/0x60
[ 134.371837] [<ffffffff8111339a>] ? is_module_text_address+0x2a/0x50
[ 134.371840] [<ffffffff8109f294>] ? __kernel_text_address+0x34/0x60
[ 134.371845] [<ffffffff8101ef86>] ? print_context_stack+0x76/0xe0
[ 134.371848] [<ffffffff8101e737>] ? dump_trace+0x117/0x300
[ 134.371852] [<ffffffff811ca9b7>] ___slab_alloc.constprop.26+0x217/0x390
[ 134.371857] [<ffffffff81439e11>] ? __debug_object_init+0x2f1/0x410
[ 134.371861] [<ffffffff810d2187>] ? add_lock_to_list.isra.9.constprop.27+0x77/0xc0
[ 134.371866] [<ffffffff810d56ae>] ? __lock_acquire+0x12de/0x1930
[ 134.371870] [<ffffffff81439e11>] ? __debug_object_init+0x2f1/0x410
[ 134.371873] [<ffffffff811cab73>] __slab_alloc.isra.21.constprop.25+0x43/0x80
[ 134.371877] [<ffffffff81439e11>] ? __debug_object_init+0x2f1/0x410
[ 134.371881] [<ffffffff811cadf1>] kmem_cache_alloc+0x241/0x2f0
[ 134.371885] [<ffffffff81439e11>] __debug_object_init+0x2f1/0x410
[ 134.371889] [<ffffffff8143a0c6>] debug_object_activate+0x156/0x1e0
[ 134.371892] [<ffffffff811ca560>] ? get_partial_node.isra.23+0x430/0x430
[ 134.371896] [<ffffffff810edfd1>] __call_rcu.constprop.60+0x31/0x2f0
[ 134.371900] [<ffffffff810ee2a2>] call_rcu+0x12/0x20
[ 134.371904] [<ffffffff811c951d>] discard_slab+0x3d/0x40
[ 134.371907] [<ffffffff811cd5d7>] __kmem_cache_shutdown+0xc7/0x360
[ 134.371911] [<ffffffff817c06af>] ? mutex_lock_nested+0x27f/0x3b0
[ 134.371915] [<ffffffff811971a9>] shutdown_cache+0x19/0x60
[ 134.371918] [<ffffffff81197d7e>] kmem_cache_destroy+0x1ae/0x220
[ 134.371933] [<ffffffffa0340ae4>] i915_gem_load_cleanup+0x14/0x40 [i915]
[ 134.371943] [<ffffffffa02fffe1>] i915_driver_unload+0x151/0x180 [i915]
[ 134.371953] [<ffffffffa030a124>] i915_pci_remove+0x14/0x20 [i915]
[ 134.371958] [<ffffffff814673e4>] pci_device_remove+0x34/0xb0
[ 134.371963] [<ffffffff8152ce6c>] __device_release_driver+0x9c/0x150
[ 134.371967] [<ffffffff8152da36>] driver_detach+0xb6/0xc0
[ 134.371971] [<ffffffff8152c883>] bus_remove_driver+0x53/0xd0
[ 134.371974] [<ffffffff8152e4f7>] driver_unregister+0x27/0x50
[ 134.371977] [<ffffffff81466465>] pci_unregister_driver+0x25/0x70
[ 134.371994] [<ffffffffa03c58ba>] i915_exit+0x1a/0x1ec [i915]
[ 134.371998] [<ffffffff81110329>] SyS_delete_module+0x199/0x1f0
[ 134.372002] [<ffffffff817c50a9>] entry_SYSCALL_64_fastpath+0x1c/0xac
Unrelated to this patch, and people seem to be looking into it already.
> Test kms_cursor_legacy:
> Subgroup basic-cursor-vs-flip-varying-size:
> pass -> FAIL (ro-ilk1-i5-650)
(kms_cursor_legacy:8166) DEBUG: Test requirement passed: target > 1
(kms_cursor_legacy:8166) DEBUG: Using a target of 32 cursor updates per half-vblank
(kms_cursor_legacy:8166) WARNING: page flip 0 was delayed, missed 1 frames
(kms_cursor_legacy:8166) WARNING: page flip 1 was delayed, missed 1 frames
(kms_cursor_legacy:8166) WARNING: page flip 3 was delayed, missed 1 frames
(kms_cursor_legacy:8166) CRITICAL: Test assertion failure function basic_cursor_vs_flip, file kms_cursor_legacy.c:670:
(kms_cursor_legacy:8166) CRITICAL: Failed assertion: vbl.sequence == vblank_start + 60
(kms_cursor_legacy:8166) CRITICAL: error: 11425 != 11422
https://bugs.freedesktop.org/show_bug.cgi?id=96701
> Subgroup basic-flip-vs-cursor-legacy:
> fail -> PASS (ro-byt-n2820)
> fail -> PASS (ro-bdw-i5-5250u)
> pass -> FAIL (ro-skl3-i5-6260u)
(kms_cursor_legacy:9330) DEBUG: Test requirement passed: target > 1
(kms_cursor_legacy:9330) DEBUG: Using a target of 64 cursor updates per half-vblank
(kms_cursor_legacy:9330) CRITICAL: Test assertion failure function basic_flip_vs_cursor, file kms_cursor_legacy.c:514:
(kms_cursor_legacy:9330) CRITICAL: Failed assertion: get_vblank(display->drm_fd, pipe, 0) == vblank_start
(kms_cursor_legacy:9330) CRITICAL: error: 12169 != 12168
https://bugs.freedesktop.org/show_bug.cgi?id=97188
> Subgroup basic-flip-vs-cursor-varying-size:
> pass -> FAIL (ro-snb-i7-2620M)
(kms_cursor_legacy:7948) DEBUG: Test requirement passed: target > 1
(kms_cursor_legacy:7948) DEBUG: Using a target of 64 cursor updates per half-vblank
(kms_cursor_legacy:7948) CRITICAL: Test assertion failure function basic_flip_vs_cursor, file kms_cursor_legacy.c:514:
(kms_cursor_legacy:7948) CRITICAL: Failed assertion: get_vblank(display->drm_fd, pipe, 0) == vblank_start
(kms_cursor_legacy:7948) CRITICAL: error: 13766 != 13765
https://bugs.freedesktop.org/show_bug.cgi?id=97188
> fail -> PASS (ro-bdw-i5-5250u)
>
> fi-kbl-qkkr total:244 pass:185 dwarn:29 dfail:0 fail:3 skip:27
> ro-bdw-i5-5250u total:240 pass:220 dwarn:4 dfail:0 fail:0 skip:16
> ro-bdw-i7-5557U total:240 pass:224 dwarn:0 dfail:0 fail:0 skip:16
> ro-bdw-i7-5600u total:240 pass:207 dwarn:0 dfail:0 fail:1 skip:32
> ro-bsw-n3050 total:240 pass:194 dwarn:0 dfail:0 fail:4 skip:42
> ro-byt-n2820 total:240 pass:198 dwarn:0 dfail:0 fail:2 skip:40
> ro-hsw-i3-4010u total:240 pass:214 dwarn:0 dfail:0 fail:0 skip:26
> ro-hsw-i7-4770r total:240 pass:213 dwarn:1 dfail:0 fail:0 skip:26
> ro-ilk-i7-620lm total:240 pass:173 dwarn:1 dfail:0 fail:1 skip:65
> ro-ilk1-i5-650 total:235 pass:173 dwarn:0 dfail:0 fail:2 skip:60
> ro-ivb-i7-3770 total:240 pass:205 dwarn:0 dfail:0 fail:0 skip:35
> ro-ivb2-i7-3770 total:240 pass:209 dwarn:0 dfail:0 fail:0 skip:31
> ro-skl3-i5-6260u total:240 pass:222 dwarn:0 dfail:0 fail:4 skip:14
> ro-snb-i7-2620M total:240 pass:197 dwarn:0 dfail:0 fail:2 skip:41
>
> Results at /archive/results/CI_IGT_test/RO_Patchwork_1736/
>
> b834992 drm-intel-nightly: 2016y-08m-05d-20h-40m-44s UTC integration manifest
> d24b0aa drm/i915: Don't mark PCH underrun reporting as diasabled for transcoder B/C on LPT-H
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915: Don't mark PCH underrun reporting as diasabled for transcoder B/C on LPT-H
2016-08-05 20:22 ` Daniel Vetter
@ 2016-08-09 15:04 ` Ville Syrjälä
0 siblings, 0 replies; 5+ messages in thread
From: Ville Syrjälä @ 2016-08-09 15:04 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Daniel Vetter, intel-gfx
On Fri, Aug 05, 2016 at 10:22:48PM +0200, Daniel Vetter wrote:
> On Fri, Aug 05, 2016 at 08:00:17PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Marking PCH transcoder FIFO underrun reporting as disabled for
> > transcoder B/C on LPT-H will block us from enabling the south error
> > interrupt. So let's only mark transcoder A underrun reporting as
> > disabled initially.
> >
> > This is a little tricky to hit since you need a machine with LPT-H, and
> > the BIOS must enable either pipe B or C at boot. Then i915 would mark
> > the "transcoder B/C" underrun reporting as disabled and never enable it
> > again, meaning south interrupts would never get enabled either. The only
> > other interrupt in there is actually the poison interrupt which, if we
> > could ever trigger it, would just result in a little error in dmesg.
> >
> > Here's the resulting change in SDEIMR on my HSW when I boot it with
> > multiple displays attached:
> > - (0x000c4004): 0xf115ffff
> > + (0x000c4004): 0xf114ffff
> >
> > My previous attempt [1] tried to fix this a little differently, but
> > Daniel requested I do this instead.
> >
> > [1] https://lists.freedesktop.org/archives/intel-gfx/2015-November/081420.html
> >
> > Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Pushed to dinq. Thanks for the review.
>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 19 ++++++++++++++++++-
> > 1 file changed, 18 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 9cbf5431c1e3..888a52c64a26 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -15771,6 +15771,13 @@ static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
> > return false;
> > }
> >
> > +static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
> > + enum transcoder pch_transcoder)
> > +{
> > + return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
> > + (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
> > +}
> > +
> > static void intel_sanitize_crtc(struct intel_crtc *crtc)
> > {
> > struct drm_device *dev = crtc->base.dev;
> > @@ -15849,7 +15856,17 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
> > * worst a fifo underrun happens which also sets this to false.
> > */
> > crtc->cpu_fifo_underrun_disabled = true;
> > - crtc->pch_fifo_underrun_disabled = true;
> > + /*
> > + * We track the PCH trancoder underrun reporting state
> > + * within the crtc. With crtc for pipe A housing the underrun
> > + * reporting state for PCH transcoder A, crtc for pipe B housing
> > + * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
> > + * and marking underrun reporting as disabled for the non-existing
> > + * PCH transcoders B and C would prevent enabling the south
> > + * error interrupt (see cpt_can_enable_serr_int()).
> > + */
> > + if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
> > + crtc->pch_fifo_underrun_disabled = true;
> > }
> > }
> >
> > --
> > 2.7.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
--
Ville Syrjälä
Intel OTC
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^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2016-08-09 15:06 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-08-05 17:00 [PATCH] drm/i915: Don't mark PCH underrun reporting as diasabled for transcoder B/C on LPT-H ville.syrjala
2016-08-05 20:22 ` Daniel Vetter
2016-08-09 15:04 ` Ville Syrjälä
2016-08-06 7:16 ` ✗ Ro.CI.BAT: failure for " Patchwork
2016-08-09 14:45 ` Ville Syrjälä
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