From: Tom Rini <trini@konsulko.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v4] arm: cache: always flush cache line size for page table
Date: Sun, 14 Aug 2016 16:01:30 -0400 [thread overview]
Message-ID: <20160814200130.GJ4188@bill-the-cat> (raw)
In-Reply-To: <a037a6209e2e74ece637ccbdfa48dc59@agner.ch>
On Mon, Aug 08, 2016 at 12:43:03AM -0700, Stefan Agner wrote:
> On 2016-08-07 23:10, Lokesh Vutla wrote:
> > Hi,
> >
> > On Sunday 07 August 2016 11:13 PM, Stefan Agner wrote:
> >> From: Stefan Agner <stefan.agner@toradex.com>
> >>
> >> The page table is maintained by the CPU, hence it is safe to always
> >> align cache flush to a whole cache line size. This allows to use
> >> mmu_page_table_flush for a single page table, e.g. when configure
> >> only small regions through mmu_set_region_dcache_behaviour.
> >>
> >> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> >> Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
> >> Reviewed-by: Simon Glass <sjg@chromium.org>
> >> ---
> >
> > I get the following warning when CONFIG_PHYS_64BIT is enabled on arm
> > platforms(dra7xx_evm_defconfig):
>
> Hm, do I see things right, this is otherwise a 32-bit architecture? Does
> that work without LPAE? What is the page table size in this case?
It's a 32bit architecture with LPAE, iirc, yes.
--
Tom
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next prev parent reply other threads:[~2016-08-14 20:01 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-07 17:43 [U-Boot] [PATCH v4] arm: cache: always flush cache line size for page table Stefan Agner
2016-08-08 4:22 ` Heiko Schocher
2016-08-08 6:10 ` Lokesh Vutla
2016-08-08 7:43 ` Stefan Agner
2016-08-14 20:01 ` Tom Rini [this message]
2016-08-15 3:44 ` Stefan Agner
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