[PATCH v3 00/21] drm/i915: Organize most GPU features by platform

[PATCH v3 00/21] drm/i915: Organize most GPU features by platform

[Carlos Santa]

 - organize most GPU features so that they are easy to group by platforms.
   It seems some of the ground work was already done for Gen7 features.

 - make most of these GPU features now a device_info flag also based on
   previous work done by others. The idea is here is to have a central place where
   to add new features, now it should also be possible to see what the supported 
   features are for a given platform by dumping of the struct definitions.
   The list of the features that were converted to a device_info flag include: PSR,
   RUNTIME_PM, CORE_RING_FREQ, CSR, GUC, RESOURCE_STREAMER, RC6,
   RC6p, DP_MST, GMBUS_IRQ, FW_BLC, HW_CONTEXTS, LOGICAL_RING_CONTEXTS, L3_DPF,
   HWS_NEEDS_PHYSICAL and GMCH_DISPLAY.

- Changes since v2, thanks to Rodrigo, Ville, Jani and others for the comments

  - Kill off the approach of inheriting GPU features from platform to platform, even though there's some code consolidation there's added complexity when going through the code to find out what feature is supported where, specifically for features supported across several generations.

- Patch 2: "drm/i915: Remove .is_mobile from platform struct"
  -  Kill off the distintion between desktop vs. mobile for HWS+ and VLV while still keeping it for ILK-IVB.

- Patch 4: "drm/i915: Move HAS_RUNTIME_PM definition to platform"
  - Remove runtime PM support for SNB as it breaks hotplut support.

- Patch 5: "drm/i915: Get rid of HAS_CORE_RING_FREQ"
  - No need for this flag anymore as this flag == .has_llc.

- Patch 20: "drm/i915: Make HWS_NEEDS_PHYSICAL the exception"
  - .hws_needs_physical should the exception, invert the logic so now older GPU h/w enables that since they are fewer to support. Remove support of .need_gfx_hws for newer GPU hardware revisions. 

Carlos Santa (21):
  drm/i915: Move HAS_PSR definition to platform struct definition
  drm/i915: Remove .is_mobile field from platform struct
  drm/i915: Introduce GEN6_FEATURES for device info
  drm/i915: Move HAS_RUNTIME_PM definition to platform
  drm/i915: Get rid of HAS_CORE_RING_FREQ
  drm/i915 Move HAS_CSR definition to platform definition
  drm/i915: Move HAS_RESOURCE_STREAMER definition to platform definition
  drm/i915: Move HAS_RC6 definition to platform definition
  drm/i915: Move HAS_RC6p definition to platform definition
  drm/i915: Move HAS_DP_MST definition to platform definition
  drm/i915: Introduce GEN5_FEATURES for device info
  drm/i915: Move HAS_GMBUS_IRQ definition to platform definition
  drm/i915: Introduce GEN4_FEATURES for device info
  drm/i915: Introduce GEN3_FEATURES for device info
  drm/i915: Introduce GEN2_FEATURES for device info
  drm/i915: Move HAS_HW_CONTEXTS definition to platform
  drm/i915: Move HAS_LOGICAL_RING_CONTEXTS definition to platform
  drm/i915: Move HAS_L3_DPF definition to platform definition
  drm/i915: Move HAS_GMCH_DISPLAY definition to platform
  drm/i915: Make HWS_NEEDS_PHYSICAL the exception
  drm/i915: Move HAS_GUC definition to platform definition

 arch/x86/kernel/early-quirks.c          |   9 +-
 drivers/gpu/drm/i915/i915_debugfs.c     |   3 +-
 drivers/gpu/drm/i915/i915_drv.h         |  57 +++----
 drivers/gpu/drm/i915/i915_gpu_error.c   |   2 +-
 drivers/gpu/drm/i915/i915_pci.c         | 275 +++++++++++++++++---------------
 drivers/gpu/drm/i915/intel_ringbuffer.c |  20 +--
 include/drm/i915_pciids.h               |  38 ++---
 7 files changed, 207 insertions(+), 197 deletions(-)

-- 
1.9.1

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[PATCH v3 01/21] drm/i915: Move HAS_PSR definition to platform struct definition

[Carlos Santa]

[patch series] Moving all GPU features to the platform struct definition
allows for
	- standard place when adding new features from new platforms
	- possible to see supported features when dumping struct definition

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 5 ++---
 drivers/gpu/drm/i915/i915_pci.c | 5 ++++-
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index feec00f..6f2f066 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -770,6 +770,7 @@ struct intel_csr {
 	func(is_kabylake) sep \
 	func(is_preliminary) sep \
 	func(has_fbc) sep \
+	func(has_psr) sep \
 	func(has_pipe_cxsr) sep \
 	func(has_hotplug) sep \
 	func(cursor_needs_physical) sep \
@@ -2767,9 +2768,7 @@ struct drm_i915_cmd_table {
 
 #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
-#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
-				 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
-				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
+#define HAS_PSR(dev)		(INTEL_INFO(dev)->has_psr)
 #define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
 				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
 				 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 2587b1b..e1caa0b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -243,6 +243,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
 
 #define VLV_FEATURES  \
 	.gen = 7, .num_pipes = 2, \
+	.has_psr = 1, \
 	.need_gfx_hws = 1, .has_hotplug = 1, \
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 	.display_mmio_offset = VLV_DISPLAY_BASE, \
@@ -264,7 +265,8 @@ static const struct intel_device_info intel_valleyview_d_info = {
 	GEN7_FEATURES, \
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 	.has_ddi = 1, \
-	.has_fpga_dbg = 1
+	.has_fpga_dbg = 1, \
+	.has_psr = 1
 
 static const struct intel_device_info intel_haswell_d_info = {
 	HSW_FEATURES,
@@ -312,6 +314,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 	.is_cherryview = 1,
+	.has_psr = 1,
 	.display_mmio_offset = VLV_DISPLAY_BASE,
 	GEN_CHV_PIPEOFFSETS,
 	CURSOR_OFFSETS,
-- 
1.9.1

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[PATCH v3 02/21] drm/i915: Remove .is_mobile field from platform struct

[Carlos Santa]

As recommended by Ville Syrjala removing .is_mobile field from the
platform struct definition for vlv and hsw+ GPUs as there's no need to
make the distinction in later hardware anymore. Keep it for older GPUs
as it is still needed for ilk-ivb.

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
---
 arch/x86/kernel/early-quirks.c  |  9 +++------
 drivers/gpu/drm/i915/i915_pci.c | 45 ++++++++---------------------------------
 include/drm/i915_pciids.h       | 38 +++++++++++++---------------------
 3 files changed, 25 insertions(+), 67 deletions(-)

diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index de7501e..e6bd329 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -512,8 +512,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
 	INTEL_I915GM_IDS(&gen3_early_ops),
 	INTEL_I945G_IDS(&gen3_early_ops),
 	INTEL_I945GM_IDS(&gen3_early_ops),
-	INTEL_VLV_M_IDS(&gen6_early_ops),
-	INTEL_VLV_D_IDS(&gen6_early_ops),
+	INTEL_VLV_IDS(&gen6_early_ops),
 	INTEL_PINEVIEW_IDS(&gen3_early_ops),
 	INTEL_I965G_IDS(&gen3_early_ops),
 	INTEL_G33_IDS(&gen3_early_ops),
@@ -526,10 +525,8 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
 	INTEL_SNB_M_IDS(&gen6_early_ops),
 	INTEL_IVB_M_IDS(&gen6_early_ops),
 	INTEL_IVB_D_IDS(&gen6_early_ops),
-	INTEL_HSW_D_IDS(&gen6_early_ops),
-	INTEL_HSW_M_IDS(&gen6_early_ops),
-	INTEL_BDW_M_IDS(&gen8_early_ops),
-	INTEL_BDW_D_IDS(&gen8_early_ops),
+	INTEL_HSW_IDS(&gen6_early_ops),
+	INTEL_BDW_IDS(&gen8_early_ops),
 	INTEL_CHV_IDS(&chv_early_ops),
 	INTEL_SKL_IDS(&gen9_early_ops),
 	INTEL_BXT_IDS(&gen9_early_ops),
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e1caa0b..b5ec8a7 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -250,13 +250,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
 	GEN_DEFAULT_PIPEOFFSETS, \
 	CURSOR_OFFSETS
 
-static const struct intel_device_info intel_valleyview_m_info = {
-	VLV_FEATURES,
-	.is_valleyview = 1,
-	.is_mobile = 1,
-};
-
-static const struct intel_device_info intel_valleyview_d_info = {
+static const struct intel_device_info intel_valleyview_info = {
 	VLV_FEATURES,
 	.is_valleyview = 1,
 };
@@ -268,47 +262,28 @@ static const struct intel_device_info intel_valleyview_d_info = {
 	.has_fpga_dbg = 1, \
 	.has_psr = 1
 
-static const struct intel_device_info intel_haswell_d_info = {
+static const struct intel_device_info intel_haswell_info = {
 	HSW_FEATURES,
 	.is_haswell = 1,
 };
 
-static const struct intel_device_info intel_haswell_m_info = {
-	HSW_FEATURES,
-	.is_haswell = 1,
-	.is_mobile = 1,
-};
-
 #define BDW_FEATURES \
 	HSW_FEATURES, \
 	BDW_COLORS
 
-static const struct intel_device_info intel_broadwell_d_info = {
+static const struct intel_device_info intel_broadwell_info = {
 	BDW_FEATURES,
 	.gen = 8,
 	.is_broadwell = 1,
 };
 
-static const struct intel_device_info intel_broadwell_m_info = {
-	BDW_FEATURES,
-	.gen = 8, .is_mobile = 1,
-	.is_broadwell = 1,
-};
-
-static const struct intel_device_info intel_broadwell_gt3d_info = {
+static const struct intel_device_info intel_broadwell_gt3_info = {
 	BDW_FEATURES,
 	.gen = 8,
 	.is_broadwell = 1,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
-static const struct intel_device_info intel_broadwell_gt3m_info = {
-	BDW_FEATURES,
-	.gen = 8, .is_mobile = 1,
-	.is_broadwell = 1,
-	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
-};
-
 static const struct intel_device_info intel_cherryview_info = {
 	.gen = 8, .num_pipes = 3,
 	.need_gfx_hws = 1, .has_hotplug = 1,
@@ -390,14 +365,10 @@ static const struct pci_device_id pciidlist[] = {
 	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
 	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
 	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
-	INTEL_HSW_D_IDS(&intel_haswell_d_info),
-	INTEL_HSW_M_IDS(&intel_haswell_m_info),
-	INTEL_VLV_M_IDS(&intel_valleyview_m_info),
-	INTEL_VLV_D_IDS(&intel_valleyview_d_info),
-	INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),
-	INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),
-	INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),
-	INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),
+	INTEL_HSW_IDS(&intel_haswell_info),
+	INTEL_VLV_IDS(&intel_valleyview_info),
+	INTEL_BDW_GT12_IDS(&intel_broadwell_info),
+	INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
 	INTEL_CHV_IDS(&intel_cherryview_info),
 	INTEL_SKL_GT1_IDS(&intel_skylake_info),
 	INTEL_SKL_GT2_IDS(&intel_skylake_info),
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 33466bf..0d5f426 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -134,7 +134,7 @@
 #define INTEL_IVB_Q_IDS(info) \
 	INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
 
-#define INTEL_HSW_D_IDS(info) \
+#define INTEL_HSW_IDS(info) \
 	INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
 	INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
 	INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
@@ -179,9 +179,7 @@
 	INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
 	INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
 	INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
-	INTEL_VGA_DEVICE(0x0D2E, info)  /* CRW GT3 reserved */ \
-
-#define INTEL_HSW_M_IDS(info) \
+	INTEL_VGA_DEVICE(0x0D2E, info),  /* CRW GT3 reserved */ \
 	INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
 	INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
 	INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
@@ -198,17 +196,15 @@
 	INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
 	INTEL_VGA_DEVICE(0x0D26, info)  /* CRW GT3 mobile */
 
-#define INTEL_VLV_M_IDS(info) \
+#define INTEL_VLV_IDS(info) \
 	INTEL_VGA_DEVICE(0x0f30, info), \
 	INTEL_VGA_DEVICE(0x0f31, info), \
 	INTEL_VGA_DEVICE(0x0f32, info), \
 	INTEL_VGA_DEVICE(0x0f33, info), \
-	INTEL_VGA_DEVICE(0x0157, info)
-
-#define INTEL_VLV_D_IDS(info) \
+	INTEL_VGA_DEVICE(0x0157, info), \
 	INTEL_VGA_DEVICE(0x0155, info)
 
-#define INTEL_BDW_GT12M_IDS(info)  \
+#define INTEL_BDW_GT12_IDS(info)  \
 	INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
 	INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
 	INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
@@ -216,21 +212,17 @@
 	INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
 	INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
 	INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
-	INTEL_VGA_DEVICE(0x161E, info)  /* GT2 ULX */
-
-#define INTEL_BDW_GT12D_IDS(info) \
+	INTEL_VGA_DEVICE(0x161E, info),  /* GT2 ULX */ \
 	INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
 	INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \
 	INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
 	INTEL_VGA_DEVICE(0x161D, info)  /* GT2 Workstation */
 
-#define INTEL_BDW_GT3M_IDS(info) \
+#define INTEL_BDW_GT3_IDS(info) \
 	INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
 	INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
 	INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \
-	INTEL_VGA_DEVICE(0x162E, info)  /* ULX */
-
-#define INTEL_BDW_GT3D_IDS(info) \
+	INTEL_VGA_DEVICE(0x162E, info),  /* ULX */\
 	INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
 	INTEL_VGA_DEVICE(0x162D, info)  /* Workstation */
 
@@ -244,14 +236,12 @@
 	INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
 	INTEL_VGA_DEVICE(0x163D, info)  /* Workstation */
 
-#define INTEL_BDW_M_IDS(info) \
-	INTEL_BDW_GT12M_IDS(info), \
-	INTEL_BDW_GT3M_IDS(info), \
-	INTEL_BDW_RSVDM_IDS(info)
-
-#define INTEL_BDW_D_IDS(info) \
-	INTEL_BDW_GT12D_IDS(info), \
-	INTEL_BDW_GT3D_IDS(info), \
+#define INTEL_BDW_IDS(info) \
+	INTEL_BDW_GT12_IDS(info), \
+	INTEL_BDW_GT3_IDS(info), \
+	INTEL_BDW_RSVDM_IDS(info), \
+	INTEL_BDW_GT12_IDS(info), \
+	INTEL_BDW_GT3_IDS(info), \
 	INTEL_BDW_RSVDD_IDS(info)
 
 #define INTEL_CHV_IDS(info) \
-- 
1.9.1

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[PATCH v3 03/21] drm/i915: Introduce GEN6_FEATURES for device info

[Carlos Santa]

Based on the GEN7_FEATURES changes from Ben W.

Use it for snb.

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 26 ++++++++++++--------------
 1 file changed, 12 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b5ec8a7..bdc2071 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -195,24 +195,22 @@ static const struct intel_device_info intel_ironlake_m_info = {
 	CURSOR_OFFSETS,
 };
 
+#define GEN6_FEATURES \
+	.gen = 6, .num_pipes = 2, \
+	.need_gfx_hws = 1, .has_hotplug = 1, \
+	.has_fbc = 1, \
+	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
+	.has_llc = 1, \
+	GEN_DEFAULT_PIPEOFFSETS, \
+	CURSOR_OFFSETS
+
 static const struct intel_device_info intel_sandybridge_d_info = {
-	.gen = 6, .num_pipes = 2,
-	.need_gfx_hws = 1, .has_hotplug = 1,
-	.has_fbc = 1,
-	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
-	.has_llc = 1,
-	GEN_DEFAULT_PIPEOFFSETS,
-	CURSOR_OFFSETS,
+	GEN6_FEATURES,
 };
 
 static const struct intel_device_info intel_sandybridge_m_info = {
-	.gen = 6, .is_mobile = 1, .num_pipes = 2,
-	.need_gfx_hws = 1, .has_hotplug = 1,
-	.has_fbc = 1,
-	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
-	.has_llc = 1,
-	GEN_DEFAULT_PIPEOFFSETS,
-	CURSOR_OFFSETS,
+	GEN6_FEATURES,
+	.is_mobile = 1,
 };
 
 #define GEN7_FEATURES  \
-- 
1.9.1

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[PATCH v3 04/21] drm/i915: Move HAS_RUNTIME_PM definition to platform

[Carlos Santa]

Moving all GPU features to the platform struct definition allows for
	- standard place when adding new features from new platforms
	- possible to see supported features when dumping struct
	  definitions

Feedback from V. Syrjala: remove runtime PM support for snb as it breaks
hotplug support.

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 6 ++----
 drivers/gpu/drm/i915/i915_pci.c | 6 +++++-
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6f2f066..0eaf28f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -771,6 +771,7 @@ struct intel_csr {
 	func(is_preliminary) sep \
 	func(has_fbc) sep \
 	func(has_psr) sep \
+	func(has_runtime_pm) sep \
 	func(has_pipe_cxsr) sep \
 	func(has_hotplug) sep \
 	func(cursor_needs_physical) sep \
@@ -2769,10 +2770,7 @@ struct drm_i915_cmd_table {
 #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
 #define HAS_PSR(dev)		(INTEL_INFO(dev)->has_psr)
-#define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
-				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
-				 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
-				 IS_KABYLAKE(dev) || IS_BROXTON(dev))
+#define HAS_RUNTIME_PM(dev)	(INTEL_INFO(dev)->has_runtime_pm)
 #define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
 #define HAS_RC6p(dev)		(IS_GEN6(dev) || IS_IVYBRIDGE(dev))
 
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index bdc2071..9d78836 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -242,6 +242,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
 #define VLV_FEATURES  \
 	.gen = 7, .num_pipes = 2, \
 	.has_psr = 1, \
+	.has_runtime_pm = 1, \
 	.need_gfx_hws = 1, .has_hotplug = 1, \
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 	.display_mmio_offset = VLV_DISPLAY_BASE, \
@@ -258,7 +259,8 @@ static const struct intel_device_info intel_valleyview_info = {
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 	.has_ddi = 1, \
 	.has_fpga_dbg = 1, \
-	.has_psr = 1
+	.has_psr = 1, \
+	.has_runtime_pm = 1
 
 static const struct intel_device_info intel_haswell_info = {
 	HSW_FEATURES,
@@ -288,6 +290,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 	.is_cherryview = 1,
 	.has_psr = 1,
+	.has_runtime_pm = 1,
 	.display_mmio_offset = VLV_DISPLAY_BASE,
 	GEN_CHV_PIPEOFFSETS,
 	CURSOR_OFFSETS,
@@ -316,6 +319,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.has_ddi = 1,
 	.has_fpga_dbg = 1,
 	.has_fbc = 1,
+	.has_runtime_pm = 1,
 	.has_pooled_eu = 0,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
-- 
1.9.1

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[PATCH v3 05/21] drm/i915: Get rid of HAS_CORE_RING_FREQ

[Carlos Santa]

No need for HAS_CORE_RING_FREQ as that flag is actually the same as
.has_llc. Feedback from V. Syrjala.

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 3 ++-
 drivers/gpu/drm/i915/i915_drv.h     | 4 ----
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 9bd4158..01b6735 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1898,11 +1898,12 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
 	struct drm_info_node *node = m->private;
 	struct drm_device *dev = node->minor->dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_device_info *info = mkwrite_device_info(dev_priv);
 	int ret = 0;
 	int gpu_freq, ia_freq;
 	unsigned int max_gpu_freq, min_gpu_freq;
 
-	if (!HAS_CORE_RING_FREQ(dev)) {
+	if (!info->has_llc) {
 		seq_puts(m, "unsupported on this chipset\n");
 		return 0;
 	}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0eaf28f..3ab63c0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2788,10 +2788,6 @@ struct drm_i915_cmd_table {
 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
 				    INTEL_INFO(dev)->gen >= 8)
 
-#define HAS_CORE_RING_FREQ(dev)	(INTEL_INFO(dev)->gen >= 6 && \
-				 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
-				 !IS_BROXTON(dev))
-
 #define HAS_POOLED_EU(dev)	(INTEL_INFO(dev)->has_pooled_eu)
 
 #define INTEL_PCH_DEVICE_ID_MASK		0xff00
-- 
1.9.1

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[PATCH v3 06/21] drm/i915 Move HAS_CSR definition to platform definition

[Carlos Santa]

Moving all GPU features to the platform struct definition allows for
	- standard place when adding new features from new platforms
	- possible to see supported features when dumping struct
	  definitions

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 3 ++-
 drivers/gpu/drm/i915/i915_pci.c | 5 +++++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3ab63c0..14e8911 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -772,6 +772,7 @@ struct intel_csr {
 	func(has_fbc) sep \
 	func(has_psr) sep \
 	func(has_runtime_pm) sep \
+	func(has_csr) sep \
 	func(has_pipe_cxsr) sep \
 	func(has_hotplug) sep \
 	func(cursor_needs_physical) sep \
@@ -2774,7 +2775,7 @@ struct drm_i915_cmd_table {
 #define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
 #define HAS_RC6p(dev)		(IS_GEN6(dev) || IS_IVYBRIDGE(dev))
 
-#define HAS_CSR(dev)	(IS_GEN9(dev))
+#define HAS_CSR(dev)	(INTEL_INFO(dev)->has_csr)
 
 /*
  * For now, anything with a GuC requires uCode loading, and then supports
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 9d78836..21a3bc5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -301,12 +301,14 @@ static const struct intel_device_info intel_skylake_info = {
 	BDW_FEATURES,
 	.is_skylake = 1,
 	.gen = 9,
+	.has_csr = 1,
 };
 
 static const struct intel_device_info intel_skylake_gt3_info = {
 	BDW_FEATURES,
 	.is_skylake = 1,
 	.gen = 9,
+	.has_csr = 1,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
@@ -321,6 +323,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.has_fbc = 1,
 	.has_runtime_pm = 1,
 	.has_pooled_eu = 0,
+	.has_csr = 1,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
 	BDW_COLORS,
@@ -330,12 +333,14 @@ static const struct intel_device_info intel_kabylake_info = {
 	BDW_FEATURES,
 	.is_kabylake = 1,
 	.gen = 9,
+	.has_csr = 1,
 };
 
 static const struct intel_device_info intel_kabylake_gt3_info = {
 	BDW_FEATURES,
 	.is_kabylake = 1,
 	.gen = 9,
+	.has_csr = 1,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
-- 
1.9.1

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[PATCH v3 07/21] drm/i915: Move HAS_RESOURCE_STREAMER definition to platform definition

[Carlos Santa]

Moving all GPU features to the platform struct definition allows for
	- standard place when adding new features from new platforms
	- possible to see supported features when dumping struct
	  definitions

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 4 ++--
 drivers/gpu/drm/i915/i915_pci.c | 3 +++
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 14e8911..e9d95c5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -773,6 +773,7 @@ struct intel_csr {
 	func(has_psr) sep \
 	func(has_runtime_pm) sep \
 	func(has_csr) sep \
+	func(has_resource_streamer) sep \
 	func(has_pipe_cxsr) sep \
 	func(has_hotplug) sep \
 	func(cursor_needs_physical) sep \
@@ -2786,8 +2787,7 @@ struct drm_i915_cmd_table {
 #define HAS_GUC_UCODE(dev)	(HAS_GUC(dev))
 #define HAS_GUC_SCHED(dev)	(HAS_GUC(dev))
 
-#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
-				    INTEL_INFO(dev)->gen >= 8)
+#define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)->has_resource_streamer)
 
 #define HAS_POOLED_EU(dev)	(INTEL_INFO(dev)->has_pooled_eu)
 
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 21a3bc5..46c48ed 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -260,6 +260,7 @@ static const struct intel_device_info intel_valleyview_info = {
 	.has_ddi = 1, \
 	.has_fpga_dbg = 1, \
 	.has_psr = 1, \
+	.has_resource_streamer = 1, \
 	.has_runtime_pm = 1
 
 static const struct intel_device_info intel_haswell_info = {
@@ -291,6 +292,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.is_cherryview = 1,
 	.has_psr = 1,
 	.has_runtime_pm = 1,
+	.has_resource_streamer = 1,
 	.display_mmio_offset = VLV_DISPLAY_BASE,
 	GEN_CHV_PIPEOFFSETS,
 	CURSOR_OFFSETS,
@@ -324,6 +326,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.has_runtime_pm = 1,
 	.has_pooled_eu = 0,
 	.has_csr = 1,
+	.has_resource_streamer = 1,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
 	BDW_COLORS,
-- 
1.9.1

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[PATCH v3 08/21] drm/i915: Move HAS_RC6 definition to platform definition

[Carlos Santa]

Moving all GPU features to the platform struct definition allows for
	- standard place when adding new features from new platforms
	- possible to see supported features when dumping struct
	  definitions

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 3 ++-
 drivers/gpu/drm/i915/i915_pci.c | 5 +++++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e9d95c5..bc6df5b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -774,6 +774,7 @@ struct intel_csr {
 	func(has_runtime_pm) sep \
 	func(has_csr) sep \
 	func(has_resource_streamer) sep \
+	func(has_rc6) sep \
 	func(has_pipe_cxsr) sep \
 	func(has_hotplug) sep \
 	func(cursor_needs_physical) sep \
@@ -2773,7 +2774,7 @@ struct drm_i915_cmd_table {
 #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
 #define HAS_PSR(dev)		(INTEL_INFO(dev)->has_psr)
 #define HAS_RUNTIME_PM(dev)	(INTEL_INFO(dev)->has_runtime_pm)
-#define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
+#define HAS_RC6(dev)		(INTEL_INFO(dev)->has_rc6)
 #define HAS_RC6p(dev)		(IS_GEN6(dev) || IS_IVYBRIDGE(dev))
 
 #define HAS_CSR(dev)	(INTEL_INFO(dev)->has_csr)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 46c48ed..42108dc 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -201,6 +201,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
 	.has_fbc = 1, \
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 	.has_llc = 1, \
+	.has_rc6 = 1, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	CURSOR_OFFSETS
 
@@ -219,6 +220,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
 	.has_fbc = 1, \
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 	.has_llc = 1, \
+	.has_rc6 = 1, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	IVB_CURSOR_OFFSETS
 
@@ -243,6 +245,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
 	.gen = 7, .num_pipes = 2, \
 	.has_psr = 1, \
 	.has_runtime_pm = 1, \
+	.has_rc6 = 1, \
 	.need_gfx_hws = 1, .has_hotplug = 1, \
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 	.display_mmio_offset = VLV_DISPLAY_BASE, \
@@ -293,6 +296,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_psr = 1,
 	.has_runtime_pm = 1,
 	.has_resource_streamer = 1,
+	.has_rc6 = 1,
 	.display_mmio_offset = VLV_DISPLAY_BASE,
 	GEN_CHV_PIPEOFFSETS,
 	CURSOR_OFFSETS,
@@ -327,6 +331,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.has_pooled_eu = 0,
 	.has_csr = 1,
 	.has_resource_streamer = 1,
+	.has_rc6 = 1,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
 	BDW_COLORS,
-- 
1.9.1

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[PATCH v3 09/21] drm/i915: Move HAS_RC6p definition to platform definition

[Carlos Santa]

Moving all GPU features to the platform struct definition allows for
	- standard place when adding new features from new platforms
	- possible to see supported features when dumping struct
	  definitions

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 3 ++-
 drivers/gpu/drm/i915/i915_pci.c | 3 +++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bc6df5b..611771b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -775,6 +775,7 @@ struct intel_csr {
 	func(has_csr) sep \
 	func(has_resource_streamer) sep \
 	func(has_rc6) sep \
+	func(has_rc6p) sep \
 	func(has_pipe_cxsr) sep \
 	func(has_hotplug) sep \
 	func(cursor_needs_physical) sep \
@@ -2775,7 +2776,7 @@ struct drm_i915_cmd_table {
 #define HAS_PSR(dev)		(INTEL_INFO(dev)->has_psr)
 #define HAS_RUNTIME_PM(dev)	(INTEL_INFO(dev)->has_runtime_pm)
 #define HAS_RC6(dev)		(INTEL_INFO(dev)->has_rc6)
-#define HAS_RC6p(dev)		(IS_GEN6(dev) || IS_IVYBRIDGE(dev))
+#define HAS_RC6p(dev)		(INTEL_INFO(dev)->has_rc6p)
 
 #define HAS_CSR(dev)	(INTEL_INFO(dev)->has_csr)
 
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 42108dc..ce78a18 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -202,6 +202,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 	.has_llc = 1, \
 	.has_rc6 = 1, \
+	.has_rc6p = 1, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	CURSOR_OFFSETS
 
@@ -221,6 +222,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 	.has_llc = 1, \
 	.has_rc6 = 1, \
+	.has_rc6p = 1, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	IVB_CURSOR_OFFSETS
 
@@ -264,6 +266,7 @@ static const struct intel_device_info intel_valleyview_info = {
 	.has_fpga_dbg = 1, \
 	.has_psr = 1, \
 	.has_resource_streamer = 1, \
+	.has_rc6p = 0 /*RC6p excludes HSW*/, \
 	.has_runtime_pm = 1
 
 static const struct intel_device_info intel_haswell_info = {
-- 
1.9.1

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[PATCH v3 10/21] drm/i915: Move HAS_DP_MST definition to platform definition

[Carlos Santa]

Moving all GPU features to the platform struct definition allows for
	- standard place when adding new features from new platforms
	- possible to see supported features when dumping struct
	  definitions

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 4 ++--
 drivers/gpu/drm/i915/i915_pci.c | 2 ++
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 611771b..c4621ae 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -776,6 +776,7 @@ struct intel_csr {
 	func(has_resource_streamer) sep \
 	func(has_rc6) sep \
 	func(has_rc6p) sep \
+	func(has_dp_mst) sep \
 	func(has_pipe_cxsr) sep \
 	func(has_hotplug) sep \
 	func(cursor_needs_physical) sep \
@@ -2768,8 +2769,7 @@ struct drm_i915_cmd_table {
 
 #define HAS_IPS(dev)		(IS_HSW_ULT(dev) || IS_BROADWELL(dev))
 
-#define HAS_DP_MST(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
-				 INTEL_INFO(dev)->gen >= 9)
+#define HAS_DP_MST(dev)		(INTEL_INFO(dev)->has_dp_mst)
 
 #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index ce78a18..ba0f5c8f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -266,6 +266,7 @@ static const struct intel_device_info intel_valleyview_info = {
 	.has_fpga_dbg = 1, \
 	.has_psr = 1, \
 	.has_resource_streamer = 1, \
+	.has_dp_mst = 1, \
 	.has_rc6p = 0 /*RC6p excludes HSW*/, \
 	.has_runtime_pm = 1
 
@@ -335,6 +336,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.has_csr = 1,
 	.has_resource_streamer = 1,
 	.has_rc6 = 1,
+	.has_dp_mst = 1,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
 	BDW_COLORS,
-- 
1.9.1

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[PATCH v3 11/21] drm/i915: Introduce GEN5_FEATURES for device info

[Carlos Santa]

Based on the GEN7_FEATURES changes from Ben w.

Use it for ilk.

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 21 ++++++++++-----------
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index ba0f5c8f..8a50e45 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -178,21 +178,20 @@ static const struct intel_device_info intel_pineview_info = {
 	CURSOR_OFFSETS,
 };
 
+#define GEN5_FEATURES \
+	.gen = 5, .num_pipes = 2, \
+	.need_gfx_hws = 1, .has_hotplug = 1, \
+	.ring_mask = RENDER_RING | BSD_RING, \
+	GEN_DEFAULT_PIPEOFFSETS, \
+	CURSOR_OFFSETS
+
 static const struct intel_device_info intel_ironlake_d_info = {
-	.gen = 5, .num_pipes = 2,
-	.need_gfx_hws = 1, .has_hotplug = 1,
-	.ring_mask = RENDER_RING | BSD_RING,
-	GEN_DEFAULT_PIPEOFFSETS,
-	CURSOR_OFFSETS,
+	GEN5_FEATURES,
 };
 
 static const struct intel_device_info intel_ironlake_m_info = {
-	.gen = 5, .is_mobile = 1, .num_pipes = 2,
-	.need_gfx_hws = 1, .has_hotplug = 1,
-	.has_fbc = 1,
-	.ring_mask = RENDER_RING | BSD_RING,
-	GEN_DEFAULT_PIPEOFFSETS,
-	CURSOR_OFFSETS,
+	GEN5_FEATURES,
+	.is_mobile = 1,
 };
 
 #define GEN6_FEATURES \
-- 
1.9.1

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[PATCH v3 12/21] drm/i915: Move HAS_GMBUS_IRQ definition to platform definition

[Carlos Santa]

Moving all GPU features to the platform struct definition allows for
	- standard place when adding new features from new platforms
	- possible to see supported features when dumping struct
	  definitions

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 3 ++-
 drivers/gpu/drm/i915/i915_pci.c | 6 ++++++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c4621ae..729a91b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -777,6 +777,7 @@ struct intel_csr {
 	func(has_rc6) sep \
 	func(has_rc6p) sep \
 	func(has_dp_mst) sep \
+	func(has_gmbus_irq) sep \
 	func(has_pipe_cxsr) sep \
 	func(has_hotplug) sep \
 	func(cursor_needs_physical) sep \
@@ -2753,7 +2754,7 @@ struct drm_i915_cmd_table {
  * interrupt source and so prevents the other device from working properly.
  */
 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
-#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
+#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->has_gmbus_irq)
 
 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  * rows, which changed the alignment requirements and fence programming.
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 8a50e45..59c958a4 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -181,6 +181,7 @@ static const struct intel_device_info intel_pineview_info = {
 #define GEN5_FEATURES \
 	.gen = 5, .num_pipes = 2, \
 	.need_gfx_hws = 1, .has_hotplug = 1, \
+	.has_gmbus_irq = 1, \
 	.ring_mask = RENDER_RING | BSD_RING, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	CURSOR_OFFSETS
@@ -202,6 +203,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
 	.has_llc = 1, \
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
+	.has_gmbus_irq = 1, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	CURSOR_OFFSETS
 
@@ -222,6 +224,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
 	.has_llc = 1, \
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
+	.has_gmbus_irq = 1, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	IVB_CURSOR_OFFSETS
 
@@ -247,6 +250,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
 	.has_psr = 1, \
 	.has_runtime_pm = 1, \
 	.has_rc6 = 1, \
+	.has_gmbus_irq = 1, \
 	.need_gfx_hws = 1, .has_hotplug = 1, \
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 	.display_mmio_offset = VLV_DISPLAY_BASE, \
@@ -300,6 +304,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_runtime_pm = 1,
 	.has_resource_streamer = 1,
 	.has_rc6 = 1,
+	.has_gmbus_irq = 1,
 	.display_mmio_offset = VLV_DISPLAY_BASE,
 	GEN_CHV_PIPEOFFSETS,
 	CURSOR_OFFSETS,
@@ -336,6 +341,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.has_resource_streamer = 1,
 	.has_rc6 = 1,
 	.has_dp_mst = 1,
+	.has_gmbus_irq = 1,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
 	BDW_COLORS,
-- 
1.9.1

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[PATCH v3 13/21] drm/i915: Introduce GEN4_FEATURES for device info

[Carlos Santa]

Based on the GEN7_FEATURES changes from Ben W.

Use it for i965g, i965gm, g45 and gm45.

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 36 ++++++++++++++++++------------------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 59c958a4..356f16d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -123,23 +123,25 @@ static const struct intel_device_info intel_i945gm_info = {
 	CURSOR_OFFSETS,
 };
 
+#define GEN4_FEATURES \
+	.gen = 4, .num_pipes = 2, \
+	.has_hotplug = 1, \
+	.ring_mask = RENDER_RING, \
+	GEN_DEFAULT_PIPEOFFSETS, \
+	CURSOR_OFFSETS
+
 static const struct intel_device_info intel_i965g_info = {
-	.gen = 4, .is_broadwater = 1, .num_pipes = 2,
-	.has_hotplug = 1,
+	GEN4_FEATURES,
+	.is_broadwater = 1,
 	.has_overlay = 1,
-	.ring_mask = RENDER_RING,
-	GEN_DEFAULT_PIPEOFFSETS,
-	CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_i965gm_info = {
-	.gen = 4, .is_crestline = 1, .num_pipes = 2,
-	.is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
+	GEN4_FEATURES,
+	.is_crestline = 1,
+	.is_mobile = 1, .has_fbc = 1,
 	.has_overlay = 1,
 	.supports_tv = 1,
-	.ring_mask = RENDER_RING,
-	GEN_DEFAULT_PIPEOFFSETS,
-	CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_g33_info = {
@@ -152,21 +154,19 @@ static const struct intel_device_info intel_g33_info = {
 };
 
 static const struct intel_device_info intel_g45_info = {
-	.gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
-	.has_pipe_cxsr = 1, .has_hotplug = 1,
+	GEN4_FEATURES,
+	.is_g4x = 1, .need_gfx_hws = 1,
+	.has_pipe_cxsr = 1,
 	.ring_mask = RENDER_RING | BSD_RING,
-	GEN_DEFAULT_PIPEOFFSETS,
-	CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_gm45_info = {
-	.gen = 4, .is_g4x = 1, .num_pipes = 2,
+	GEN4_FEATURES,
+	.is_g4x = 1,
 	.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
-	.has_pipe_cxsr = 1, .has_hotplug = 1,
+	.has_pipe_cxsr = 1,
 	.supports_tv = 1,
 	.ring_mask = RENDER_RING | BSD_RING,
-	GEN_DEFAULT_PIPEOFFSETS,
-	CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_pineview_info = {
-- 
1.9.1

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[PATCH v3 14/21] drm/i915: Introduce GEN3_FEATURES for device info

[Carlos Santa]

Based on the GEN7_FEATURES from Ben W.

Use it for i915g, i915gm, i945g, i945gm, g33 and pnv.

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 30 ++++++++++++++----------------
 1 file changed, 14 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 356f16d..2f65898 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -88,39 +88,37 @@ static const struct intel_device_info intel_i865g_info = {
 	CURSOR_OFFSETS,
 };
 
+#define GEN3_FEATURES \
+	.gen = 3, .num_pipes = 2, \
+	.ring_mask = RENDER_RING, \
+	GEN_DEFAULT_PIPEOFFSETS, \
+	CURSOR_OFFSETS
+
 static const struct intel_device_info intel_i915g_info = {
-	.gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
+	GEN3_FEATURES,
+	.is_i915g = 1, .cursor_needs_physical = 1,
 	.has_overlay = 1, .overlay_needs_physical = 1,
-	.ring_mask = RENDER_RING,
-	GEN_DEFAULT_PIPEOFFSETS,
-	CURSOR_OFFSETS,
 };
 static const struct intel_device_info intel_i915gm_info = {
-	.gen = 3, .is_mobile = 1, .num_pipes = 2,
+	GEN3_FEATURES,
+	.is_mobile = 1,
 	.cursor_needs_physical = 1,
 	.has_overlay = 1, .overlay_needs_physical = 1,
 	.supports_tv = 1,
 	.has_fbc = 1,
-	.ring_mask = RENDER_RING,
-	GEN_DEFAULT_PIPEOFFSETS,
-	CURSOR_OFFSETS,
 };
 static const struct intel_device_info intel_i945g_info = {
-	.gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
+	GEN3_FEATURES,
+	.has_hotplug = 1, .cursor_needs_physical = 1,
 	.has_overlay = 1, .overlay_needs_physical = 1,
-	.ring_mask = RENDER_RING,
-	GEN_DEFAULT_PIPEOFFSETS,
-	CURSOR_OFFSETS,
 };
 static const struct intel_device_info intel_i945gm_info = {
-	.gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
+	GEN3_FEATURES,
+	.is_i945gm = 1, .is_mobile = 1,
 	.has_hotplug = 1, .cursor_needs_physical = 1,
 	.has_overlay = 1, .overlay_needs_physical = 1,
 	.supports_tv = 1,
 	.has_fbc = 1,
-	.ring_mask = RENDER_RING,
-	GEN_DEFAULT_PIPEOFFSETS,
-	CURSOR_OFFSETS,
 };
 
 #define GEN4_FEATURES \
-- 
1.9.1

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[PATCH v3 15/21] drm/i915: Introduce GEN2_FEATURES for device info

[Carlos Santa]

Based on the GEN7_FEATURES changes from Ben W.

Use it for 830, 845g, i85x, i865g.

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 37 ++++++++++++++++---------------------
 1 file changed, 16 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 2f65898..3cd0d8f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -54,38 +54,33 @@
 #define CHV_COLORS \
 	.color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
 
+#define GEN2_FEATURES \
+	.gen = 2, \
+	.has_overlay = 1, .overlay_needs_physical = 1, \
+	.ring_mask = RENDER_RING, \
+	GEN_DEFAULT_PIPEOFFSETS, \
+	CURSOR_OFFSETS
+
 static const struct intel_device_info intel_i830_info = {
-	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
-	.has_overlay = 1, .overlay_needs_physical = 1,
-	.ring_mask = RENDER_RING,
-	GEN_DEFAULT_PIPEOFFSETS,
-	CURSOR_OFFSETS,
+	GEN2_FEATURES,
+	.is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 };
 
 static const struct intel_device_info intel_845g_info = {
-	.gen = 2, .num_pipes = 1,
-	.has_overlay = 1, .overlay_needs_physical = 1,
-	.ring_mask = RENDER_RING,
-	GEN_DEFAULT_PIPEOFFSETS,
-	CURSOR_OFFSETS,
+	GEN2_FEATURES,
+	.num_pipes = 1,
 };
 
 static const struct intel_device_info intel_i85x_info = {
-	.gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
-	.cursor_needs_physical = 1,
-	.has_overlay = 1, .overlay_needs_physical = 1,
+	GEN2_FEATURES,
+	.is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
+	.is_i85x = 1,
 	.has_fbc = 1,
-	.ring_mask = RENDER_RING,
-	GEN_DEFAULT_PIPEOFFSETS,
-	CURSOR_OFFSETS,
 };
 
 static const struct intel_device_info intel_i865g_info = {
-	.gen = 2, .num_pipes = 1,
-	.has_overlay = 1, .overlay_needs_physical = 1,
-	.ring_mask = RENDER_RING,
-	GEN_DEFAULT_PIPEOFFSETS,
-	CURSOR_OFFSETS,
+	GEN2_FEATURES,
+	.num_pipes = 1,
 };
 
 #define GEN3_FEATURES \
-- 
1.9.1

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[PATCH v3 16/21] drm/i915: Move HAS_HW_CONTEXTS definition to platform

[Carlos Santa]

Moving all GPU features to the platform definition allows for
	- standard place when adding new features from new platforms
	- possible to see supported features when dumping struct
	  definitions

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 3 ++-
 drivers/gpu/drm/i915/i915_pci.c | 5 +++++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 729a91b..919ae65 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -778,6 +778,7 @@ struct intel_csr {
 	func(has_rc6p) sep \
 	func(has_dp_mst) sep \
 	func(has_gmbus_irq) sep \
+	func(has_hw_contexts) sep \
 	func(has_pipe_cxsr) sep \
 	func(has_hotplug) sep \
 	func(cursor_needs_physical) sep \
@@ -2729,7 +2730,7 @@ struct drm_i915_cmd_table {
 				 HAS_EDRAM(dev))
 #define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)
 
-#define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 6)
+#define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->has_hw_contexts)
 #define HAS_LOGICAL_RING_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 8)
 #define USES_PPGTT(dev)		(i915.enable_ppgtt)
 #define USES_FULL_PPGTT(dev)	(i915.enable_ppgtt >= 2)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 3cd0d8f..9d42b68 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -196,6 +196,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
 	.has_llc = 1, \
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
+	.has_hw_contexts = 1, \
 	.has_gmbus_irq = 1, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	CURSOR_OFFSETS
@@ -218,6 +219,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
 	.has_gmbus_irq = 1, \
+	.has_hw_contexts = 1, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	IVB_CURSOR_OFFSETS
 
@@ -244,6 +246,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
 	.has_runtime_pm = 1, \
 	.has_rc6 = 1, \
 	.has_gmbus_irq = 1, \
+	.has_hw_contexts = 1, \
 	.need_gfx_hws = 1, .has_hotplug = 1, \
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 	.display_mmio_offset = VLV_DISPLAY_BASE, \
@@ -298,6 +301,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_resource_streamer = 1,
 	.has_rc6 = 1,
 	.has_gmbus_irq = 1,
+	.has_hw_contexts = 1,
 	.display_mmio_offset = VLV_DISPLAY_BASE,
 	GEN_CHV_PIPEOFFSETS,
 	CURSOR_OFFSETS,
@@ -335,6 +339,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.has_rc6 = 1,
 	.has_dp_mst = 1,
 	.has_gmbus_irq = 1,
+	.has_hw_contexts = 1,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
 	BDW_COLORS,
-- 
1.9.1

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[PATCH v3 17/21] drm/i915: Move HAS_LOGICAL_RING_CONTEXTS definition to platform

[Carlos Santa]

Moving all GPU features to the platform definition allows for
	- standard place when adding new features from new platforms
	- possible to see supported features when dumping struct
	  definitions

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 3 ++-
 drivers/gpu/drm/i915/i915_pci.c | 5 ++++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 919ae65..18c9fc5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -779,6 +779,7 @@ struct intel_csr {
 	func(has_dp_mst) sep \
 	func(has_gmbus_irq) sep \
 	func(has_hw_contexts) sep \
+	func(has_logical_ring_contexts) sep \
 	func(has_pipe_cxsr) sep \
 	func(has_hotplug) sep \
 	func(cursor_needs_physical) sep \
@@ -2731,7 +2732,7 @@ struct drm_i915_cmd_table {
 #define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)
 
 #define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->has_hw_contexts)
-#define HAS_LOGICAL_RING_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 8)
+#define HAS_LOGICAL_RING_CONTEXTS(dev)	(INTEL_INFO(dev)->has_logical_ring_contexts)
 #define USES_PPGTT(dev)		(i915.enable_ppgtt)
 #define USES_FULL_PPGTT(dev)	(i915.enable_ppgtt >= 2)
 #define USES_FULL_48BIT_PPGTT(dev)	(i915.enable_ppgtt == 3)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 9d42b68..db15fc2 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -276,7 +276,8 @@ static const struct intel_device_info intel_haswell_info = {
 
 #define BDW_FEATURES \
 	HSW_FEATURES, \
-	BDW_COLORS
+	BDW_COLORS, \
+	.has_logical_ring_contexts = 1
 
 static const struct intel_device_info intel_broadwell_info = {
 	BDW_FEATURES,
@@ -302,6 +303,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_rc6 = 1,
 	.has_gmbus_irq = 1,
 	.has_hw_contexts = 1,
+	.has_logical_ring_contexts = 1,
 	.display_mmio_offset = VLV_DISPLAY_BASE,
 	GEN_CHV_PIPEOFFSETS,
 	CURSOR_OFFSETS,
@@ -340,6 +342,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.has_dp_mst = 1,
 	.has_gmbus_irq = 1,
 	.has_hw_contexts = 1,
+	.has_logical_ring_contexts = 1,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
 	BDW_COLORS,
-- 
1.9.1

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[PATCH v3 18/21] drm/i915: Move HAS_L3_DPF definition to platform definition

[Carlos Santa]

Moving all GPU features to the platform definition allows for
	- standard place when adding new features from new platforms
	- possible to see supported features when dumping struct
	  definitions

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 3 ++-
 drivers/gpu/drm/i915/i915_pci.c | 4 ++++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 18c9fc5..20c793f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -780,6 +780,7 @@ struct intel_csr {
 	func(has_gmbus_irq) sep \
 	func(has_hw_contexts) sep \
 	func(has_logical_ring_contexts) sep \
+	func(has_l3_dpf) sep \
 	func(has_pipe_cxsr) sep \
 	func(has_hotplug) sep \
 	func(cursor_needs_physical) sep \
@@ -2824,7 +2825,7 @@ struct drm_i915_cmd_table {
 			       IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 
 /* DPF == dynamic parity feature */
-#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
+#define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf)
 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
 
 #define GT_FREQUENCY_MULTIPLIER 50
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index db15fc2..d219a01 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -226,18 +226,21 @@ static const struct intel_device_info intel_sandybridge_m_info = {
 static const struct intel_device_info intel_ivybridge_d_info = {
 	GEN7_FEATURES,
 	.is_ivybridge = 1,
+	.has_l3_dpf = 1,
 };
 
 static const struct intel_device_info intel_ivybridge_m_info = {
 	GEN7_FEATURES,
 	.is_ivybridge = 1,
 	.is_mobile = 1,
+	.has_l3_dpf = 1,
 };
 
 static const struct intel_device_info intel_ivybridge_q_info = {
 	GEN7_FEATURES,
 	.is_ivybridge = 1,
 	.num_pipes = 0, /* legal, last one wins */
+	.has_l3_dpf = 1,
 };
 
 #define VLV_FEATURES  \
@@ -272,6 +275,7 @@ static const struct intel_device_info intel_valleyview_info = {
 static const struct intel_device_info intel_haswell_info = {
 	HSW_FEATURES,
 	.is_haswell = 1,
+	.has_l3_dpf = 1,
 };
 
 #define BDW_FEATURES \
-- 
1.9.1

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[PATCH v3 19/21] drm/i915: Move HAS_GMCH_DISPLAY definition to platform

[Carlos Santa]

Moving all GPU features to the platform definition allows for
	- standard place when adding new features from new platforms
	- possible to see supported features when dumping struct
	  definitions

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 4 ++--
 drivers/gpu/drm/i915/i915_pci.c | 5 +++++
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 20c793f..233feb9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -781,6 +781,7 @@ struct intel_csr {
 	func(has_hw_contexts) sep \
 	func(has_logical_ring_contexts) sep \
 	func(has_l3_dpf) sep \
+	func(has_gmch_display) sep \
 	func(has_pipe_cxsr) sep \
 	func(has_hotplug) sep \
 	func(cursor_needs_physical) sep \
@@ -2821,8 +2822,7 @@ struct drm_i915_cmd_table {
 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
 
-#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
-			       IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->has_gmch_display)
 
 /* DPF == dynamic parity feature */
 #define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d219a01..1c2f5fa 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -57,6 +57,7 @@
 #define GEN2_FEATURES \
 	.gen = 2, \
 	.has_overlay = 1, .overlay_needs_physical = 1, \
+	.has_gmch_display = 1, \
 	.ring_mask = RENDER_RING, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	CURSOR_OFFSETS
@@ -85,6 +86,7 @@ static const struct intel_device_info intel_i865g_info = {
 
 #define GEN3_FEATURES \
 	.gen = 3, .num_pipes = 2, \
+	.has_gmch_display = 1, \
 	.ring_mask = RENDER_RING, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	CURSOR_OFFSETS
@@ -119,6 +121,7 @@ static const struct intel_device_info intel_i945gm_info = {
 #define GEN4_FEATURES \
 	.gen = 4, .num_pipes = 2, \
 	.has_hotplug = 1, \
+	.has_gmch_display = 1, \
 	.ring_mask = RENDER_RING, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	CURSOR_OFFSETS
@@ -250,6 +253,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
 	.has_rc6 = 1, \
 	.has_gmbus_irq = 1, \
 	.has_hw_contexts = 1, \
+	.has_gmch_display = 1, \
 	.need_gfx_hws = 1, .has_hotplug = 1, \
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 	.display_mmio_offset = VLV_DISPLAY_BASE, \
@@ -308,6 +312,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_gmbus_irq = 1,
 	.has_hw_contexts = 1,
 	.has_logical_ring_contexts = 1,
+	.has_gmch_display = 1,
 	.display_mmio_offset = VLV_DISPLAY_BASE,
 	GEN_CHV_PIPEOFFSETS,
 	CURSOR_OFFSETS,
-- 
1.9.1

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[PATCH v3 20/21] drm/i915: Make HWS_NEEDS_PHYSICAL the exception

[Carlos Santa]

Make the .hws_needs_physical the exception by switching the flag
on earlier platforms since they are fewer to support. Remove the flag on
later GPUs hardware since they all use GTT hws by default.

Switch the logic as well in the driver to reflect this change.

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         |  4 ++--
 drivers/gpu/drm/i915/i915_gpu_error.c   |  2 +-
 drivers/gpu/drm/i915/i915_pci.c         | 27 +++++++++++++++++----------
 drivers/gpu/drm/i915/intel_ringbuffer.c | 20 ++++++++++----------
 4 files changed, 30 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 233feb9..8e0e0fa 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -755,7 +755,7 @@ struct intel_csr {
 	func(is_i915g) sep \
 	func(is_i945gm) sep \
 	func(is_g33) sep \
-	func(need_gfx_hws) sep \
+	func(hws_needs_physical) sep \
 	func(is_g4x) sep \
 	func(is_pineview) sep \
 	func(is_broadwater) sep \
@@ -2731,7 +2731,7 @@ struct drm_i915_cmd_table {
 #define HAS_EDRAM(dev)		(!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
 #define HAS_WT(dev)		((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
 				 HAS_EDRAM(dev))
-#define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)
+#define HWS_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->hws_needs_physical)
 
 #define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->has_hw_contexts)
 #define HAS_LOGICAL_RING_CONTEXTS(dev)	(INTEL_INFO(dev)->has_logical_ring_contexts)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index eecb870..ba68327 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1008,7 +1008,7 @@ static void error_record_engine_registers(struct drm_i915_error_state *error,
 	ee->tail = I915_READ_TAIL(engine);
 	ee->ctl = I915_READ_CTL(engine);
 
-	if (I915_NEED_GFX_HWS(dev_priv)) {
+	if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
 		i915_reg_t mmio;
 
 		if (IS_GEN7(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 1c2f5fa..c5f4078 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -58,6 +58,7 @@
 	.gen = 2, \
 	.has_overlay = 1, .overlay_needs_physical = 1, \
 	.has_gmch_display = 1, \
+	.hws_needs_physical = 1, \
 	.ring_mask = RENDER_RING, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	CURSOR_OFFSETS
@@ -95,6 +96,7 @@ static const struct intel_device_info intel_i915g_info = {
 	GEN3_FEATURES,
 	.is_i915g = 1, .cursor_needs_physical = 1,
 	.has_overlay = 1, .overlay_needs_physical = 1,
+	.hws_needs_physical = 1,
 };
 static const struct intel_device_info intel_i915gm_info = {
 	GEN3_FEATURES,
@@ -103,11 +105,13 @@ static const struct intel_device_info intel_i915gm_info = {
 	.has_overlay = 1, .overlay_needs_physical = 1,
 	.supports_tv = 1,
 	.has_fbc = 1,
+	.hws_needs_physical = 1,
 };
 static const struct intel_device_info intel_i945g_info = {
 	GEN3_FEATURES,
 	.has_hotplug = 1, .cursor_needs_physical = 1,
 	.has_overlay = 1, .overlay_needs_physical = 1,
+	.hws_needs_physical = 1,
 };
 static const struct intel_device_info intel_i945gm_info = {
 	GEN3_FEATURES,
@@ -116,6 +120,7 @@ static const struct intel_device_info intel_i945gm_info = {
 	.has_overlay = 1, .overlay_needs_physical = 1,
 	.supports_tv = 1,
 	.has_fbc = 1,
+	.hws_needs_physical = 1,
 };
 
 #define GEN4_FEATURES \
@@ -130,6 +135,7 @@ static const struct intel_device_info intel_i965g_info = {
 	GEN4_FEATURES,
 	.is_broadwater = 1,
 	.has_overlay = 1,
+	.hws_needs_physical = 1,
 };
 
 static const struct intel_device_info intel_i965gm_info = {
@@ -138,11 +144,12 @@ static const struct intel_device_info intel_i965gm_info = {
 	.is_mobile = 1, .has_fbc = 1,
 	.has_overlay = 1,
 	.supports_tv = 1,
+	.hws_needs_physical = 1,
 };
 
 static const struct intel_device_info intel_g33_info = {
 	.gen = 3, .is_g33 = 1, .num_pipes = 2,
-	.need_gfx_hws = 1, .has_hotplug = 1,
+	.has_hotplug = 1,
 	.has_overlay = 1,
 	.ring_mask = RENDER_RING,
 	GEN_DEFAULT_PIPEOFFSETS,
@@ -151,7 +158,7 @@ static const struct intel_device_info intel_g33_info = {
 
 static const struct intel_device_info intel_g45_info = {
 	GEN4_FEATURES,
-	.is_g4x = 1, .need_gfx_hws = 1,
+	.is_g4x = 1,
 	.has_pipe_cxsr = 1,
 	.ring_mask = RENDER_RING | BSD_RING,
 };
@@ -159,7 +166,7 @@ static const struct intel_device_info intel_g45_info = {
 static const struct intel_device_info intel_gm45_info = {
 	GEN4_FEATURES,
 	.is_g4x = 1,
-	.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
+	.is_mobile = 1, .has_fbc = 1,
 	.has_pipe_cxsr = 1,
 	.supports_tv = 1,
 	.ring_mask = RENDER_RING | BSD_RING,
@@ -167,7 +174,7 @@ static const struct intel_device_info intel_gm45_info = {
 
 static const struct intel_device_info intel_pineview_info = {
 	.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
-	.need_gfx_hws = 1, .has_hotplug = 1,
+	.has_hotplug = 1,
 	.has_overlay = 1,
 	.ring_mask = RENDER_RING,
 	GEN_DEFAULT_PIPEOFFSETS,
@@ -176,7 +183,7 @@ static const struct intel_device_info intel_pineview_info = {
 
 #define GEN5_FEATURES \
 	.gen = 5, .num_pipes = 2, \
-	.need_gfx_hws = 1, .has_hotplug = 1, \
+	.has_hotplug = 1, \
 	.has_gmbus_irq = 1, \
 	.ring_mask = RENDER_RING | BSD_RING, \
 	GEN_DEFAULT_PIPEOFFSETS, \
@@ -193,7 +200,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
 
 #define GEN6_FEATURES \
 	.gen = 6, .num_pipes = 2, \
-	.need_gfx_hws = 1, .has_hotplug = 1, \
+	.has_hotplug = 1, \
 	.has_fbc = 1, \
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 	.has_llc = 1, \
@@ -215,7 +222,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
 
 #define GEN7_FEATURES  \
 	.gen = 7, .num_pipes = 3, \
-	.need_gfx_hws = 1, .has_hotplug = 1, \
+	.has_hotplug = 1, \
 	.has_fbc = 1, \
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 	.has_llc = 1, \
@@ -254,7 +261,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
 	.has_gmbus_irq = 1, \
 	.has_hw_contexts = 1, \
 	.has_gmch_display = 1, \
-	.need_gfx_hws = 1, .has_hotplug = 1, \
+	.has_hotplug = 1, \
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 	.display_mmio_offset = VLV_DISPLAY_BASE, \
 	GEN_DEFAULT_PIPEOFFSETS, \
@@ -302,7 +309,7 @@ static const struct intel_device_info intel_broadwell_gt3_info = {
 
 static const struct intel_device_info intel_cherryview_info = {
 	.gen = 8, .num_pipes = 3,
-	.need_gfx_hws = 1, .has_hotplug = 1,
+	.has_hotplug = 1,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 	.is_cherryview = 1,
 	.has_psr = 1,
@@ -337,7 +344,7 @@ static const struct intel_device_info intel_skylake_gt3_info = {
 static const struct intel_device_info intel_broxton_info = {
 	.is_broxton = 1,
 	.gen = 9,
-	.need_gfx_hws = 1, .has_hotplug = 1,
+	.has_hotplug = 1,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 	.num_pipes = 3,
 	.has_ddi = 1,
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e08a1e1..f19ce8a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -559,10 +559,10 @@ static int init_ring_common(struct intel_engine_cs *engine)
 		}
 	}
 
-	if (I915_NEED_GFX_HWS(dev_priv))
-		intel_ring_setup_status_page(engine);
-	else
+	if (HWS_NEEDS_PHYSICAL(dev_priv))
 		ring_setup_phys_status_page(engine);
+	else
+		intel_ring_setup_status_page(engine);
 
 	/* Enforce ordering by reading HEAD register back */
 	I915_READ_HEAD(engine);
@@ -2167,13 +2167,13 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine)
 	}
 	engine->buffer = ring;
 
-	if (I915_NEED_GFX_HWS(dev_priv)) {
-		ret = init_status_page(engine);
+	if (HWS_NEEDS_PHYSICAL(dev_priv)) {
+		WARN_ON(engine->id != RCS);
+		ret = init_phys_status_page(engine);
 		if (ret)
 			goto error;
 	} else {
-		WARN_ON(engine->id != RCS);
-		ret = init_phys_status_page(engine);
+		ret = init_status_page(engine);
 		if (ret)
 			goto error;
 	}
@@ -2213,11 +2213,11 @@ void intel_engine_cleanup(struct intel_engine_cs *engine)
 	if (engine->cleanup)
 		engine->cleanup(engine);
 
-	if (I915_NEED_GFX_HWS(dev_priv)) {
-		cleanup_status_page(engine);
-	} else {
+	if (HWS_NEEDS_PHYSICAL(dev_priv)) {
 		WARN_ON(engine->id != RCS);
 		cleanup_phys_status_page(engine);
+	} else {
+		cleanup_status_page(engine);
 	}
 
 	intel_engine_cleanup_common(engine);
-- 
1.9.1

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[PATCH v3 21/21] drm/i915: Move HAS_GUC definition to platform definition

[Carlos Santa]

Moving all GPU features to the platform definition allows for
	- standard place when adding new features from new platform
	- possible to see supported features when dumping struct
          definitions

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 3 ++-
 drivers/gpu/drm/i915/i915_pci.c | 5 +++++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8e0e0fa..497854e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -782,6 +782,7 @@ struct intel_csr {
 	func(has_logical_ring_contexts) sep \
 	func(has_l3_dpf) sep \
 	func(has_gmch_display) sep \
+	func(has_guc) sep \
 	func(has_pipe_cxsr) sep \
 	func(has_hotplug) sep \
 	func(cursor_needs_physical) sep \
@@ -2790,7 +2791,7 @@ struct drm_i915_cmd_table {
  * command submission once loaded. But these are logically independent
  * properties, so we have separate macros to test them.
  */
-#define HAS_GUC(dev)		(IS_GEN9(dev))
+#define HAS_GUC(dev)		(INTEL_INFO(dev)->has_guc)
 #define HAS_GUC_UCODE(dev)	(HAS_GUC(dev))
 #define HAS_GUC_SCHED(dev)	(HAS_GUC(dev))
 
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index c5f4078..02a7619 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -331,6 +331,7 @@ static const struct intel_device_info intel_skylake_info = {
 	.is_skylake = 1,
 	.gen = 9,
 	.has_csr = 1,
+	.has_guc = 1,
 };
 
 static const struct intel_device_info intel_skylake_gt3_info = {
@@ -338,6 +339,7 @@ static const struct intel_device_info intel_skylake_gt3_info = {
 	.is_skylake = 1,
 	.gen = 9,
 	.has_csr = 1,
+	.has_guc = 1,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
@@ -359,6 +361,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.has_gmbus_irq = 1,
 	.has_hw_contexts = 1,
 	.has_logical_ring_contexts = 1,
+	.has_guc = 1,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
 	BDW_COLORS,
@@ -369,6 +372,7 @@ static const struct intel_device_info intel_kabylake_info = {
 	.is_kabylake = 1,
 	.gen = 9,
 	.has_csr = 1,
+	.has_guc = 1,
 };
 
 static const struct intel_device_info intel_kabylake_gt3_info = {
@@ -376,6 +380,7 @@ static const struct intel_device_info intel_kabylake_gt3_info = {
 	.is_kabylake = 1,
 	.gen = 9,
 	.has_csr = 1,
+	.has_guc = 1,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
-- 
1.9.1

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Re: [PATCH v3 05/21] drm/i915: Get rid of HAS_CORE_RING_FREQ

[Chris Wilson]

On Tue, Aug 09, 2016 at 11:45:11AM -0700, Carlos Santa wrote:
> No need for HAS_CORE_RING_FREQ as that flag is actually the same as
> .has_llc. Feedback from V. Syrjala.
> 
> Signed-off-by: Carlos Santa <carlos.santa@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 3 ++-
>  drivers/gpu/drm/i915/i915_drv.h     | 4 ----
>  2 files changed, 2 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 9bd4158..01b6735 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1898,11 +1898,12 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
>  	struct drm_info_node *node = m->private;
>  	struct drm_device *dev = node->minor->dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct intel_device_info *info = mkwrite_device_info(dev_priv);
>  	int ret = 0;
>  	int gpu_freq, ia_freq;
>  	unsigned int max_gpu_freq, min_gpu_freq;
>  
> -	if (!HAS_CORE_RING_FREQ(dev)) {
> +	if (!info->has_llc) {

Why do you need write access?

	if (INTEL_INFO(dev_priv)->has_llc)

or even if (HAS_LLC(dev_priv).
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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✗ Ro.CI.BAT: failure for drm/i915: Organize most GPU features by platform (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Organize most GPU features by platform (rev3)
URL   : https://patchwork.freedesktop.org/series/10102/
State : failure

== Summary ==

Series 10102v3 drm/i915: Organize most GPU features by platform
http://patchwork.freedesktop.org/api/1.0/series/10102/revisions/3/mbox

Test kms_cursor_legacy:
        Subgroup basic-flip-vs-cursor-legacy:
                pass       -> FAIL       (ro-byt-n2820)
                pass       -> FAIL       (ro-bdw-i5-5250u)
                pass       -> FAIL       (ro-skl3-i5-6260u)
        Subgroup basic-flip-vs-cursor-varying-size:
                pass       -> FAIL       (ro-skl3-i5-6260u)
Test kms_pipe_crc_basic:
        Subgroup read-crc-pipe-c-frame-sequence:
                fail       -> PASS       (ro-ivb-i7-3770)
        Subgroup suspend-read-crc-pipe-a:
                incomplete -> PASS       (fi-hsw-i7-4770k)
        Subgroup suspend-read-crc-pipe-b:
                pass       -> DMESG-WARN (ro-bdw-i7-5600u)
        Subgroup suspend-read-crc-pipe-c:
                dmesg-warn -> SKIP       (ro-bdw-i5-5250u)
Test pm_rpm:
        Subgroup basic-pci-d3-state:
                pass       -> SKIP       (fi-snb-i7-2600)
        Subgroup basic-rte:
                pass       -> SKIP       (fi-snb-i7-2600)

fi-hsw-i7-4770k  total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-kbl-qkkr      total:244  pass:185  dwarn:29  dfail:0   fail:3   skip:27 
fi-skl-i5-6260u  total:244  pass:224  dwarn:4   dfail:0   fail:2   skip:14 
fi-snb-i7-2600   total:244  pass:200  dwarn:0   dfail:0   fail:0   skip:44 
ro-bdw-i5-5250u  total:240  pass:219  dwarn:1   dfail:0   fail:1   skip:19 
ro-bdw-i7-5557U  total:240  pass:220  dwarn:1   dfail:0   fail:0   skip:19 
ro-bdw-i7-5600u  total:240  pass:205  dwarn:2   dfail:0   fail:1   skip:32 
ro-bsw-n3050     total:240  pass:193  dwarn:1   dfail:0   fail:4   skip:42 
ro-byt-n2820     total:240  pass:197  dwarn:0   dfail:0   fail:3   skip:40 
ro-hsw-i3-4010u  total:240  pass:214  dwarn:0   dfail:0   fail:0   skip:26 
ro-hsw-i7-4770r  total:240  pass:214  dwarn:0   dfail:0   fail:0   skip:26 
ro-ilk1-i5-650   total:235  pass:173  dwarn:0   dfail:0   fail:2   skip:60 
ro-ivb-i7-3770   total:240  pass:205  dwarn:0   dfail:0   fail:0   skip:35 
ro-ivb2-i7-3770  total:240  pass:209  dwarn:0   dfail:0   fail:0   skip:31 
ro-skl3-i5-6260u total:240  pass:222  dwarn:0   dfail:0   fail:4   skip:14 
fi-skl-i7-6700k failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1804/

d0e3a4b drm-intel-nightly: 2016y-08m-09d-20h-18m-38s UTC integration manifest
3a679fc drm/i915: Move HAS_GUC definition to platform definition
9e89288 drm/i915: Make HWS_NEEDS_PHYSICAL the exception
9e09f99 drm/i915: Move HAS_GMCH_DISPLAY definition to platform
0510fdc drm/i915: Move HAS_L3_DPF definition to platform definition
de65dfb drm/i915: Move HAS_LOGICAL_RING_CONTEXTS definition to platform
234544c drm/i915: Move HAS_HW_CONTEXTS definition to platform
433c31a drm/i915: Introduce GEN2_FEATURES for device info
6e59db7 drm/i915: Introduce GEN3_FEATURES for device info
d30d05b drm/i915: Introduce GEN4_FEATURES for device info
f4deaca drm/i915: Move HAS_GMBUS_IRQ definition to platform definition
70ff07fa drm/i915: Introduce GEN5_FEATURES for device info
0879461 drm/i915: Move HAS_DP_MST definition to platform definition
35959a8 drm/i915: Move HAS_RC6p definition to platform definition
f06ae57 drm/i915: Move HAS_RC6 definition to platform definition
b9e3d01 drm/i915: Move HAS_RESOURCE_STREAMER definition to platform definition
057f338 drm/i915 Move HAS_CSR definition to platform definition
a93cc8b drm/i915: Get rid of HAS_CORE_RING_FREQ
8bc6c29 drm/i915: Move HAS_RUNTIME_PM definition to platform
574b841 drm/i915: Introduce GEN6_FEATURES for device info
0772bef drm/i915: Remove .is_mobile field from platform struct
45bc446 drm/i915: Move HAS_PSR definition to platform struct definition

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Re: [PATCH v3 05/21] drm/i915: Get rid of HAS_CORE_RING_FREQ

[Rodrigo Vivi]

On Tue, Aug 09, 2016 at 07:59:38PM +0100, Chris Wilson wrote:
> On Tue, Aug 09, 2016 at 11:45:11AM -0700, Carlos Santa wrote:
> > No need for HAS_CORE_RING_FREQ as that flag is actually the same as
> > .has_llc. Feedback from V. Syrjala.
> > 
> > Signed-off-by: Carlos Santa <carlos.santa@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_debugfs.c | 3 ++-
> >  drivers/gpu/drm/i915/i915_drv.h     | 4 ----
> >  2 files changed, 2 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 9bd4158..01b6735 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -1898,11 +1898,12 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
> >  	struct drm_info_node *node = m->private;
> >  	struct drm_device *dev = node->minor->dev;
> >  	struct drm_i915_private *dev_priv = to_i915(dev);
> > +	struct intel_device_info *info = mkwrite_device_info(dev_priv);
> >  	int ret = 0;
> >  	int gpu_freq, ia_freq;
> >  	unsigned int max_gpu_freq, min_gpu_freq;
> >  
> > -	if (!HAS_CORE_RING_FREQ(dev)) {
> > +	if (!info->has_llc) {
> 
> Why do you need write access?
> 
> 	if (INTEL_INFO(dev_priv)->has_llc)
> 
> or even if (HAS_LLC(dev_priv).

indeed better with HAS_() than with write access.

> -Chris
> 
> -- 
> Chris Wilson, Intel Open Source Technology Centre
> _______________________________________________
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Re: [PATCH v3 02/21] drm/i915: Remove .is_mobile field from platform struct

[Rodrigo Vivi]

On Tue, Aug 09, 2016 at 11:45:08AM -0700, Carlos Santa wrote:
> As recommended by Ville Syrjala removing .is_mobile field from the
> platform struct definition for vlv and hsw+ GPUs as there's no need to
> make the distinction in later hardware anymore. Keep it for older GPUs
> as it is still needed for ilk-ivb.

good idea!

> 
> Signed-off-by: Carlos Santa <carlos.santa@intel.com>


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  arch/x86/kernel/early-quirks.c  |  9 +++------
>  drivers/gpu/drm/i915/i915_pci.c | 45 ++++++++---------------------------------
>  include/drm/i915_pciids.h       | 38 +++++++++++++---------------------
>  3 files changed, 25 insertions(+), 67 deletions(-)
> 
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index de7501e..e6bd329 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -512,8 +512,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
>  	INTEL_I915GM_IDS(&gen3_early_ops),
>  	INTEL_I945G_IDS(&gen3_early_ops),
>  	INTEL_I945GM_IDS(&gen3_early_ops),
> -	INTEL_VLV_M_IDS(&gen6_early_ops),
> -	INTEL_VLV_D_IDS(&gen6_early_ops),
> +	INTEL_VLV_IDS(&gen6_early_ops),
>  	INTEL_PINEVIEW_IDS(&gen3_early_ops),
>  	INTEL_I965G_IDS(&gen3_early_ops),
>  	INTEL_G33_IDS(&gen3_early_ops),
> @@ -526,10 +525,8 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
>  	INTEL_SNB_M_IDS(&gen6_early_ops),
>  	INTEL_IVB_M_IDS(&gen6_early_ops),
>  	INTEL_IVB_D_IDS(&gen6_early_ops),
> -	INTEL_HSW_D_IDS(&gen6_early_ops),
> -	INTEL_HSW_M_IDS(&gen6_early_ops),
> -	INTEL_BDW_M_IDS(&gen8_early_ops),
> -	INTEL_BDW_D_IDS(&gen8_early_ops),
> +	INTEL_HSW_IDS(&gen6_early_ops),
> +	INTEL_BDW_IDS(&gen8_early_ops),
>  	INTEL_CHV_IDS(&chv_early_ops),
>  	INTEL_SKL_IDS(&gen9_early_ops),
>  	INTEL_BXT_IDS(&gen9_early_ops),
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index e1caa0b..b5ec8a7 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -250,13 +250,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
>  	GEN_DEFAULT_PIPEOFFSETS, \
>  	CURSOR_OFFSETS
>  
> -static const struct intel_device_info intel_valleyview_m_info = {
> -	VLV_FEATURES,
> -	.is_valleyview = 1,
> -	.is_mobile = 1,
> -};
> -
> -static const struct intel_device_info intel_valleyview_d_info = {
> +static const struct intel_device_info intel_valleyview_info = {
>  	VLV_FEATURES,
>  	.is_valleyview = 1,
>  };
> @@ -268,47 +262,28 @@ static const struct intel_device_info intel_valleyview_d_info = {
>  	.has_fpga_dbg = 1, \
>  	.has_psr = 1
>  
> -static const struct intel_device_info intel_haswell_d_info = {
> +static const struct intel_device_info intel_haswell_info = {
>  	HSW_FEATURES,
>  	.is_haswell = 1,
>  };
>  
> -static const struct intel_device_info intel_haswell_m_info = {
> -	HSW_FEATURES,
> -	.is_haswell = 1,
> -	.is_mobile = 1,
> -};
> -
>  #define BDW_FEATURES \
>  	HSW_FEATURES, \
>  	BDW_COLORS
>  
> -static const struct intel_device_info intel_broadwell_d_info = {
> +static const struct intel_device_info intel_broadwell_info = {
>  	BDW_FEATURES,
>  	.gen = 8,
>  	.is_broadwell = 1,
>  };
>  
> -static const struct intel_device_info intel_broadwell_m_info = {
> -	BDW_FEATURES,
> -	.gen = 8, .is_mobile = 1,
> -	.is_broadwell = 1,
> -};
> -
> -static const struct intel_device_info intel_broadwell_gt3d_info = {
> +static const struct intel_device_info intel_broadwell_gt3_info = {
>  	BDW_FEATURES,
>  	.gen = 8,
>  	.is_broadwell = 1,
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
>  };
>  
> -static const struct intel_device_info intel_broadwell_gt3m_info = {
> -	BDW_FEATURES,
> -	.gen = 8, .is_mobile = 1,
> -	.is_broadwell = 1,
> -	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
> -};
> -
>  static const struct intel_device_info intel_cherryview_info = {
>  	.gen = 8, .num_pipes = 3,
>  	.need_gfx_hws = 1, .has_hotplug = 1,
> @@ -390,14 +365,10 @@ static const struct pci_device_id pciidlist[] = {
>  	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
>  	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
>  	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
> -	INTEL_HSW_D_IDS(&intel_haswell_d_info),
> -	INTEL_HSW_M_IDS(&intel_haswell_m_info),
> -	INTEL_VLV_M_IDS(&intel_valleyview_m_info),
> -	INTEL_VLV_D_IDS(&intel_valleyview_d_info),
> -	INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),
> -	INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),
> -	INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),
> -	INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),
> +	INTEL_HSW_IDS(&intel_haswell_info),
> +	INTEL_VLV_IDS(&intel_valleyview_info),
> +	INTEL_BDW_GT12_IDS(&intel_broadwell_info),
> +	INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
>  	INTEL_CHV_IDS(&intel_cherryview_info),
>  	INTEL_SKL_GT1_IDS(&intel_skylake_info),
>  	INTEL_SKL_GT2_IDS(&intel_skylake_info),
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 33466bf..0d5f426 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -134,7 +134,7 @@
>  #define INTEL_IVB_Q_IDS(info) \
>  	INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
>  
> -#define INTEL_HSW_D_IDS(info) \
> +#define INTEL_HSW_IDS(info) \
>  	INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
>  	INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
>  	INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
> @@ -179,9 +179,7 @@
>  	INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
>  	INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
>  	INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
> -	INTEL_VGA_DEVICE(0x0D2E, info)  /* CRW GT3 reserved */ \
> -
> -#define INTEL_HSW_M_IDS(info) \
> +	INTEL_VGA_DEVICE(0x0D2E, info),  /* CRW GT3 reserved */ \
>  	INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
>  	INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
>  	INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
> @@ -198,17 +196,15 @@
>  	INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
>  	INTEL_VGA_DEVICE(0x0D26, info)  /* CRW GT3 mobile */
>  
> -#define INTEL_VLV_M_IDS(info) \
> +#define INTEL_VLV_IDS(info) \
>  	INTEL_VGA_DEVICE(0x0f30, info), \
>  	INTEL_VGA_DEVICE(0x0f31, info), \
>  	INTEL_VGA_DEVICE(0x0f32, info), \
>  	INTEL_VGA_DEVICE(0x0f33, info), \
> -	INTEL_VGA_DEVICE(0x0157, info)
> -
> -#define INTEL_VLV_D_IDS(info) \
> +	INTEL_VGA_DEVICE(0x0157, info), \
>  	INTEL_VGA_DEVICE(0x0155, info)
>  
> -#define INTEL_BDW_GT12M_IDS(info)  \
> +#define INTEL_BDW_GT12_IDS(info)  \
>  	INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
>  	INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
>  	INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
> @@ -216,21 +212,17 @@
>  	INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
>  	INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
>  	INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
> -	INTEL_VGA_DEVICE(0x161E, info)  /* GT2 ULX */
> -
> -#define INTEL_BDW_GT12D_IDS(info) \
> +	INTEL_VGA_DEVICE(0x161E, info),  /* GT2 ULX */ \
>  	INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
>  	INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \
>  	INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
>  	INTEL_VGA_DEVICE(0x161D, info)  /* GT2 Workstation */
>  
> -#define INTEL_BDW_GT3M_IDS(info) \
> +#define INTEL_BDW_GT3_IDS(info) \
>  	INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
>  	INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
>  	INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \
> -	INTEL_VGA_DEVICE(0x162E, info)  /* ULX */
> -
> -#define INTEL_BDW_GT3D_IDS(info) \
> +	INTEL_VGA_DEVICE(0x162E, info),  /* ULX */\
>  	INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
>  	INTEL_VGA_DEVICE(0x162D, info)  /* Workstation */
>  
> @@ -244,14 +236,12 @@
>  	INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
>  	INTEL_VGA_DEVICE(0x163D, info)  /* Workstation */
>  
> -#define INTEL_BDW_M_IDS(info) \
> -	INTEL_BDW_GT12M_IDS(info), \
> -	INTEL_BDW_GT3M_IDS(info), \
> -	INTEL_BDW_RSVDM_IDS(info)
> -
> -#define INTEL_BDW_D_IDS(info) \
> -	INTEL_BDW_GT12D_IDS(info), \
> -	INTEL_BDW_GT3D_IDS(info), \
> +#define INTEL_BDW_IDS(info) \
> +	INTEL_BDW_GT12_IDS(info), \
> +	INTEL_BDW_GT3_IDS(info), \
> +	INTEL_BDW_RSVDM_IDS(info), \
> +	INTEL_BDW_GT12_IDS(info), \
> +	INTEL_BDW_GT3_IDS(info), \
>  	INTEL_BDW_RSVDD_IDS(info)
>  
>  #define INTEL_CHV_IDS(info) \
> -- 
> 1.9.1
> 
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Re: [PATCH v3 04/21] drm/i915: Move HAS_RUNTIME_PM definition to platform

[Rodrigo Vivi]

On Tue, Aug 09, 2016 at 11:45:10AM -0700, Carlos Santa wrote:
> Moving all GPU features to the platform struct definition allows for
> 	- standard place when adding new features from new platforms
> 	- possible to see supported features when dumping struct
> 	  definitions
> 
> Feedback from V. Syrjala: remove runtime PM support for snb as it breaks
> hotplug support.

I believe it is better a separated patch on top of this re-org. Just in case
it needs to be reverted.

> 
> Signed-off-by: Carlos Santa <carlos.santa@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 6 ++----
>  drivers/gpu/drm/i915/i915_pci.c | 6 +++++-
>  2 files changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6f2f066..0eaf28f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -771,6 +771,7 @@ struct intel_csr {
>  	func(is_preliminary) sep \
>  	func(has_fbc) sep \
>  	func(has_psr) sep \
> +	func(has_runtime_pm) sep \
>  	func(has_pipe_cxsr) sep \
>  	func(has_hotplug) sep \
>  	func(cursor_needs_physical) sep \
> @@ -2769,10 +2770,7 @@ struct drm_i915_cmd_table {
>  #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
>  #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
>  #define HAS_PSR(dev)		(INTEL_INFO(dev)->has_psr)
> -#define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
> -				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
> -				 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
> -				 IS_KABYLAKE(dev) || IS_BROXTON(dev))
> +#define HAS_RUNTIME_PM(dev)	(INTEL_INFO(dev)->has_runtime_pm)
>  #define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
>  #define HAS_RC6p(dev)		(IS_GEN6(dev) || IS_IVYBRIDGE(dev))
>  
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index bdc2071..9d78836 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -242,6 +242,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
>  #define VLV_FEATURES  \
>  	.gen = 7, .num_pipes = 2, \
>  	.has_psr = 1, \
> +	.has_runtime_pm = 1, \
>  	.need_gfx_hws = 1, .has_hotplug = 1, \
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
>  	.display_mmio_offset = VLV_DISPLAY_BASE, \
> @@ -258,7 +259,8 @@ static const struct intel_device_info intel_valleyview_info = {
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
>  	.has_ddi = 1, \
>  	.has_fpga_dbg = 1, \
> -	.has_psr = 1
> +	.has_psr = 1, \
> +	.has_runtime_pm = 1
>  
>  static const struct intel_device_info intel_haswell_info = {
>  	HSW_FEATURES,
> @@ -288,6 +290,7 @@ static const struct intel_device_info intel_cherryview_info = {
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
>  	.is_cherryview = 1,
>  	.has_psr = 1,
> +	.has_runtime_pm = 1,
>  	.display_mmio_offset = VLV_DISPLAY_BASE,
>  	GEN_CHV_PIPEOFFSETS,
>  	CURSOR_OFFSETS,
> @@ -316,6 +319,7 @@ static const struct intel_device_info intel_broxton_info = {
>  	.has_ddi = 1,
>  	.has_fpga_dbg = 1,
>  	.has_fbc = 1,
> +	.has_runtime_pm = 1,
>  	.has_pooled_eu = 0,
>  	GEN_DEFAULT_PIPEOFFSETS,
>  	IVB_CURSOR_OFFSETS,
> -- 
> 1.9.1
> 
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Re: [PATCH v3 06/21] drm/i915 Move HAS_CSR definition to platform definition

[Rodrigo Vivi]

On Tue, Aug 09, 2016 at 11:45:12AM -0700, Carlos Santa wrote:
> Moving all GPU features to the platform struct definition allows for
> 	- standard place when adding new features from new platforms
> 	- possible to see supported features when dumping struct
> 	  definitions
> 
> Signed-off-by: Carlos Santa <carlos.santa@intel.com>


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 3 ++-
>  drivers/gpu/drm/i915/i915_pci.c | 5 +++++
>  2 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3ab63c0..14e8911 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -772,6 +772,7 @@ struct intel_csr {
>  	func(has_fbc) sep \
>  	func(has_psr) sep \
>  	func(has_runtime_pm) sep \
> +	func(has_csr) sep \
>  	func(has_pipe_cxsr) sep \
>  	func(has_hotplug) sep \
>  	func(cursor_needs_physical) sep \
> @@ -2774,7 +2775,7 @@ struct drm_i915_cmd_table {
>  #define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
>  #define HAS_RC6p(dev)		(IS_GEN6(dev) || IS_IVYBRIDGE(dev))
>  
> -#define HAS_CSR(dev)	(IS_GEN9(dev))
> +#define HAS_CSR(dev)	(INTEL_INFO(dev)->has_csr)
>  
>  /*
>   * For now, anything with a GuC requires uCode loading, and then supports
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 9d78836..21a3bc5 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -301,12 +301,14 @@ static const struct intel_device_info intel_skylake_info = {
>  	BDW_FEATURES,
>  	.is_skylake = 1,
>  	.gen = 9,
> +	.has_csr = 1,
>  };
>  
>  static const struct intel_device_info intel_skylake_gt3_info = {
>  	BDW_FEATURES,
>  	.is_skylake = 1,
>  	.gen = 9,
> +	.has_csr = 1,
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
>  };
>  
> @@ -321,6 +323,7 @@ static const struct intel_device_info intel_broxton_info = {
>  	.has_fbc = 1,
>  	.has_runtime_pm = 1,
>  	.has_pooled_eu = 0,
> +	.has_csr = 1,
>  	GEN_DEFAULT_PIPEOFFSETS,
>  	IVB_CURSOR_OFFSETS,
>  	BDW_COLORS,
> @@ -330,12 +333,14 @@ static const struct intel_device_info intel_kabylake_info = {
>  	BDW_FEATURES,
>  	.is_kabylake = 1,
>  	.gen = 9,
> +	.has_csr = 1,
>  };
>  
>  static const struct intel_device_info intel_kabylake_gt3_info = {
>  	BDW_FEATURES,
>  	.is_kabylake = 1,
>  	.gen = 9,
> +	.has_csr = 1,
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
>  };
>  
> -- 
> 1.9.1
> 
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Re: [PATCH v3 07/21] drm/i915: Move HAS_RESOURCE_STREAMER definition to platform definition

[Rodrigo Vivi]

On Tue, Aug 09, 2016 at 11:45:13AM -0700, Carlos Santa wrote:
> Moving all GPU features to the platform struct definition allows for
> 	- standard place when adding new features from new platforms
> 	- possible to see supported features when dumping struct
> 	  definitions
> 
> Signed-off-by: Carlos Santa <carlos.santa@intel.com>

This is one of those patches where only reading the patch it looks like
the definition went to the wrong place, but looking to the final results
it is possible to see that has_resource_streamer went to the correct
platforms.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 4 ++--
>  drivers/gpu/drm/i915/i915_pci.c | 3 +++
>  2 files changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 14e8911..e9d95c5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -773,6 +773,7 @@ struct intel_csr {
>  	func(has_psr) sep \
>  	func(has_runtime_pm) sep \
>  	func(has_csr) sep \
> +	func(has_resource_streamer) sep \
>  	func(has_pipe_cxsr) sep \
>  	func(has_hotplug) sep \
>  	func(cursor_needs_physical) sep \
> @@ -2786,8 +2787,7 @@ struct drm_i915_cmd_table {
>  #define HAS_GUC_UCODE(dev)	(HAS_GUC(dev))
>  #define HAS_GUC_SCHED(dev)	(HAS_GUC(dev))
>  
> -#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
> -				    INTEL_INFO(dev)->gen >= 8)
> +#define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)->has_resource_streamer)
>  
>  #define HAS_POOLED_EU(dev)	(INTEL_INFO(dev)->has_pooled_eu)
>  
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 21a3bc5..46c48ed 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -260,6 +260,7 @@ static const struct intel_device_info intel_valleyview_info = {
>  	.has_ddi = 1, \
>  	.has_fpga_dbg = 1, \
>  	.has_psr = 1, \
> +	.has_resource_streamer = 1, \
>  	.has_runtime_pm = 1
>  
>  static const struct intel_device_info intel_haswell_info = {
> @@ -291,6 +292,7 @@ static const struct intel_device_info intel_cherryview_info = {
>  	.is_cherryview = 1,
>  	.has_psr = 1,
>  	.has_runtime_pm = 1,
> +	.has_resource_streamer = 1,
>  	.display_mmio_offset = VLV_DISPLAY_BASE,
>  	GEN_CHV_PIPEOFFSETS,
>  	CURSOR_OFFSETS,
> @@ -324,6 +326,7 @@ static const struct intel_device_info intel_broxton_info = {
>  	.has_runtime_pm = 1,
>  	.has_pooled_eu = 0,
>  	.has_csr = 1,
> +	.has_resource_streamer = 1,
>  	GEN_DEFAULT_PIPEOFFSETS,
>  	IVB_CURSOR_OFFSETS,
>  	BDW_COLORS,
> -- 
> 1.9.1
> 
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Re: [PATCH v3 08/21] drm/i915: Move HAS_RC6 definition to platform definition

[Rodrigo Vivi]

On Tue, Aug 09, 2016 at 11:45:14AM -0700, Carlos Santa wrote:
> Moving all GPU features to the platform struct definition allows for
> 	- standard place when adding new features from new platforms
> 	- possible to see supported features when dumping struct
> 	  definitions
> 
> Signed-off-by: Carlos Santa <carlos.santa@intel.com>


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 3 ++-
>  drivers/gpu/drm/i915/i915_pci.c | 5 +++++
>  2 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e9d95c5..bc6df5b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -774,6 +774,7 @@ struct intel_csr {
>  	func(has_runtime_pm) sep \
>  	func(has_csr) sep \
>  	func(has_resource_streamer) sep \
> +	func(has_rc6) sep \
>  	func(has_pipe_cxsr) sep \
>  	func(has_hotplug) sep \
>  	func(cursor_needs_physical) sep \
> @@ -2773,7 +2774,7 @@ struct drm_i915_cmd_table {
>  #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
>  #define HAS_PSR(dev)		(INTEL_INFO(dev)->has_psr)
>  #define HAS_RUNTIME_PM(dev)	(INTEL_INFO(dev)->has_runtime_pm)
> -#define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
> +#define HAS_RC6(dev)		(INTEL_INFO(dev)->has_rc6)
>  #define HAS_RC6p(dev)		(IS_GEN6(dev) || IS_IVYBRIDGE(dev))
>  
>  #define HAS_CSR(dev)	(INTEL_INFO(dev)->has_csr)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 46c48ed..42108dc 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -201,6 +201,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
>  	.has_fbc = 1, \
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
>  	.has_llc = 1, \
> +	.has_rc6 = 1, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
>  	CURSOR_OFFSETS
>  
> @@ -219,6 +220,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
>  	.has_fbc = 1, \
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
>  	.has_llc = 1, \
> +	.has_rc6 = 1, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
>  	IVB_CURSOR_OFFSETS
>  
> @@ -243,6 +245,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
>  	.gen = 7, .num_pipes = 2, \
>  	.has_psr = 1, \
>  	.has_runtime_pm = 1, \
> +	.has_rc6 = 1, \
>  	.need_gfx_hws = 1, .has_hotplug = 1, \
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
>  	.display_mmio_offset = VLV_DISPLAY_BASE, \
> @@ -293,6 +296,7 @@ static const struct intel_device_info intel_cherryview_info = {
>  	.has_psr = 1,
>  	.has_runtime_pm = 1,
>  	.has_resource_streamer = 1,
> +	.has_rc6 = 1,
>  	.display_mmio_offset = VLV_DISPLAY_BASE,
>  	GEN_CHV_PIPEOFFSETS,
>  	CURSOR_OFFSETS,
> @@ -327,6 +331,7 @@ static const struct intel_device_info intel_broxton_info = {
>  	.has_pooled_eu = 0,
>  	.has_csr = 1,
>  	.has_resource_streamer = 1,
> +	.has_rc6 = 1,
>  	GEN_DEFAULT_PIPEOFFSETS,
>  	IVB_CURSOR_OFFSETS,
>  	BDW_COLORS,
> -- 
> 1.9.1
> 
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Re: [PATCH v3 09/21] drm/i915: Move HAS_RC6p definition to platform definition

[Rodrigo Vivi]

On Tue, Aug 09, 2016 at 11:45:15AM -0700, Carlos Santa wrote:
> Moving all GPU features to the platform struct definition allows for
> 	- standard place when adding new features from new platforms
> 	- possible to see supported features when dumping struct
> 	  definitions
> 
> Signed-off-by: Carlos Santa <carlos.santa@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 3 ++-
>  drivers/gpu/drm/i915/i915_pci.c | 3 +++
>  2 files changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index bc6df5b..611771b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -775,6 +775,7 @@ struct intel_csr {
>  	func(has_csr) sep \
>  	func(has_resource_streamer) sep \
>  	func(has_rc6) sep \
> +	func(has_rc6p) sep \
>  	func(has_pipe_cxsr) sep \
>  	func(has_hotplug) sep \
>  	func(cursor_needs_physical) sep \
> @@ -2775,7 +2776,7 @@ struct drm_i915_cmd_table {
>  #define HAS_PSR(dev)		(INTEL_INFO(dev)->has_psr)
>  #define HAS_RUNTIME_PM(dev)	(INTEL_INFO(dev)->has_runtime_pm)
>  #define HAS_RC6(dev)		(INTEL_INFO(dev)->has_rc6)
> -#define HAS_RC6p(dev)		(IS_GEN6(dev) || IS_IVYBRIDGE(dev))
> +#define HAS_RC6p(dev)		(INTEL_INFO(dev)->has_rc6p)
>  
>  #define HAS_CSR(dev)	(INTEL_INFO(dev)->has_csr)
>  
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 42108dc..ce78a18 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -202,6 +202,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
>  	.has_llc = 1, \
>  	.has_rc6 = 1, \
> +	.has_rc6p = 1, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
>  	CURSOR_OFFSETS
>  
> @@ -221,6 +222,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
>  	.has_llc = 1, \
>  	.has_rc6 = 1, \
> +	.has_rc6p = 1, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
>  	IVB_CURSOR_OFFSETS
>  
> @@ -264,6 +266,7 @@ static const struct intel_device_info intel_valleyview_info = {
>  	.has_fpga_dbg = 1, \
>  	.has_psr = 1, \
>  	.has_resource_streamer = 1, \
> +	.has_rc6p = 0 /*RC6p excludes HSW*/, \

better with spaces /* Comment */
But also I don't like the message content. This one seems to tell that HSW is the only platform
without RC6p.

What about: "RC6p removed-by HSW". So we kind of follow new BSpec scheme of "REMOVEDBY"

>  	.has_runtime_pm = 1
>  
>  static const struct intel_device_info intel_haswell_info = {
> -- 
> 1.9.1
> 
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Re: [PATCH v3 10/21] drm/i915: Move HAS_DP_MST definition to platform definition

[Rodrigo Vivi]

On Tue, Aug 09, 2016 at 11:45:16AM -0700, Carlos Santa wrote:
> Moving all GPU features to the platform struct definition allows for
> 	- standard place when adding new features from new platforms
> 	- possible to see supported features when dumping struct
> 	  definitions
> 
> Signed-off-by: Carlos Santa <carlos.santa@intel.com>


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 4 ++--
>  drivers/gpu/drm/i915/i915_pci.c | 2 ++
>  2 files changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 611771b..c4621ae 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -776,6 +776,7 @@ struct intel_csr {
>  	func(has_resource_streamer) sep \
>  	func(has_rc6) sep \
>  	func(has_rc6p) sep \
> +	func(has_dp_mst) sep \
>  	func(has_pipe_cxsr) sep \
>  	func(has_hotplug) sep \
>  	func(cursor_needs_physical) sep \
> @@ -2768,8 +2769,7 @@ struct drm_i915_cmd_table {
>  
>  #define HAS_IPS(dev)		(IS_HSW_ULT(dev) || IS_BROADWELL(dev))
>  
> -#define HAS_DP_MST(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
> -				 INTEL_INFO(dev)->gen >= 9)
> +#define HAS_DP_MST(dev)		(INTEL_INFO(dev)->has_dp_mst)
>  
>  #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
>  #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index ce78a18..ba0f5c8f 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -266,6 +266,7 @@ static const struct intel_device_info intel_valleyview_info = {
>  	.has_fpga_dbg = 1, \
>  	.has_psr = 1, \
>  	.has_resource_streamer = 1, \
> +	.has_dp_mst = 1, \
>  	.has_rc6p = 0 /*RC6p excludes HSW*/, \
>  	.has_runtime_pm = 1
>  
> @@ -335,6 +336,7 @@ static const struct intel_device_info intel_broxton_info = {
>  	.has_csr = 1,
>  	.has_resource_streamer = 1,
>  	.has_rc6 = 1,
> +	.has_dp_mst = 1,
>  	GEN_DEFAULT_PIPEOFFSETS,
>  	IVB_CURSOR_OFFSETS,
>  	BDW_COLORS,
> -- 
> 1.9.1
> 
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Re: [PATCH v3 11/21] drm/i915: Introduce GEN5_FEATURES for device info

[Rodrigo Vivi]

On Tue, Aug 09, 2016 at 11:45:17AM -0700, Carlos Santa wrote:
> Based on the GEN7_FEATURES changes from Ben w.

Maybe this comment and also on the previous GEN6_FEATURE could be improved.
And also good to Cc people you are mentioning on the commit message.

Besides I still believe we should add this but also making the next platform get based on the previous one.
Anyway this can be done later so I won't block the progress here. Feel free to use

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>



> 
> Use it for ilk.



> 
> Signed-off-by: Carlos Santa <carlos.santa@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_pci.c | 21 ++++++++++-----------
>  1 file changed, 10 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index ba0f5c8f..8a50e45 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -178,21 +178,20 @@ static const struct intel_device_info intel_pineview_info = {
>  	CURSOR_OFFSETS,
>  };
>  
> +#define GEN5_FEATURES \
> +	.gen = 5, .num_pipes = 2, \
> +	.need_gfx_hws = 1, .has_hotplug = 1, \
> +	.ring_mask = RENDER_RING | BSD_RING, \
> +	GEN_DEFAULT_PIPEOFFSETS, \
> +	CURSOR_OFFSETS
> +
>  static const struct intel_device_info intel_ironlake_d_info = {
> -	.gen = 5, .num_pipes = 2,
> -	.need_gfx_hws = 1, .has_hotplug = 1,
> -	.ring_mask = RENDER_RING | BSD_RING,
> -	GEN_DEFAULT_PIPEOFFSETS,
> -	CURSOR_OFFSETS,
> +	GEN5_FEATURES,
>  };
>  
>  static const struct intel_device_info intel_ironlake_m_info = {
> -	.gen = 5, .is_mobile = 1, .num_pipes = 2,
> -	.need_gfx_hws = 1, .has_hotplug = 1,
> -	.has_fbc = 1,
> -	.ring_mask = RENDER_RING | BSD_RING,
> -	GEN_DEFAULT_PIPEOFFSETS,
> -	CURSOR_OFFSETS,
> +	GEN5_FEATURES,
> +	.is_mobile = 1,
>  };
>  
>  #define GEN6_FEATURES \
> -- 
> 1.9.1
> 
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Re: [PATCH v3 12/21] drm/i915: Move HAS_GMBUS_IRQ definition to platform definition

[Rodrigo Vivi]

On Tue, Aug 09, 2016 at 11:45:18AM -0700, Carlos Santa wrote:
> Moving all GPU features to the platform struct definition allows for
> 	- standard place when adding new features from new platforms
> 	- possible to see supported features when dumping struct
> 	  definitions
> 


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> Signed-off-by: Carlos Santa <carlos.santa@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 3 ++-
>  drivers/gpu/drm/i915/i915_pci.c | 6 ++++++
>  2 files changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c4621ae..729a91b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -777,6 +777,7 @@ struct intel_csr {
>  	func(has_rc6) sep \
>  	func(has_rc6p) sep \
>  	func(has_dp_mst) sep \
> +	func(has_gmbus_irq) sep \
>  	func(has_pipe_cxsr) sep \
>  	func(has_hotplug) sep \
>  	func(cursor_needs_physical) sep \
> @@ -2753,7 +2754,7 @@ struct drm_i915_cmd_table {
>   * interrupt source and so prevents the other device from working properly.
>   */
>  #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
> -#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
> +#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->has_gmbus_irq)
>  
>  /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
>   * rows, which changed the alignment requirements and fence programming.
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 8a50e45..59c958a4 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -181,6 +181,7 @@ static const struct intel_device_info intel_pineview_info = {
>  #define GEN5_FEATURES \
>  	.gen = 5, .num_pipes = 2, \
>  	.need_gfx_hws = 1, .has_hotplug = 1, \
> +	.has_gmbus_irq = 1, \
>  	.ring_mask = RENDER_RING | BSD_RING, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
>  	CURSOR_OFFSETS
> @@ -202,6 +203,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
>  	.has_llc = 1, \
>  	.has_rc6 = 1, \
>  	.has_rc6p = 1, \
> +	.has_gmbus_irq = 1, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
>  	CURSOR_OFFSETS
>  
> @@ -222,6 +224,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
>  	.has_llc = 1, \
>  	.has_rc6 = 1, \
>  	.has_rc6p = 1, \
> +	.has_gmbus_irq = 1, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
>  	IVB_CURSOR_OFFSETS
>  
> @@ -247,6 +250,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
>  	.has_psr = 1, \
>  	.has_runtime_pm = 1, \
>  	.has_rc6 = 1, \
> +	.has_gmbus_irq = 1, \
>  	.need_gfx_hws = 1, .has_hotplug = 1, \
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
>  	.display_mmio_offset = VLV_DISPLAY_BASE, \
> @@ -300,6 +304,7 @@ static const struct intel_device_info intel_cherryview_info = {
>  	.has_runtime_pm = 1,
>  	.has_resource_streamer = 1,
>  	.has_rc6 = 1,
> +	.has_gmbus_irq = 1,
>  	.display_mmio_offset = VLV_DISPLAY_BASE,
>  	GEN_CHV_PIPEOFFSETS,
>  	CURSOR_OFFSETS,
> @@ -336,6 +341,7 @@ static const struct intel_device_info intel_broxton_info = {
>  	.has_resource_streamer = 1,
>  	.has_rc6 = 1,
>  	.has_dp_mst = 1,
> +	.has_gmbus_irq = 1,
>  	GEN_DEFAULT_PIPEOFFSETS,
>  	IVB_CURSOR_OFFSETS,
>  	BDW_COLORS,
> -- 
> 1.9.1
> 
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v3 13/21] drm/i915: Introduce GEN4_FEATURES for device info

[Rodrigo Vivi]

On Tue, Aug 09, 2016 at 11:45:19AM -0700, Carlos Santa wrote:
> Based on the GEN7_FEATURES changes from Ben W.

same comments as for gen5

> 
> Use it for i965g, i965gm, g45 and gm45.
> 
> Signed-off-by: Carlos Santa <carlos.santa@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_pci.c | 36 ++++++++++++++++++------------------
>  1 file changed, 18 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 59c958a4..356f16d 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -123,23 +123,25 @@ static const struct intel_device_info intel_i945gm_info = {
>  	CURSOR_OFFSETS,
>  };
>  
> +#define GEN4_FEATURES \
> +	.gen = 4, .num_pipes = 2, \
> +	.has_hotplug = 1, \
> +	.ring_mask = RENDER_RING, \
> +	GEN_DEFAULT_PIPEOFFSETS, \
> +	CURSOR_OFFSETS
> +
>  static const struct intel_device_info intel_i965g_info = {
> -	.gen = 4, .is_broadwater = 1, .num_pipes = 2,
> -	.has_hotplug = 1,
> +	GEN4_FEATURES,
> +	.is_broadwater = 1,
>  	.has_overlay = 1,
> -	.ring_mask = RENDER_RING,
> -	GEN_DEFAULT_PIPEOFFSETS,
> -	CURSOR_OFFSETS,
>  };
>  
>  static const struct intel_device_info intel_i965gm_info = {
> -	.gen = 4, .is_crestline = 1, .num_pipes = 2,
> -	.is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
> +	GEN4_FEATURES,
> +	.is_crestline = 1,
> +	.is_mobile = 1, .has_fbc = 1,
>  	.has_overlay = 1,
>  	.supports_tv = 1,
> -	.ring_mask = RENDER_RING,
> -	GEN_DEFAULT_PIPEOFFSETS,
> -	CURSOR_OFFSETS,
>  };
>  
>  static const struct intel_device_info intel_g33_info = {
> @@ -152,21 +154,19 @@ static const struct intel_device_info intel_g33_info = {
>  };
>  
>  static const struct intel_device_info intel_g45_info = {
> -	.gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
> -	.has_pipe_cxsr = 1, .has_hotplug = 1,
> +	GEN4_FEATURES,
> +	.is_g4x = 1, .need_gfx_hws = 1,
> +	.has_pipe_cxsr = 1,
>  	.ring_mask = RENDER_RING | BSD_RING,
> -	GEN_DEFAULT_PIPEOFFSETS,
> -	CURSOR_OFFSETS,
>  };
>  
>  static const struct intel_device_info intel_gm45_info = {
> -	.gen = 4, .is_g4x = 1, .num_pipes = 2,
> +	GEN4_FEATURES,
> +	.is_g4x = 1,
>  	.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
> -	.has_pipe_cxsr = 1, .has_hotplug = 1,
> +	.has_pipe_cxsr = 1,
>  	.supports_tv = 1,
>  	.ring_mask = RENDER_RING | BSD_RING,
> -	GEN_DEFAULT_PIPEOFFSETS,
> -	CURSOR_OFFSETS,
>  };
>  
>  static const struct intel_device_info intel_pineview_info = {
> -- 
> 1.9.1
> 
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Re: [PATCH v3 14/21] drm/i915: Introduce GEN3_FEATURES for device info

[Rodrigo Vivi]

On Tue, Aug 09, 2016 at 11:45:20AM -0700, Carlos Santa wrote:
> Based on the GEN7_FEATURES from Ben W.
>

same as previous

> Use it for i915g, i915gm, i945g, i945gm, g33 and pnv.
> 
> Signed-off-by: Carlos Santa <carlos.santa@intel.com>


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_pci.c | 30 ++++++++++++++----------------
>  1 file changed, 14 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 356f16d..2f65898 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -88,39 +88,37 @@ static const struct intel_device_info intel_i865g_info = {
>  	CURSOR_OFFSETS,
>  };
>  
> +#define GEN3_FEATURES \
> +	.gen = 3, .num_pipes = 2, \
> +	.ring_mask = RENDER_RING, \
> +	GEN_DEFAULT_PIPEOFFSETS, \
> +	CURSOR_OFFSETS
> +
>  static const struct intel_device_info intel_i915g_info = {
> -	.gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
> +	GEN3_FEATURES,
> +	.is_i915g = 1, .cursor_needs_physical = 1,
>  	.has_overlay = 1, .overlay_needs_physical = 1,
> -	.ring_mask = RENDER_RING,
> -	GEN_DEFAULT_PIPEOFFSETS,
> -	CURSOR_OFFSETS,
>  };
>  static const struct intel_device_info intel_i915gm_info = {
> -	.gen = 3, .is_mobile = 1, .num_pipes = 2,
> +	GEN3_FEATURES,
> +	.is_mobile = 1,
>  	.cursor_needs_physical = 1,
>  	.has_overlay = 1, .overlay_needs_physical = 1,
>  	.supports_tv = 1,
>  	.has_fbc = 1,
> -	.ring_mask = RENDER_RING,
> -	GEN_DEFAULT_PIPEOFFSETS,
> -	CURSOR_OFFSETS,
>  };
>  static const struct intel_device_info intel_i945g_info = {
> -	.gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
> +	GEN3_FEATURES,
> +	.has_hotplug = 1, .cursor_needs_physical = 1,
>  	.has_overlay = 1, .overlay_needs_physical = 1,
> -	.ring_mask = RENDER_RING,
> -	GEN_DEFAULT_PIPEOFFSETS,
> -	CURSOR_OFFSETS,
>  };
>  static const struct intel_device_info intel_i945gm_info = {
> -	.gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
> +	GEN3_FEATURES,
> +	.is_i945gm = 1, .is_mobile = 1,
>  	.has_hotplug = 1, .cursor_needs_physical = 1,
>  	.has_overlay = 1, .overlay_needs_physical = 1,
>  	.supports_tv = 1,
>  	.has_fbc = 1,
> -	.ring_mask = RENDER_RING,
> -	GEN_DEFAULT_PIPEOFFSETS,
> -	CURSOR_OFFSETS,
>  };
>  
>  #define GEN4_FEATURES \
> -- 
> 1.9.1
> 
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Re: [PATCH v3 15/21] drm/i915: Introduce GEN2_FEATURES for device info

[Rodrigo Vivi]

On Tue, Aug 09, 2016 at 11:45:21AM -0700, Carlos Santa wrote:
> Based on the GEN7_FEATURES changes from Ben W.
>

same as others

> Use it for 830, 845g, i85x, i865g.
> 
> Signed-off-by: Carlos Santa <carlos.santa@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_pci.c | 37 ++++++++++++++++---------------------
>  1 file changed, 16 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 2f65898..3cd0d8f 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -54,38 +54,33 @@
>  #define CHV_COLORS \
>  	.color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
>  
> +#define GEN2_FEATURES \
> +	.gen = 2, \
> +	.has_overlay = 1, .overlay_needs_physical = 1, \
> +	.ring_mask = RENDER_RING, \
> +	GEN_DEFAULT_PIPEOFFSETS, \
> +	CURSOR_OFFSETS
> +
>  static const struct intel_device_info intel_i830_info = {
> -	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
> -	.has_overlay = 1, .overlay_needs_physical = 1,
> -	.ring_mask = RENDER_RING,
> -	GEN_DEFAULT_PIPEOFFSETS,
> -	CURSOR_OFFSETS,
> +	GEN2_FEATURES,
> +	.is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,

maybe GEN2_FEATURES should define num_pipes = 1 and this overwrites it, like you have the ring in gen3 or gen4...

anyways:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

>  };
>  
>  static const struct intel_device_info intel_845g_info = {
> -	.gen = 2, .num_pipes = 1,
> -	.has_overlay = 1, .overlay_needs_physical = 1,
> -	.ring_mask = RENDER_RING,
> -	GEN_DEFAULT_PIPEOFFSETS,
> -	CURSOR_OFFSETS,
> +	GEN2_FEATURES,
> +	.num_pipes = 1,
>  };
>  
>  static const struct intel_device_info intel_i85x_info = {
> -	.gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
> -	.cursor_needs_physical = 1,
> -	.has_overlay = 1, .overlay_needs_physical = 1,
> +	GEN2_FEATURES,
> +	.is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
> +	.is_i85x = 1,
>  	.has_fbc = 1,
> -	.ring_mask = RENDER_RING,
> -	GEN_DEFAULT_PIPEOFFSETS,
> -	CURSOR_OFFSETS,
>  };
>  
>  static const struct intel_device_info intel_i865g_info = {
> -	.gen = 2, .num_pipes = 1,
> -	.has_overlay = 1, .overlay_needs_physical = 1,
> -	.ring_mask = RENDER_RING,
> -	GEN_DEFAULT_PIPEOFFSETS,
> -	CURSOR_OFFSETS,
> +	GEN2_FEATURES,
> +	.num_pipes = 1,
>  };
>  
>  #define GEN3_FEATURES \
> -- 
> 1.9.1
> 
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Re: [PATCH v3 16/21] drm/i915: Move HAS_HW_CONTEXTS definition to platform

[Rodrigo Vivi]

On Tue, Aug 09, 2016 at 11:45:22AM -0700, Carlos Santa wrote:
> Moving all GPU features to the platform definition allows for
> 	- standard place when adding new features from new platforms
> 	- possible to see supported features when dumping struct
> 	  definitions
> 
> Signed-off-by: Carlos Santa <carlos.santa@intel.com>


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 3 ++-
>  drivers/gpu/drm/i915/i915_pci.c | 5 +++++
>  2 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 729a91b..919ae65 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -778,6 +778,7 @@ struct intel_csr {
>  	func(has_rc6p) sep \
>  	func(has_dp_mst) sep \
>  	func(has_gmbus_irq) sep \
> +	func(has_hw_contexts) sep \
>  	func(has_pipe_cxsr) sep \
>  	func(has_hotplug) sep \
>  	func(cursor_needs_physical) sep \
> @@ -2729,7 +2730,7 @@ struct drm_i915_cmd_table {
>  				 HAS_EDRAM(dev))
>  #define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)
>  
> -#define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 6)
> +#define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->has_hw_contexts)
>  #define HAS_LOGICAL_RING_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 8)
>  #define USES_PPGTT(dev)		(i915.enable_ppgtt)
>  #define USES_FULL_PPGTT(dev)	(i915.enable_ppgtt >= 2)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 3cd0d8f..9d42b68 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -196,6 +196,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
>  	.has_llc = 1, \
>  	.has_rc6 = 1, \
>  	.has_rc6p = 1, \
> +	.has_hw_contexts = 1, \
>  	.has_gmbus_irq = 1, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
>  	CURSOR_OFFSETS
> @@ -218,6 +219,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
>  	.has_rc6 = 1, \
>  	.has_rc6p = 1, \
>  	.has_gmbus_irq = 1, \
> +	.has_hw_contexts = 1, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
>  	IVB_CURSOR_OFFSETS
>  
> @@ -244,6 +246,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
>  	.has_runtime_pm = 1, \
>  	.has_rc6 = 1, \
>  	.has_gmbus_irq = 1, \
> +	.has_hw_contexts = 1, \
>  	.need_gfx_hws = 1, .has_hotplug = 1, \
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
>  	.display_mmio_offset = VLV_DISPLAY_BASE, \
> @@ -298,6 +301,7 @@ static const struct intel_device_info intel_cherryview_info = {
>  	.has_resource_streamer = 1,
>  	.has_rc6 = 1,
>  	.has_gmbus_irq = 1,
> +	.has_hw_contexts = 1,
>  	.display_mmio_offset = VLV_DISPLAY_BASE,
>  	GEN_CHV_PIPEOFFSETS,
>  	CURSOR_OFFSETS,
> @@ -335,6 +339,7 @@ static const struct intel_device_info intel_broxton_info = {
>  	.has_rc6 = 1,
>  	.has_dp_mst = 1,
>  	.has_gmbus_irq = 1,
> +	.has_hw_contexts = 1,
>  	GEN_DEFAULT_PIPEOFFSETS,
>  	IVB_CURSOR_OFFSETS,
>  	BDW_COLORS,
> -- 
> 1.9.1
> 
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Re: [PATCH v3 17/21] drm/i915: Move HAS_LOGICAL_RING_CONTEXTS definition to platform

[Rodrigo Vivi]

On Tue, Aug 09, 2016 at 11:45:23AM -0700, Carlos Santa wrote:
> Moving all GPU features to the platform definition allows for
> 	- standard place when adding new features from new platforms
> 	- possible to see supported features when dumping struct
> 	  definitions
> 


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> Signed-off-by: Carlos Santa <carlos.santa@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 3 ++-
>  drivers/gpu/drm/i915/i915_pci.c | 5 ++++-
>  2 files changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 919ae65..18c9fc5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -779,6 +779,7 @@ struct intel_csr {
>  	func(has_dp_mst) sep \
>  	func(has_gmbus_irq) sep \
>  	func(has_hw_contexts) sep \
> +	func(has_logical_ring_contexts) sep \
>  	func(has_pipe_cxsr) sep \
>  	func(has_hotplug) sep \
>  	func(cursor_needs_physical) sep \
> @@ -2731,7 +2732,7 @@ struct drm_i915_cmd_table {
>  #define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)
>  
>  #define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->has_hw_contexts)
> -#define HAS_LOGICAL_RING_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 8)
> +#define HAS_LOGICAL_RING_CONTEXTS(dev)	(INTEL_INFO(dev)->has_logical_ring_contexts)
>  #define USES_PPGTT(dev)		(i915.enable_ppgtt)
>  #define USES_FULL_PPGTT(dev)	(i915.enable_ppgtt >= 2)
>  #define USES_FULL_48BIT_PPGTT(dev)	(i915.enable_ppgtt == 3)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 9d42b68..db15fc2 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -276,7 +276,8 @@ static const struct intel_device_info intel_haswell_info = {
>  
>  #define BDW_FEATURES \
>  	HSW_FEATURES, \
> -	BDW_COLORS
> +	BDW_COLORS, \
> +	.has_logical_ring_contexts = 1
>  
>  static const struct intel_device_info intel_broadwell_info = {
>  	BDW_FEATURES,
> @@ -302,6 +303,7 @@ static const struct intel_device_info intel_cherryview_info = {
>  	.has_rc6 = 1,
>  	.has_gmbus_irq = 1,
>  	.has_hw_contexts = 1,
> +	.has_logical_ring_contexts = 1,
>  	.display_mmio_offset = VLV_DISPLAY_BASE,
>  	GEN_CHV_PIPEOFFSETS,
>  	CURSOR_OFFSETS,
> @@ -340,6 +342,7 @@ static const struct intel_device_info intel_broxton_info = {
>  	.has_dp_mst = 1,
>  	.has_gmbus_irq = 1,
>  	.has_hw_contexts = 1,
> +	.has_logical_ring_contexts = 1,
>  	GEN_DEFAULT_PIPEOFFSETS,
>  	IVB_CURSOR_OFFSETS,
>  	BDW_COLORS,
> -- 
> 1.9.1
> 
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Re: [PATCH v3 18/21] drm/i915: Move HAS_L3_DPF definition to platform definition

[Rodrigo Vivi]

On Tue, Aug 09, 2016 at 11:45:24AM -0700, Carlos Santa wrote:
> Moving all GPU features to the platform definition allows for
> 	- standard place when adding new features from new platforms
> 	- possible to see supported features when dumping struct
> 	  definitions
> 


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> Signed-off-by: Carlos Santa <carlos.santa@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 3 ++-
>  drivers/gpu/drm/i915/i915_pci.c | 4 ++++
>  2 files changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 18c9fc5..20c793f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -780,6 +780,7 @@ struct intel_csr {
>  	func(has_gmbus_irq) sep \
>  	func(has_hw_contexts) sep \
>  	func(has_logical_ring_contexts) sep \
> +	func(has_l3_dpf) sep \
>  	func(has_pipe_cxsr) sep \
>  	func(has_hotplug) sep \
>  	func(cursor_needs_physical) sep \
> @@ -2824,7 +2825,7 @@ struct drm_i915_cmd_table {
>  			       IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>  
>  /* DPF == dynamic parity feature */
> -#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
> +#define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf)
>  #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
>  
>  #define GT_FREQUENCY_MULTIPLIER 50
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index db15fc2..d219a01 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -226,18 +226,21 @@ static const struct intel_device_info intel_sandybridge_m_info = {
>  static const struct intel_device_info intel_ivybridge_d_info = {
>  	GEN7_FEATURES,
>  	.is_ivybridge = 1,
> +	.has_l3_dpf = 1,
>  };
>  
>  static const struct intel_device_info intel_ivybridge_m_info = {
>  	GEN7_FEATURES,
>  	.is_ivybridge = 1,
>  	.is_mobile = 1,
> +	.has_l3_dpf = 1,
>  };
>  
>  static const struct intel_device_info intel_ivybridge_q_info = {
>  	GEN7_FEATURES,
>  	.is_ivybridge = 1,
>  	.num_pipes = 0, /* legal, last one wins */
> +	.has_l3_dpf = 1,
>  };
>  
>  #define VLV_FEATURES  \
> @@ -272,6 +275,7 @@ static const struct intel_device_info intel_valleyview_info = {
>  static const struct intel_device_info intel_haswell_info = {
>  	HSW_FEATURES,
>  	.is_haswell = 1,
> +	.has_l3_dpf = 1,
>  };
>  
>  #define BDW_FEATURES \
> -- 
> 1.9.1
> 
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v3 19/21] drm/i915: Move HAS_GMCH_DISPLAY definition to platform

[Rodrigo Vivi]

On Tue, Aug 09, 2016 at 11:45:25AM -0700, Carlos Santa wrote:
> Moving all GPU features to the platform definition allows for
> 	- standard place when adding new features from new platforms
> 	- possible to see supported features when dumping struct
> 	  definitions
> 
> Signed-off-by: Carlos Santa <carlos.santa@intel.com>


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 4 ++--
>  drivers/gpu/drm/i915/i915_pci.c | 5 +++++
>  2 files changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 20c793f..233feb9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -781,6 +781,7 @@ struct intel_csr {
>  	func(has_hw_contexts) sep \
>  	func(has_logical_ring_contexts) sep \
>  	func(has_l3_dpf) sep \
> +	func(has_gmch_display) sep \
>  	func(has_pipe_cxsr) sep \
>  	func(has_hotplug) sep \
>  	func(cursor_needs_physical) sep \
> @@ -2821,8 +2822,7 @@ struct drm_i915_cmd_table {
>  #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
>  #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
>  
> -#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
> -			       IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> +#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->has_gmch_display)
>  
>  /* DPF == dynamic parity feature */
>  #define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index d219a01..1c2f5fa 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -57,6 +57,7 @@
>  #define GEN2_FEATURES \
>  	.gen = 2, \
>  	.has_overlay = 1, .overlay_needs_physical = 1, \
> +	.has_gmch_display = 1, \
>  	.ring_mask = RENDER_RING, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
>  	CURSOR_OFFSETS
> @@ -85,6 +86,7 @@ static const struct intel_device_info intel_i865g_info = {
>  
>  #define GEN3_FEATURES \
>  	.gen = 3, .num_pipes = 2, \
> +	.has_gmch_display = 1, \
>  	.ring_mask = RENDER_RING, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
>  	CURSOR_OFFSETS
> @@ -119,6 +121,7 @@ static const struct intel_device_info intel_i945gm_info = {
>  #define GEN4_FEATURES \
>  	.gen = 4, .num_pipes = 2, \
>  	.has_hotplug = 1, \
> +	.has_gmch_display = 1, \
>  	.ring_mask = RENDER_RING, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
>  	CURSOR_OFFSETS
> @@ -250,6 +253,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
>  	.has_rc6 = 1, \
>  	.has_gmbus_irq = 1, \
>  	.has_hw_contexts = 1, \
> +	.has_gmch_display = 1, \
>  	.need_gfx_hws = 1, .has_hotplug = 1, \
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
>  	.display_mmio_offset = VLV_DISPLAY_BASE, \
> @@ -308,6 +312,7 @@ static const struct intel_device_info intel_cherryview_info = {
>  	.has_gmbus_irq = 1,
>  	.has_hw_contexts = 1,
>  	.has_logical_ring_contexts = 1,
> +	.has_gmch_display = 1,
>  	.display_mmio_offset = VLV_DISPLAY_BASE,
>  	GEN_CHV_PIPEOFFSETS,
>  	CURSOR_OFFSETS,
> -- 
> 1.9.1
> 
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Re: [PATCH v3 20/21] drm/i915: Make HWS_NEEDS_PHYSICAL the exception

[Rodrigo Vivi]

On Tue, Aug 09, 2016 at 11:45:26AM -0700, Carlos Santa wrote:
> Make the .hws_needs_physical the exception by switching the flag
> on earlier platforms since they are fewer to support. Remove the flag on
> later GPUs hardware since they all use GTT hws by default.
> 
> Switch the logic as well in the driver to reflect this change.
> 
> Signed-off-by: Carlos Santa <carlos.santa@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h         |  4 ++--
>  drivers/gpu/drm/i915/i915_gpu_error.c   |  2 +-
>  drivers/gpu/drm/i915/i915_pci.c         | 27 +++++++++++++++++----------
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 20 ++++++++++----------
>  4 files changed, 30 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 233feb9..8e0e0fa 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -755,7 +755,7 @@ struct intel_csr {
>  	func(is_i915g) sep \
>  	func(is_i945gm) sep \
>  	func(is_g33) sep \
> -	func(need_gfx_hws) sep \
> +	func(hws_needs_physical) sep \
>  	func(is_g4x) sep \
>  	func(is_pineview) sep \
>  	func(is_broadwater) sep \
> @@ -2731,7 +2731,7 @@ struct drm_i915_cmd_table {
>  #define HAS_EDRAM(dev)		(!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
>  #define HAS_WT(dev)		((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
>  				 HAS_EDRAM(dev))
> -#define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)
> +#define HWS_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->hws_needs_physical)

At first sight I was going to complain about the name, since need_hws_physical sounded the correct,
but indeed it seems that for this HWS (what ever that is) we need this physical status page because
we don't have the HSW specific registers on those platforms.
So now I believe the name you chose is indeed better.

When applying this patch I got one conflict... wiggle could solve and it seems correct but maybe a
rebased version is better.

Anyways:


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>



>  
>  #define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->has_hw_contexts)
>  #define HAS_LOGICAL_RING_CONTEXTS(dev)	(INTEL_INFO(dev)->has_logical_ring_contexts)
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index eecb870..ba68327 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1008,7 +1008,7 @@ static void error_record_engine_registers(struct drm_i915_error_state *error,
>  	ee->tail = I915_READ_TAIL(engine);
>  	ee->ctl = I915_READ_CTL(engine);
>  
> -	if (I915_NEED_GFX_HWS(dev_priv)) {
> +	if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
>  		i915_reg_t mmio;
>  
>  		if (IS_GEN7(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 1c2f5fa..c5f4078 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -58,6 +58,7 @@
>  	.gen = 2, \
>  	.has_overlay = 1, .overlay_needs_physical = 1, \
>  	.has_gmch_display = 1, \
> +	.hws_needs_physical = 1, \
>  	.ring_mask = RENDER_RING, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
>  	CURSOR_OFFSETS
> @@ -95,6 +96,7 @@ static const struct intel_device_info intel_i915g_info = {
>  	GEN3_FEATURES,
>  	.is_i915g = 1, .cursor_needs_physical = 1,
>  	.has_overlay = 1, .overlay_needs_physical = 1,
> +	.hws_needs_physical = 1,
>  };
>  static const struct intel_device_info intel_i915gm_info = {
>  	GEN3_FEATURES,
> @@ -103,11 +105,13 @@ static const struct intel_device_info intel_i915gm_info = {
>  	.has_overlay = 1, .overlay_needs_physical = 1,
>  	.supports_tv = 1,
>  	.has_fbc = 1,
> +	.hws_needs_physical = 1,
>  };
>  static const struct intel_device_info intel_i945g_info = {
>  	GEN3_FEATURES,
>  	.has_hotplug = 1, .cursor_needs_physical = 1,
>  	.has_overlay = 1, .overlay_needs_physical = 1,
> +	.hws_needs_physical = 1,
>  };
>  static const struct intel_device_info intel_i945gm_info = {
>  	GEN3_FEATURES,
> @@ -116,6 +120,7 @@ static const struct intel_device_info intel_i945gm_info = {
>  	.has_overlay = 1, .overlay_needs_physical = 1,
>  	.supports_tv = 1,
>  	.has_fbc = 1,
> +	.hws_needs_physical = 1,
>  };
>  
>  #define GEN4_FEATURES \
> @@ -130,6 +135,7 @@ static const struct intel_device_info intel_i965g_info = {
>  	GEN4_FEATURES,
>  	.is_broadwater = 1,
>  	.has_overlay = 1,
> +	.hws_needs_physical = 1,
>  };
>  
>  static const struct intel_device_info intel_i965gm_info = {
> @@ -138,11 +144,12 @@ static const struct intel_device_info intel_i965gm_info = {
>  	.is_mobile = 1, .has_fbc = 1,
>  	.has_overlay = 1,
>  	.supports_tv = 1,
> +	.hws_needs_physical = 1,
>  };
>  
>  static const struct intel_device_info intel_g33_info = {
>  	.gen = 3, .is_g33 = 1, .num_pipes = 2,
> -	.need_gfx_hws = 1, .has_hotplug = 1,
> +	.has_hotplug = 1,
>  	.has_overlay = 1,
>  	.ring_mask = RENDER_RING,
>  	GEN_DEFAULT_PIPEOFFSETS,
> @@ -151,7 +158,7 @@ static const struct intel_device_info intel_g33_info = {
>  
>  static const struct intel_device_info intel_g45_info = {
>  	GEN4_FEATURES,
> -	.is_g4x = 1, .need_gfx_hws = 1,
> +	.is_g4x = 1,
>  	.has_pipe_cxsr = 1,
>  	.ring_mask = RENDER_RING | BSD_RING,
>  };
> @@ -159,7 +166,7 @@ static const struct intel_device_info intel_g45_info = {
>  static const struct intel_device_info intel_gm45_info = {
>  	GEN4_FEATURES,
>  	.is_g4x = 1,
> -	.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
> +	.is_mobile = 1, .has_fbc = 1,
>  	.has_pipe_cxsr = 1,
>  	.supports_tv = 1,
>  	.ring_mask = RENDER_RING | BSD_RING,
> @@ -167,7 +174,7 @@ static const struct intel_device_info intel_gm45_info = {
>  
>  static const struct intel_device_info intel_pineview_info = {
>  	.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
> -	.need_gfx_hws = 1, .has_hotplug = 1,
> +	.has_hotplug = 1,
>  	.has_overlay = 1,
>  	.ring_mask = RENDER_RING,
>  	GEN_DEFAULT_PIPEOFFSETS,
> @@ -176,7 +183,7 @@ static const struct intel_device_info intel_pineview_info = {
>  
>  #define GEN5_FEATURES \
>  	.gen = 5, .num_pipes = 2, \
> -	.need_gfx_hws = 1, .has_hotplug = 1, \
> +	.has_hotplug = 1, \
>  	.has_gmbus_irq = 1, \
>  	.ring_mask = RENDER_RING | BSD_RING, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
> @@ -193,7 +200,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
>  
>  #define GEN6_FEATURES \
>  	.gen = 6, .num_pipes = 2, \
> -	.need_gfx_hws = 1, .has_hotplug = 1, \
> +	.has_hotplug = 1, \
>  	.has_fbc = 1, \
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
>  	.has_llc = 1, \
> @@ -215,7 +222,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
>  
>  #define GEN7_FEATURES  \
>  	.gen = 7, .num_pipes = 3, \
> -	.need_gfx_hws = 1, .has_hotplug = 1, \
> +	.has_hotplug = 1, \
>  	.has_fbc = 1, \
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
>  	.has_llc = 1, \
> @@ -254,7 +261,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
>  	.has_gmbus_irq = 1, \
>  	.has_hw_contexts = 1, \
>  	.has_gmch_display = 1, \
> -	.need_gfx_hws = 1, .has_hotplug = 1, \
> +	.has_hotplug = 1, \
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
>  	.display_mmio_offset = VLV_DISPLAY_BASE, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
> @@ -302,7 +309,7 @@ static const struct intel_device_info intel_broadwell_gt3_info = {
>  
>  static const struct intel_device_info intel_cherryview_info = {
>  	.gen = 8, .num_pipes = 3,
> -	.need_gfx_hws = 1, .has_hotplug = 1,
> +	.has_hotplug = 1,
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
>  	.is_cherryview = 1,
>  	.has_psr = 1,
> @@ -337,7 +344,7 @@ static const struct intel_device_info intel_skylake_gt3_info = {
>  static const struct intel_device_info intel_broxton_info = {
>  	.is_broxton = 1,
>  	.gen = 9,
> -	.need_gfx_hws = 1, .has_hotplug = 1,
> +	.has_hotplug = 1,
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
>  	.num_pipes = 3,
>  	.has_ddi = 1,
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index e08a1e1..f19ce8a 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -559,10 +559,10 @@ static int init_ring_common(struct intel_engine_cs *engine)
>  		}
>  	}
>  
> -	if (I915_NEED_GFX_HWS(dev_priv))
> -		intel_ring_setup_status_page(engine);
> -	else
> +	if (HWS_NEEDS_PHYSICAL(dev_priv))
>  		ring_setup_phys_status_page(engine);
> +	else
> +		intel_ring_setup_status_page(engine);
>  
>  	/* Enforce ordering by reading HEAD register back */
>  	I915_READ_HEAD(engine);
> @@ -2167,13 +2167,13 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine)
>  	}
>  	engine->buffer = ring;
>  
> -	if (I915_NEED_GFX_HWS(dev_priv)) {
> -		ret = init_status_page(engine);
> +	if (HWS_NEEDS_PHYSICAL(dev_priv)) {
> +		WARN_ON(engine->id != RCS);
> +		ret = init_phys_status_page(engine);
>  		if (ret)
>  			goto error;
>  	} else {
> -		WARN_ON(engine->id != RCS);
> -		ret = init_phys_status_page(engine);
> +		ret = init_status_page(engine);
>  		if (ret)
>  			goto error;
>  	}
> @@ -2213,11 +2213,11 @@ void intel_engine_cleanup(struct intel_engine_cs *engine)
>  	if (engine->cleanup)
>  		engine->cleanup(engine);
>  
> -	if (I915_NEED_GFX_HWS(dev_priv)) {
> -		cleanup_status_page(engine);
> -	} else {
> +	if (HWS_NEEDS_PHYSICAL(dev_priv)) {
>  		WARN_ON(engine->id != RCS);
>  		cleanup_phys_status_page(engine);
> +	} else {
> +		cleanup_status_page(engine);
>  	}
>  
>  	intel_engine_cleanup_common(engine);
> -- 
> 1.9.1
> 
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Re: [PATCH v3 21/21] drm/i915: Move HAS_GUC definition to platform definition

[Rodrigo Vivi]

On Tue, Aug 09, 2016 at 11:45:27AM -0700, Carlos Santa wrote:
> Moving all GPU features to the platform definition allows for
> 	- standard place when adding new features from new platform
> 	- possible to see supported features when dumping struct
>           definitions
> 


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> Signed-off-by: Carlos Santa <carlos.santa@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 3 ++-
>  drivers/gpu/drm/i915/i915_pci.c | 5 +++++
>  2 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8e0e0fa..497854e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -782,6 +782,7 @@ struct intel_csr {
>  	func(has_logical_ring_contexts) sep \
>  	func(has_l3_dpf) sep \
>  	func(has_gmch_display) sep \
> +	func(has_guc) sep \
>  	func(has_pipe_cxsr) sep \
>  	func(has_hotplug) sep \
>  	func(cursor_needs_physical) sep \
> @@ -2790,7 +2791,7 @@ struct drm_i915_cmd_table {
>   * command submission once loaded. But these are logically independent
>   * properties, so we have separate macros to test them.
>   */
> -#define HAS_GUC(dev)		(IS_GEN9(dev))
> +#define HAS_GUC(dev)		(INTEL_INFO(dev)->has_guc)
>  #define HAS_GUC_UCODE(dev)	(HAS_GUC(dev))
>  #define HAS_GUC_SCHED(dev)	(HAS_GUC(dev))
>  
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index c5f4078..02a7619 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -331,6 +331,7 @@ static const struct intel_device_info intel_skylake_info = {
>  	.is_skylake = 1,
>  	.gen = 9,
>  	.has_csr = 1,
> +	.has_guc = 1,
>  };
>  
>  static const struct intel_device_info intel_skylake_gt3_info = {
> @@ -338,6 +339,7 @@ static const struct intel_device_info intel_skylake_gt3_info = {
>  	.is_skylake = 1,
>  	.gen = 9,
>  	.has_csr = 1,
> +	.has_guc = 1,
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
>  };
>  
> @@ -359,6 +361,7 @@ static const struct intel_device_info intel_broxton_info = {
>  	.has_gmbus_irq = 1,
>  	.has_hw_contexts = 1,
>  	.has_logical_ring_contexts = 1,
> +	.has_guc = 1,
>  	GEN_DEFAULT_PIPEOFFSETS,
>  	IVB_CURSOR_OFFSETS,
>  	BDW_COLORS,
> @@ -369,6 +372,7 @@ static const struct intel_device_info intel_kabylake_info = {
>  	.is_kabylake = 1,
>  	.gen = 9,
>  	.has_csr = 1,
> +	.has_guc = 1,
>  };
>  
>  static const struct intel_device_info intel_kabylake_gt3_info = {
> @@ -376,6 +380,7 @@ static const struct intel_device_info intel_kabylake_gt3_info = {
>  	.is_kabylake = 1,
>  	.gen = 9,
>  	.has_csr = 1,
> +	.has_guc = 1,
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
>  };
>  
> -- 
> 1.9.1
> 
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> Intel-gfx@lists.freedesktop.org
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