[PATCH] arm64: KVM: remove misleading comment on pmu status

[PATCH] arm64: KVM: remove misleading comment on pmu status

[Vladimir Murzin]

Comment about how PMU access is handled is not relavant since v4.6
where proper PMU support was added in.

Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm64/kvm/sys_regs.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index bffc93a..6f5203d 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -825,14 +825,6 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
  * Architected system registers.
  * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
  *
- * We could trap ID_DFR0 and tell the guest we don't support performance
- * monitoring.  Unfortunately the patch to make the kernel check ID_DFR0 was
- * NAKed, so it will read the PMCR anyway.
- *
- * Therefore we tell the guest we have 0 counters.  Unfortunately, we
- * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
- * all PM registers, which doesn't crash the guest kernel at least.
- *
  * Debug handling: We do trap most, if not all debug related system
  * registers. The implementation is good enough to ensure that a guest
  * can use these with minimal performance degradation. The drawback is
-- 
2.0.0

[PATCH] arm64: KVM: report configured SRE value to 32-bit world

[Vladimir Murzin]

After commit b34f2bc ("arm64: KVM: Make ICC_SRE_EL1 access return the
configured SRE value") we report SRE value to 64-bit guest, but 32-bit
one still handled as RAZ/WI what leads to funny promise we do not keep:

"GICv3: GIC: unable to set SRE (disabled at EL2), panic ahead"

We could keep that promise and force panic, but it doesn't look
reliable, instead report configured SRE value to 32-bit guest.

Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm64/kvm/sys_regs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index b0b225c..0940bfc 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1360,7 +1360,7 @@ static const struct sys_reg_desc cp15_regs[] = {
 	{ Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
 
 	/* ICC_SRE */
-	{ Op1( 0), CRn(12), CRm(12), Op2( 5), trap_raz_wi },
+	{ Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
 
 	{ Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
 
-- 
2.0.0

Re: [PATCH] arm64: KVM: report configured SRE value to 32-bit world

[Christoffer Dall]

On Wed, Aug 10, 2016 at 10:49:43AM +0100, Vladimir Murzin wrote:
> After commit b34f2bc ("arm64: KVM: Make ICC_SRE_EL1 access return the
> configured SRE value") we report SRE value to 64-bit guest, but 32-bit
> one still handled as RAZ/WI what leads to funny promise we do not keep:
> 
> "GICv3: GIC: unable to set SRE (disabled at EL2), panic ahead"
> 
> We could keep that promise and force panic, but it doesn't look
> reliable, instead report configured SRE value to 32-bit guest.

I don't really understand this part of the commit message?

Why would we force a panic, and at what time?

It is obviously correct to return the actual value that the guest should
see...

Thanks,
-Christoffer

> 
> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
>  arch/arm64/kvm/sys_regs.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index b0b225c..0940bfc 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -1360,7 +1360,7 @@ static const struct sys_reg_desc cp15_regs[] = {
>  	{ Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
>  
>  	/* ICC_SRE */
> -	{ Op1( 0), CRn(12), CRm(12), Op2( 5), trap_raz_wi },
> +	{ Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
>  
>  	{ Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
>  
> -- 
> 2.0.0
> 

Re: [PATCH] arm64: KVM: report configured SRE value to 32-bit world

[Vladimir Murzin]

On 17/08/16 11:46, Christoffer Dall wrote:
> On Wed, Aug 10, 2016 at 10:49:43AM +0100, Vladimir Murzin wrote:
>> After commit b34f2bc ("arm64: KVM: Make ICC_SRE_EL1 access return the
>> configured SRE value") we report SRE value to 64-bit guest, but 32-bit
>> one still handled as RAZ/WI what leads to funny promise we do not keep:
>>
>> "GICv3: GIC: unable to set SRE (disabled at EL2), panic ahead"
>>
>> We could keep that promise and force panic, but it doesn't look
>> reliable, instead report configured SRE value to 32-bit guest.
> 
> I don't really understand this part of the commit message?
> 
> Why would we force a panic, and at what time?

To make statement "panic ahead" true ;) kind of irony, so feel free to
remove that part (alternatively I can re-spin v2)

Cheers
Vladimir

> 
> It is obviously correct to return the actual value that the guest should
> see...
> 
> Thanks,
> -Christoffer
> 
>>
>> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
>> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
>> ---
>>  arch/arm64/kvm/sys_regs.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>> index b0b225c..0940bfc 100644
>> --- a/arch/arm64/kvm/sys_regs.c
>> +++ b/arch/arm64/kvm/sys_regs.c
>> @@ -1360,7 +1360,7 @@ static const struct sys_reg_desc cp15_regs[] = {
>>  	{ Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
>>  
>>  	/* ICC_SRE */
>> -	{ Op1( 0), CRn(12), CRm(12), Op2( 5), trap_raz_wi },
>> +	{ Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
>>  
>>  	{ Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
>>  
>> -- 
>> 2.0.0
>>
> 
> 

Re: [PATCH] arm64: KVM: report configured SRE value to 32-bit world

[Christoffer Dall]

On Wed, Aug 17, 2016 at 11:55:21AM +0100, Vladimir Murzin wrote:
> On 17/08/16 11:46, Christoffer Dall wrote:
> > On Wed, Aug 10, 2016 at 10:49:43AM +0100, Vladimir Murzin wrote:
> >> After commit b34f2bc ("arm64: KVM: Make ICC_SRE_EL1 access return the
> >> configured SRE value") we report SRE value to 64-bit guest, but 32-bit
> >> one still handled as RAZ/WI what leads to funny promise we do not keep:
> >>
> >> "GICv3: GIC: unable to set SRE (disabled at EL2), panic ahead"
> >>
> >> We could keep that promise and force panic, but it doesn't look
> >> reliable, instead report configured SRE value to 32-bit guest.
> > 
> > I don't really understand this part of the commit message?
> > 
> > Why would we force a panic, and at what time?
> 
> To make statement "panic ahead" true ;) kind of irony, so feel free to
> remove that part (alternatively I can re-spin v2)
> 
No need, I just replaced it with:

  Instead, return the actual value of the ICC_SRE_EL1 register that the
  guest should see.

Thanks,
-Christoffer