All of lore.kernel.org
 help / color / mirror / Atom feed
From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 08/13] drm/i915: Drive request submission through fence callbacks
Date: Thu, 25 Aug 2016 10:08:26 +0100	[thread overview]
Message-ID: <20160825090839.9952-9-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <20160825090839.9952-1-chris@chris-wilson.co.uk>

Drive final request submission from a callback from the fence. This way
the request is queued until all dependencies are resolved, at which
point it is handed to the backend for queueing to hardware. At this
point, no dependencies are set on the request, so the callback is
immediate.

A side-effect of imposing a heavier-irqsafe spinlock for execlist
submission is that we lose the softirq enabling after scheduling the
execlists tasklet. To compensate, we manually kickstart the softirq by
disabling and enabling the bh around the fence signaling.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_gem_request.c  | 20 +++++++++++++++++++-
 drivers/gpu/drm/i915/i915_gem_request.h  |  3 +++
 drivers/gpu/drm/i915/intel_breadcrumbs.c |  3 +++
 drivers/gpu/drm/i915/intel_lrc.c         |  5 +++--
 4 files changed, 28 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index fa5e36de55d0..db45482ea194 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -314,6 +314,19 @@ static int i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno)
 	return 0;
 }
 
+static int __i915_sw_fence_call submit_notify(struct i915_sw_fence *fence)
+{
+	struct drm_i915_gem_request *request =
+		container_of(fence, typeof(*request), submit);
+
+	if (i915_sw_fence_done(fence))
+		i915_gem_request_put(request);
+	else
+		request->engine->submit_request(request);
+
+	return NOTIFY_DONE;
+}
+
 /**
  * i915_gem_request_alloc - allocate a request structure
  *
@@ -412,6 +425,8 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
 	 */
 	req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST;
 
+	i915_sw_fence_init(&i915_gem_request_get(req)->submit, submit_notify);
+
 	if (i915.enable_execlists)
 		ret = intel_logical_ring_alloc_request_extras(req);
 	else
@@ -527,7 +542,10 @@ void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches)
 		  reserved_tail, ret);
 
 	i915_gem_mark_busy(engine);
-	engine->submit_request(request);
+
+	local_bh_disable();
+	i915_sw_fence_commit(&request->submit);
+	local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
 }
 
 static unsigned long local_clock_us(unsigned int *cpu)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h b/drivers/gpu/drm/i915/i915_gem_request.h
index a231bd318ef0..a85723463978 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -28,6 +28,7 @@
 #include <linux/fence.h>
 
 #include "i915_gem.h"
+#include "i915_sw_fence.h"
 
 struct intel_wait {
 	struct rb_node node;
@@ -82,6 +83,8 @@ struct drm_i915_gem_request {
 	struct intel_ring *ring;
 	struct intel_signal_node signaling;
 
+	struct i915_sw_fence submit;
+
 	/** GEM sequence number associated with the previous request,
 	 * when the HWS breadcrumb is equal to this the GPU is processing
 	 * this request.
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 2491e4c1eaf0..9bad14d22c95 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -462,7 +462,10 @@ static int intel_breadcrumbs_signaler(void *arg)
 			 */
 			intel_engine_remove_wait(engine,
 						 &request->signaling.wait);
+
+			local_bh_disable();
 			fence_signal(&request->fence);
+			local_bh_enable(); /* kick start the tasklets */
 
 			/* Find the next oldest signal. Note that as we have
 			 * not been holding the lock, another client may
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 5e60519ede8d..babeaa8b1273 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -538,14 +538,15 @@ static void intel_lrc_irq_handler(unsigned long data)
 static void execlists_submit_request(struct drm_i915_gem_request *request)
 {
 	struct intel_engine_cs *engine = request->engine;
+	unsigned long flags;
 
-	spin_lock_bh(&engine->execlist_lock);
+	spin_lock_irqsave(&engine->execlist_lock, flags);
 
 	list_add_tail(&request->execlist_link, &engine->execlist_queue);
 	if (execlists_elsp_idle(engine))
 		tasklet_hi_schedule(&engine->irq_tasklet);
 
-	spin_unlock_bh(&engine->execlist_lock);
+	spin_unlock_irqrestore(&engine->execlist_lock, flags);
 }
 
 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
-- 
2.9.3

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2016-08-25  9:08 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-25  9:08 Shortest path to EGL_ANDRIOD_native_sync Chris Wilson
2016-08-25  9:08 ` [PATCH 01/13] drm/i915: Add a sw fence for collecting up dma fences Chris Wilson
2016-08-25 10:42   ` John Harrison
2016-08-25 10:51     ` Chris Wilson
2016-08-25 11:49   ` Joonas Lahtinen
2016-08-25 12:25     ` Chris Wilson
2016-08-25 16:52     ` Chris Wilson
2016-08-25  9:08 ` [PATCH 02/13] drm/i915: Only queue requests during execlists submission Chris Wilson
2016-08-26  9:41   ` Mika Kuoppala
2016-08-26  9:51     ` Chris Wilson
2016-08-26  9:54     ` Chris Wilson
2016-08-26 10:43       ` Mika Kuoppala
2016-08-26 10:53         ` Chris Wilson
2016-08-25  9:08 ` [PATCH 03/13] drm/i915: Record the position of the workarounds in the tail of the request Chris Wilson
2016-08-25  9:35   ` Mika Kuoppala
2016-08-25  9:08 ` [PATCH 04/13] drm/i915: Compute the ELSP register location once Chris Wilson
2016-08-25  9:51   ` Mika Kuoppala
2016-08-25 10:37     ` Chris Wilson
2016-08-25  9:08 ` [PATCH 05/13] drm/i915: Reorder submitting the requests to ELSP Chris Wilson
2016-08-25 13:02   ` Mika Kuoppala
2016-08-25  9:08 ` [PATCH 06/13] drm/i915: Simplify ELSP queue request tracking Chris Wilson
2016-08-25  9:08 ` [PATCH 07/13] drm/i915: Update reset path to fix incomplete requests Chris Wilson
2016-08-25  9:08 ` Chris Wilson [this message]
2016-08-25 12:08   ` [PATCH 08/13] drm/i915: Drive request submission through fence callbacks Joonas Lahtinen
2016-08-25 12:35     ` Chris Wilson
2016-08-26 12:47   ` John Harrison
2016-08-26 16:20     ` Chris Wilson
2016-08-25  9:08 ` [PATCH 09/13] drm/i915: Move execbuf object synchronisation to i915_gem_execbuffer Chris Wilson
2016-08-26 13:29   ` John Harrison
2016-08-25  9:08 ` [PATCH 10/13] drm/i915: Nonblocking request submission Chris Wilson
2016-08-26 13:39   ` John Harrison
2016-08-26 16:14     ` Chris Wilson
2016-08-25  9:08 ` [PATCH 11/13] drm/i915: Serialise execbuf operation after a dma-buf reservation object Chris Wilson
2016-08-26 13:52   ` John Harrison
2016-08-25  9:08 ` [PATCH 12/13] drm/i915: Enable userspace to opt-out of implicit fencing Chris Wilson
2016-08-25  9:08 ` [PATCH 13/13] drm/i915: Support explicit fencing for execbuf Chris Wilson
2016-08-26 15:08   ` John Harrison
2016-08-26 15:29     ` John Harrison
2016-08-26 15:44       ` Chris Wilson
2016-08-25  9:08 ` [PATCH libdrm 14/15] intel: Allow the client to control implicit synchronisation Chris Wilson
2016-08-25  9:08 ` [PATCH libdrm 15/15] intel: Support passing of explicit fencing from execbuf Chris Wilson
2016-09-30 20:53   ` Rafael Antognolli
2016-10-01  8:36     ` Chris Wilson
2016-08-25  9:08 ` [PATCH 16/21] i965: Add explicit fence tracking to batch flush Chris Wilson
2016-08-25  9:08 ` [PATCH 17/21] i965: Split intel_syncobject into vfuncs Chris Wilson
2016-08-25  9:08 ` [PATCH 18/21] i965: Add fd-fence backend to intel_syncobject Chris Wilson
2016-08-25  9:08 ` [PATCH 19/21] rfc! i965: Add intel_screen::has_fence_fd Chris Wilson
2016-08-25  9:08 ` [PATCH 20/21] i965: Implement EGL_ANDROID_native_fence_sync support for DRI2_FENCE Chris Wilson
2016-08-25  9:08 ` [PATCH 21/21] i965: Disable implicit sync when using EGL_ANDROID_native_fence_sync Chris Wilson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20160825090839.9952-9-chris@chris-wilson.co.uk \
    --to=chris@chris-wilson.co.uk \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.