[PATCH v4 1/4] arm64: arch_timer: Add device tree binding for A-008585 erratum

[PATCH v4 1/4] arm64: arch_timer: Add device tree binding for A-008585 erratum

[Scott Wood]

This erratum describes a bug in logic outside the core, so MIDR can't be
used to identify its presence, and reading an SoC-specific revision
register from common arch timer code would be awkward.  So, describe it
in the device tree.

Signed-off-by: Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
 Documentation/devicetree/bindings/arm/arch_timer.txt | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
index e774128..ef5fbe9 100644
--- a/Documentation/devicetree/bindings/arm/arch_timer.txt
+++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
@@ -25,6 +25,12 @@ to deliver its interrupts via SPIs.
 - always-on : a boolean property. If present, the timer is powered through an
   always-on power domain, therefore it never loses context.
 
+- fsl,erratum-a008585 : A boolean property. Indicates the presence of
+  QorIQ erratum A-008585, which says that reading the counter is
+  unreliable unless the same value is returned by back-to-back reads.
+  This also affects writes to the tval register, due to the implicit
+  counter read.
+
 ** Optional properties:
 
 - arm,cpu-registers-not-fw-configured : Firmware does not initialize
-- 
2.7.4

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[PATCH v4 1/4] arm64: arch_timer: Add device tree binding for A-008585 erratum

[Scott Wood]

This erratum describes a bug in logic outside the core, so MIDR can't be
used to identify its presence, and reading an SoC-specific revision
register from common arch timer code would be awkward.  So, describe it
in the device tree.

Signed-off-by: Scott Wood <oss@buserror.net>
Acked-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/arm/arch_timer.txt | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
index e774128..ef5fbe9 100644
--- a/Documentation/devicetree/bindings/arm/arch_timer.txt
+++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
@@ -25,6 +25,12 @@ to deliver its interrupts via SPIs.
 - always-on : a boolean property. If present, the timer is powered through an
   always-on power domain, therefore it never loses context.
 
+- fsl,erratum-a008585 : A boolean property. Indicates the presence of
+  QorIQ erratum A-008585, which says that reading the counter is
+  unreliable unless the same value is returned by back-to-back reads.
+  This also affects writes to the tval register, due to the implicit
+  counter read.
+
 ** Optional properties:
 
 - arm,cpu-registers-not-fw-configured : Firmware does not initialize
-- 
2.7.4

[PATCH v4 2/4] arm64: dts: Add timer erratum property for LS2080A and LS1043A

[Scott Wood]

Signed-off-by: Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org>
---
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 +
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index de0323b..c277ba6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -115,6 +115,7 @@
 			     <1 14 0x1>, /* Physical Non-Secure PPI */
 			     <1 11 0x1>, /* Virtual PPI */
 			     <1 10 0x1>; /* Hypervisor PPI */
+		fsl,erratum-a008585;
 	};
 
 	pmu {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 3187c82..768b899 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -171,6 +171,7 @@
 			     <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
 			     <1 11 0x8>, /* Virtual PPI, active-low */
 			     <1 10 0x8>; /* Hypervisor PPI, active-low */
+		fsl,erratum-a008585;
 	};
 
 	pmu {
-- 
2.7.4

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[PATCH v4 2/4] arm64: dts: Add timer erratum property for LS2080A and LS1043A

[Scott Wood]

Signed-off-by: Scott Wood <oss@buserror.net>
---
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 +
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index de0323b..c277ba6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -115,6 +115,7 @@
 			     <1 14 0x1>, /* Physical Non-Secure PPI */
 			     <1 11 0x1>, /* Virtual PPI */
 			     <1 10 0x1>; /* Hypervisor PPI */
+		fsl,erratum-a008585;
 	};
 
 	pmu {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 3187c82..768b899 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -171,6 +171,7 @@
 			     <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
 			     <1 11 0x8>, /* Virtual PPI, active-low */
 			     <1 10 0x8>; /* Hypervisor PPI, active-low */
+		fsl,erratum-a008585;
 	};
 
 	pmu {
-- 
2.7.4

[PATCH v4 3/4] arm64: arch_timer: Work around QorIQ Erratum A-008585

[Scott Wood]

Erratum A-008585 says that the ARM generic timer counter "has the
potential to contain an erroneous value for a small number of core
clock cycles every time the timer value changes".  Accesses to TVAL
(both read and write) are also affected due to the implicit counter
read.  Accesses to CVAL are not affected.

The workaround is to reread TVAL and count registers until successive reads
return the same value, and when writing TVAL to retry until counter
reads before and after the write return the same value.

This erratum can be found on LS1043A and LS2080A.

Signed-off-by: Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org>
---
v4:
- Undef ARCH_TIMER_REG_READ after use

v3:
- Used cval rather than a loop for the write side of the erratum
- Added a Kconfig control
- Moved the device tree binding into its own patch
- Added erratum to silicon-errata.txt
- Changed function names to contain the erratum name
- Factored out the setting of erratum versions of set_next_event
  to improve readability
- Added a comment clarifying that the timeout is arbitrary

v2:
Significant rework based on feedback, including using static_key,
disabling VDSO counter access rather than adding the workaround to the
VDSO, and uninlining the loops.

Dropped the separate property for indicating that writes to TVAL are
affected, as I believe that's just a side effect of the implicit
counter read being corrupted, and thus a chip that is affected by one
will always be affected by the other.

Dropped the arm32 portion as it seems there was confusion about whether
LS1021A is affected.  Currently I am being told that it is not
affected.

I considered writing to CVAL rather than looping on TVAL writes, but
that would still have required separate set_next_event() code for the
erratum, and adding CVAL to the enum would have required a bunch of
extra handlers in switch statements (even where unused, due to compiler
warnings about unhandled enum values) including in an arm32 header.  It
seemed better to avoid the arm32 interaction and new untested
accessors.
---
 Documentation/arm64/silicon-errata.txt |   2 +
 arch/arm64/include/asm/arch_timer.h    |  50 +++++++++++++---
 drivers/clocksource/Kconfig            |  10 ++++
 drivers/clocksource/arm_arch_timer.c   | 103 +++++++++++++++++++++++++++++++++
 4 files changed, 156 insertions(+), 9 deletions(-)

diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index 4da60b4..041e3a9 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -60,3 +60,5 @@ stable kernels.
 | Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154    |
 | Cavium         | ThunderX Core   | #27456          | CAVIUM_ERRATUM_27456    |
 | Cavium         | ThunderX SMMUv2 | #27704          | N/A		       |
+|                |                 |                 |                         |
+| Freescale/NXP  | LS2080A/LS1043A | A-008585        | FSL_ERRATUM_A008585     |
diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
index fbe0ca3..927dc6f 100644
--- a/arch/arm64/include/asm/arch_timer.h
+++ b/arch/arm64/include/asm/arch_timer.h
@@ -23,10 +23,36 @@
 
 #include <linux/bug.h>
 #include <linux/init.h>
+#include <linux/jump_label.h>
 #include <linux/types.h>
 
 #include <clocksource/arm_arch_timer.h>
 
+extern struct static_key_false arch_timer_read_ool_enabled;
+
+#define ARCH_TIMER_REG_READ(reg, func) \
+extern u64 func##_ool(void); \
+static inline u64 __##func(void) \
+{ \
+	u64 val; \
+	asm volatile("mrs %0, " reg : "=r" (val)); \
+	return val; \
+} \
+static inline u64 _##func(void) \
+{ \
+	if (IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) && \
+	    static_branch_unlikely(&arch_timer_read_ool_enabled)) \
+		return func##_ool(); \
+	else \
+		return __##func(); \
+}
+
+ARCH_TIMER_REG_READ("cntp_tval_el0", arch_timer_get_ptval)
+ARCH_TIMER_REG_READ("cntv_tval_el0", arch_timer_get_vtval)
+ARCH_TIMER_REG_READ("cntvct_el0", arch_counter_get_cntvct)
+
+#undef ARCH_TIMER_REG_READ
+
 /*
  * These register accessors are marked inline so the compiler can
  * nicely work out which register we want, and chuck away the rest of
@@ -58,6 +84,16 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
 	isb();
 }
 
+static __always_inline void arch_timer_cval_write_cp15(int access, u64 val)
+{
+	if (access == ARCH_TIMER_PHYS_ACCESS)
+		asm volatile("msr cntp_cval_el0, %0" : : "r" (val));
+	else if (access == ARCH_TIMER_VIRT_ACCESS)
+		asm volatile("msr cntv_cval_el0, %0" : : "r" (val));
+
+	isb();
+}
+
 static __always_inline
 u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
 {
@@ -66,19 +102,19 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
 	if (access == ARCH_TIMER_PHYS_ACCESS) {
 		switch (reg) {
 		case ARCH_TIMER_REG_CTRL:
-			asm volatile("mrs %0,  cntp_ctl_el0" : "=r" (val));
+			asm volatile("mrs %0, cntp_ctl_el0" : "=r" (val));
 			break;
 		case ARCH_TIMER_REG_TVAL:
-			asm volatile("mrs %0, cntp_tval_el0" : "=r" (val));
+			val = _arch_timer_get_ptval();
 			break;
 		}
 	} else if (access == ARCH_TIMER_VIRT_ACCESS) {
 		switch (reg) {
 		case ARCH_TIMER_REG_CTRL:
-			asm volatile("mrs %0,  cntv_ctl_el0" : "=r" (val));
+			asm volatile("mrs %0, cntv_ctl_el0" : "=r" (val));
 			break;
 		case ARCH_TIMER_REG_TVAL:
-			asm volatile("mrs %0, cntv_tval_el0" : "=r" (val));
+			val = _arch_timer_get_vtval();
 			break;
 		}
 	}
@@ -116,12 +152,8 @@ static inline u64 arch_counter_get_cntpct(void)
 
 static inline u64 arch_counter_get_cntvct(void)
 {
-	u64 cval;
-
 	isb();
-	asm volatile("mrs %0, cntvct_el0" : "=r" (cval));
-
-	return cval;
+	return _arch_counter_get_cntvct();
 }
 
 static inline int arch_timer_arch_init(void)
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 47352d2..48c6039 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -223,6 +223,16 @@ config ARM_ARCH_TIMER_EVTSTREAM
 	  This must be disabled for hardware validation purposes to detect any
 	  hardware anomalies of missing events.
 
+config FSL_ERRATUM_A008585
+	bool "Workaround for Freescale/NXP Erratum A-008585"
+	default y
+	depends on ARM_ARCH_TIMER && ARM64
+	help
+	  This option enables a workaround for Freescale/NXP Erratum
+	  A-008585 ("ARM generic timer may contain an erroneous
+	  value").  The workaround will only be active if the
+	  fsl,erratum-a008585 property is found in the timer node.
+
 config ARM_GLOBAL_TIMER
 	bool
 	select CLKSRC_OF if OF
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 4814446..b857027 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -83,6 +83,51 @@ static bool arch_timer_mem_use_virtual;
  * Architected system timer support.
  */
 
+#ifdef CONFIG_FSL_ERRATUM_A008585
+DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled);
+EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled);
+
+/*
+ * __always_inline is used to ensure that func() is not an actual function
+ * pointer, which would result in the register accesses potentially being too
+ * far apart for the loop to work.
+ *
+ * The timeout is an arbitrary value well beyond the highest number
+ * of iterations the loop has been observed to take.
+ */
+static __always_inline u64 fsl_a008585_reread_counter(u64 (*func)(void))
+{
+	u64 cval_old, cval_new;
+	int timeout = 200;
+
+	do {
+		isb();
+		cval_old = func();
+		cval_new = func();
+		timeout--;
+	} while (unlikely(cval_old != cval_new) && timeout);
+
+	WARN_ON_ONCE(!timeout);
+	return cval_new;
+}
+
+u64 arch_counter_get_cntvct_ool(void)
+{
+	return fsl_a008585_reread_counter(__arch_counter_get_cntvct);
+}
+
+u64 arch_timer_get_vtval_ool(void)
+{
+	return fsl_a008585_reread_counter(__arch_timer_get_vtval);
+}
+
+u64 arch_timer_get_ptval_ool(void)
+{
+	return fsl_a008585_reread_counter(__arch_timer_get_ptval);
+}
+
+#endif /* CONFIG_FSL_ERRATUM_A008585 */
+
 static __always_inline
 void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
 			  struct clock_event_device *clk)
@@ -232,6 +277,35 @@ static __always_inline void set_next_event(const int access, unsigned long evt,
 	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
 }
 
+#ifdef CONFIG_FSL_ERRATUM_A008585
+static __always_inline void fsl_a008585_set_next_event(const int access,
+		unsigned long evt, struct clock_event_device *clk)
+{
+	unsigned long ctrl;
+	u64 cval = evt + arch_counter_get_cntvct();
+
+	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
+	ctrl |= ARCH_TIMER_CTRL_ENABLE;
+	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
+	arch_timer_cval_write_cp15(access, cval);
+	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
+}
+
+static int fsl_a008585_set_next_event_virt(unsigned long evt,
+					   struct clock_event_device *clk)
+{
+	fsl_a008585_set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
+	return 0;
+}
+
+static int fsl_a008585_set_next_event_phys(unsigned long evt,
+					   struct clock_event_device *clk)
+{
+	fsl_a008585_set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
+	return 0;
+}
+#endif /* CONFIG_FSL_ERRATUM_A008585 */
+
 static int arch_timer_set_next_event_virt(unsigned long evt,
 					  struct clock_event_device *clk)
 {
@@ -260,6 +334,19 @@ static int arch_timer_set_next_event_phys_mem(unsigned long evt,
 	return 0;
 }
 
+static void fsl_a008585_set_sne(struct clock_event_device *clk)
+{
+#ifdef CONFIG_FSL_ERRATUM_A008585
+	if (!static_branch_unlikely(&arch_timer_read_ool_enabled))
+		return;
+
+	if (arch_timer_uses_ppi == VIRT_PPI)
+		clk->set_next_event = fsl_a008585_set_next_event_virt;
+	else
+		clk->set_next_event = fsl_a008585_set_next_event_phys;
+#endif
+}
+
 static void __arch_timer_setup(unsigned type,
 			       struct clock_event_device *clk)
 {
@@ -288,6 +375,8 @@ static void __arch_timer_setup(unsigned type,
 		default:
 			BUG();
 		}
+
+		fsl_a008585_set_sne(clk);
 	} else {
 		clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
 		clk->name = "arch_mem_timer";
@@ -485,6 +574,15 @@ static void __init arch_counter_register(unsigned type)
 			arch_timer_read_counter = arch_counter_get_cntvct;
 		else
 			arch_timer_read_counter = arch_counter_get_cntpct;
+
+#ifdef CONFIG_FSL_ERRATUM_A008585
+		/*
+		 * Don't use the vdso fastpath if errata require using
+		 * the out-of-line counter accessor.
+		 */
+		if (static_branch_unlikely(&arch_timer_read_ool_enabled))
+			clocksource_counter.name = "arch_sys_counter_ool";
+#endif
 	} else {
 		arch_timer_read_counter = arch_counter_get_cntvct_mem;
 
@@ -766,6 +864,11 @@ static void __init arch_timer_of_init(struct device_node *np)
 
 	arch_timer_c3stop = !of_property_read_bool(np, "always-on");
 
+#ifdef CONFIG_FSL_ERRATUM_A008585
+	if (of_property_read_bool(np, "fsl,erratum-a008585"))
+		static_branch_enable(&arch_timer_read_ool_enabled);
+#endif
+
 	/*
 	 * If we cannot rely on firmware initializing the timer registers then
 	 * we should use the physical timers instead.
-- 
2.7.4

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[PATCH v4 3/4] arm64: arch_timer: Work around QorIQ Erratum A-008585

[Scott Wood]

Erratum A-008585 says that the ARM generic timer counter "has the
potential to contain an erroneous value for a small number of core
clock cycles every time the timer value changes".  Accesses to TVAL
(both read and write) are also affected due to the implicit counter
read.  Accesses to CVAL are not affected.

The workaround is to reread TVAL and count registers until successive reads
return the same value, and when writing TVAL to retry until counter
reads before and after the write return the same value.

This erratum can be found on LS1043A and LS2080A.

Signed-off-by: Scott Wood <oss@buserror.net>
---
v4:
- Undef ARCH_TIMER_REG_READ after use

v3:
- Used cval rather than a loop for the write side of the erratum
- Added a Kconfig control
- Moved the device tree binding into its own patch
- Added erratum to silicon-errata.txt
- Changed function names to contain the erratum name
- Factored out the setting of erratum versions of set_next_event
  to improve readability
- Added a comment clarifying that the timeout is arbitrary

v2:
Significant rework based on feedback, including using static_key,
disabling VDSO counter access rather than adding the workaround to the
VDSO, and uninlining the loops.

Dropped the separate property for indicating that writes to TVAL are
affected, as I believe that's just a side effect of the implicit
counter read being corrupted, and thus a chip that is affected by one
will always be affected by the other.

Dropped the arm32 portion as it seems there was confusion about whether
LS1021A is affected.  Currently I am being told that it is not
affected.

I considered writing to CVAL rather than looping on TVAL writes, but
that would still have required separate set_next_event() code for the
erratum, and adding CVAL to the enum would have required a bunch of
extra handlers in switch statements (even where unused, due to compiler
warnings about unhandled enum values) including in an arm32 header.  It
seemed better to avoid the arm32 interaction and new untested
accessors.
---
 Documentation/arm64/silicon-errata.txt |   2 +
 arch/arm64/include/asm/arch_timer.h    |  50 +++++++++++++---
 drivers/clocksource/Kconfig            |  10 ++++
 drivers/clocksource/arm_arch_timer.c   | 103 +++++++++++++++++++++++++++++++++
 4 files changed, 156 insertions(+), 9 deletions(-)

diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index 4da60b4..041e3a9 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -60,3 +60,5 @@ stable kernels.
 | Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154    |
 | Cavium         | ThunderX Core   | #27456          | CAVIUM_ERRATUM_27456    |
 | Cavium         | ThunderX SMMUv2 | #27704          | N/A		       |
+|                |                 |                 |                         |
+| Freescale/NXP  | LS2080A/LS1043A | A-008585        | FSL_ERRATUM_A008585     |
diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
index fbe0ca3..927dc6f 100644
--- a/arch/arm64/include/asm/arch_timer.h
+++ b/arch/arm64/include/asm/arch_timer.h
@@ -23,10 +23,36 @@
 
 #include <linux/bug.h>
 #include <linux/init.h>
+#include <linux/jump_label.h>
 #include <linux/types.h>
 
 #include <clocksource/arm_arch_timer.h>
 
+extern struct static_key_false arch_timer_read_ool_enabled;
+
+#define ARCH_TIMER_REG_READ(reg, func) \
+extern u64 func##_ool(void); \
+static inline u64 __##func(void) \
+{ \
+	u64 val; \
+	asm volatile("mrs %0, " reg : "=r" (val)); \
+	return val; \
+} \
+static inline u64 _##func(void) \
+{ \
+	if (IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) && \
+	    static_branch_unlikely(&arch_timer_read_ool_enabled)) \
+		return func##_ool(); \
+	else \
+		return __##func(); \
+}
+
+ARCH_TIMER_REG_READ("cntp_tval_el0", arch_timer_get_ptval)
+ARCH_TIMER_REG_READ("cntv_tval_el0", arch_timer_get_vtval)
+ARCH_TIMER_REG_READ("cntvct_el0", arch_counter_get_cntvct)
+
+#undef ARCH_TIMER_REG_READ
+
 /*
  * These register accessors are marked inline so the compiler can
  * nicely work out which register we want, and chuck away the rest of
@@ -58,6 +84,16 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
 	isb();
 }
 
+static __always_inline void arch_timer_cval_write_cp15(int access, u64 val)
+{
+	if (access == ARCH_TIMER_PHYS_ACCESS)
+		asm volatile("msr cntp_cval_el0, %0" : : "r" (val));
+	else if (access == ARCH_TIMER_VIRT_ACCESS)
+		asm volatile("msr cntv_cval_el0, %0" : : "r" (val));
+
+	isb();
+}
+
 static __always_inline
 u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
 {
@@ -66,19 +102,19 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
 	if (access == ARCH_TIMER_PHYS_ACCESS) {
 		switch (reg) {
 		case ARCH_TIMER_REG_CTRL:
-			asm volatile("mrs %0,  cntp_ctl_el0" : "=r" (val));
+			asm volatile("mrs %0, cntp_ctl_el0" : "=r" (val));
 			break;
 		case ARCH_TIMER_REG_TVAL:
-			asm volatile("mrs %0, cntp_tval_el0" : "=r" (val));
+			val = _arch_timer_get_ptval();
 			break;
 		}
 	} else if (access == ARCH_TIMER_VIRT_ACCESS) {
 		switch (reg) {
 		case ARCH_TIMER_REG_CTRL:
-			asm volatile("mrs %0,  cntv_ctl_el0" : "=r" (val));
+			asm volatile("mrs %0, cntv_ctl_el0" : "=r" (val));
 			break;
 		case ARCH_TIMER_REG_TVAL:
-			asm volatile("mrs %0, cntv_tval_el0" : "=r" (val));
+			val = _arch_timer_get_vtval();
 			break;
 		}
 	}
@@ -116,12 +152,8 @@ static inline u64 arch_counter_get_cntpct(void)
 
 static inline u64 arch_counter_get_cntvct(void)
 {
-	u64 cval;
-
 	isb();
-	asm volatile("mrs %0, cntvct_el0" : "=r" (cval));
-
-	return cval;
+	return _arch_counter_get_cntvct();
 }
 
 static inline int arch_timer_arch_init(void)
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 47352d2..48c6039 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -223,6 +223,16 @@ config ARM_ARCH_TIMER_EVTSTREAM
 	  This must be disabled for hardware validation purposes to detect any
 	  hardware anomalies of missing events.
 
+config FSL_ERRATUM_A008585
+	bool "Workaround for Freescale/NXP Erratum A-008585"
+	default y
+	depends on ARM_ARCH_TIMER && ARM64
+	help
+	  This option enables a workaround for Freescale/NXP Erratum
+	  A-008585 ("ARM generic timer may contain an erroneous
+	  value").  The workaround will only be active if the
+	  fsl,erratum-a008585 property is found in the timer node.
+
 config ARM_GLOBAL_TIMER
 	bool
 	select CLKSRC_OF if OF
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 4814446..b857027 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -83,6 +83,51 @@ static bool arch_timer_mem_use_virtual;
  * Architected system timer support.
  */
 
+#ifdef CONFIG_FSL_ERRATUM_A008585
+DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled);
+EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled);
+
+/*
+ * __always_inline is used to ensure that func() is not an actual function
+ * pointer, which would result in the register accesses potentially being too
+ * far apart for the loop to work.
+ *
+ * The timeout is an arbitrary value well beyond the highest number
+ * of iterations the loop has been observed to take.
+ */
+static __always_inline u64 fsl_a008585_reread_counter(u64 (*func)(void))
+{
+	u64 cval_old, cval_new;
+	int timeout = 200;
+
+	do {
+		isb();
+		cval_old = func();
+		cval_new = func();
+		timeout--;
+	} while (unlikely(cval_old != cval_new) && timeout);
+
+	WARN_ON_ONCE(!timeout);
+	return cval_new;
+}
+
+u64 arch_counter_get_cntvct_ool(void)
+{
+	return fsl_a008585_reread_counter(__arch_counter_get_cntvct);
+}
+
+u64 arch_timer_get_vtval_ool(void)
+{
+	return fsl_a008585_reread_counter(__arch_timer_get_vtval);
+}
+
+u64 arch_timer_get_ptval_ool(void)
+{
+	return fsl_a008585_reread_counter(__arch_timer_get_ptval);
+}
+
+#endif /* CONFIG_FSL_ERRATUM_A008585 */
+
 static __always_inline
 void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
 			  struct clock_event_device *clk)
@@ -232,6 +277,35 @@ static __always_inline void set_next_event(const int access, unsigned long evt,
 	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
 }
 
+#ifdef CONFIG_FSL_ERRATUM_A008585
+static __always_inline void fsl_a008585_set_next_event(const int access,
+		unsigned long evt, struct clock_event_device *clk)
+{
+	unsigned long ctrl;
+	u64 cval = evt + arch_counter_get_cntvct();
+
+	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
+	ctrl |= ARCH_TIMER_CTRL_ENABLE;
+	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
+	arch_timer_cval_write_cp15(access, cval);
+	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
+}
+
+static int fsl_a008585_set_next_event_virt(unsigned long evt,
+					   struct clock_event_device *clk)
+{
+	fsl_a008585_set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
+	return 0;
+}
+
+static int fsl_a008585_set_next_event_phys(unsigned long evt,
+					   struct clock_event_device *clk)
+{
+	fsl_a008585_set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
+	return 0;
+}
+#endif /* CONFIG_FSL_ERRATUM_A008585 */
+
 static int arch_timer_set_next_event_virt(unsigned long evt,
 					  struct clock_event_device *clk)
 {
@@ -260,6 +334,19 @@ static int arch_timer_set_next_event_phys_mem(unsigned long evt,
 	return 0;
 }
 
+static void fsl_a008585_set_sne(struct clock_event_device *clk)
+{
+#ifdef CONFIG_FSL_ERRATUM_A008585
+	if (!static_branch_unlikely(&arch_timer_read_ool_enabled))
+		return;
+
+	if (arch_timer_uses_ppi == VIRT_PPI)
+		clk->set_next_event = fsl_a008585_set_next_event_virt;
+	else
+		clk->set_next_event = fsl_a008585_set_next_event_phys;
+#endif
+}
+
 static void __arch_timer_setup(unsigned type,
 			       struct clock_event_device *clk)
 {
@@ -288,6 +375,8 @@ static void __arch_timer_setup(unsigned type,
 		default:
 			BUG();
 		}
+
+		fsl_a008585_set_sne(clk);
 	} else {
 		clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
 		clk->name = "arch_mem_timer";
@@ -485,6 +574,15 @@ static void __init arch_counter_register(unsigned type)
 			arch_timer_read_counter = arch_counter_get_cntvct;
 		else
 			arch_timer_read_counter = arch_counter_get_cntpct;
+
+#ifdef CONFIG_FSL_ERRATUM_A008585
+		/*
+		 * Don't use the vdso fastpath if errata require using
+		 * the out-of-line counter accessor.
+		 */
+		if (static_branch_unlikely(&arch_timer_read_ool_enabled))
+			clocksource_counter.name = "arch_sys_counter_ool";
+#endif
 	} else {
 		arch_timer_read_counter = arch_counter_get_cntvct_mem;
 
@@ -766,6 +864,11 @@ static void __init arch_timer_of_init(struct device_node *np)
 
 	arch_timer_c3stop = !of_property_read_bool(np, "always-on");
 
+#ifdef CONFIG_FSL_ERRATUM_A008585
+	if (of_property_read_bool(np, "fsl,erratum-a008585"))
+		static_branch_enable(&arch_timer_read_ool_enabled);
+#endif
+
 	/*
 	 * If we cannot rely on firmware initializing the timer registers then
 	 * we should use the physical timers instead.
-- 
2.7.4

[PATCH v4 4/4] arm/arm64: arch_timer: Use archdata to indicate vdso suitability

[Scott Wood]

Instead of comparing the name to a magic string, use archdata to
explicitly communicate whether the arch timer is suitable for
direct vdso access.

Signed-off-by: Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org>
---
v4: new patch

I'm putting this after the other patches, in the hopes that if there
are issues with this patch, it doesn't hold up the others.

 arch/arm/Kconfig                     |  1 +
 arch/arm/include/asm/clocksource.h   |  8 ++++++++
 arch/arm/kernel/vdso.c               |  2 +-
 arch/arm64/Kconfig                   |  1 +
 arch/arm64/include/asm/clocksource.h |  8 ++++++++
 arch/arm64/kernel/vdso.c             |  2 +-
 drivers/clocksource/arm_arch_timer.c | 11 +++--------
 7 files changed, 23 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm/include/asm/clocksource.h
 create mode 100644 arch/arm64/include/asm/clocksource.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 90542db..dcdcd78 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1,6 +1,7 @@
 config ARM
 	bool
 	default y
+	select ARCH_CLOCKSOURCE_DATA
 	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
 	select ARCH_HAS_DEVMEM_IS_ALLOWED
 	select ARCH_HAS_ELF_RANDOMIZE
diff --git a/arch/arm/include/asm/clocksource.h b/arch/arm/include/asm/clocksource.h
new file mode 100644
index 0000000..0b350a7
--- /dev/null
+++ b/arch/arm/include/asm/clocksource.h
@@ -0,0 +1,8 @@
+#ifndef _ASM_CLOCKSOURCE_H
+#define _ASM_CLOCKSOURCE_H
+
+struct arch_clocksource_data {
+	bool vdso_direct;	/* Usable for direct VDSO access? */
+};
+
+#endif
diff --git a/arch/arm/kernel/vdso.c b/arch/arm/kernel/vdso.c
index 994e971..a0affd1 100644
--- a/arch/arm/kernel/vdso.c
+++ b/arch/arm/kernel/vdso.c
@@ -270,7 +270,7 @@ static bool tk_is_cntvct(const struct timekeeper *tk)
 	if (!IS_ENABLED(CONFIG_ARM_ARCH_TIMER))
 		return false;
 
-	if (strcmp(tk->tkr_mono.clock->name, "arch_sys_counter") != 0)
+	if (!tk->tkr_mono.clock->archdata.vdso_direct)
 		return false;
 
 	return true;
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 5a0a691..24c4b2c 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -3,6 +3,7 @@ config ARM64
 	select ACPI_CCA_REQUIRED if ACPI
 	select ACPI_GENERIC_GSI if ACPI
 	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
+	select ARCH_CLOCKSOURCE_DATA
 	select ARCH_HAS_DEVMEM_IS_ALLOWED
 	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
 	select ARCH_HAS_ELF_RANDOMIZE
diff --git a/arch/arm64/include/asm/clocksource.h b/arch/arm64/include/asm/clocksource.h
new file mode 100644
index 0000000..0b350a7
--- /dev/null
+++ b/arch/arm64/include/asm/clocksource.h
@@ -0,0 +1,8 @@
+#ifndef _ASM_CLOCKSOURCE_H
+#define _ASM_CLOCKSOURCE_H
+
+struct arch_clocksource_data {
+	bool vdso_direct;	/* Usable for direct VDSO access? */
+};
+
+#endif
diff --git a/arch/arm64/kernel/vdso.c b/arch/arm64/kernel/vdso.c
index 9fefb00..ee107f2 100644
--- a/arch/arm64/kernel/vdso.c
+++ b/arch/arm64/kernel/vdso.c
@@ -201,7 +201,7 @@ up_fail:
  */
 void update_vsyscall(struct timekeeper *tk)
 {
-	u32 use_syscall = strcmp(tk->tkr_mono.clock->name, "arch_sys_counter");
+	u32 use_syscall = !tk->tkr_mono.clock->archdata.vdso_direct;
 
 	++vdso_data->tb_seq_count;
 	smp_wmb();
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index b857027..a5654a4 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -575,23 +575,18 @@ static void __init arch_counter_register(unsigned type)
 		else
 			arch_timer_read_counter = arch_counter_get_cntpct;
 
+		clocksource_counter.archdata.vdso_direct = true;
+
 #ifdef CONFIG_FSL_ERRATUM_A008585
 		/*
 		 * Don't use the vdso fastpath if errata require using
 		 * the out-of-line counter accessor.
 		 */
 		if (static_branch_unlikely(&arch_timer_read_ool_enabled))
-			clocksource_counter.name = "arch_sys_counter_ool";
+			clocksource_counter.archdata.vdso_direct = false;
 #endif
 	} else {
 		arch_timer_read_counter = arch_counter_get_cntvct_mem;
-
-		/* If the clocksource name is "arch_sys_counter" the
-		 * VDSO will attempt to read the CP15-based counter.
-		 * Ensure this does not happen when CP15-based
-		 * counter is not available.
-		 */
-		clocksource_counter.name = "arch_mem_counter";
 	}
 
 	start_count = arch_timer_read_counter();
-- 
2.7.4

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[PATCH v4 4/4] arm/arm64: arch_timer: Use archdata to indicate vdso suitability

[Scott Wood]

Instead of comparing the name to a magic string, use archdata to
explicitly communicate whether the arch timer is suitable for
direct vdso access.

Signed-off-by: Scott Wood <oss@buserror.net>
---
v4: new patch

I'm putting this after the other patches, in the hopes that if there
are issues with this patch, it doesn't hold up the others.

 arch/arm/Kconfig                     |  1 +
 arch/arm/include/asm/clocksource.h   |  8 ++++++++
 arch/arm/kernel/vdso.c               |  2 +-
 arch/arm64/Kconfig                   |  1 +
 arch/arm64/include/asm/clocksource.h |  8 ++++++++
 arch/arm64/kernel/vdso.c             |  2 +-
 drivers/clocksource/arm_arch_timer.c | 11 +++--------
 7 files changed, 23 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm/include/asm/clocksource.h
 create mode 100644 arch/arm64/include/asm/clocksource.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 90542db..dcdcd78 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1,6 +1,7 @@
 config ARM
 	bool
 	default y
+	select ARCH_CLOCKSOURCE_DATA
 	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
 	select ARCH_HAS_DEVMEM_IS_ALLOWED
 	select ARCH_HAS_ELF_RANDOMIZE
diff --git a/arch/arm/include/asm/clocksource.h b/arch/arm/include/asm/clocksource.h
new file mode 100644
index 0000000..0b350a7
--- /dev/null
+++ b/arch/arm/include/asm/clocksource.h
@@ -0,0 +1,8 @@
+#ifndef _ASM_CLOCKSOURCE_H
+#define _ASM_CLOCKSOURCE_H
+
+struct arch_clocksource_data {
+	bool vdso_direct;	/* Usable for direct VDSO access? */
+};
+
+#endif
diff --git a/arch/arm/kernel/vdso.c b/arch/arm/kernel/vdso.c
index 994e971..a0affd1 100644
--- a/arch/arm/kernel/vdso.c
+++ b/arch/arm/kernel/vdso.c
@@ -270,7 +270,7 @@ static bool tk_is_cntvct(const struct timekeeper *tk)
 	if (!IS_ENABLED(CONFIG_ARM_ARCH_TIMER))
 		return false;
 
-	if (strcmp(tk->tkr_mono.clock->name, "arch_sys_counter") != 0)
+	if (!tk->tkr_mono.clock->archdata.vdso_direct)
 		return false;
 
 	return true;
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 5a0a691..24c4b2c 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -3,6 +3,7 @@ config ARM64
 	select ACPI_CCA_REQUIRED if ACPI
 	select ACPI_GENERIC_GSI if ACPI
 	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
+	select ARCH_CLOCKSOURCE_DATA
 	select ARCH_HAS_DEVMEM_IS_ALLOWED
 	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
 	select ARCH_HAS_ELF_RANDOMIZE
diff --git a/arch/arm64/include/asm/clocksource.h b/arch/arm64/include/asm/clocksource.h
new file mode 100644
index 0000000..0b350a7
--- /dev/null
+++ b/arch/arm64/include/asm/clocksource.h
@@ -0,0 +1,8 @@
+#ifndef _ASM_CLOCKSOURCE_H
+#define _ASM_CLOCKSOURCE_H
+
+struct arch_clocksource_data {
+	bool vdso_direct;	/* Usable for direct VDSO access? */
+};
+
+#endif
diff --git a/arch/arm64/kernel/vdso.c b/arch/arm64/kernel/vdso.c
index 9fefb00..ee107f2 100644
--- a/arch/arm64/kernel/vdso.c
+++ b/arch/arm64/kernel/vdso.c
@@ -201,7 +201,7 @@ up_fail:
  */
 void update_vsyscall(struct timekeeper *tk)
 {
-	u32 use_syscall = strcmp(tk->tkr_mono.clock->name, "arch_sys_counter");
+	u32 use_syscall = !tk->tkr_mono.clock->archdata.vdso_direct;
 
 	++vdso_data->tb_seq_count;
 	smp_wmb();
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index b857027..a5654a4 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -575,23 +575,18 @@ static void __init arch_counter_register(unsigned type)
 		else
 			arch_timer_read_counter = arch_counter_get_cntpct;
 
+		clocksource_counter.archdata.vdso_direct = true;
+
 #ifdef CONFIG_FSL_ERRATUM_A008585
 		/*
 		 * Don't use the vdso fastpath if errata require using
 		 * the out-of-line counter accessor.
 		 */
 		if (static_branch_unlikely(&arch_timer_read_ool_enabled))
-			clocksource_counter.name = "arch_sys_counter_ool";
+			clocksource_counter.archdata.vdso_direct = false;
 #endif
 	} else {
 		arch_timer_read_counter = arch_counter_get_cntvct_mem;
-
-		/* If the clocksource name is "arch_sys_counter" the
-		 * VDSO will attempt to read the CP15-based counter.
-		 * Ensure this does not happen when CP15-based
-		 * counter is not available.
-		 */
-		clocksource_counter.name = "arch_mem_counter";
 	}
 
 	start_count = arch_timer_read_counter();
-- 
2.7.4

Re: [PATCH v4 4/4] arm/arm64: arch_timer: Use archdata to indicate vdso suitability

[Will Deacon]

On Thu, Jul 07, 2016 at 02:46:12AM -0500, Scott Wood wrote:
> Instead of comparing the name to a magic string, use archdata to
> explicitly communicate whether the arch timer is suitable for
> direct vdso access.
> 
> Signed-off-by: Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org>
> ---
> v4: new patch
> 
> I'm putting this after the other patches, in the hopes that if there
> are issues with this patch, it doesn't hold up the others.
> 
>  arch/arm/Kconfig                     |  1 +
>  arch/arm/include/asm/clocksource.h   |  8 ++++++++
>  arch/arm/kernel/vdso.c               |  2 +-
>  arch/arm64/Kconfig                   |  1 +
>  arch/arm64/include/asm/clocksource.h |  8 ++++++++
>  arch/arm64/kernel/vdso.c             |  2 +-
>  drivers/clocksource/arm_arch_timer.c | 11 +++--------
>  7 files changed, 23 insertions(+), 10 deletions(-)
>  create mode 100644 arch/arm/include/asm/clocksource.h
>  create mode 100644 arch/arm64/include/asm/clocksource.h
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 90542db..dcdcd78 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1,6 +1,7 @@
>  config ARM
>  	bool
>  	default y
> +	select ARCH_CLOCKSOURCE_DATA
>  	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
>  	select ARCH_HAS_DEVMEM_IS_ALLOWED
>  	select ARCH_HAS_ELF_RANDOMIZE
> diff --git a/arch/arm/include/asm/clocksource.h b/arch/arm/include/asm/clocksource.h
> new file mode 100644
> index 0000000..0b350a7
> --- /dev/null
> +++ b/arch/arm/include/asm/clocksource.h
> @@ -0,0 +1,8 @@
> +#ifndef _ASM_CLOCKSOURCE_H
> +#define _ASM_CLOCKSOURCE_H
> +
> +struct arch_clocksource_data {
> +	bool vdso_direct;	/* Usable for direct VDSO access? */
> +};
> +
> +#endif
> diff --git a/arch/arm/kernel/vdso.c b/arch/arm/kernel/vdso.c
> index 994e971..a0affd1 100644
> --- a/arch/arm/kernel/vdso.c
> +++ b/arch/arm/kernel/vdso.c
> @@ -270,7 +270,7 @@ static bool tk_is_cntvct(const struct timekeeper *tk)
>  	if (!IS_ENABLED(CONFIG_ARM_ARCH_TIMER))
>  		return false;
>  
> -	if (strcmp(tk->tkr_mono.clock->name, "arch_sys_counter") != 0)
> +	if (!tk->tkr_mono.clock->archdata.vdso_direct)
>  		return false;
>  
>  	return true;
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 5a0a691..24c4b2c 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -3,6 +3,7 @@ config ARM64
>  	select ACPI_CCA_REQUIRED if ACPI
>  	select ACPI_GENERIC_GSI if ACPI
>  	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
> +	select ARCH_CLOCKSOURCE_DATA
>  	select ARCH_HAS_DEVMEM_IS_ALLOWED
>  	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
>  	select ARCH_HAS_ELF_RANDOMIZE
> diff --git a/arch/arm64/include/asm/clocksource.h b/arch/arm64/include/asm/clocksource.h
> new file mode 100644
> index 0000000..0b350a7
> --- /dev/null
> +++ b/arch/arm64/include/asm/clocksource.h
> @@ -0,0 +1,8 @@
> +#ifndef _ASM_CLOCKSOURCE_H
> +#define _ASM_CLOCKSOURCE_H
> +
> +struct arch_clocksource_data {
> +	bool vdso_direct;	/* Usable for direct VDSO access? */
> +};

Looks fine to me. I'd rather we followed exactly what x86 does here, in
the hope that it can eventually find its way into core code, but there's
no ABI implication for this structure so we can always do that later.

Acked-by: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>

Will
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[PATCH v4 4/4] arm/arm64: arch_timer: Use archdata to indicate vdso suitability

[Will Deacon]

On Thu, Jul 07, 2016 at 02:46:12AM -0500, Scott Wood wrote:
> Instead of comparing the name to a magic string, use archdata to
> explicitly communicate whether the arch timer is suitable for
> direct vdso access.
> 
> Signed-off-by: Scott Wood <oss@buserror.net>
> ---
> v4: new patch
> 
> I'm putting this after the other patches, in the hopes that if there
> are issues with this patch, it doesn't hold up the others.
> 
>  arch/arm/Kconfig                     |  1 +
>  arch/arm/include/asm/clocksource.h   |  8 ++++++++
>  arch/arm/kernel/vdso.c               |  2 +-
>  arch/arm64/Kconfig                   |  1 +
>  arch/arm64/include/asm/clocksource.h |  8 ++++++++
>  arch/arm64/kernel/vdso.c             |  2 +-
>  drivers/clocksource/arm_arch_timer.c | 11 +++--------
>  7 files changed, 23 insertions(+), 10 deletions(-)
>  create mode 100644 arch/arm/include/asm/clocksource.h
>  create mode 100644 arch/arm64/include/asm/clocksource.h
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 90542db..dcdcd78 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1,6 +1,7 @@
>  config ARM
>  	bool
>  	default y
> +	select ARCH_CLOCKSOURCE_DATA
>  	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
>  	select ARCH_HAS_DEVMEM_IS_ALLOWED
>  	select ARCH_HAS_ELF_RANDOMIZE
> diff --git a/arch/arm/include/asm/clocksource.h b/arch/arm/include/asm/clocksource.h
> new file mode 100644
> index 0000000..0b350a7
> --- /dev/null
> +++ b/arch/arm/include/asm/clocksource.h
> @@ -0,0 +1,8 @@
> +#ifndef _ASM_CLOCKSOURCE_H
> +#define _ASM_CLOCKSOURCE_H
> +
> +struct arch_clocksource_data {
> +	bool vdso_direct;	/* Usable for direct VDSO access? */
> +};
> +
> +#endif
> diff --git a/arch/arm/kernel/vdso.c b/arch/arm/kernel/vdso.c
> index 994e971..a0affd1 100644
> --- a/arch/arm/kernel/vdso.c
> +++ b/arch/arm/kernel/vdso.c
> @@ -270,7 +270,7 @@ static bool tk_is_cntvct(const struct timekeeper *tk)
>  	if (!IS_ENABLED(CONFIG_ARM_ARCH_TIMER))
>  		return false;
>  
> -	if (strcmp(tk->tkr_mono.clock->name, "arch_sys_counter") != 0)
> +	if (!tk->tkr_mono.clock->archdata.vdso_direct)
>  		return false;
>  
>  	return true;
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 5a0a691..24c4b2c 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -3,6 +3,7 @@ config ARM64
>  	select ACPI_CCA_REQUIRED if ACPI
>  	select ACPI_GENERIC_GSI if ACPI
>  	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
> +	select ARCH_CLOCKSOURCE_DATA
>  	select ARCH_HAS_DEVMEM_IS_ALLOWED
>  	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
>  	select ARCH_HAS_ELF_RANDOMIZE
> diff --git a/arch/arm64/include/asm/clocksource.h b/arch/arm64/include/asm/clocksource.h
> new file mode 100644
> index 0000000..0b350a7
> --- /dev/null
> +++ b/arch/arm64/include/asm/clocksource.h
> @@ -0,0 +1,8 @@
> +#ifndef _ASM_CLOCKSOURCE_H
> +#define _ASM_CLOCKSOURCE_H
> +
> +struct arch_clocksource_data {
> +	bool vdso_direct;	/* Usable for direct VDSO access? */
> +};

Looks fine to me. I'd rather we followed exactly what x86 does here, in
the hope that it can eventually find its way into core code, but there's
no ABI implication for this structure so we can always do that later.

Acked-by: Will Deacon <will.deacon@arm.com>

Will

Re: [PATCH v4 1/4] arm64: arch_timer: Add device tree binding for A-008585 erratum

[Matthias Brugger]

Hi all,

On 07/07/16 09:46, Scott Wood wrote:
> This erratum describes a bug in logic outside the core, so MIDR can't be
> used to identify its presence, and reading an SoC-specific revision
> register from common arch timer code would be awkward.  So, describe it
> in the device tree.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Acked-by: Rob Herring <robh@kernel.org>
> ---

As of today I wasn't able to find this series in linux-next. Was this 
series somehow forgotten? Scott maybe you can resend the patches adding 
the clocksource maintainer.

Regards,
Matthias

[PATCH v4 1/4] arm64: arch_timer: Add device tree binding for A-008585 erratum

[Matthias Brugger]

Hi all,

On 07/07/16 09:46, Scott Wood wrote:
> This erratum describes a bug in logic outside the core, so MIDR can't be
> used to identify its presence, and reading an SoC-specific revision
> register from common arch timer code would be awkward.  So, describe it
> in the device tree.
>
> Signed-off-by: Scott Wood <oss@buserror.net>
> Acked-by: Rob Herring <robh@kernel.org>
> ---

As of today I wasn't able to find this series in linux-next. Was this 
series somehow forgotten? Scott maybe you can resend the patches adding 
the clocksource maintainer.

Regards,
Matthias

Re: [PATCH v4 3/4] arm64: arch_timer: Work around QorIQ Erratum A-008585

[Marc Zyngier]

On Thu, 7 Jul 2016 02:46:11 -0500
Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org> wrote:

(+Mark)

> Erratum A-008585 says that the ARM generic timer counter "has the
> potential to contain an erroneous value for a small number of core
> clock cycles every time the timer value changes".  Accesses to TVAL
> (both read and write) are also affected due to the implicit counter
> read.  Accesses to CVAL are not affected.
> 
> The workaround is to reread TVAL and count registers until successive reads
> return the same value, and when writing TVAL to retry until counter
> reads before and after the write return the same value.
> 
> This erratum can be found on LS1043A and LS2080A.
> 
> Signed-off-by: Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org>
> ---
> v4:
> - Undef ARCH_TIMER_REG_READ after use
> 
> v3:
> - Used cval rather than a loop for the write side of the erratum
> - Added a Kconfig control
> - Moved the device tree binding into its own patch
> - Added erratum to silicon-errata.txt
> - Changed function names to contain the erratum name
> - Factored out the setting of erratum versions of set_next_event
>   to improve readability
> - Added a comment clarifying that the timeout is arbitrary
> 
> v2:
> Significant rework based on feedback, including using static_key,
> disabling VDSO counter access rather than adding the workaround to the
> VDSO, and uninlining the loops.
> 
> Dropped the separate property for indicating that writes to TVAL are
> affected, as I believe that's just a side effect of the implicit
> counter read being corrupted, and thus a chip that is affected by one
> will always be affected by the other.
> 
> Dropped the arm32 portion as it seems there was confusion about whether
> LS1021A is affected.  Currently I am being told that it is not
> affected.
> 
> I considered writing to CVAL rather than looping on TVAL writes, but
> that would still have required separate set_next_event() code for the
> erratum, and adding CVAL to the enum would have required a bunch of
> extra handlers in switch statements (even where unused, due to compiler
> warnings about unhandled enum values) including in an arm32 header.  It
> seemed better to avoid the arm32 interaction and new untested
> accessors.
> ---
>  Documentation/arm64/silicon-errata.txt |   2 +
>  arch/arm64/include/asm/arch_timer.h    |  50 +++++++++++++---
>  drivers/clocksource/Kconfig            |  10 ++++
>  drivers/clocksource/arm_arch_timer.c   | 103 +++++++++++++++++++++++++++++++++
>  4 files changed, 156 insertions(+), 9 deletions(-)
> 
> diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
> index 4da60b4..041e3a9 100644
> --- a/Documentation/arm64/silicon-errata.txt
> +++ b/Documentation/arm64/silicon-errata.txt
> @@ -60,3 +60,5 @@ stable kernels.
>  | Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154    |
>  | Cavium         | ThunderX Core   | #27456          | CAVIUM_ERRATUM_27456    |
>  | Cavium         | ThunderX SMMUv2 | #27704          | N/A		       |
> +|                |                 |                 |                         |
> +| Freescale/NXP  | LS2080A/LS1043A | A-008585        | FSL_ERRATUM_A008585     |
> diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
> index fbe0ca3..927dc6f 100644
> --- a/arch/arm64/include/asm/arch_timer.h
> +++ b/arch/arm64/include/asm/arch_timer.h
> @@ -23,10 +23,36 @@
>  
>  #include <linux/bug.h>
>  #include <linux/init.h>
> +#include <linux/jump_label.h>
>  #include <linux/types.h>
>  
>  #include <clocksource/arm_arch_timer.h>
>  
> +extern struct static_key_false arch_timer_read_ool_enabled;
> +
> +#define ARCH_TIMER_REG_READ(reg, func) \
> +extern u64 func##_ool(void); \
> +static inline u64 __##func(void) \
> +{ \
> +	u64 val; \
> +	asm volatile("mrs %0, " reg : "=r" (val)); \
> +	return val; \
> +} \
> +static inline u64 _##func(void) \
> +{ \
> +	if (IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) && \
> +	    static_branch_unlikely(&arch_timer_read_ool_enabled)) \
> +		return func##_ool(); \
> +	else \
> +		return __##func(); \
> +}
> +
> +ARCH_TIMER_REG_READ("cntp_tval_el0", arch_timer_get_ptval)
> +ARCH_TIMER_REG_READ("cntv_tval_el0", arch_timer_get_vtval)
> +ARCH_TIMER_REG_READ("cntvct_el0", arch_counter_get_cntvct)
> +
> +#undef ARCH_TIMER_REG_READ
> +
>  /*
>   * These register accessors are marked inline so the compiler can
>   * nicely work out which register we want, and chuck away the rest of
> @@ -58,6 +84,16 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
>  	isb();
>  }
>  
> +static __always_inline void arch_timer_cval_write_cp15(int access, u64 val)
> +{
> +	if (access == ARCH_TIMER_PHYS_ACCESS)
> +		asm volatile("msr cntp_cval_el0, %0" : : "r" (val));
> +	else if (access == ARCH_TIMER_VIRT_ACCESS)
> +		asm volatile("msr cntv_cval_el0, %0" : : "r" (val));
> +
> +	isb();
> +}
> +
>  static __always_inline
>  u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
>  {
> @@ -66,19 +102,19 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
>  	if (access == ARCH_TIMER_PHYS_ACCESS) {
>  		switch (reg) {
>  		case ARCH_TIMER_REG_CTRL:
> -			asm volatile("mrs %0,  cntp_ctl_el0" : "=r" (val));
> +			asm volatile("mrs %0, cntp_ctl_el0" : "=r" (val));

Spurious change?

>  			break;
>  		case ARCH_TIMER_REG_TVAL:
> -			asm volatile("mrs %0, cntp_tval_el0" : "=r" (val));
> +			val = _arch_timer_get_ptval();
>  			break;
>  		}
>  	} else if (access == ARCH_TIMER_VIRT_ACCESS) {
>  		switch (reg) {
>  		case ARCH_TIMER_REG_CTRL:
> -			asm volatile("mrs %0,  cntv_ctl_el0" : "=r" (val));
> +			asm volatile("mrs %0, cntv_ctl_el0" : "=r" (val));

Here too?

>  			break;
>  		case ARCH_TIMER_REG_TVAL:
> -			asm volatile("mrs %0, cntv_tval_el0" : "=r" (val));
> +			val = _arch_timer_get_vtval();
>  			break;
>  		}
>  	}
> @@ -116,12 +152,8 @@ static inline u64 arch_counter_get_cntpct(void)
>  
>  static inline u64 arch_counter_get_cntvct(void)
>  {
> -	u64 cval;
> -
>  	isb();
> -	asm volatile("mrs %0, cntvct_el0" : "=r" (cval));
> -
> -	return cval;
> +	return _arch_counter_get_cntvct();
>  }
>  
>  static inline int arch_timer_arch_init(void)
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 47352d2..48c6039 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -223,6 +223,16 @@ config ARM_ARCH_TIMER_EVTSTREAM
>  	  This must be disabled for hardware validation purposes to detect any
>  	  hardware anomalies of missing events.
>  
> +config FSL_ERRATUM_A008585
> +	bool "Workaround for Freescale/NXP Erratum A-008585"
> +	default y
> +	depends on ARM_ARCH_TIMER && ARM64
> +	help
> +	  This option enables a workaround for Freescale/NXP Erratum
> +	  A-008585 ("ARM generic timer may contain an erroneous
> +	  value").  The workaround will only be active if the
> +	  fsl,erratum-a008585 property is found in the timer node.
> +
>  config ARM_GLOBAL_TIMER
>  	bool
>  	select CLKSRC_OF if OF
> diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
> index 4814446..b857027 100644
> --- a/drivers/clocksource/arm_arch_timer.c
> +++ b/drivers/clocksource/arm_arch_timer.c
> @@ -83,6 +83,51 @@ static bool arch_timer_mem_use_virtual;
>   * Architected system timer support.
>   */
>  
> +#ifdef CONFIG_FSL_ERRATUM_A008585
> +DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled);
> +EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled);
> +
> +/*
> + * __always_inline is used to ensure that func() is not an actual function
> + * pointer, which would result in the register accesses potentially being too
> + * far apart for the loop to work.
> + *
> + * The timeout is an arbitrary value well beyond the highest number
> + * of iterations the loop has been observed to take.
> + */
> +static __always_inline u64 fsl_a008585_reread_counter(u64 (*func)(void))
> +{
> +	u64 cval_old, cval_new;
> +	int timeout = 200;
> +
> +	do {
> +		isb();
> +		cval_old = func();
> +		cval_new = func();
> +		timeout--;
> +	} while (unlikely(cval_old != cval_new) && timeout);
> +
> +	WARN_ON_ONCE(!timeout);
> +	return cval_new;
> +}
> +
> +u64 arch_counter_get_cntvct_ool(void)
> +{
> +	return fsl_a008585_reread_counter(__arch_counter_get_cntvct);
> +}
> +
> +u64 arch_timer_get_vtval_ool(void)
> +{
> +	return fsl_a008585_reread_counter(__arch_timer_get_vtval);
> +}
> +
> +u64 arch_timer_get_ptval_ool(void)
> +{
> +	return fsl_a008585_reread_counter(__arch_timer_get_ptval);
> +}
> +
> +#endif /* CONFIG_FSL_ERRATUM_A008585 */
> +
>  static __always_inline
>  void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
>  			  struct clock_event_device *clk)
> @@ -232,6 +277,35 @@ static __always_inline void set_next_event(const int access, unsigned long evt,
>  	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
>  }
>  
> +#ifdef CONFIG_FSL_ERRATUM_A008585
> +static __always_inline void fsl_a008585_set_next_event(const int access,
> +		unsigned long evt, struct clock_event_device *clk)
> +{
> +	unsigned long ctrl;
> +	u64 cval = evt + arch_counter_get_cntvct();
> +
> +	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
> +	ctrl |= ARCH_TIMER_CTRL_ENABLE;
> +	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
> +	arch_timer_cval_write_cp15(access, cval);
> +	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
> +}
> +
> +static int fsl_a008585_set_next_event_virt(unsigned long evt,
> +					   struct clock_event_device *clk)
> +{
> +	fsl_a008585_set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
> +	return 0;
> +}
> +
> +static int fsl_a008585_set_next_event_phys(unsigned long evt,
> +					   struct clock_event_device *clk)
> +{
> +	fsl_a008585_set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
> +	return 0;
> +}
> +#endif /* CONFIG_FSL_ERRATUM_A008585 */
> +
>  static int arch_timer_set_next_event_virt(unsigned long evt,
>  					  struct clock_event_device *clk)
>  {
> @@ -260,6 +334,19 @@ static int arch_timer_set_next_event_phys_mem(unsigned long evt,
>  	return 0;
>  }
>  
> +static void fsl_a008585_set_sne(struct clock_event_device *clk)
> +{
> +#ifdef CONFIG_FSL_ERRATUM_A008585
> +	if (!static_branch_unlikely(&arch_timer_read_ool_enabled))
> +		return;
> +
> +	if (arch_timer_uses_ppi == VIRT_PPI)
> +		clk->set_next_event = fsl_a008585_set_next_event_virt;
> +	else
> +		clk->set_next_event = fsl_a008585_set_next_event_phys;
> +#endif
> +}
> +
>  static void __arch_timer_setup(unsigned type,
>  			       struct clock_event_device *clk)
>  {
> @@ -288,6 +375,8 @@ static void __arch_timer_setup(unsigned type,
>  		default:
>  			BUG();
>  		}
> +
> +		fsl_a008585_set_sne(clk);
>  	} else {
>  		clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
>  		clk->name = "arch_mem_timer";
> @@ -485,6 +574,15 @@ static void __init arch_counter_register(unsigned type)
>  			arch_timer_read_counter = arch_counter_get_cntvct;
>  		else
>  			arch_timer_read_counter = arch_counter_get_cntpct;
> +
> +#ifdef CONFIG_FSL_ERRATUM_A008585
> +		/*
> +		 * Don't use the vdso fastpath if errata require using
> +		 * the out-of-line counter accessor.
> +		 */
> +		if (static_branch_unlikely(&arch_timer_read_ool_enabled))
> +			clocksource_counter.name = "arch_sys_counter_ool";
> +#endif
>  	} else {
>  		arch_timer_read_counter = arch_counter_get_cntvct_mem;
>  
> @@ -766,6 +864,11 @@ static void __init arch_timer_of_init(struct device_node *np)
>  
>  	arch_timer_c3stop = !of_property_read_bool(np, "always-on");
>  
> +#ifdef CONFIG_FSL_ERRATUM_A008585
> +	if (of_property_read_bool(np, "fsl,erratum-a008585"))
> +		static_branch_enable(&arch_timer_read_ool_enabled);
> +#endif
> +
>  	/*
>  	 * If we cannot rely on firmware initializing the timer registers then
>  	 * we should use the physical timers instead.


I'm still worried that this series doesn't address Xen or KVM guests
that need to be made aware of the broken timers.

At the very least, I'd like a kernel command line option that'd let the
user reliably run its VMs. You can do something along the lines of
46fd5c6b, and have a command line argument like
"clocksource.arm_arch_timer.fsl-a008585=1", which would enable the
workaround.

Thanks,

	M.
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[PATCH v4 3/4] arm64: arch_timer: Work around QorIQ Erratum A-008585

[Marc Zyngier]

On Thu, 7 Jul 2016 02:46:11 -0500
Scott Wood <oss@buserror.net> wrote:

(+Mark)

> Erratum A-008585 says that the ARM generic timer counter "has the
> potential to contain an erroneous value for a small number of core
> clock cycles every time the timer value changes".  Accesses to TVAL
> (both read and write) are also affected due to the implicit counter
> read.  Accesses to CVAL are not affected.
> 
> The workaround is to reread TVAL and count registers until successive reads
> return the same value, and when writing TVAL to retry until counter
> reads before and after the write return the same value.
> 
> This erratum can be found on LS1043A and LS2080A.
> 
> Signed-off-by: Scott Wood <oss@buserror.net>
> ---
> v4:
> - Undef ARCH_TIMER_REG_READ after use
> 
> v3:
> - Used cval rather than a loop for the write side of the erratum
> - Added a Kconfig control
> - Moved the device tree binding into its own patch
> - Added erratum to silicon-errata.txt
> - Changed function names to contain the erratum name
> - Factored out the setting of erratum versions of set_next_event
>   to improve readability
> - Added a comment clarifying that the timeout is arbitrary
> 
> v2:
> Significant rework based on feedback, including using static_key,
> disabling VDSO counter access rather than adding the workaround to the
> VDSO, and uninlining the loops.
> 
> Dropped the separate property for indicating that writes to TVAL are
> affected, as I believe that's just a side effect of the implicit
> counter read being corrupted, and thus a chip that is affected by one
> will always be affected by the other.
> 
> Dropped the arm32 portion as it seems there was confusion about whether
> LS1021A is affected.  Currently I am being told that it is not
> affected.
> 
> I considered writing to CVAL rather than looping on TVAL writes, but
> that would still have required separate set_next_event() code for the
> erratum, and adding CVAL to the enum would have required a bunch of
> extra handlers in switch statements (even where unused, due to compiler
> warnings about unhandled enum values) including in an arm32 header.  It
> seemed better to avoid the arm32 interaction and new untested
> accessors.
> ---
>  Documentation/arm64/silicon-errata.txt |   2 +
>  arch/arm64/include/asm/arch_timer.h    |  50 +++++++++++++---
>  drivers/clocksource/Kconfig            |  10 ++++
>  drivers/clocksource/arm_arch_timer.c   | 103 +++++++++++++++++++++++++++++++++
>  4 files changed, 156 insertions(+), 9 deletions(-)
> 
> diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
> index 4da60b4..041e3a9 100644
> --- a/Documentation/arm64/silicon-errata.txt
> +++ b/Documentation/arm64/silicon-errata.txt
> @@ -60,3 +60,5 @@ stable kernels.
>  | Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154    |
>  | Cavium         | ThunderX Core   | #27456          | CAVIUM_ERRATUM_27456    |
>  | Cavium         | ThunderX SMMUv2 | #27704          | N/A		       |
> +|                |                 |                 |                         |
> +| Freescale/NXP  | LS2080A/LS1043A | A-008585        | FSL_ERRATUM_A008585     |
> diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
> index fbe0ca3..927dc6f 100644
> --- a/arch/arm64/include/asm/arch_timer.h
> +++ b/arch/arm64/include/asm/arch_timer.h
> @@ -23,10 +23,36 @@
>  
>  #include <linux/bug.h>
>  #include <linux/init.h>
> +#include <linux/jump_label.h>
>  #include <linux/types.h>
>  
>  #include <clocksource/arm_arch_timer.h>
>  
> +extern struct static_key_false arch_timer_read_ool_enabled;
> +
> +#define ARCH_TIMER_REG_READ(reg, func) \
> +extern u64 func##_ool(void); \
> +static inline u64 __##func(void) \
> +{ \
> +	u64 val; \
> +	asm volatile("mrs %0, " reg : "=r" (val)); \
> +	return val; \
> +} \
> +static inline u64 _##func(void) \
> +{ \
> +	if (IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) && \
> +	    static_branch_unlikely(&arch_timer_read_ool_enabled)) \
> +		return func##_ool(); \
> +	else \
> +		return __##func(); \
> +}
> +
> +ARCH_TIMER_REG_READ("cntp_tval_el0", arch_timer_get_ptval)
> +ARCH_TIMER_REG_READ("cntv_tval_el0", arch_timer_get_vtval)
> +ARCH_TIMER_REG_READ("cntvct_el0", arch_counter_get_cntvct)
> +
> +#undef ARCH_TIMER_REG_READ
> +
>  /*
>   * These register accessors are marked inline so the compiler can
>   * nicely work out which register we want, and chuck away the rest of
> @@ -58,6 +84,16 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
>  	isb();
>  }
>  
> +static __always_inline void arch_timer_cval_write_cp15(int access, u64 val)
> +{
> +	if (access == ARCH_TIMER_PHYS_ACCESS)
> +		asm volatile("msr cntp_cval_el0, %0" : : "r" (val));
> +	else if (access == ARCH_TIMER_VIRT_ACCESS)
> +		asm volatile("msr cntv_cval_el0, %0" : : "r" (val));
> +
> +	isb();
> +}
> +
>  static __always_inline
>  u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
>  {
> @@ -66,19 +102,19 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
>  	if (access == ARCH_TIMER_PHYS_ACCESS) {
>  		switch (reg) {
>  		case ARCH_TIMER_REG_CTRL:
> -			asm volatile("mrs %0,  cntp_ctl_el0" : "=r" (val));
> +			asm volatile("mrs %0, cntp_ctl_el0" : "=r" (val));

Spurious change?

>  			break;
>  		case ARCH_TIMER_REG_TVAL:
> -			asm volatile("mrs %0, cntp_tval_el0" : "=r" (val));
> +			val = _arch_timer_get_ptval();
>  			break;
>  		}
>  	} else if (access == ARCH_TIMER_VIRT_ACCESS) {
>  		switch (reg) {
>  		case ARCH_TIMER_REG_CTRL:
> -			asm volatile("mrs %0,  cntv_ctl_el0" : "=r" (val));
> +			asm volatile("mrs %0, cntv_ctl_el0" : "=r" (val));

Here too?

>  			break;
>  		case ARCH_TIMER_REG_TVAL:
> -			asm volatile("mrs %0, cntv_tval_el0" : "=r" (val));
> +			val = _arch_timer_get_vtval();
>  			break;
>  		}
>  	}
> @@ -116,12 +152,8 @@ static inline u64 arch_counter_get_cntpct(void)
>  
>  static inline u64 arch_counter_get_cntvct(void)
>  {
> -	u64 cval;
> -
>  	isb();
> -	asm volatile("mrs %0, cntvct_el0" : "=r" (cval));
> -
> -	return cval;
> +	return _arch_counter_get_cntvct();
>  }
>  
>  static inline int arch_timer_arch_init(void)
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 47352d2..48c6039 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -223,6 +223,16 @@ config ARM_ARCH_TIMER_EVTSTREAM
>  	  This must be disabled for hardware validation purposes to detect any
>  	  hardware anomalies of missing events.
>  
> +config FSL_ERRATUM_A008585
> +	bool "Workaround for Freescale/NXP Erratum A-008585"
> +	default y
> +	depends on ARM_ARCH_TIMER && ARM64
> +	help
> +	  This option enables a workaround for Freescale/NXP Erratum
> +	  A-008585 ("ARM generic timer may contain an erroneous
> +	  value").  The workaround will only be active if the
> +	  fsl,erratum-a008585 property is found in the timer node.
> +
>  config ARM_GLOBAL_TIMER
>  	bool
>  	select CLKSRC_OF if OF
> diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
> index 4814446..b857027 100644
> --- a/drivers/clocksource/arm_arch_timer.c
> +++ b/drivers/clocksource/arm_arch_timer.c
> @@ -83,6 +83,51 @@ static bool arch_timer_mem_use_virtual;
>   * Architected system timer support.
>   */
>  
> +#ifdef CONFIG_FSL_ERRATUM_A008585
> +DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled);
> +EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled);
> +
> +/*
> + * __always_inline is used to ensure that func() is not an actual function
> + * pointer, which would result in the register accesses potentially being too
> + * far apart for the loop to work.
> + *
> + * The timeout is an arbitrary value well beyond the highest number
> + * of iterations the loop has been observed to take.
> + */
> +static __always_inline u64 fsl_a008585_reread_counter(u64 (*func)(void))
> +{
> +	u64 cval_old, cval_new;
> +	int timeout = 200;
> +
> +	do {
> +		isb();
> +		cval_old = func();
> +		cval_new = func();
> +		timeout--;
> +	} while (unlikely(cval_old != cval_new) && timeout);
> +
> +	WARN_ON_ONCE(!timeout);
> +	return cval_new;
> +}
> +
> +u64 arch_counter_get_cntvct_ool(void)
> +{
> +	return fsl_a008585_reread_counter(__arch_counter_get_cntvct);
> +}
> +
> +u64 arch_timer_get_vtval_ool(void)
> +{
> +	return fsl_a008585_reread_counter(__arch_timer_get_vtval);
> +}
> +
> +u64 arch_timer_get_ptval_ool(void)
> +{
> +	return fsl_a008585_reread_counter(__arch_timer_get_ptval);
> +}
> +
> +#endif /* CONFIG_FSL_ERRATUM_A008585 */
> +
>  static __always_inline
>  void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
>  			  struct clock_event_device *clk)
> @@ -232,6 +277,35 @@ static __always_inline void set_next_event(const int access, unsigned long evt,
>  	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
>  }
>  
> +#ifdef CONFIG_FSL_ERRATUM_A008585
> +static __always_inline void fsl_a008585_set_next_event(const int access,
> +		unsigned long evt, struct clock_event_device *clk)
> +{
> +	unsigned long ctrl;
> +	u64 cval = evt + arch_counter_get_cntvct();
> +
> +	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
> +	ctrl |= ARCH_TIMER_CTRL_ENABLE;
> +	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
> +	arch_timer_cval_write_cp15(access, cval);
> +	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
> +}
> +
> +static int fsl_a008585_set_next_event_virt(unsigned long evt,
> +					   struct clock_event_device *clk)
> +{
> +	fsl_a008585_set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
> +	return 0;
> +}
> +
> +static int fsl_a008585_set_next_event_phys(unsigned long evt,
> +					   struct clock_event_device *clk)
> +{
> +	fsl_a008585_set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
> +	return 0;
> +}
> +#endif /* CONFIG_FSL_ERRATUM_A008585 */
> +
>  static int arch_timer_set_next_event_virt(unsigned long evt,
>  					  struct clock_event_device *clk)
>  {
> @@ -260,6 +334,19 @@ static int arch_timer_set_next_event_phys_mem(unsigned long evt,
>  	return 0;
>  }
>  
> +static void fsl_a008585_set_sne(struct clock_event_device *clk)
> +{
> +#ifdef CONFIG_FSL_ERRATUM_A008585
> +	if (!static_branch_unlikely(&arch_timer_read_ool_enabled))
> +		return;
> +
> +	if (arch_timer_uses_ppi == VIRT_PPI)
> +		clk->set_next_event = fsl_a008585_set_next_event_virt;
> +	else
> +		clk->set_next_event = fsl_a008585_set_next_event_phys;
> +#endif
> +}
> +
>  static void __arch_timer_setup(unsigned type,
>  			       struct clock_event_device *clk)
>  {
> @@ -288,6 +375,8 @@ static void __arch_timer_setup(unsigned type,
>  		default:
>  			BUG();
>  		}
> +
> +		fsl_a008585_set_sne(clk);
>  	} else {
>  		clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
>  		clk->name = "arch_mem_timer";
> @@ -485,6 +574,15 @@ static void __init arch_counter_register(unsigned type)
>  			arch_timer_read_counter = arch_counter_get_cntvct;
>  		else
>  			arch_timer_read_counter = arch_counter_get_cntpct;
> +
> +#ifdef CONFIG_FSL_ERRATUM_A008585
> +		/*
> +		 * Don't use the vdso fastpath if errata require using
> +		 * the out-of-line counter accessor.
> +		 */
> +		if (static_branch_unlikely(&arch_timer_read_ool_enabled))
> +			clocksource_counter.name = "arch_sys_counter_ool";
> +#endif
>  	} else {
>  		arch_timer_read_counter = arch_counter_get_cntvct_mem;
>  
> @@ -766,6 +864,11 @@ static void __init arch_timer_of_init(struct device_node *np)
>  
>  	arch_timer_c3stop = !of_property_read_bool(np, "always-on");
>  
> +#ifdef CONFIG_FSL_ERRATUM_A008585
> +	if (of_property_read_bool(np, "fsl,erratum-a008585"))
> +		static_branch_enable(&arch_timer_read_ool_enabled);
> +#endif
> +
>  	/*
>  	 * If we cannot rely on firmware initializing the timer registers then
>  	 * we should use the physical timers instead.


I'm still worried that this series doesn't address Xen or KVM guests
that need to be made aware of the broken timers.

At the very least, I'd like a kernel command line option that'd let the
user reliably run its VMs. You can do something along the lines of
46fd5c6b, and have a command line argument like
"clocksource.arm_arch_timer.fsl-a008585=1", which would enable the
workaround.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny.

Re: [PATCH v4 1/4] arm64: arch_timer: Add device tree binding for A-008585 erratum

[Ding Tianhong]

Ping

On 2016/8/25 19:04, Matthias Brugger wrote:
> Hi all,
> 
> On 07/07/16 09:46, Scott Wood wrote:
>> This erratum describes a bug in logic outside the core, so MIDR can't be
>> used to identify its presence, and reading an SoC-specific revision
>> register from common arch timer code would be awkward.  So, describe it
>> in the device tree.
>>
>> Signed-off-by: Scott Wood <oss@buserror.net>
>> Acked-by: Rob Herring <robh@kernel.org>
>> ---
> 
> As of today I wasn't able to find this series in linux-next. Was this series somehow forgotten? Scott maybe you can resend the patches adding the clocksource maintainer.
> 
> Regards,
> Matthias
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 
> 

[PATCH v4 1/4] arm64: arch_timer: Add device tree binding for A-008585 erratum

[Ding Tianhong]

Ping

On 2016/8/25 19:04, Matthias Brugger wrote:
> Hi all,
> 
> On 07/07/16 09:46, Scott Wood wrote:
>> This erratum describes a bug in logic outside the core, so MIDR can't be
>> used to identify its presence, and reading an SoC-specific revision
>> register from common arch timer code would be awkward.  So, describe it
>> in the device tree.
>>
>> Signed-off-by: Scott Wood <oss@buserror.net>
>> Acked-by: Rob Herring <robh@kernel.org>
>> ---
> 
> As of today I wasn't able to find this series in linux-next. Was this series somehow forgotten? Scott maybe you can resend the patches adding the clocksource maintainer.
> 
> Regards,
> Matthias
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 
> 

Re: [PATCH v4 1/4] arm64: arch_timer: Add device tree binding for A-008585 erratum

[Marc Zyngier]

On 08/09/16 12:46, Ding Tianhong wrote:
> Ping

Oh please! Maybe you could look at the couple of points I've raised in
this thread and help addressing them, given that you have a vested
interest in seeing these patches being merged? Pinging people this way
is not very productive.

Thanks,

	M.

> 
> On 2016/8/25 19:04, Matthias Brugger wrote:
>> Hi all,
>>
>> On 07/07/16 09:46, Scott Wood wrote:
>>> This erratum describes a bug in logic outside the core, so MIDR can't be
>>> used to identify its presence, and reading an SoC-specific revision
>>> register from common arch timer code would be awkward.  So, describe it
>>> in the device tree.
>>>
>>> Signed-off-by: Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org>
>>> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>>> ---
>>
>> As of today I wasn't able to find this series in linux-next. Was this series somehow forgotten? Scott maybe you can resend the patches adding the clocksource maintainer.
>>
>> Regards,
>> Matthias
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
>>
> 
> 


-- 
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[PATCH v4 1/4] arm64: arch_timer: Add device tree binding for A-008585 erratum

[Marc Zyngier]

On 08/09/16 12:46, Ding Tianhong wrote:
> Ping

Oh please! Maybe you could look at the couple of points I've raised in
this thread and help addressing them, given that you have a vested
interest in seeing these patches being merged? Pinging people this way
is not very productive.

Thanks,

	M.

> 
> On 2016/8/25 19:04, Matthias Brugger wrote:
>> Hi all,
>>
>> On 07/07/16 09:46, Scott Wood wrote:
>>> This erratum describes a bug in logic outside the core, so MIDR can't be
>>> used to identify its presence, and reading an SoC-specific revision
>>> register from common arch timer code would be awkward.  So, describe it
>>> in the device tree.
>>>
>>> Signed-off-by: Scott Wood <oss@buserror.net>
>>> Acked-by: Rob Herring <robh@kernel.org>
>>> ---
>>
>> As of today I wasn't able to find this series in linux-next. Was this series somehow forgotten? Scott maybe you can resend the patches adding the clocksource maintainer.
>>
>> Regards,
>> Matthias
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
>>
> 
> 


-- 
Jazz is not dead. It just smells funny...

Re: [PATCH v4 1/4] arm64: arch_timer: Add device tree binding for A-008585 erratum

[Ding Tianhong]

On 2016/9/8 20:07, Marc Zyngier wrote:
> On 08/09/16 12:46, Ding Tianhong wrote:
>> Ping
> 
> Oh please! Maybe you could look at the couple of points I've raised in
> this thread and help addressing them, given that you have a vested
> interest in seeing these patches being merged? Pinging people this way
> is not very productive.
> 
> Thanks,
> 

Ok, I miss that patch, I will review your command and feedback, thanks.

Ding

> 	M.
> 
>>
>> On 2016/8/25 19:04, Matthias Brugger wrote:
>>> Hi all,
>>>
>>> On 07/07/16 09:46, Scott Wood wrote:
>>>> This erratum describes a bug in logic outside the core, so MIDR can't be
>>>> used to identify its presence, and reading an SoC-specific revision
>>>> register from common arch timer code would be awkward.  So, describe it
>>>> in the device tree.
>>>>
>>>> Signed-off-by: Scott Wood <oss@buserror.net>
>>>> Acked-by: Rob Herring <robh@kernel.org>
>>>> ---
>>>
>>> As of today I wasn't able to find this series in linux-next. Was this series somehow forgotten? Scott maybe you can resend the patches adding the clocksource maintainer.
>>>
>>> Regards,
>>> Matthias
>>>
>>> _______________________________________________
>>> linux-arm-kernel mailing list
>>> linux-arm-kernel@lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>>
>>>
>>
>>
> 
> 

[PATCH v4 1/4] arm64: arch_timer: Add device tree binding for A-008585 erratum

[Ding Tianhong]

On 2016/9/8 20:07, Marc Zyngier wrote:
> On 08/09/16 12:46, Ding Tianhong wrote:
>> Ping
> 
> Oh please! Maybe you could look at the couple of points I've raised in
> this thread and help addressing them, given that you have a vested
> interest in seeing these patches being merged? Pinging people this way
> is not very productive.
> 
> Thanks,
> 

Ok, I miss that patch, I will review your command and feedback, thanks.

Ding

> 	M.
> 
>>
>> On 2016/8/25 19:04, Matthias Brugger wrote:
>>> Hi all,
>>>
>>> On 07/07/16 09:46, Scott Wood wrote:
>>>> This erratum describes a bug in logic outside the core, so MIDR can't be
>>>> used to identify its presence, and reading an SoC-specific revision
>>>> register from common arch timer code would be awkward.  So, describe it
>>>> in the device tree.
>>>>
>>>> Signed-off-by: Scott Wood <oss@buserror.net>
>>>> Acked-by: Rob Herring <robh@kernel.org>
>>>> ---
>>>
>>> As of today I wasn't able to find this series in linux-next. Was this series somehow forgotten? Scott maybe you can resend the patches adding the clocksource maintainer.
>>>
>>> Regards,
>>> Matthias
>>>
>>> _______________________________________________
>>> linux-arm-kernel mailing list
>>> linux-arm-kernel at lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>>
>>>
>>
>>
> 
> 

Re: [PATCH v4 3/4] arm64: arch_timer: Work around QorIQ Erratum A-008585

[Scott Wood]

On Fri, 2016-08-26 at 13:40 +0100, Marc Zyngier wrote:
> On Thu, 7 Jul 2016 02:46:11 -0500
> Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org> wrote:
> 
> (+Mark)
> 
> > 
> >  static __always_inline
> >  u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
> >  {
> > @@ -66,19 +102,19 @@ u32 arch_timer_reg_read_cp15(int access, enum
> > arch_timer_reg reg)
> >  	if (access == ARCH_TIMER_PHYS_ACCESS) {
> >  		switch (reg) {
> >  		case ARCH_TIMER_REG_CTRL:
> > -			asm volatile("mrs %0,  cntp_ctl_el0" : "=r"
> > (val));
> > +			asm volatile("mrs %0, cntp_ctl_el0" : "=r"
> > (val));
> Spurious change?
> 
> > 
> >  			break;
> >  		case ARCH_TIMER_REG_TVAL:
> > -			asm volatile("mrs %0, cntp_tval_el0" : "=r"
> > (val));
> > +			val = _arch_timer_get_ptval();
> >  			break;
> >  		}
> >  	} else if (access == ARCH_TIMER_VIRT_ACCESS) {
> >  		switch (reg) {
> >  		case ARCH_TIMER_REG_CTRL:
> > -			asm volatile("mrs %0,  cntv_ctl_el0" : "=r"
> > (val));
> > +			asm volatile("mrs %0, cntv_ctl_el0" : "=r"
> > (val));
> Here too?

No, it's not spurious.

I answered this in http://lists.infradead.org/pipermail/linux-arm-kernel/2016-
June/438310.html

The extra spacing seemed to be an attempt to get things to line up between the
CTRL and TVAL asm statements.  When the TVAL case was converted to a function
call, there was nothing for the above to line up with, so I moved it back to
normal spacing.

> I'm still worried that this series doesn't address Xen or KVM guests
> that need to be made aware of the broken timers.
> 
> At the very least, I'd like a kernel command line option that'd let the
> user reliably run its VMs. You can do something along the lines of
> 46fd5c6b, and have a command line argument like
> "clocksource.arm_arch_timer.fsl-a008585=1", which would enable the
> workaround.

OK, I'll respin with a command line argument to use for now.  Mike Caraman has
said he plans to do a better solution for KVM -- Mike, have you had a chance
to look at this?

-Scott

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[PATCH v4 3/4] arm64: arch_timer: Work around QorIQ Erratum A-008585

[Scott Wood]

On Fri, 2016-08-26 at 13:40 +0100, Marc Zyngier wrote:
> On Thu, 7 Jul 2016 02:46:11 -0500
> Scott Wood <oss@buserror.net> wrote:
> 
> (+Mark)
> 
> > 
> > ?static __always_inline
> > ?u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
> > ?{
> > @@ -66,19 +102,19 @@ u32 arch_timer_reg_read_cp15(int access, enum
> > arch_timer_reg reg)
> > ?	if (access == ARCH_TIMER_PHYS_ACCESS) {
> > ?		switch (reg) {
> > ?		case ARCH_TIMER_REG_CTRL:
> > -			asm volatile("mrs %0,??cntp_ctl_el0" : "=r"
> > (val));
> > +			asm volatile("mrs %0, cntp_ctl_el0" : "=r"
> > (val));
> Spurious change?
> 
> > 
> > ?			break;
> > ?		case ARCH_TIMER_REG_TVAL:
> > -			asm volatile("mrs %0, cntp_tval_el0" : "=r"
> > (val));
> > +			val = _arch_timer_get_ptval();
> > ?			break;
> > ?		}
> > ?	} else if (access == ARCH_TIMER_VIRT_ACCESS) {
> > ?		switch (reg) {
> > ?		case ARCH_TIMER_REG_CTRL:
> > -			asm volatile("mrs %0,??cntv_ctl_el0" : "=r"
> > (val));
> > +			asm volatile("mrs %0, cntv_ctl_el0" : "=r"
> > (val));
> Here too?

No, it's not spurious.

I answered this in?http://lists.infradead.org/pipermail/linux-arm-kernel/2016-
June/438310.html

The extra spacing seemed to be an attempt to get things to line up between the
CTRL and TVAL asm statements.??When the TVAL case was converted to a function
call, there was nothing for the above to line up with, so I moved it back to
normal spacing.

> I'm still worried that this series doesn't address Xen or KVM guests
> that need to be made aware of the broken timers.
> 
> At the very least, I'd like a kernel command line option that'd let the
> user reliably run its VMs. You can do something along the lines of
> 46fd5c6b, and have a command line argument like
> "clocksource.arm_arch_timer.fsl-a008585=1", which would enable the
> workaround.

OK, I'll respin with a command line argument to use for now. ?Mike Caraman has
said he plans to do a better solution for KVM -- Mike, have you had a chance
to look at this?

-Scott

Re: [PATCH v4 3/4] arm64: arch_timer: Work around QorIQ Erratum A-008585

[Ding Tianhong]

On 2016/8/26 20:40, Marc Zyngier wrote:
> On Thu, 7 Jul 2016 02:46:11 -0500
> Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org> wrote:
> 
> (+Mark)
> 
>> Erratum A-008585 says that the ARM generic timer counter "has the
>> potential to contain an erroneous value for a small number of core
>> clock cycles every time the timer value changes".  Accesses to TVAL
>> (both read and write) are also affected due to the implicit counter
>> read.  Accesses to CVAL are not affected.
>>
>> The workaround is to reread TVAL and count registers until successive reads
>> return the same value, and when writing TVAL to retry until counter
>> reads before and after the write return the same value.
>>
>> This erratum can be found on LS1043A and LS2080A.
>>
>> Signed-off-by: Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org>
>> ---
>> v4:
>> - Undef ARCH_TIMER_REG_READ after use
>>
>> v3:
>> - Used cval rather than a loop for the write side of the erratum
>> - Added a Kconfig control
>> - Moved the device tree binding into its own patch
>> - Added erratum to silicon-errata.txt
>> - Changed function names to contain the erratum name
>> - Factored out the setting of erratum versions of set_next_event
>>   to improve readability
>> - Added a comment clarifying that the timeout is arbitrary
>>
>> v2:
>> Significant rework based on feedback, including using static_key,
>> disabling VDSO counter access rather than adding the workaround to the
>> VDSO, and uninlining the loops.
>>
>> Dropped the separate property for indicating that writes to TVAL are
>> affected, as I believe that's just a side effect of the implicit
>> counter read being corrupted, and thus a chip that is affected by one
>> will always be affected by the other.
>>
>> Dropped the arm32 portion as it seems there was confusion about whether
>> LS1021A is affected.  Currently I am being told that it is not
>> affected.
>>
>> I considered writing to CVAL rather than looping on TVAL writes, but
>> that would still have required separate set_next_event() code for the
>> erratum, and adding CVAL to the enum would have required a bunch of
>> extra handlers in switch statements (even where unused, due to compiler
>> warnings about unhandled enum values) including in an arm32 header.  It
>> seemed better to avoid the arm32 interaction and new untested
>> accessors.
>> ---
>>  Documentation/arm64/silicon-errata.txt |   2 +
>>  arch/arm64/include/asm/arch_timer.h    |  50 +++++++++++++---
>>  drivers/clocksource/Kconfig            |  10 ++++
>>  drivers/clocksource/arm_arch_timer.c   | 103 +++++++++++++++++++++++++++++++++
>>  4 files changed, 156 insertions(+), 9 deletions(-)
>>
>> diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
>> index 4da60b4..041e3a9 100644
>> --- a/Documentation/arm64/silicon-errata.txt
>> +++ b/Documentation/arm64/silicon-errata.txt
>> @@ -60,3 +60,5 @@ stable kernels.
>>  | Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154    |
>>  | Cavium         | ThunderX Core   | #27456          | CAVIUM_ERRATUM_27456    |
>>  | Cavium         | ThunderX SMMUv2 | #27704          | N/A		       |
>> +|                |                 |                 |                         |
>> +| Freescale/NXP  | LS2080A/LS1043A | A-008585        | FSL_ERRATUM_A008585     |
>> diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
>> index fbe0ca3..927dc6f 100644
>> --- a/arch/arm64/include/asm/arch_timer.h
>> +++ b/arch/arm64/include/asm/arch_timer.h
>> @@ -23,10 +23,36 @@
>>  
>>  #include <linux/bug.h>
>>  #include <linux/init.h>
>> +#include <linux/jump_label.h>
>>  #include <linux/types.h>
>>  
>>  #include <clocksource/arm_arch_timer.h>
>>  
>> +extern struct static_key_false arch_timer_read_ool_enabled;
>> +
>> +#define ARCH_TIMER_REG_READ(reg, func) \
>> +extern u64 func##_ool(void); \
>> +static inline u64 __##func(void) \
>> +{ \
>> +	u64 val; \
>> +	asm volatile("mrs %0, " reg : "=r" (val)); \
>> +	return val; \
>> +} \
>> +static inline u64 _##func(void) \
>> +{ \
>> +	if (IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) && \
>> +	    static_branch_unlikely(&arch_timer_read_ool_enabled)) \
>> +		return func##_ool(); \
>> +	else \
>> +		return __##func(); \
>> +}
>> +
>> +ARCH_TIMER_REG_READ("cntp_tval_el0", arch_timer_get_ptval)
>> +ARCH_TIMER_REG_READ("cntv_tval_el0", arch_timer_get_vtval)
>> +ARCH_TIMER_REG_READ("cntvct_el0", arch_counter_get_cntvct)
>> +
>> +#undef ARCH_TIMER_REG_READ
>> +
>>  /*
>>   * These register accessors are marked inline so the compiler can
>>   * nicely work out which register we want, and chuck away the rest of
>> @@ -58,6 +84,16 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
>>  	isb();
>>  }
>>  
>> +static __always_inline void arch_timer_cval_write_cp15(int access, u64 val)
>> +{
>> +	if (access == ARCH_TIMER_PHYS_ACCESS)
>> +		asm volatile("msr cntp_cval_el0, %0" : : "r" (val));
>> +	else if (access == ARCH_TIMER_VIRT_ACCESS)
>> +		asm volatile("msr cntv_cval_el0, %0" : : "r" (val));
>> +
>> +	isb();
>> +}
>> +
>>  static __always_inline
>>  u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
>>  {
>> @@ -66,19 +102,19 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
>>  	if (access == ARCH_TIMER_PHYS_ACCESS) {
>>  		switch (reg) {
>>  		case ARCH_TIMER_REG_CTRL:
>> -			asm volatile("mrs %0,  cntp_ctl_el0" : "=r" (val));
>> +			asm volatile("mrs %0, cntp_ctl_el0" : "=r" (val));
> 
> Spurious change?
> 
>>  			break;
>>  		case ARCH_TIMER_REG_TVAL:
>> -			asm volatile("mrs %0, cntp_tval_el0" : "=r" (val));
>> +			val = _arch_timer_get_ptval();
>>  			break;
>>  		}
>>  	} else if (access == ARCH_TIMER_VIRT_ACCESS) {
>>  		switch (reg) {
>>  		case ARCH_TIMER_REG_CTRL:
>> -			asm volatile("mrs %0,  cntv_ctl_el0" : "=r" (val));
>> +			asm volatile("mrs %0, cntv_ctl_el0" : "=r" (val));
> 
> Here too?
> 
>>  			break;
>>  		case ARCH_TIMER_REG_TVAL:
>> -			asm volatile("mrs %0, cntv_tval_el0" : "=r" (val));
>> +			val = _arch_timer_get_vtval();
>>  			break;
>>  		}
>>  	}
>> @@ -116,12 +152,8 @@ static inline u64 arch_counter_get_cntpct(void)
>>  
>>  static inline u64 arch_counter_get_cntvct(void)
>>  {
>> -	u64 cval;
>> -
>>  	isb();
>> -	asm volatile("mrs %0, cntvct_el0" : "=r" (cval));
>> -
>> -	return cval;
>> +	return _arch_counter_get_cntvct();
>>  }
>>  
>>  static inline int arch_timer_arch_init(void)
>> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
>> index 47352d2..48c6039 100644
>> --- a/drivers/clocksource/Kconfig
>> +++ b/drivers/clocksource/Kconfig
>> @@ -223,6 +223,16 @@ config ARM_ARCH_TIMER_EVTSTREAM
>>  	  This must be disabled for hardware validation purposes to detect any
>>  	  hardware anomalies of missing events.
>>  
>> +config FSL_ERRATUM_A008585
>> +	bool "Workaround for Freescale/NXP Erratum A-008585"
>> +	default y
>> +	depends on ARM_ARCH_TIMER && ARM64
>> +	help
>> +	  This option enables a workaround for Freescale/NXP Erratum
>> +	  A-008585 ("ARM generic timer may contain an erroneous
>> +	  value").  The workaround will only be active if the
>> +	  fsl,erratum-a008585 property is found in the timer node.
>> +
>>  config ARM_GLOBAL_TIMER
>>  	bool
>>  	select CLKSRC_OF if OF
>> diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
>> index 4814446..b857027 100644
>> --- a/drivers/clocksource/arm_arch_timer.c
>> +++ b/drivers/clocksource/arm_arch_timer.c
>> @@ -83,6 +83,51 @@ static bool arch_timer_mem_use_virtual;
>>   * Architected system timer support.
>>   */
>>  
>> +#ifdef CONFIG_FSL_ERRATUM_A008585
>> +DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled);
>> +EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled);
>> +
>> +/*
>> + * __always_inline is used to ensure that func() is not an actual function
>> + * pointer, which would result in the register accesses potentially being too
>> + * far apart for the loop to work.
>> + *
>> + * The timeout is an arbitrary value well beyond the highest number
>> + * of iterations the loop has been observed to take.
>> + */
>> +static __always_inline u64 fsl_a008585_reread_counter(u64 (*func)(void))
>> +{
>> +	u64 cval_old, cval_new;
>> +	int timeout = 200;
>> +
>> +	do {
>> +		isb();
>> +		cval_old = func();
>> +		cval_new = func();
>> +		timeout--;
>> +	} while (unlikely(cval_old != cval_new) && timeout);
>> +
>> +	WARN_ON_ONCE(!timeout);
>> +	return cval_new;
>> +}
>> +
>> +u64 arch_counter_get_cntvct_ool(void)
>> +{
>> +	return fsl_a008585_reread_counter(__arch_counter_get_cntvct);
>> +}
>> +
>> +u64 arch_timer_get_vtval_ool(void)
>> +{
>> +	return fsl_a008585_reread_counter(__arch_timer_get_vtval);
>> +}
>> +
>> +u64 arch_timer_get_ptval_ool(void)
>> +{
>> +	return fsl_a008585_reread_counter(__arch_timer_get_ptval);
>> +}
>> +
>> +#endif /* CONFIG_FSL_ERRATUM_A008585 */
>> +
>>  static __always_inline
>>  void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
>>  			  struct clock_event_device *clk)
>> @@ -232,6 +277,35 @@ static __always_inline void set_next_event(const int access, unsigned long evt,
>>  	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
>>  }
>>  
>> +#ifdef CONFIG_FSL_ERRATUM_A008585
>> +static __always_inline void fsl_a008585_set_next_event(const int access,
>> +		unsigned long evt, struct clock_event_device *clk)
>> +{
>> +	unsigned long ctrl;
>> +	u64 cval = evt + arch_counter_get_cntvct();
>> +
>> +	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
>> +	ctrl |= ARCH_TIMER_CTRL_ENABLE;
>> +	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
>> +	arch_timer_cval_write_cp15(access, cval);
>> +	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
>> +}
>> +
>> +static int fsl_a008585_set_next_event_virt(unsigned long evt,
>> +					   struct clock_event_device *clk)
>> +{
>> +	fsl_a008585_set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
>> +	return 0;
>> +}
>> +
>> +static int fsl_a008585_set_next_event_phys(unsigned long evt,
>> +					   struct clock_event_device *clk)
>> +{
>> +	fsl_a008585_set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
>> +	return 0;
>> +}
>> +#endif /* CONFIG_FSL_ERRATUM_A008585 */
>> +
>>  static int arch_timer_set_next_event_virt(unsigned long evt,
>>  					  struct clock_event_device *clk)
>>  {
>> @@ -260,6 +334,19 @@ static int arch_timer_set_next_event_phys_mem(unsigned long evt,
>>  	return 0;
>>  }
>>  
>> +static void fsl_a008585_set_sne(struct clock_event_device *clk)
>> +{
>> +#ifdef CONFIG_FSL_ERRATUM_A008585
>> +	if (!static_branch_unlikely(&arch_timer_read_ool_enabled))
>> +		return;
>> +
>> +	if (arch_timer_uses_ppi == VIRT_PPI)
>> +		clk->set_next_event = fsl_a008585_set_next_event_virt;
>> +	else
>> +		clk->set_next_event = fsl_a008585_set_next_event_phys;
>> +#endif
>> +}
>> +
>>  static void __arch_timer_setup(unsigned type,
>>  			       struct clock_event_device *clk)
>>  {
>> @@ -288,6 +375,8 @@ static void __arch_timer_setup(unsigned type,
>>  		default:
>>  			BUG();
>>  		}
>> +
>> +		fsl_a008585_set_sne(clk);
>>  	} else {
>>  		clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
>>  		clk->name = "arch_mem_timer";
>> @@ -485,6 +574,15 @@ static void __init arch_counter_register(unsigned type)
>>  			arch_timer_read_counter = arch_counter_get_cntvct;
>>  		else
>>  			arch_timer_read_counter = arch_counter_get_cntpct;
>> +
>> +#ifdef CONFIG_FSL_ERRATUM_A008585
>> +		/*
>> +		 * Don't use the vdso fastpath if errata require using
>> +		 * the out-of-line counter accessor.
>> +		 */
>> +		if (static_branch_unlikely(&arch_timer_read_ool_enabled))
>> +			clocksource_counter.name = "arch_sys_counter_ool";
>> +#endif
>>  	} else {
>>  		arch_timer_read_counter = arch_counter_get_cntvct_mem;
>>  
>> @@ -766,6 +864,11 @@ static void __init arch_timer_of_init(struct device_node *np)
>>  
>>  	arch_timer_c3stop = !of_property_read_bool(np, "always-on");
>>  
>> +#ifdef CONFIG_FSL_ERRATUM_A008585
>> +	if (of_property_read_bool(np, "fsl,erratum-a008585"))
>> +		static_branch_enable(&arch_timer_read_ool_enabled);
>> +#endif
>> +
>>  	/*
>>  	 * If we cannot rely on firmware initializing the timer registers then
>>  	 * we should use the physical timers instead.
> 
> 
> I'm still worried that this series doesn't address Xen or KVM guests
> that need to be made aware of the broken timers.
> 
Hi Marc:

I think "ARCH_TIMER_REG_READ("cntv_tval_el0", arch_timer_get_vtval)" could cover the tval changes in KVM guest, and
I fould the guest still use the get_cycles() to get the timer cycles, if I miss something, please remind me, thanks.


> At the very least, I'd like a kernel command line option that'd let the
> user reliably run its VMs. You can do something along the lines of
> 46fd5c6b, and have a command line argument like
> "clocksource.arm_arch_timer.fsl-a008585=1", which would enable the
> workaround.
> 

I don't think adding in command line is a good solution for this bug, we should not told the OS user how to fix it
by adding command line option, and need to fix it by dts or ACPI.

Thanks.
Ding

> Thanks,
> 
> 	M.
> 


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[PATCH v4 3/4] arm64: arch_timer: Work around QorIQ Erratum A-008585

[Ding Tianhong]

On 2016/8/26 20:40, Marc Zyngier wrote:
> On Thu, 7 Jul 2016 02:46:11 -0500
> Scott Wood <oss@buserror.net> wrote:
> 
> (+Mark)
> 
>> Erratum A-008585 says that the ARM generic timer counter "has the
>> potential to contain an erroneous value for a small number of core
>> clock cycles every time the timer value changes".  Accesses to TVAL
>> (both read and write) are also affected due to the implicit counter
>> read.  Accesses to CVAL are not affected.
>>
>> The workaround is to reread TVAL and count registers until successive reads
>> return the same value, and when writing TVAL to retry until counter
>> reads before and after the write return the same value.
>>
>> This erratum can be found on LS1043A and LS2080A.
>>
>> Signed-off-by: Scott Wood <oss@buserror.net>
>> ---
>> v4:
>> - Undef ARCH_TIMER_REG_READ after use
>>
>> v3:
>> - Used cval rather than a loop for the write side of the erratum
>> - Added a Kconfig control
>> - Moved the device tree binding into its own patch
>> - Added erratum to silicon-errata.txt
>> - Changed function names to contain the erratum name
>> - Factored out the setting of erratum versions of set_next_event
>>   to improve readability
>> - Added a comment clarifying that the timeout is arbitrary
>>
>> v2:
>> Significant rework based on feedback, including using static_key,
>> disabling VDSO counter access rather than adding the workaround to the
>> VDSO, and uninlining the loops.
>>
>> Dropped the separate property for indicating that writes to TVAL are
>> affected, as I believe that's just a side effect of the implicit
>> counter read being corrupted, and thus a chip that is affected by one
>> will always be affected by the other.
>>
>> Dropped the arm32 portion as it seems there was confusion about whether
>> LS1021A is affected.  Currently I am being told that it is not
>> affected.
>>
>> I considered writing to CVAL rather than looping on TVAL writes, but
>> that would still have required separate set_next_event() code for the
>> erratum, and adding CVAL to the enum would have required a bunch of
>> extra handlers in switch statements (even where unused, due to compiler
>> warnings about unhandled enum values) including in an arm32 header.  It
>> seemed better to avoid the arm32 interaction and new untested
>> accessors.
>> ---
>>  Documentation/arm64/silicon-errata.txt |   2 +
>>  arch/arm64/include/asm/arch_timer.h    |  50 +++++++++++++---
>>  drivers/clocksource/Kconfig            |  10 ++++
>>  drivers/clocksource/arm_arch_timer.c   | 103 +++++++++++++++++++++++++++++++++
>>  4 files changed, 156 insertions(+), 9 deletions(-)
>>
>> diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
>> index 4da60b4..041e3a9 100644
>> --- a/Documentation/arm64/silicon-errata.txt
>> +++ b/Documentation/arm64/silicon-errata.txt
>> @@ -60,3 +60,5 @@ stable kernels.
>>  | Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154    |
>>  | Cavium         | ThunderX Core   | #27456          | CAVIUM_ERRATUM_27456    |
>>  | Cavium         | ThunderX SMMUv2 | #27704          | N/A		       |
>> +|                |                 |                 |                         |
>> +| Freescale/NXP  | LS2080A/LS1043A | A-008585        | FSL_ERRATUM_A008585     |
>> diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
>> index fbe0ca3..927dc6f 100644
>> --- a/arch/arm64/include/asm/arch_timer.h
>> +++ b/arch/arm64/include/asm/arch_timer.h
>> @@ -23,10 +23,36 @@
>>  
>>  #include <linux/bug.h>
>>  #include <linux/init.h>
>> +#include <linux/jump_label.h>
>>  #include <linux/types.h>
>>  
>>  #include <clocksource/arm_arch_timer.h>
>>  
>> +extern struct static_key_false arch_timer_read_ool_enabled;
>> +
>> +#define ARCH_TIMER_REG_READ(reg, func) \
>> +extern u64 func##_ool(void); \
>> +static inline u64 __##func(void) \
>> +{ \
>> +	u64 val; \
>> +	asm volatile("mrs %0, " reg : "=r" (val)); \
>> +	return val; \
>> +} \
>> +static inline u64 _##func(void) \
>> +{ \
>> +	if (IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) && \
>> +	    static_branch_unlikely(&arch_timer_read_ool_enabled)) \
>> +		return func##_ool(); \
>> +	else \
>> +		return __##func(); \
>> +}
>> +
>> +ARCH_TIMER_REG_READ("cntp_tval_el0", arch_timer_get_ptval)
>> +ARCH_TIMER_REG_READ("cntv_tval_el0", arch_timer_get_vtval)
>> +ARCH_TIMER_REG_READ("cntvct_el0", arch_counter_get_cntvct)
>> +
>> +#undef ARCH_TIMER_REG_READ
>> +
>>  /*
>>   * These register accessors are marked inline so the compiler can
>>   * nicely work out which register we want, and chuck away the rest of
>> @@ -58,6 +84,16 @@ void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
>>  	isb();
>>  }
>>  
>> +static __always_inline void arch_timer_cval_write_cp15(int access, u64 val)
>> +{
>> +	if (access == ARCH_TIMER_PHYS_ACCESS)
>> +		asm volatile("msr cntp_cval_el0, %0" : : "r" (val));
>> +	else if (access == ARCH_TIMER_VIRT_ACCESS)
>> +		asm volatile("msr cntv_cval_el0, %0" : : "r" (val));
>> +
>> +	isb();
>> +}
>> +
>>  static __always_inline
>>  u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
>>  {
>> @@ -66,19 +102,19 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
>>  	if (access == ARCH_TIMER_PHYS_ACCESS) {
>>  		switch (reg) {
>>  		case ARCH_TIMER_REG_CTRL:
>> -			asm volatile("mrs %0,  cntp_ctl_el0" : "=r" (val));
>> +			asm volatile("mrs %0, cntp_ctl_el0" : "=r" (val));
> 
> Spurious change?
> 
>>  			break;
>>  		case ARCH_TIMER_REG_TVAL:
>> -			asm volatile("mrs %0, cntp_tval_el0" : "=r" (val));
>> +			val = _arch_timer_get_ptval();
>>  			break;
>>  		}
>>  	} else if (access == ARCH_TIMER_VIRT_ACCESS) {
>>  		switch (reg) {
>>  		case ARCH_TIMER_REG_CTRL:
>> -			asm volatile("mrs %0,  cntv_ctl_el0" : "=r" (val));
>> +			asm volatile("mrs %0, cntv_ctl_el0" : "=r" (val));
> 
> Here too?
> 
>>  			break;
>>  		case ARCH_TIMER_REG_TVAL:
>> -			asm volatile("mrs %0, cntv_tval_el0" : "=r" (val));
>> +			val = _arch_timer_get_vtval();
>>  			break;
>>  		}
>>  	}
>> @@ -116,12 +152,8 @@ static inline u64 arch_counter_get_cntpct(void)
>>  
>>  static inline u64 arch_counter_get_cntvct(void)
>>  {
>> -	u64 cval;
>> -
>>  	isb();
>> -	asm volatile("mrs %0, cntvct_el0" : "=r" (cval));
>> -
>> -	return cval;
>> +	return _arch_counter_get_cntvct();
>>  }
>>  
>>  static inline int arch_timer_arch_init(void)
>> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
>> index 47352d2..48c6039 100644
>> --- a/drivers/clocksource/Kconfig
>> +++ b/drivers/clocksource/Kconfig
>> @@ -223,6 +223,16 @@ config ARM_ARCH_TIMER_EVTSTREAM
>>  	  This must be disabled for hardware validation purposes to detect any
>>  	  hardware anomalies of missing events.
>>  
>> +config FSL_ERRATUM_A008585
>> +	bool "Workaround for Freescale/NXP Erratum A-008585"
>> +	default y
>> +	depends on ARM_ARCH_TIMER && ARM64
>> +	help
>> +	  This option enables a workaround for Freescale/NXP Erratum
>> +	  A-008585 ("ARM generic timer may contain an erroneous
>> +	  value").  The workaround will only be active if the
>> +	  fsl,erratum-a008585 property is found in the timer node.
>> +
>>  config ARM_GLOBAL_TIMER
>>  	bool
>>  	select CLKSRC_OF if OF
>> diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
>> index 4814446..b857027 100644
>> --- a/drivers/clocksource/arm_arch_timer.c
>> +++ b/drivers/clocksource/arm_arch_timer.c
>> @@ -83,6 +83,51 @@ static bool arch_timer_mem_use_virtual;
>>   * Architected system timer support.
>>   */
>>  
>> +#ifdef CONFIG_FSL_ERRATUM_A008585
>> +DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled);
>> +EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled);
>> +
>> +/*
>> + * __always_inline is used to ensure that func() is not an actual function
>> + * pointer, which would result in the register accesses potentially being too
>> + * far apart for the loop to work.
>> + *
>> + * The timeout is an arbitrary value well beyond the highest number
>> + * of iterations the loop has been observed to take.
>> + */
>> +static __always_inline u64 fsl_a008585_reread_counter(u64 (*func)(void))
>> +{
>> +	u64 cval_old, cval_new;
>> +	int timeout = 200;
>> +
>> +	do {
>> +		isb();
>> +		cval_old = func();
>> +		cval_new = func();
>> +		timeout--;
>> +	} while (unlikely(cval_old != cval_new) && timeout);
>> +
>> +	WARN_ON_ONCE(!timeout);
>> +	return cval_new;
>> +}
>> +
>> +u64 arch_counter_get_cntvct_ool(void)
>> +{
>> +	return fsl_a008585_reread_counter(__arch_counter_get_cntvct);
>> +}
>> +
>> +u64 arch_timer_get_vtval_ool(void)
>> +{
>> +	return fsl_a008585_reread_counter(__arch_timer_get_vtval);
>> +}
>> +
>> +u64 arch_timer_get_ptval_ool(void)
>> +{
>> +	return fsl_a008585_reread_counter(__arch_timer_get_ptval);
>> +}
>> +
>> +#endif /* CONFIG_FSL_ERRATUM_A008585 */
>> +
>>  static __always_inline
>>  void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
>>  			  struct clock_event_device *clk)
>> @@ -232,6 +277,35 @@ static __always_inline void set_next_event(const int access, unsigned long evt,
>>  	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
>>  }
>>  
>> +#ifdef CONFIG_FSL_ERRATUM_A008585
>> +static __always_inline void fsl_a008585_set_next_event(const int access,
>> +		unsigned long evt, struct clock_event_device *clk)
>> +{
>> +	unsigned long ctrl;
>> +	u64 cval = evt + arch_counter_get_cntvct();
>> +
>> +	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
>> +	ctrl |= ARCH_TIMER_CTRL_ENABLE;
>> +	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
>> +	arch_timer_cval_write_cp15(access, cval);
>> +	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
>> +}
>> +
>> +static int fsl_a008585_set_next_event_virt(unsigned long evt,
>> +					   struct clock_event_device *clk)
>> +{
>> +	fsl_a008585_set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
>> +	return 0;
>> +}
>> +
>> +static int fsl_a008585_set_next_event_phys(unsigned long evt,
>> +					   struct clock_event_device *clk)
>> +{
>> +	fsl_a008585_set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
>> +	return 0;
>> +}
>> +#endif /* CONFIG_FSL_ERRATUM_A008585 */
>> +
>>  static int arch_timer_set_next_event_virt(unsigned long evt,
>>  					  struct clock_event_device *clk)
>>  {
>> @@ -260,6 +334,19 @@ static int arch_timer_set_next_event_phys_mem(unsigned long evt,
>>  	return 0;
>>  }
>>  
>> +static void fsl_a008585_set_sne(struct clock_event_device *clk)
>> +{
>> +#ifdef CONFIG_FSL_ERRATUM_A008585
>> +	if (!static_branch_unlikely(&arch_timer_read_ool_enabled))
>> +		return;
>> +
>> +	if (arch_timer_uses_ppi == VIRT_PPI)
>> +		clk->set_next_event = fsl_a008585_set_next_event_virt;
>> +	else
>> +		clk->set_next_event = fsl_a008585_set_next_event_phys;
>> +#endif
>> +}
>> +
>>  static void __arch_timer_setup(unsigned type,
>>  			       struct clock_event_device *clk)
>>  {
>> @@ -288,6 +375,8 @@ static void __arch_timer_setup(unsigned type,
>>  		default:
>>  			BUG();
>>  		}
>> +
>> +		fsl_a008585_set_sne(clk);
>>  	} else {
>>  		clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
>>  		clk->name = "arch_mem_timer";
>> @@ -485,6 +574,15 @@ static void __init arch_counter_register(unsigned type)
>>  			arch_timer_read_counter = arch_counter_get_cntvct;
>>  		else
>>  			arch_timer_read_counter = arch_counter_get_cntpct;
>> +
>> +#ifdef CONFIG_FSL_ERRATUM_A008585
>> +		/*
>> +		 * Don't use the vdso fastpath if errata require using
>> +		 * the out-of-line counter accessor.
>> +		 */
>> +		if (static_branch_unlikely(&arch_timer_read_ool_enabled))
>> +			clocksource_counter.name = "arch_sys_counter_ool";
>> +#endif
>>  	} else {
>>  		arch_timer_read_counter = arch_counter_get_cntvct_mem;
>>  
>> @@ -766,6 +864,11 @@ static void __init arch_timer_of_init(struct device_node *np)
>>  
>>  	arch_timer_c3stop = !of_property_read_bool(np, "always-on");
>>  
>> +#ifdef CONFIG_FSL_ERRATUM_A008585
>> +	if (of_property_read_bool(np, "fsl,erratum-a008585"))
>> +		static_branch_enable(&arch_timer_read_ool_enabled);
>> +#endif
>> +
>>  	/*
>>  	 * If we cannot rely on firmware initializing the timer registers then
>>  	 * we should use the physical timers instead.
> 
> 
> I'm still worried that this series doesn't address Xen or KVM guests
> that need to be made aware of the broken timers.
> 
Hi Marc:

I think "ARCH_TIMER_REG_READ("cntv_tval_el0", arch_timer_get_vtval)" could cover the tval changes in KVM guest, and
I fould the guest still use the get_cycles() to get the timer cycles, if I miss something, please remind me, thanks.


> At the very least, I'd like a kernel command line option that'd let the
> user reliably run its VMs. You can do something along the lines of
> 46fd5c6b, and have a command line argument like
> "clocksource.arm_arch_timer.fsl-a008585=1", which would enable the
> workaround.
> 

I don't think adding in command line is a good solution for this bug, we should not told the OS user how to fix it
by adding command line option, and need to fix it by dts or ACPI.

Thanks.
Ding

> Thanks,
> 
> 	M.
> 

Re: [PATCH v4 3/4] arm64: arch_timer: Work around QorIQ Erratum A-008585

[Marc Zyngier]

On Thu, 8 Sep 2016 20:08:56 -0500
Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org> wrote:

> On Fri, 2016-08-26 at 13:40 +0100, Marc Zyngier wrote:
> > On Thu, 7 Jul 2016 02:46:11 -0500
> > Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org> wrote:
> > 
> > (+Mark)
> >   
> > > 
> > >  static __always_inline
> > >  u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
> > >  {
> > > @@ -66,19 +102,19 @@ u32 arch_timer_reg_read_cp15(int access, enum
> > > arch_timer_reg reg)
> > >  	if (access == ARCH_TIMER_PHYS_ACCESS) {
> > >  		switch (reg) {
> > >  		case ARCH_TIMER_REG_CTRL:
> > > -			asm volatile("mrs %0,  cntp_ctl_el0" : "=r"
> > > (val));
> > > +			asm volatile("mrs %0, cntp_ctl_el0" : "=r"
> > > (val));  
> > Spurious change?
> >   
> > > 
> > >  			break;
> > >  		case ARCH_TIMER_REG_TVAL:
> > > -			asm volatile("mrs %0, cntp_tval_el0" : "=r"
> > > (val));
> > > +			val = _arch_timer_get_ptval();
> > >  			break;
> > >  		}
> > >  	} else if (access == ARCH_TIMER_VIRT_ACCESS) {
> > >  		switch (reg) {
> > >  		case ARCH_TIMER_REG_CTRL:
> > > -			asm volatile("mrs %0,  cntv_ctl_el0" : "=r"
> > > (val));
> > > +			asm volatile("mrs %0, cntv_ctl_el0" : "=r"
> > > (val));  
> > Here too?  
> 
> No, it's not spurious.
> 
> I answered this in http://lists.infradead.org/pipermail/linux-arm-kernel/2016-
> June/438310.html
> 
> The extra spacing seemed to be an attempt to get things to line up between the
> CTRL and TVAL asm statements.  When the TVAL case was converted to a function
> call, there was nothing for the above to line up with, so I moved it back to
> normal spacing.
> 
> > I'm still worried that this series doesn't address Xen or KVM guests
> > that need to be made aware of the broken timers.
> > 
> > At the very least, I'd like a kernel command line option that'd let the
> > user reliably run its VMs. You can do something along the lines of
> > 46fd5c6b, and have a command line argument like
> > "clocksource.arm_arch_timer.fsl-a008585=1", which would enable the
> > workaround.  
> 
> OK, I'll respin with a command line argument to use for now.  Mike Caraman has
> said he plans to do a better solution for KVM -- Mike, have you had a chance
> to look at this?

If there is a plan, we'd all like to hear about it, specially if this
involves a userspace ABI (which is likely).

Thanks,

	M.
-- 
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[PATCH v4 3/4] arm64: arch_timer: Work around QorIQ Erratum A-008585

[Marc Zyngier]

On Thu, 8 Sep 2016 20:08:56 -0500
Scott Wood <oss@buserror.net> wrote:

> On Fri, 2016-08-26 at 13:40 +0100, Marc Zyngier wrote:
> > On Thu, 7 Jul 2016 02:46:11 -0500
> > Scott Wood <oss@buserror.net> wrote:
> > 
> > (+Mark)
> >   
> > > 
> > > ?static __always_inline
> > > ?u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
> > > ?{
> > > @@ -66,19 +102,19 @@ u32 arch_timer_reg_read_cp15(int access, enum
> > > arch_timer_reg reg)
> > > ?	if (access == ARCH_TIMER_PHYS_ACCESS) {
> > > ?		switch (reg) {
> > > ?		case ARCH_TIMER_REG_CTRL:
> > > -			asm volatile("mrs %0,??cntp_ctl_el0" : "=r"
> > > (val));
> > > +			asm volatile("mrs %0, cntp_ctl_el0" : "=r"
> > > (val));  
> > Spurious change?
> >   
> > > 
> > > ?			break;
> > > ?		case ARCH_TIMER_REG_TVAL:
> > > -			asm volatile("mrs %0, cntp_tval_el0" : "=r"
> > > (val));
> > > +			val = _arch_timer_get_ptval();
> > > ?			break;
> > > ?		}
> > > ?	} else if (access == ARCH_TIMER_VIRT_ACCESS) {
> > > ?		switch (reg) {
> > > ?		case ARCH_TIMER_REG_CTRL:
> > > -			asm volatile("mrs %0,??cntv_ctl_el0" : "=r"
> > > (val));
> > > +			asm volatile("mrs %0, cntv_ctl_el0" : "=r"
> > > (val));  
> > Here too?  
> 
> No, it's not spurious.
> 
> I answered this in?http://lists.infradead.org/pipermail/linux-arm-kernel/2016-
> June/438310.html
> 
> The extra spacing seemed to be an attempt to get things to line up between the
> CTRL and TVAL asm statements.??When the TVAL case was converted to a function
> call, there was nothing for the above to line up with, so I moved it back to
> normal spacing.
> 
> > I'm still worried that this series doesn't address Xen or KVM guests
> > that need to be made aware of the broken timers.
> > 
> > At the very least, I'd like a kernel command line option that'd let the
> > user reliably run its VMs. You can do something along the lines of
> > 46fd5c6b, and have a command line argument like
> > "clocksource.arm_arch_timer.fsl-a008585=1", which would enable the
> > workaround.  
> 
> OK, I'll respin with a command line argument to use for now. ?Mike Caraman has
> said he plans to do a better solution for KVM -- Mike, have you had a chance
> to look at this?

If there is a plan, we'd all like to hear about it, specially if this
involves a userspace ABI (which is likely).

Thanks,

	M.
-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH v4 3/4] arm64: arch_timer: Work around QorIQ Erratum A-008585

[Marc Zyngier]

On Fri, 9 Sep 2016 13:20:46 +0800
Ding Tianhong <dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> wrote:

Hi Ding,

> > I'm still worried that this series doesn't address Xen or KVM guests
> > that need to be made aware of the broken timers.
> >   
> Hi Marc:
> 
> I think "ARCH_TIMER_REG_READ("cntv_tval_el0", arch_timer_get_vtval)"
> could cover the tval changes in KVM guest, and I fould the guest
> still use the get_cycles() to get the timer cycles, if I miss
> something, please remind me, thanks.

You're missing the point that to tell the guest that the HW has this
erratum, we need the DT to be populated with the right property.

> > At the very least, I'd like a kernel command line option that'd let
> > the user reliably run its VMs. You can do something along the lines
> > of 46fd5c6b, and have a command line argument like
> > "clocksource.arm_arch_timer.fsl-a008585=1", which would enable the
> > workaround.
> >   
> 
> I don't think adding in command line is a good solution for this bug,
> we should not told the OS user how to fix it by adding command line
> option, and need to fix it by dts or ACPI.

Sure. I'm happy to review the patches that will:
- Add a new KVM kernel API describing properties for the timer so that
  we can expose the erratum from the kernel to userspace
- Add a similar API for Xen
- Have all the userspace (QEMU, kvmtool, the Xen tools) to be converted
  to use this new API so that they can emit the correct DT
- Point to a change in the ACPI spec so that we can encode errata there
- Add support for handling this erratum using ACPI in the kernel
- Allow QEMU and the Xen tools to expose this erratum in the guests
  ACPI tables

Unless you're in a position to write all this code (and
specifications), and post the patches *now*, I'll stand by my
recommendation to have a command-line option. Not exposing this issue
to the guest results in unreliable operations. You may not care, but I
do.

Thanks,

	M.
-- 
Without deviation from the norm, progress is not possible.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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[PATCH v4 3/4] arm64: arch_timer: Work around QorIQ Erratum A-008585

[Marc Zyngier]

On Fri, 9 Sep 2016 13:20:46 +0800
Ding Tianhong <dingtianhong@huawei.com> wrote:

Hi Ding,

> > I'm still worried that this series doesn't address Xen or KVM guests
> > that need to be made aware of the broken timers.
> >   
> Hi Marc:
> 
> I think "ARCH_TIMER_REG_READ("cntv_tval_el0", arch_timer_get_vtval)"
> could cover the tval changes in KVM guest, and I fould the guest
> still use the get_cycles() to get the timer cycles, if I miss
> something, please remind me, thanks.

You're missing the point that to tell the guest that the HW has this
erratum, we need the DT to be populated with the right property.

> > At the very least, I'd like a kernel command line option that'd let
> > the user reliably run its VMs. You can do something along the lines
> > of 46fd5c6b, and have a command line argument like
> > "clocksource.arm_arch_timer.fsl-a008585=1", which would enable the
> > workaround.
> >   
> 
> I don't think adding in command line is a good solution for this bug,
> we should not told the OS user how to fix it by adding command line
> option, and need to fix it by dts or ACPI.

Sure. I'm happy to review the patches that will:
- Add a new KVM kernel API describing properties for the timer so that
  we can expose the erratum from the kernel to userspace
- Add a similar API for Xen
- Have all the userspace (QEMU, kvmtool, the Xen tools) to be converted
  to use this new API so that they can emit the correct DT
- Point to a change in the ACPI spec so that we can encode errata there
- Add support for handling this erratum using ACPI in the kernel
- Allow QEMU and the Xen tools to expose this erratum in the guests
  ACPI tables

Unless you're in a position to write all this code (and
specifications), and post the patches *now*, I'll stand by my
recommendation to have a command-line option. Not exposing this issue
to the guest results in unreliable operations. You may not care, but I
do.

Thanks,

	M.
-- 
Without deviation from the norm, progress is not possible.