[PATCH 01/10] dt-bindings: Add compatible property for LS1012A

[PATCH 01/10] dt-bindings: Add compatible property for LS1012A

[Bhaskar Upadhaya]

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
 Documentation/devicetree/bindings/arm/fsl.txt | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index dbbc095..51b6b03 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -119,7 +119,7 @@ Freescale DCFG
 configuration and status for the device. Such as setting the secondary
 core start address and release the secondary core from holdoff and startup.
   Required properties:
-  - compatible: should be "fsl,ls1021a-dcfg"
+  - compatible: can be "fsl,ls1021a-dcfg", "fsl,ls1012a-dcfg", "fsl,ls1043a-dcfg"
   - reg : should contain base address and length of DCFG memory-mapped registers
 
 Example:
@@ -151,3 +151,14 @@ LS2080A ARMv8 based RDB Board
 Required root node properties:
     - compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
 
+LS1012A ARMv8 based FRDM Board
+Required root node properties:
+    - compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
+
+LS1012A ARMv8 based RDB Board
+Required root node properties:
+    - compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
+
+LS1012A ARMv8 based QDS Board
+Required root node properties:
+    - compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
-- 
1.9.1

[PATCH 01/10] dt-bindings: Add compatible property for LS1012A

[Bhaskar Upadhaya]

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
 Documentation/devicetree/bindings/arm/fsl.txt | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index dbbc095..51b6b03 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -119,7 +119,7 @@ Freescale DCFG
 configuration and status for the device. Such as setting the secondary
 core start address and release the secondary core from holdoff and startup.
   Required properties:
-  - compatible: should be "fsl,ls1021a-dcfg"
+  - compatible: can be "fsl,ls1021a-dcfg", "fsl,ls1012a-dcfg", "fsl,ls1043a-dcfg"
   - reg : should contain base address and length of DCFG memory-mapped registers
 
 Example:
@@ -151,3 +151,14 @@ LS2080A ARMv8 based RDB Board
 Required root node properties:
     - compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
 
+LS1012A ARMv8 based FRDM Board
+Required root node properties:
+    - compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
+
+LS1012A ARMv8 based RDB Board
+Required root node properties:
+    - compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
+
+LS1012A ARMv8 based QDS Board
+Required root node properties:
+    - compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
-- 
1.9.1

[PATCH 02/10] dt-bindings: esdhc: Update bindings for LS1012A

[Bhaskar Upadhaya]

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
 Documentation/devicetree/bindings/mmc/fsl-esdhc.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
index dedfb02..3257b4a 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
+++ b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
@@ -7,9 +7,9 @@ This file documents differences between the core properties described
 by mmc.txt and the properties used by the sdhci-esdhc driver.
 
 Required properties:
+  - compatible : "fsl,mpc8378-esdhc", "fsl,ls1012a-esdhc0", "fsl,ls1012a-esdhc1".
   - interrupt-parent : interrupt source phandle.
   - clock-frequency : specifies eSDHC base clock frequency.
-
 Optional properties:
   - sdhci,wp-inverted : specifies that eSDHC controller reports
     inverted write-protect state; New devices should use the generic
-- 
1.9.1

[PATCH 02/10] dt-bindings: esdhc: Update bindings for LS1012A

[Bhaskar Upadhaya]

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
 Documentation/devicetree/bindings/mmc/fsl-esdhc.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
index dedfb02..3257b4a 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
+++ b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
@@ -7,9 +7,9 @@ This file documents differences between the core properties described
 by mmc.txt and the properties used by the sdhci-esdhc driver.
 
 Required properties:
+  - compatible : "fsl,mpc8378-esdhc", "fsl,ls1012a-esdhc0", "fsl,ls1012a-esdhc1".
   - interrupt-parent : interrupt source phandle.
   - clock-frequency : specifies eSDHC base clock frequency.
-
 Optional properties:
   - sdhci,wp-inverted : specifies that eSDHC controller reports
     inverted write-protect state; New devices should use the generic
-- 
1.9.1

[PATCH 03/10] dt-bindings: quadspi: Update bindings for LS1012A

[Bhaskar Upadhaya]

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
index c34aa6f..071e87e 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
@@ -3,7 +3,7 @@
 Required properties:
   - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi",
 		 "fsl,imx7d-qspi", "fsl,imx6ul-qspi",
-		 "fsl,ls1021a-qspi"
+		 "fsl,ls1012a-qspi, "fsl,ls1021a-qspi"
 		 or
 		 "fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi",
 		 "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
-- 
1.9.1

[PATCH 03/10] dt-bindings: quadspi: Update bindings for LS1012A

[Bhaskar Upadhaya]

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
index c34aa6f..071e87e 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
@@ -3,7 +3,7 @@
 Required properties:
   - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi",
 		 "fsl,imx7d-qspi", "fsl,imx6ul-qspi",
-		 "fsl,ls1021a-qspi"
+		 "fsl,ls1012a-qspi, "fsl,ls1021a-qspi"
 		 or
 		 "fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi",
 		 "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
-- 
1.9.1

[PATCH 04/10] dt-bindings: spi-nor: Update bindings for LS1012A

[Bhaskar Upadhaya]

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
 Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
index 2c91c03..fc99ef2 100644
--- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
+++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
@@ -13,6 +13,7 @@ Required properties:
                  at25df321a
                  at25df641
                  at26df081a
+		 eon,en25s64
                  mr25h256
                  mx25l4005a
                  mx25l1606e
@@ -29,6 +30,7 @@ Required properties:
                  s25fl008k
                  s25fl064k
                  sst25vf040b
+		 sst,sst25wf040b
                  m25p40
                  m25p80
                  m25p16
-- 
1.9.1

[PATCH 04/10] dt-bindings: spi-nor: Update bindings for LS1012A

[Bhaskar Upadhaya]

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
 Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
index 2c91c03..fc99ef2 100644
--- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
+++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
@@ -13,6 +13,7 @@ Required properties:
                  at25df321a
                  at25df641
                  at26df081a
+		 eon,en25s64
                  mr25h256
                  mx25l4005a
                  mx25l1606e
@@ -29,6 +30,7 @@ Required properties:
                  s25fl008k
                  s25fl064k
                  sst25vf040b
+		 sst,sst25wf040b
                  m25p40
                  m25p80
                  m25p16
-- 
1.9.1

[PATCH 05/10] dt-bindings: pci: Update bindings for LS1012A

[Bhaskar Upadhaya]

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
 Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 41e9f55..5755697 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -15,6 +15,7 @@ Required properties:
 - compatible: should contain the platform identifier such as:
         "fsl,ls1021a-pcie", "snps,dw-pcie"
         "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie"
+	"fsl,ls1012a-pcie", "fsl,ls1043a-pcie" ,"snps,dw-pcie"
 - reg: base addresses and lengths of the PCIe controller
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.
-- 
1.9.1

[PATCH 05/10] dt-bindings: pci: Update bindings for LS1012A

[Bhaskar Upadhaya]

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
 Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 41e9f55..5755697 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -15,6 +15,7 @@ Required properties:
 - compatible: should contain the platform identifier such as:
         "fsl,ls1021a-pcie", "snps,dw-pcie"
         "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie"
+	"fsl,ls1012a-pcie", "fsl,ls1043a-pcie" ,"snps,dw-pcie"
 - reg: base addresses and lengths of the PCIe controller
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.
-- 
1.9.1

[PATCH 06/10] dt-bindings: dspi: Update bindings for LS1012A

[Bhaskar Upadhaya]

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
 Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
index ff5893d..dad6409 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
@@ -2,6 +2,7 @@ ARM Freescale DSPI controller
 
 Required properties:
 - compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi",
+		"fsl,ls1012a-dspi", "fsl,ls1043a-dspi",
 		"fsl,ls2085a-dspi"
 		or
 		"fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
-- 
1.9.1

[PATCH 06/10] dt-bindings: dspi: Update bindings for LS1012A

[Bhaskar Upadhaya]

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
 Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
index ff5893d..dad6409 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
@@ -2,6 +2,7 @@ ARM Freescale DSPI controller
 
 Required properties:
 - compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi",
+		"fsl,ls1012a-dspi", "fsl,ls1043a-dspi",
 		"fsl,ls2085a-dspi"
 		or
 		"fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
-- 
1.9.1

[PATCH 07/10] dt-bindings: thermal: Update bindings for LS1012A

[Bhaskar Upadhaya]

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
 Documentation/devicetree/bindings/thermal/qoriq-thermal.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
index 66223d5..8e2b211 100644
--- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
@@ -1,7 +1,7 @@
 * Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
 
 Required properties:
-- compatible : Must include "fsl,qoriq-tmu". The version of the device is
+- compatible :"fsl,qoriq-tmu", "fsl,ls1012a-tmu". The version of the device is
 	determined by the TMU IP Block Revision Register (IPBRR0) at
 	offset 0x0BF8.
 	Table of correspondences between IPBRR0 values and example  chips:
-- 
1.9.1

[PATCH 07/10] dt-bindings: thermal: Update bindings for LS1012A

[Bhaskar Upadhaya]

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
 Documentation/devicetree/bindings/thermal/qoriq-thermal.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
index 66223d5..8e2b211 100644
--- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
@@ -1,7 +1,7 @@
 * Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
 
 Required properties:
-- compatible : Must include "fsl,qoriq-tmu". The version of the device is
+- compatible :"fsl,qoriq-tmu", "fsl,ls1012a-tmu". The version of the device is
 	determined by the TMU IP Block Revision Register (IPBRR0) at
 	offset 0x0BF8.
 	Table of correspondences between IPBRR0 values and example  chips:
-- 
1.9.1

[PATCH 08/10] dt-bindings: usb: Update bindings for LS1012A

[Bhaskar Upadhaya]

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
 Documentation/devicetree/bindings/usb/fsl-usb.txt | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/fsl-usb.txt b/Documentation/devicetree/bindings/usb/fsl-usb.txt
index 4779c02..08ccc6e 100644
--- a/Documentation/devicetree/bindings/usb/fsl-usb.txt
+++ b/Documentation/devicetree/bindings/usb/fsl-usb.txt
@@ -81,3 +81,13 @@ Example dual role USB controller device node for MPC5121ADS:
 		fsl,invert-drvvbus;
 		fsl,invert-pwr-fault;
 	};
+
+Example dual role USB controller device node for LS1012A:
+	usb@8600000 {
+		compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
+		reg = <0x0 0x8600000 0x0 0x1000>;
+		interrupts = <0 139 0x4>;
+		dr_mode = "host";
+		phy_type = "ulpi";
+		fsl,usb-erratum-a005697;
+	};
-- 
1.9.1

[PATCH 08/10] dt-bindings: usb: Update bindings for LS1012A

[Bhaskar Upadhaya]

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
 Documentation/devicetree/bindings/usb/fsl-usb.txt | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/fsl-usb.txt b/Documentation/devicetree/bindings/usb/fsl-usb.txt
index 4779c02..08ccc6e 100644
--- a/Documentation/devicetree/bindings/usb/fsl-usb.txt
+++ b/Documentation/devicetree/bindings/usb/fsl-usb.txt
@@ -81,3 +81,13 @@ Example dual role USB controller device node for MPC5121ADS:
 		fsl,invert-drvvbus;
 		fsl,invert-pwr-fault;
 	};
+
+Example dual role USB controller device node for LS1012A:
+	usb at 8600000 {
+		compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
+		reg = <0x0 0x8600000 0x0 0x1000>;
+		interrupts = <0 139 0x4>;
+		dr_mode = "host";
+		phy_type = "ulpi";
+		fsl,usb-erratum-a005697;
+	};
-- 
1.9.1

[PATCH 09/10] dt-bindings: Update bindings with additional vendor for LS1012A

[Bhaskar Upadhaya]

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index a7440bc..e9f923d 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -85,6 +85,7 @@ elan	Elan Microelectronic Corp.
 embest	Shenzhen Embest Technology Co., Ltd.
 emmicro	EM Microelectronic
 energymicro	Silicon Laboratories (formerly Energy Micro AS)
+eon	Eon Silicon Solution, Inc.
 epcos	EPCOS AG
 epfl	Ecole Polytechnique Fédérale de Lausanne
 epson	Seiko Epson Corp.
@@ -246,6 +247,7 @@ solomon        Solomon Systech Limited
 sony	Sony Corporation
 spansion	Spansion Inc.
 sprd	Spreadtrum Communications Inc.
+sst	Silicon Storage Technology, Inc.
 st	STMicroelectronics
 startek	Startek
 ste	ST-Ericsson
-- 
1.9.1


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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 09/10] dt-bindings: Update bindings with additional vendor for LS1012A

[Bhaskar Upadhaya]

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index a7440bc..e9f923d 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -85,6 +85,7 @@ elan	Elan Microelectronic Corp.
 embest	Shenzhen Embest Technology Co., Ltd.
 emmicro	EM Microelectronic
 energymicro	Silicon Laboratories (formerly Energy Micro AS)
+eon	Eon Silicon Solution, Inc.
 epcos	EPCOS AG
 epfl	Ecole Polytechnique F?d?rale de Lausanne
 epson	Seiko Epson Corp.
@@ -246,6 +247,7 @@ solomon        Solomon Systech Limited
 sony	Sony Corporation
 spansion	Spansion Inc.
 sprd	Spreadtrum Communications Inc.
+sst	Silicon Storage Technology, Inc.
 st	STMicroelectronics
 startek	Startek
 ste	ST-Ericsson
-- 
1.9.1

[PATCH 10/10] dt-bindings: sec: Update bindings for LS1012A

[Bhaskar Upadhaya]

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
 .../devicetree/bindings/crypto/fsl-sec5.txt        | 153 +++++++++++++++++++++
 1 file changed, 153 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec5.txt

diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec5.txt b/Documentation/devicetree/bindings/crypto/fsl-sec5.txt
new file mode 100644
index 0000000..7bcaa6f
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/fsl-sec5.txt
@@ -0,0 +1,153 @@
+SEC 5 is Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
+Currently Freescale arm chip LS1012A is embedded with SEC 5.
+SEC 5 device tree binding include:
+   -SEC 5 Node
+   -Job Ring Node
+   -Full Example
+
+=====================================================================
+SEC 5 Node
+
+Description
+
+    Node defines the base address of the SEC 5 block.
+    This block specifies the address range of all global
+    configuration registers for the SEC 5 block.
+    For example, In LS1012A, we could see three SEC 5 node.
+
+PROPERTIES
+
+   - compatible
+      Usage: required
+      Value type: <string>
+      Definition: Must include "fsl,sec-v5.4".
+
+   - fsl,sec-era
+      Usage: optional
+      Value type: <u32>
+      Definition: A standard property. Define the 'ERA' of the SEC
+          device.
+
+   - #address-cells
+       Usage: required
+       Value type: <u32>
+       Definition: A standard property.  Defines the number of cells
+           for representing physical addresses in child nodes.
+
+   - #size-cells
+       Usage: required
+       Value type: <u32>
+       Definition: A standard property.  Defines the number of cells
+           for representing the size of physical addresses in
+           child nodes.
+
+   - reg
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: A standard property.  Specifies the physical
+          address and length of the SEC 5 configuration registers.
+
+   - ranges
+       Usage: required
+       Value type: <prop-encoded-array>
+       Definition: A standard property.  Specifies the physical address
+           range of the SEC 5.0 register space (-SNVS not included).  A
+           triplet that includes the child address, parent address, &
+           length.
+
+   Note: All other standard properties (see the ePAPR) are allowed
+   but are optional.
+
+EXAMPLE
+	crypto: crypto@1700000 {
+                        compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+                                     "fsl,sec-v4.0";
+                        fsl,sec-era = <8>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x0 0x00 0x1700000 0x100000>;
+                        reg = <0x00 0x1700000 0x0 0x100000>;
+                        interrupts = <0 75 0x4>;
+	}
+
+=====================================================================
+Job Ring (JR) Node
+
+    Child of the crypto node defines data processing interface to SEC 5
+    across the peripheral bus for purposes of processing
+    cryptographic descriptors. The specified address
+    range can be made visible to one (or more) cores.
+    The interrupt defined for this node is controlled within
+    the address range of this node.
+
+  - compatible
+      Usage: required
+      Value type: <string>
+      Definition: Must include "fsl,sec-v5.4-job-ring".
+
+  - reg
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: Specifies a two JR parameters:  an offset from
+           the parent physical address and the length the JR registers.
+
+   - interrupts
+      Usage: required
+      Value type: <prop_encoded-array>
+      Definition:  Specifies the interrupts generated by this
+           device.  The value of the interrupts property
+           consists of one interrupt specifier. The format
+           of the specifier is defined by the binding document
+           describing the node's interrupt parent.
+
+EXAMPLE
+	sec_jr0: jr@10000 {
+		compatible = "fsl,sec-v5.4-job-ring",
+			"fsl,sec-v5.0-job-ring",
+			"fsl,sec-v4.0-job-ring";
+			reg = <0x10000 0x10000>;
+			interrupts = <0 71 0x4>;
+	};
+
+===================================================================
+Full Example
+
+Since some chips may contain more than one SEC, the dtsi contains
+only the node contents, not the node itself.  A chip using the SEC
+should include the dtsi inside each SEC node.  Example:
+
+In fsl-ls1012a.dtsi:
+
+	compatible = "fsl,sec-v5.4";
+	fsl,sec-era = <8>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	sec_jr0: jr@10000 {
+		compatible = "fsl,sec-v5.4-job-ring",
+			"fsl,sec-v5.0-job-ring",
+			"fsl,sec-v4.0-job-ring";
+			reg = <0x10000 0x10000>;
+			interrupts = <0 71 0x4>;
+	};
+	sec_jr1: jr@20000 {
+		compatible = "fsl,sec-v5.4-job-ring",
+			"fsl,sec-v5.0-job-ring",
+			"fsl,sec-v4.0-job-ring";
+			reg = <0x20000 0x10000>;
+			interrupts = <0 72 0x4>;
+	};
+	sec_jr2: jr@30000 {
+		compatible = "fsl,sec-v5.4-job-ring",
+			"fsl,sec-v5.0-job-ring",
+			"fsl,sec-v4.0-job-ring";
+			reg = <0x30000 0x10000>;
+			interrupts = <0 73 0x4>;
+	};
+	sec_jr3: jr@40000 {
+		compatible = "fsl,sec-v5.4-job-ring",
+			"fsl,sec-v5.0-job-ring",
+			"fsl,sec-v4.0-job-ring";
+			reg = <0x40000 0x10000>;
+			interrupts = <0 74 0x4>;
+	};
-- 
1.9.1

[PATCH 10/10] dt-bindings: sec: Update bindings for LS1012A

[Bhaskar Upadhaya]

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
 .../devicetree/bindings/crypto/fsl-sec5.txt        | 153 +++++++++++++++++++++
 1 file changed, 153 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec5.txt

diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec5.txt b/Documentation/devicetree/bindings/crypto/fsl-sec5.txt
new file mode 100644
index 0000000..7bcaa6f
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/fsl-sec5.txt
@@ -0,0 +1,153 @@
+SEC 5 is Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
+Currently Freescale arm chip LS1012A is embedded with SEC 5.
+SEC 5 device tree binding include:
+   -SEC 5 Node
+   -Job Ring Node
+   -Full Example
+
+=====================================================================
+SEC 5 Node
+
+Description
+
+    Node defines the base address of the SEC 5 block.
+    This block specifies the address range of all global
+    configuration registers for the SEC 5 block.
+    For example, In LS1012A, we could see three SEC 5 node.
+
+PROPERTIES
+
+   - compatible
+      Usage: required
+      Value type: <string>
+      Definition: Must include "fsl,sec-v5.4".
+
+   - fsl,sec-era
+      Usage: optional
+      Value type: <u32>
+      Definition: A standard property. Define the 'ERA' of the SEC
+          device.
+
+   - #address-cells
+       Usage: required
+       Value type: <u32>
+       Definition: A standard property.  Defines the number of cells
+           for representing physical addresses in child nodes.
+
+   - #size-cells
+       Usage: required
+       Value type: <u32>
+       Definition: A standard property.  Defines the number of cells
+           for representing the size of physical addresses in
+           child nodes.
+
+   - reg
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: A standard property.  Specifies the physical
+          address and length of the SEC 5 configuration registers.
+
+   - ranges
+       Usage: required
+       Value type: <prop-encoded-array>
+       Definition: A standard property.  Specifies the physical address
+           range of the SEC 5.0 register space (-SNVS not included).  A
+           triplet that includes the child address, parent address, &
+           length.
+
+   Note: All other standard properties (see the ePAPR) are allowed
+   but are optional.
+
+EXAMPLE
+	crypto: crypto at 1700000 {
+                        compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+                                     "fsl,sec-v4.0";
+                        fsl,sec-era = <8>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x0 0x00 0x1700000 0x100000>;
+                        reg = <0x00 0x1700000 0x0 0x100000>;
+                        interrupts = <0 75 0x4>;
+	}
+
+=====================================================================
+Job Ring (JR) Node
+
+    Child of the crypto node defines data processing interface to SEC 5
+    across the peripheral bus for purposes of processing
+    cryptographic descriptors. The specified address
+    range can be made visible to one (or more) cores.
+    The interrupt defined for this node is controlled within
+    the address range of this node.
+
+  - compatible
+      Usage: required
+      Value type: <string>
+      Definition: Must include "fsl,sec-v5.4-job-ring".
+
+  - reg
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: Specifies a two JR parameters:  an offset from
+           the parent physical address and the length the JR registers.
+
+   - interrupts
+      Usage: required
+      Value type: <prop_encoded-array>
+      Definition:  Specifies the interrupts generated by this
+           device.  The value of the interrupts property
+           consists of one interrupt specifier. The format
+           of the specifier is defined by the binding document
+           describing the node's interrupt parent.
+
+EXAMPLE
+	sec_jr0: jr at 10000 {
+		compatible = "fsl,sec-v5.4-job-ring",
+			"fsl,sec-v5.0-job-ring",
+			"fsl,sec-v4.0-job-ring";
+			reg = <0x10000 0x10000>;
+			interrupts = <0 71 0x4>;
+	};
+
+===================================================================
+Full Example
+
+Since some chips may contain more than one SEC, the dtsi contains
+only the node contents, not the node itself.  A chip using the SEC
+should include the dtsi inside each SEC node.  Example:
+
+In fsl-ls1012a.dtsi:
+
+	compatible = "fsl,sec-v5.4";
+	fsl,sec-era = <8>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	sec_jr0: jr at 10000 {
+		compatible = "fsl,sec-v5.4-job-ring",
+			"fsl,sec-v5.0-job-ring",
+			"fsl,sec-v4.0-job-ring";
+			reg = <0x10000 0x10000>;
+			interrupts = <0 71 0x4>;
+	};
+	sec_jr1: jr at 20000 {
+		compatible = "fsl,sec-v5.4-job-ring",
+			"fsl,sec-v5.0-job-ring",
+			"fsl,sec-v4.0-job-ring";
+			reg = <0x20000 0x10000>;
+			interrupts = <0 72 0x4>;
+	};
+	sec_jr2: jr at 30000 {
+		compatible = "fsl,sec-v5.4-job-ring",
+			"fsl,sec-v5.0-job-ring",
+			"fsl,sec-v4.0-job-ring";
+			reg = <0x30000 0x10000>;
+			interrupts = <0 73 0x4>;
+	};
+	sec_jr3: jr at 40000 {
+		compatible = "fsl,sec-v5.4-job-ring",
+			"fsl,sec-v5.0-job-ring",
+			"fsl,sec-v4.0-job-ring";
+			reg = <0x40000 0x10000>;
+			interrupts = <0 74 0x4>;
+	};
-- 
1.9.1

RE: [linux-devel] [PATCH 02/10] dt-bindings: esdhc: Update bindings for LS1012A

[Yang-Leo Li]

> -----Original Message-----
> From: linux-devel-bounces@gforge.freescale.net [mailto:linux-devel-
> bounces@gforge.freescale.net] On Behalf Of Bhaskar Upadhaya
> Sent: Friday, August 26, 2016 5:28 AM
> To: devicetree@vger.kernel.org; shawnguo@kernel.org
> Cc: oss@buserror.net; linux-devel@gforge.freescale.net; Bhaskar U
> <bhaskar.upadhaya@nxp.com>; linux-arm-kernel@lists.infradead.org
> Subject: [linux-devel] [PATCH 02/10] dt-bindings: esdhc: Update bindings for
> LS1012A
> 
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
> ---
>  Documentation/devicetree/bindings/mmc/fsl-esdhc.txt | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
> b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
> index dedfb02..3257b4a 100644
> --- a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
> +++ b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
> @@ -7,9 +7,9 @@ This file documents differences between the core properties
> described  by mmc.txt and the properties used by the sdhci-esdhc driver.
> 
>  Required properties:
> +  - compatible : "fsl,mpc8378-esdhc", "fsl,ls1012a-esdhc0", "fsl,ls1012a-
> esdhc1".

What does it mean for esdhc0 and esdhc1?  If these are two different controllers used on the same chip, please describe what is the difference.  It is not clear from the name itself.

>    - interrupt-parent : interrupt source phandle.
>    - clock-frequency : specifies eSDHC base clock frequency.
> -
>  Optional properties:
>    - sdhci,wp-inverted : specifies that eSDHC controller reports
>      inverted write-protect state; New devices should use the generic
> --
> 1.9.1
> 
> _______________________________________________
> linux-devel mailing list
> linux-devel@gforge.freescale.net
> http://gforge.freescale.net/mailman/listinfo/linux-devel

[linux-devel] [PATCH 02/10] dt-bindings: esdhc: Update bindings for LS1012A

[Yang-Leo Li]

> -----Original Message-----
> From: linux-devel-bounces at gforge.freescale.net [mailto:linux-devel-
> bounces at gforge.freescale.net] On Behalf Of Bhaskar Upadhaya
> Sent: Friday, August 26, 2016 5:28 AM
> To: devicetree at vger.kernel.org; shawnguo at kernel.org
> Cc: oss at buserror.net; linux-devel at gforge.freescale.net; Bhaskar U
> <bhaskar.upadhaya@nxp.com>; linux-arm-kernel at lists.infradead.org
> Subject: [linux-devel] [PATCH 02/10] dt-bindings: esdhc: Update bindings for
> LS1012A
> 
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
> ---
>  Documentation/devicetree/bindings/mmc/fsl-esdhc.txt | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
> b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
> index dedfb02..3257b4a 100644
> --- a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
> +++ b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
> @@ -7,9 +7,9 @@ This file documents differences between the core properties
> described  by mmc.txt and the properties used by the sdhci-esdhc driver.
> 
>  Required properties:
> +  - compatible : "fsl,mpc8378-esdhc", "fsl,ls1012a-esdhc0", "fsl,ls1012a-
> esdhc1".

What does it mean for esdhc0 and esdhc1?  If these are two different controllers used on the same chip, please describe what is the difference.  It is not clear from the name itself.

>    - interrupt-parent : interrupt source phandle.
>    - clock-frequency : specifies eSDHC base clock frequency.
> -
>  Optional properties:
>    - sdhci,wp-inverted : specifies that eSDHC controller reports
>      inverted write-protect state; New devices should use the generic
> --
> 1.9.1
> 
> _______________________________________________
> linux-devel mailing list
> linux-devel at gforge.freescale.net
> http://gforge.freescale.net/mailman/listinfo/linux-devel

Re: [PATCH 04/10] dt-bindings: spi-nor: Update bindings for LS1012A

[Scott Wood]

On Fri, 2016-08-26 at 15:57 +0530, Bhaskar Upadhaya wrote:
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya-3arQi8VN3Tc@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
> b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
> index 2c91c03..fc99ef2 100644
> --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
> +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
> @@ -13,6 +13,7 @@ Required properties:
>                   at25df321a
>                   at25df641
>                   at26df081a
> +		 eon,en25s64
>                   mr25h256
>                   mx25l4005a
>                   mx25l1606e
> @@ -29,6 +30,7 @@ Required properties:
>                   s25fl008k
>                   s25fl064k
>                   sst25vf040b
> +		 sst,sst25wf040b
>                   m25p40
>                   m25p80
>                   m25p16

Whitespace doesn't match what's already there.

Why are these the only lines that have a vendor prefix?

-Scott

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[PATCH 04/10] dt-bindings: spi-nor: Update bindings for LS1012A

[Scott Wood]

On Fri, 2016-08-26 at 15:57 +0530, Bhaskar Upadhaya wrote:
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
> ---
> ?Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt | 2 ++
> ?1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
> b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
> index 2c91c03..fc99ef2 100644
> --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
> +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
> @@ -13,6 +13,7 @@ Required properties:
> ??????????????????at25df321a
> ??????????????????at25df641
> ??????????????????at26df081a
> +		?eon,en25s64
> ??????????????????mr25h256
> ??????????????????mx25l4005a
> ??????????????????mx25l1606e
> @@ -29,6 +30,7 @@ Required properties:
> ??????????????????s25fl008k
> ??????????????????s25fl064k
> ??????????????????sst25vf040b
> +		?sst,sst25wf040b
> ??????????????????m25p40
> ??????????????????m25p80
> ??????????????????m25p16

Whitespace doesn't match what's already there.

Why are these the only lines that have a vendor prefix?

-Scott

Re: [PATCH 05/10] dt-bindings: pci: Update bindings for LS1012A

[Scott Wood]

On Fri, 2016-08-26 at 15:57 +0530, Bhaskar Upadhaya wrote:
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya-3arQi8VN3Tc@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> index 41e9f55..5755697 100644
> --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> @@ -15,6 +15,7 @@ Required properties:
>  - compatible: should contain the platform identifier such as:
>          "fsl,ls1021a-pcie", "snps,dw-pcie"
>          "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie"
> +	"fsl,ls1012a-pcie", "fsl,ls1043a-pcie" ,"snps,dw-pcie"

Whitespace doesn't match.

Why are you listing both ls1012a and ls1043a together?  Are they 100%
compatible?

Why are we updating all these bindings every time we come out with a new chip,
rather than having a <chip> pattern like we did in other bindings?

-Scott

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[PATCH 05/10] dt-bindings: pci: Update bindings for LS1012A

[Scott Wood]

On Fri, 2016-08-26 at 15:57 +0530, Bhaskar Upadhaya wrote:
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
> ---
> ?Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 +
> ?1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> index 41e9f55..5755697 100644
> --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> @@ -15,6 +15,7 @@ Required properties:
> ?- compatible: should contain the platform identifier such as:
> ?????????"fsl,ls1021a-pcie", "snps,dw-pcie"
> ?????????"fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie"
> +	"fsl,ls1012a-pcie", "fsl,ls1043a-pcie" ,"snps,dw-pcie"

Whitespace doesn't match.

Why are you listing both ls1012a and ls1043a together? ?Are they 100%
compatible?

Why are we updating all these bindings every time we come out with a new chip,
rather than having a <chip> pattern like we did in other bindings?

-Scott

Re: [PATCH 07/10] dt-bindings: thermal: Update bindings for LS1012A

[Scott Wood]

On Fri, 2016-08-26 at 15:57 +0530, Bhaskar Upadhaya wrote:
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya-3arQi8VN3Tc@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/thermal/qoriq-thermal.txt | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> index 66223d5..8e2b211 100644
> --- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> @@ -1,7 +1,7 @@
>  * Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
>  
>  Required properties:
> -- compatible : Must include "fsl,qoriq-tmu". The version of the device is
> +- compatible :"fsl,qoriq-tmu", "fsl,ls1012a-tmu". The version of the device
> is
>  	determined by the TMU IP Block Revision Register (IPBRR0) at
>  	offset 0x0BF8.
>  	Table of correspondences between IPBRR0 values and example  chips:

Why is this needed given that the block has a version register?

-Scott

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[PATCH 07/10] dt-bindings: thermal: Update bindings for LS1012A

[Scott Wood]

On Fri, 2016-08-26 at 15:57 +0530, Bhaskar Upadhaya wrote:
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
> ---
> ?Documentation/devicetree/bindings/thermal/qoriq-thermal.txt | 2 +-
> ?1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> index 66223d5..8e2b211 100644
> --- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> @@ -1,7 +1,7 @@
> ?* Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
> ?
> ?Required properties:
> -- compatible : Must include "fsl,qoriq-tmu". The version of the device is
> +- compatible :"fsl,qoriq-tmu", "fsl,ls1012a-tmu". The version of the device
> is
> ?	determined by the TMU IP Block Revision Register (IPBRR0) at
> ?	offset 0x0BF8.
> ?	Table of correspondences between IPBRR0 values and example??chips:

Why is this needed given that the block has a version register?

-Scott

Re: [PATCH 08/10] dt-bindings: usb: Update bindings for LS1012A

[Scott Wood]

On Fri, 2016-08-26 at 15:57 +0530, Bhaskar Upadhaya wrote:
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya-3arQi8VN3Tc@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/usb/fsl-usb.txt | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/fsl-usb.txt
> b/Documentation/devicetree/bindings/usb/fsl-usb.txt
> index 4779c02..08ccc6e 100644
> --- a/Documentation/devicetree/bindings/usb/fsl-usb.txt
> +++ b/Documentation/devicetree/bindings/usb/fsl-usb.txt
> @@ -81,3 +81,13 @@ Example dual role USB controller device node for
> MPC5121ADS:
>  		fsl,invert-drvvbus;
>  		fsl,invert-pwr-fault;
>  	};
> +
> +Example dual role USB controller device node for LS1012A:
> +	usb@8600000 {
> +		compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
> +		reg = <0x0 0x8600000 0x0 0x1000>;
> +		interrupts = <0 139 0x4>;
> +		dr_mode = "host";
> +		phy_type = "ulpi";
> +		fsl,usb-erratum-a005697;
> +	};

What does this change have to do with the incredibly vague changelog of
"Update bindings for LS1012A"?

-Scott

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[PATCH 08/10] dt-bindings: usb: Update bindings for LS1012A

[Scott Wood]

On Fri, 2016-08-26 at 15:57 +0530, Bhaskar Upadhaya wrote:
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
> ---
> ?Documentation/devicetree/bindings/usb/fsl-usb.txt | 10 ++++++++++
> ?1 file changed, 10 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/fsl-usb.txt
> b/Documentation/devicetree/bindings/usb/fsl-usb.txt
> index 4779c02..08ccc6e 100644
> --- a/Documentation/devicetree/bindings/usb/fsl-usb.txt
> +++ b/Documentation/devicetree/bindings/usb/fsl-usb.txt
> @@ -81,3 +81,13 @@ Example dual role USB controller device node for
> MPC5121ADS:
> ?		fsl,invert-drvvbus;
> ?		fsl,invert-pwr-fault;
> ?	};
> +
> +Example dual role USB controller device node for LS1012A:
> +	usb at 8600000 {
> +		compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
> +		reg = <0x0 0x8600000 0x0 0x1000>;
> +		interrupts = <0 139 0x4>;
> +		dr_mode = "host";
> +		phy_type = "ulpi";
> +		fsl,usb-erratum-a005697;
> +	};

What does this change have to do with the incredibly vague changelog of
"Update bindings for LS1012A"?

-Scott

Re: [PATCH 09/10] dt-bindings: Update bindings with additional vendor for LS1012A

[Scott Wood]

On Fri, 2016-08-26 at 15:57 +0530, Bhaskar Upadhaya wrote:
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya-3arQi8VN3Tc@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.txt | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
> b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index a7440bc..e9f923d 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> @@ -85,6 +85,7 @@ elan	Elan Microelectronic Corp.
>  embest	Shenzhen Embest Technology Co., Ltd.
>  emmicro	EM Microelectronic
>  energymicro	Silicon Laboratories (formerly Energy Micro AS)
> +eon	Eon Silicon Solution, Inc.
>  epcos	EPCOS AG
>  epfl	Ecole Polytechnique Fédérale de Lausanne
>  epson	Seiko Epson Corp.
> @@ -246,6 +247,7 @@ solomon        Solomon Systech Limited
>  sony	Sony Corporation
>  spansion	Spansion Inc.
>  sprd	Spreadtrum Communications Inc.
> +sst	Silicon Storage Technology, Inc.
>  st	STMicroelectronics
>  startek	Startek
>  ste	ST-Ericsson

What does LS1012A have to do with these vendors?  At most your motivation
might be that these chips are on a board that happens to also have an LS1012A
on it, but that doesn't make it an appropriate patch description.  Better
would be something like "dt-bindings: Add eon and sst vendor strings" with the
changelog body mentioning that you're documenting prefixes that are already in
use.

-Scott

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[PATCH 09/10] dt-bindings: Update bindings with additional vendor for LS1012A

[Scott Wood]

On Fri, 2016-08-26 at 15:57 +0530, Bhaskar Upadhaya wrote:
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
> ---
> ?Documentation/devicetree/bindings/vendor-prefixes.txt | 2 ++
> ?1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
> b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index a7440bc..e9f923d 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> @@ -85,6 +85,7 @@ elan	Elan Microelectronic Corp.
> ?embest	Shenzhen Embest Technology Co., Ltd.
> ?emmicro	EM Microelectronic
> ?energymicro	Silicon Laboratories (formerly Energy Micro AS)
> +eon	Eon Silicon Solution, Inc.
> ?epcos	EPCOS AG
> ?epfl	Ecole Polytechnique F?d?rale de Lausanne
> ?epson	Seiko Epson Corp.
> @@ -246,6 +247,7 @@ solomon????????Solomon Systech Limited
> ?sony	Sony Corporation
> ?spansion	Spansion Inc.
> ?sprd	Spreadtrum Communications Inc.
> +sst	Silicon Storage Technology, Inc.
> ?st	STMicroelectronics
> ?startek	Startek
> ?ste	ST-Ericsson

What does LS1012A have to do with these vendors? ?At most your motivation
might be that these chips are on a board that happens to also have an LS1012A
on it, but that doesn't make it an appropriate patch description. ?Better
would be something like "dt-bindings: Add eon and sst vendor strings" with the
changelog body mentioning that you're documenting prefixes that are already in
use.

-Scott

Re: [PATCH 10/10] dt-bindings: sec: Update bindings for LS1012A

[Scott Wood]

On Fri, 2016-08-26 at 15:57 +0530, Bhaskar Upadhaya wrote:
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya-3arQi8VN3Tc@public.gmane.org>
> ---
>  .../devicetree/bindings/crypto/fsl-sec5.txt        | 153
> +++++++++++++++++++++
>  1 file changed, 153 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec5.txt

Again, the subject should explain what you're adding, not why.  You're adding
a sec5 binding, not an LS1012A binding.

Why aren't the crypto maintainers/list CCed?

Why do we need a separate binding document for each SEC version?  What is
different from the sec4 binding or the sec6 binding?  Especially given that
the example claims compatibility with sec4?

> diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec5.txt
> b/Documentation/devicetree/bindings/crypto/fsl-sec5.txt
> new file mode 100644
> index 0000000..7bcaa6f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/crypto/fsl-sec5.txt
> @@ -0,0 +1,153 @@
> +SEC 5 is Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
> +Currently Freescale arm chip LS1012A is embedded with SEC 5.
> +SEC 5 device tree binding include:
> +   -SEC 5 Node
> +   -Job Ring Node
> +   -Full Example
> +
> +=====================================================================
> +SEC 5 Node
> +
> +Description
> +
> +    Node defines the base address of the SEC 5 block.
> +    This block specifies the address range of all global
> +    configuration registers for the SEC 5 block.
> +    For example, In LS1012A, we could see three SEC 5 node.
> +
> +PROPERTIES
> +
> +   - compatible
> +      Usage: required
> +      Value type: <string>
> +      Definition: Must include "fsl,sec-v5.4".

There was no v5.x prior to v5.4?

> +   - fsl,sec-era
> +      Usage: optional
> +      Value type: <u32>
> +      Definition: A standard property. Define the 'ERA' of the SEC
> +          device.

This is not "a standard property".

> +   - reg
> +      Usage: required
> +      Value type: <prop-encoded-array>
> +      Definition: A standard property.  Specifies the physical
> +          address and length of the SEC 5 configuration registers.

Whether this property expresses the raw physical address depends on the ranges
of the parent node.  Just say that there's one reg resource which is the SEC
configuration registers.

> +
> +   - ranges
> +       Usage: required
> +       Value type: <prop-encoded-array>
> +       Definition: A standard property.  Specifies the physical address
> +           range of the SEC 5.0 register space (-SNVS not included).  A
> +           triplet that includes the child address, parent address, &
> +           length.

Likewise with the talk about "physical address".  It's also not required that
it contain such a triplet -- it could theoretically be an empty ranges
property, or there could be multiple translations.  Bindings shouldn't try to
(poorly) repeat the definition of standard properties.  They should specify
information that is specific to this binding.

The only thing worth mentioning here about ranges is if the driver will expect
a particular translation independently of whether a child reg is using it.

> +===================================================================
> +Full Example
> +
> +Since some chips may contain more than one SEC, the dtsi contains
> +only the node contents, not the node itself.  A chip using the SEC
> +should include the dtsi inside each SEC node.  Example:

Bindings generally describe what the OS expects to see, not the details of the
dtsi structure.

> +
> +In fsl-ls1012a.dtsi:
> +
> +	compatible = "fsl,sec-v5.4";
> +	fsl,sec-era = <8>;
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	sec_jr0: jr@10000 {
> +		compatible = "fsl,sec-v5.4-job-ring",
> +			"fsl,sec-v5.0-job-ring",
> +			"fsl,sec-v4.0-job-ring";
> +			reg = <0x10000 0x10000>;
> +			interrupts = <0 71 0x4>;
> +	};
> +	sec_jr1: jr@20000 {
> +		compatible = "fsl,sec-v5.4-job-ring",
> +			"fsl,sec-v5.0-job-ring",
> +			"fsl,sec-v4.0-job-ring";
> +			reg = <0x20000 0x10000>;
> +			interrupts = <0 72 0x4>;
> +	};
> +	sec_jr2: jr@30000 {
> +		compatible = "fsl,sec-v5.4-job-ring",
> +			"fsl,sec-v5.0-job-ring",
> +			"fsl,sec-v4.0-job-ring";
> +			reg = <0x30000 0x10000>;
> +			interrupts = <0 73 0x4>;
> +	};
> +	sec_jr3: jr@40000 {
> +		compatible = "fsl,sec-v5.4-job-ring",
> +			"fsl,sec-v5.0-job-ring",
> +			"fsl,sec-v4.0-job-ring";
> +			reg = <0x40000 0x10000>;
> +			interrupts = <0 74 0x4>;
> +	};

This is terrible whitespace.

-Scott

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[PATCH 10/10] dt-bindings: sec: Update bindings for LS1012A

[Scott Wood]

On Fri, 2016-08-26 at 15:57 +0530, Bhaskar Upadhaya wrote:
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
> ---
> ?.../devicetree/bindings/crypto/fsl-sec5.txt????????| 153
> +++++++++++++++++++++
> ?1 file changed, 153 insertions(+)
> ?create mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec5.txt

Again, the subject should explain what you're adding, not why. ?You're adding
a sec5 binding, not an LS1012A binding.

Why aren't the crypto maintainers/list CCed?

Why do we need a separate binding document for each SEC version? ?What is
different from the sec4 binding or the sec6 binding? ?Especially given that
the example claims compatibility with sec4?

> diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec5.txt
> b/Documentation/devicetree/bindings/crypto/fsl-sec5.txt
> new file mode 100644
> index 0000000..7bcaa6f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/crypto/fsl-sec5.txt
> @@ -0,0 +1,153 @@
> +SEC 5 is Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
> +Currently Freescale arm chip LS1012A is embedded with SEC 5.
> +SEC 5 device tree binding include:
> +???-SEC 5 Node
> +???-Job Ring Node
> +???-Full Example
> +
> +=====================================================================
> +SEC 5 Node
> +
> +Description
> +
> +????Node defines the base address of the SEC 5 block.
> +????This block specifies the address range of all global
> +????configuration registers for the SEC 5 block.
> +????For example, In LS1012A, we could see three SEC 5 node.
> +
> +PROPERTIES
> +
> +???- compatible
> +??????Usage: required
> +??????Value type: <string>
> +??????Definition: Must include "fsl,sec-v5.4".

There was no v5.x prior to v5.4?

> +???- fsl,sec-era
> +??????Usage: optional
> +??????Value type: <u32>
> +??????Definition: A standard property. Define the 'ERA' of the SEC
> +??????????device.

This is not "a standard property".

> +???- reg
> +??????Usage: required
> +??????Value type: <prop-encoded-array>
> +??????Definition: A standard property.??Specifies the physical
> +??????????address and length of the SEC 5 configuration registers.

Whether this property expresses the raw physical address depends on the ranges
of the parent node. ?Just say that there's one reg resource which is the SEC
configuration registers.

> +
> +???- ranges
> +???????Usage: required
> +???????Value type: <prop-encoded-array>
> +???????Definition: A standard property.??Specifies the physical address
> +???????????range of the SEC 5.0 register space (-SNVS not included).??A
> +???????????triplet that includes the child address, parent address, &
> +???????????length.

Likewise with the talk about "physical address". ?It's also not required that
it contain such a triplet -- it could theoretically be an empty ranges
property, or there could be multiple translations. ?Bindings shouldn't try to
(poorly) repeat the definition of standard properties. ?They should specify
information that is specific to this binding.

The only thing worth mentioning here about ranges is if the driver will expect
a particular translation independently of whether a child reg is using it.

> +===================================================================
> +Full Example
> +
> +Since some chips may contain more than one SEC, the dtsi contains
> +only the node contents, not the node itself.??A chip using the SEC
> +should include the dtsi inside each SEC node.??Example:

Bindings generally describe what the OS expects to see, not the details of the
dtsi structure.

> +
> +In fsl-ls1012a.dtsi:
> +
> +	compatible = "fsl,sec-v5.4";
> +	fsl,sec-era = <8>;
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	sec_jr0: jr at 10000 {
> +		compatible = "fsl,sec-v5.4-job-ring",
> +			"fsl,sec-v5.0-job-ring",
> +			"fsl,sec-v4.0-job-ring";
> +			reg = <0x10000 0x10000>;
> +			interrupts = <0 71 0x4>;
> +	};
> +	sec_jr1: jr at 20000 {
> +		compatible = "fsl,sec-v5.4-job-ring",
> +			"fsl,sec-v5.0-job-ring",
> +			"fsl,sec-v4.0-job-ring";
> +			reg = <0x20000 0x10000>;
> +			interrupts = <0 72 0x4>;
> +	};
> +	sec_jr2: jr at 30000 {
> +		compatible = "fsl,sec-v5.4-job-ring",
> +			"fsl,sec-v5.0-job-ring",
> +			"fsl,sec-v4.0-job-ring";
> +			reg = <0x30000 0x10000>;
> +			interrupts = <0 73 0x4>;
> +	};
> +	sec_jr3: jr at 40000 {
> +		compatible = "fsl,sec-v5.4-job-ring",
> +			"fsl,sec-v5.0-job-ring",
> +			"fsl,sec-v4.0-job-ring";
> +			reg = <0x40000 0x10000>;
> +			interrupts = <0 74 0x4>;
> +	};

This is terrible whitespace.

-Scott

Re: [PATCH 08/10] dt-bindings: usb: Update bindings for LS1012A

[Shawn Guo]

On Fri, Aug 26, 2016 at 03:57:47PM +0530, Bhaskar Upadhaya wrote:
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya-3arQi8VN3Tc@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/usb/fsl-usb.txt | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/fsl-usb.txt b/Documentation/devicetree/bindings/usb/fsl-usb.txt
> index 4779c02..08ccc6e 100644
> --- a/Documentation/devicetree/bindings/usb/fsl-usb.txt
> +++ b/Documentation/devicetree/bindings/usb/fsl-usb.txt
> @@ -81,3 +81,13 @@ Example dual role USB controller device node for MPC5121ADS:
>  		fsl,invert-drvvbus;
>  		fsl,invert-pwr-fault;
>  	};
> +
> +Example dual role USB controller device node for LS1012A:
> +	usb@8600000 {
> +		compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
> +		reg = <0x0 0x8600000 0x0 0x1000>;
> +		interrupts = <0 139 0x4>;
> +		dr_mode = "host";
> +		phy_type = "ulpi";
> +		fsl,usb-erratum-a005697;

I cannot find this 'fsl,usb-erratum-a005697' property definition in the
bindings doc.

Shawn

> +	};
> -- 
> 1.9.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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[PATCH 08/10] dt-bindings: usb: Update bindings for LS1012A

[Shawn Guo]

On Fri, Aug 26, 2016 at 03:57:47PM +0530, Bhaskar Upadhaya wrote:
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
> ---
>  Documentation/devicetree/bindings/usb/fsl-usb.txt | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/fsl-usb.txt b/Documentation/devicetree/bindings/usb/fsl-usb.txt
> index 4779c02..08ccc6e 100644
> --- a/Documentation/devicetree/bindings/usb/fsl-usb.txt
> +++ b/Documentation/devicetree/bindings/usb/fsl-usb.txt
> @@ -81,3 +81,13 @@ Example dual role USB controller device node for MPC5121ADS:
>  		fsl,invert-drvvbus;
>  		fsl,invert-pwr-fault;
>  	};
> +
> +Example dual role USB controller device node for LS1012A:
> +	usb at 8600000 {
> +		compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
> +		reg = <0x0 0x8600000 0x0 0x1000>;
> +		interrupts = <0 139 0x4>;
> +		dr_mode = "host";
> +		phy_type = "ulpi";
> +		fsl,usb-erratum-a005697;

I cannot find this 'fsl,usb-erratum-a005697' property definition in the
bindings doc.

Shawn

> +	};
> -- 
> 1.9.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 04/10] dt-bindings: spi-nor: Update bindings for LS1012A

[Rob Herring]

On Fri, Aug 26, 2016 at 5:27 AM, Bhaskar Upadhaya
<Bhaskar.Upadhaya-3arQi8VN3Tc@public.gmane.org> wrote:

Make the subject reflect what the patch does.

> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya-3arQi8VN3Tc@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
> index 2c91c03..fc99ef2 100644
> --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
> +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
> @@ -13,6 +13,7 @@ Required properties:
>                   at25df321a
>                   at25df641
>                   at26df081a
> +                eon,en25s64

To answer Scott's question, see the paragraph above this.

Rob
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[PATCH 04/10] dt-bindings: spi-nor: Update bindings for LS1012A

[Rob Herring]

On Fri, Aug 26, 2016 at 5:27 AM, Bhaskar Upadhaya
<Bhaskar.Upadhaya@nxp.com> wrote:

Make the subject reflect what the patch does.

> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
> ---
>  Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
> index 2c91c03..fc99ef2 100644
> --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
> +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
> @@ -13,6 +13,7 @@ Required properties:
>                   at25df321a
>                   at25df641
>                   at26df081a
> +                eon,en25s64

To answer Scott's question, see the paragraph above this.

Rob

Re: [PATCH 01/10] dt-bindings: Add compatible property for LS1012A

[Rob Herring]

On Fri, Aug 26, 2016 at 03:57:40PM +0530, Bhaskar Upadhaya wrote:
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya-3arQi8VN3Tc@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/arm/fsl.txt | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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[PATCH 01/10] dt-bindings: Add compatible property for LS1012A

[Rob Herring]

On Fri, Aug 26, 2016 at 03:57:40PM +0530, Bhaskar Upadhaya wrote:
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
> ---
>  Documentation/devicetree/bindings/arm/fsl.txt | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH 03/10] dt-bindings: quadspi: Update bindings for LS1012A

[Rob Herring]

On Fri, Aug 26, 2016 at 03:57:42PM +0530, Bhaskar Upadhaya wrote:
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya-3arQi8VN3Tc@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
 
> diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
> index c34aa6f..071e87e 100644
> --- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
> +++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
> @@ -3,7 +3,7 @@
>  Required properties:
>    - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi",
>  		 "fsl,imx7d-qspi", "fsl,imx6ul-qspi",
> -		 "fsl,ls1021a-qspi"
> +		 "fsl,ls1012a-qspi, "fsl,ls1021a-qspi"
>  		 or
>  		 "fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi",
>  		 "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
> -- 
> 1.9.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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[PATCH 03/10] dt-bindings: quadspi: Update bindings for LS1012A

[Rob Herring]

On Fri, Aug 26, 2016 at 03:57:42PM +0530, Bhaskar Upadhaya wrote:
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
> ---
>  Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Acked-by: Rob Herring <robh@kernel.org>
 
> diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
> index c34aa6f..071e87e 100644
> --- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
> +++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
> @@ -3,7 +3,7 @@
>  Required properties:
>    - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi",
>  		 "fsl,imx7d-qspi", "fsl,imx6ul-qspi",
> -		 "fsl,ls1021a-qspi"
> +		 "fsl,ls1012a-qspi, "fsl,ls1021a-qspi"
>  		 or
>  		 "fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi",
>  		 "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
> -- 
> 1.9.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 06/10] dt-bindings: dspi: Update bindings for LS1012A

[Rob Herring]

On Fri, Aug 26, 2016 at 03:57:45PM +0530, Bhaskar Upadhaya wrote:
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya-3arQi8VN3Tc@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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[PATCH 06/10] dt-bindings: dspi: Update bindings for LS1012A

[Rob Herring]

On Fri, Aug 26, 2016 at 03:57:45PM +0530, Bhaskar Upadhaya wrote:
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
> ---
>  Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Rob Herring <robh@kernel.org>

Re: [linux-devel] [PATCH 10/10] dt-bindings: sec: Update bindings for LS1012A

[Horia Geanta Neag]

On 8/26/2016 6:36 PM, Bhaskar Upadhaya wrote:
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
> ---
>  .../devicetree/bindings/crypto/fsl-sec5.txt        | 153 +++++++++++++++++++++
>  1 file changed, 153 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec5.txt
> 
> diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec5.txt b/Documentation/devicetree/bindings/crypto/fsl-sec5.txt
> new file mode 100644
> index 0000000..7bcaa6f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/crypto/fsl-sec5.txt
> @@ -0,0 +1,153 @@
> +SEC 5 is Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
> +Currently Freescale arm chip LS1012A is embedded with SEC 5.
This sounds like LS1012A is the only platform with SEC5, which is far
from the truth.

> +SEC 5 device tree binding include:
> +   -SEC 5 Node
> +   -Job Ring Node
> +   -Full Example
> +
> +=====================================================================
> +SEC 5 Node
> +
> +Description
> +
> +    Node defines the base address of the SEC 5 block.
> +    This block specifies the address range of all global
> +    configuration registers for the SEC 5 block.
> +    For example, In LS1012A, we could see three SEC 5 node.
There's only one SEC / CAAM crypto engine, thus only one node.
Copy & paste typo from SEC6 binding?

> +
> +PROPERTIES
> +
> +   - compatible
> +      Usage: required
> +      Value type: <string>
> +      Definition: Must include "fsl,sec-v5.4".
Since you are adding a binding for SEC5, make sure you are accounting
for already-existing trees that are using "fsl,sec-v5.0",
"fsl,sec-v5.2", "fsl,sec-v5.3".
See SoCs in arch/powerpc/boot/dts/fsl/

> +
> +   - fsl,sec-era
> +      Usage: optional
> +      Value type: <u32>
> +      Definition: A standard property. Define the 'ERA' of the SEC
> +          device.
> +
> +   - #address-cells
> +       Usage: required
> +       Value type: <u32>
> +       Definition: A standard property.  Defines the number of cells
> +           for representing physical addresses in child nodes.
> +
> +   - #size-cells
> +       Usage: required
> +       Value type: <u32>
> +       Definition: A standard property.  Defines the number of cells
> +           for representing the size of physical addresses in
> +           child nodes.
> +
> +   - reg
> +      Usage: required
> +      Value type: <prop-encoded-array>
> +      Definition: A standard property.  Specifies the physical
> +          address and length of the SEC 5 configuration registers.
> +
> +   - ranges
> +       Usage: required
> +       Value type: <prop-encoded-array>
> +       Definition: A standard property.  Specifies the physical address
> +           range of the SEC 5.0 register space (-SNVS not included).  A
> +           triplet that includes the child address, parent address, &
> +           length.
> +
> +   Note: All other standard properties (see the ePAPR) are allowed
> +   but are optional.
> +
> +EXAMPLE
> +	crypto: crypto@1700000 {
> +                        compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
> +                                     "fsl,sec-v4.0";
> +                        fsl,sec-era = <8>;
> +                        #address-cells = <1>;
> +                        #size-cells = <1>;
> +                        ranges = <0x0 0x00 0x1700000 0x100000>;
> +                        reg = <0x00 0x1700000 0x0 0x100000>;
> +                        interrupts = <0 75 0x4>;
> +	}
> +
> +=====================================================================
> +Job Ring (JR) Node
> +
> +    Child of the crypto node defines data processing interface to SEC 5
> +    across the peripheral bus for purposes of processing
> +    cryptographic descriptors. The specified address
> +    range can be made visible to one (or more) cores.
> +    The interrupt defined for this node is controlled within
> +    the address range of this node.
> +
> +  - compatible
> +      Usage: required
> +      Value type: <string>
> +      Definition: Must include "fsl,sec-v5.4-job-ring".
> +
> +  - reg
> +      Usage: required
> +      Value type: <prop-encoded-array>
> +      Definition: Specifies a two JR parameters:  an offset from
> +           the parent physical address and the length the JR registers.
> +
> +   - interrupts
> +      Usage: required
> +      Value type: <prop_encoded-array>
> +      Definition:  Specifies the interrupts generated by this
> +           device.  The value of the interrupts property
> +           consists of one interrupt specifier. The format
> +           of the specifier is defined by the binding document
> +           describing the node's interrupt parent.
> +
> +EXAMPLE
> +	sec_jr0: jr@10000 {
> +		compatible = "fsl,sec-v5.4-job-ring",
> +			"fsl,sec-v5.0-job-ring",
> +			"fsl,sec-v4.0-job-ring";
> +			reg = <0x10000 0x10000>;
> +			interrupts = <0 71 0x4>;
> +	};
> +
> +===================================================================
> +Full Example
> +
> +Since some chips may contain more than one SEC, the dtsi contains
> +only the node contents, not the node itself.  A chip using the SEC
> +should include the dtsi inside each SEC node.  Example:
> +
> +In fsl-ls1012a.dtsi:
> +
> +	compatible = "fsl,sec-v5.4";
> +	fsl,sec-era = <8>;
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	sec_jr0: jr@10000 {
> +		compatible = "fsl,sec-v5.4-job-ring",
> +			"fsl,sec-v5.0-job-ring",
> +			"fsl,sec-v4.0-job-ring";
> +			reg = <0x10000 0x10000>;
> +			interrupts = <0 71 0x4>;
> +	};
> +	sec_jr1: jr@20000 {
> +		compatible = "fsl,sec-v5.4-job-ring",
> +			"fsl,sec-v5.0-job-ring",
> +			"fsl,sec-v4.0-job-ring";
> +			reg = <0x20000 0x10000>;
> +			interrupts = <0 72 0x4>;
> +	};
> +	sec_jr2: jr@30000 {
> +		compatible = "fsl,sec-v5.4-job-ring",
> +			"fsl,sec-v5.0-job-ring",
> +			"fsl,sec-v4.0-job-ring";
> +			reg = <0x30000 0x10000>;
> +			interrupts = <0 73 0x4>;
> +	};
> +	sec_jr3: jr@40000 {
> +		compatible = "fsl,sec-v5.4-job-ring",
> +			"fsl,sec-v5.0-job-ring",
> +			"fsl,sec-v4.0-job-ring";
> +			reg = <0x40000 0x10000>;
> +			interrupts = <0 74 0x4>;
> +	};
> 

[linux-devel] [PATCH 10/10] dt-bindings: sec: Update bindings for LS1012A

[Horia Geanta Neag]

On 8/26/2016 6:36 PM, Bhaskar Upadhaya wrote:
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
> ---
>  .../devicetree/bindings/crypto/fsl-sec5.txt        | 153 +++++++++++++++++++++
>  1 file changed, 153 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec5.txt
> 
> diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec5.txt b/Documentation/devicetree/bindings/crypto/fsl-sec5.txt
> new file mode 100644
> index 0000000..7bcaa6f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/crypto/fsl-sec5.txt
> @@ -0,0 +1,153 @@
> +SEC 5 is Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
> +Currently Freescale arm chip LS1012A is embedded with SEC 5.
This sounds like LS1012A is the only platform with SEC5, which is far
from the truth.

> +SEC 5 device tree binding include:
> +   -SEC 5 Node
> +   -Job Ring Node
> +   -Full Example
> +
> +=====================================================================
> +SEC 5 Node
> +
> +Description
> +
> +    Node defines the base address of the SEC 5 block.
> +    This block specifies the address range of all global
> +    configuration registers for the SEC 5 block.
> +    For example, In LS1012A, we could see three SEC 5 node.
There's only one SEC / CAAM crypto engine, thus only one node.
Copy & paste typo from SEC6 binding?

> +
> +PROPERTIES
> +
> +   - compatible
> +      Usage: required
> +      Value type: <string>
> +      Definition: Must include "fsl,sec-v5.4".
Since you are adding a binding for SEC5, make sure you are accounting
for already-existing trees that are using "fsl,sec-v5.0",
"fsl,sec-v5.2", "fsl,sec-v5.3".
See SoCs in arch/powerpc/boot/dts/fsl/

> +
> +   - fsl,sec-era
> +      Usage: optional
> +      Value type: <u32>
> +      Definition: A standard property. Define the 'ERA' of the SEC
> +          device.
> +
> +   - #address-cells
> +       Usage: required
> +       Value type: <u32>
> +       Definition: A standard property.  Defines the number of cells
> +           for representing physical addresses in child nodes.
> +
> +   - #size-cells
> +       Usage: required
> +       Value type: <u32>
> +       Definition: A standard property.  Defines the number of cells
> +           for representing the size of physical addresses in
> +           child nodes.
> +
> +   - reg
> +      Usage: required
> +      Value type: <prop-encoded-array>
> +      Definition: A standard property.  Specifies the physical
> +          address and length of the SEC 5 configuration registers.
> +
> +   - ranges
> +       Usage: required
> +       Value type: <prop-encoded-array>
> +       Definition: A standard property.  Specifies the physical address
> +           range of the SEC 5.0 register space (-SNVS not included).  A
> +           triplet that includes the child address, parent address, &
> +           length.
> +
> +   Note: All other standard properties (see the ePAPR) are allowed
> +   but are optional.
> +
> +EXAMPLE
> +	crypto: crypto at 1700000 {
> +                        compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
> +                                     "fsl,sec-v4.0";
> +                        fsl,sec-era = <8>;
> +                        #address-cells = <1>;
> +                        #size-cells = <1>;
> +                        ranges = <0x0 0x00 0x1700000 0x100000>;
> +                        reg = <0x00 0x1700000 0x0 0x100000>;
> +                        interrupts = <0 75 0x4>;
> +	}
> +
> +=====================================================================
> +Job Ring (JR) Node
> +
> +    Child of the crypto node defines data processing interface to SEC 5
> +    across the peripheral bus for purposes of processing
> +    cryptographic descriptors. The specified address
> +    range can be made visible to one (or more) cores.
> +    The interrupt defined for this node is controlled within
> +    the address range of this node.
> +
> +  - compatible
> +      Usage: required
> +      Value type: <string>
> +      Definition: Must include "fsl,sec-v5.4-job-ring".
> +
> +  - reg
> +      Usage: required
> +      Value type: <prop-encoded-array>
> +      Definition: Specifies a two JR parameters:  an offset from
> +           the parent physical address and the length the JR registers.
> +
> +   - interrupts
> +      Usage: required
> +      Value type: <prop_encoded-array>
> +      Definition:  Specifies the interrupts generated by this
> +           device.  The value of the interrupts property
> +           consists of one interrupt specifier. The format
> +           of the specifier is defined by the binding document
> +           describing the node's interrupt parent.
> +
> +EXAMPLE
> +	sec_jr0: jr at 10000 {
> +		compatible = "fsl,sec-v5.4-job-ring",
> +			"fsl,sec-v5.0-job-ring",
> +			"fsl,sec-v4.0-job-ring";
> +			reg = <0x10000 0x10000>;
> +			interrupts = <0 71 0x4>;
> +	};
> +
> +===================================================================
> +Full Example
> +
> +Since some chips may contain more than one SEC, the dtsi contains
> +only the node contents, not the node itself.  A chip using the SEC
> +should include the dtsi inside each SEC node.  Example:
> +
> +In fsl-ls1012a.dtsi:
> +
> +	compatible = "fsl,sec-v5.4";
> +	fsl,sec-era = <8>;
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	sec_jr0: jr at 10000 {
> +		compatible = "fsl,sec-v5.4-job-ring",
> +			"fsl,sec-v5.0-job-ring",
> +			"fsl,sec-v4.0-job-ring";
> +			reg = <0x10000 0x10000>;
> +			interrupts = <0 71 0x4>;
> +	};
> +	sec_jr1: jr at 20000 {
> +		compatible = "fsl,sec-v5.4-job-ring",
> +			"fsl,sec-v5.0-job-ring",
> +			"fsl,sec-v4.0-job-ring";
> +			reg = <0x20000 0x10000>;
> +			interrupts = <0 72 0x4>;
> +	};
> +	sec_jr2: jr at 30000 {
> +		compatible = "fsl,sec-v5.4-job-ring",
> +			"fsl,sec-v5.0-job-ring",
> +			"fsl,sec-v4.0-job-ring";
> +			reg = <0x30000 0x10000>;
> +			interrupts = <0 73 0x4>;
> +	};
> +	sec_jr3: jr at 40000 {
> +		compatible = "fsl,sec-v5.4-job-ring",
> +			"fsl,sec-v5.0-job-ring",
> +			"fsl,sec-v4.0-job-ring";
> +			reg = <0x40000 0x10000>;
> +			interrupts = <0 74 0x4>;
> +	};
>