From: Bjorn Helgaas <helgaas@kernel.org> To: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> Cc: robh@kernel.org, bhelgaas@google.com, colin.king@canonical.com, soren.brinkmann@xilinx.com, marc.zyngier@arm.com, michal.simek@xilinx.com, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, rgummal@xilinx.com, Bharat Kumar Gogada <bharatku@xilinx.com> Subject: Re: [PATCH 1/3] PCI: Xilinx NWL PCIe: Expanding PCIe core errors and printing event occurred. Date: Tue, 13 Sep 2016 10:18:05 -0500 [thread overview] Message-ID: <20160913151805.GD27748@localhost> (raw) In-Reply-To: <1472553558-27215-1-git-send-email-bharatku@xilinx.com> On Tue, Aug 30, 2016 at 04:09:16PM +0530, Bharat Kumar Gogada wrote: > The current driver prints pcie core error, for all core events. > Instead of just printing PCIe core error, now adding prints to show > individual core events occurred. > > Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> I applied the first two patches to pci/host-xilinx for v4.9, thanks! I'd like to work on the third one a little more, as I mentioned in my response to it. > --- > drivers/pci/host/pcie-xilinx-nwl.c | 48 +++++++++++++++++++++++++++++++------- > 1 file changed, 40 insertions(+), 8 deletions(-) > > diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c > index 3479d30..86c1834 100644 > --- a/drivers/pci/host/pcie-xilinx-nwl.c > +++ b/drivers/pci/host/pcie-xilinx-nwl.c > @@ -85,10 +85,15 @@ > #define MSGF_MISC_SR_MASTER_ERR BIT(5) > #define MSGF_MISC_SR_I_ADDR_ERR BIT(6) > #define MSGF_MISC_SR_E_ADDR_ERR BIT(7) > -#define MSGF_MISC_SR_UR_DETECT BIT(20) > - > -#define MSGF_MISC_SR_PCIE_CORE GENMASK(18, 16) > -#define MSGF_MISC_SR_PCIE_CORE_ERR GENMASK(31, 22) > +#define MSGF_MISC_SR_FATAL_AER BIT(16) > +#define MSGF_MISC_SR_NON_FATAL_AER BIT(17) > +#define MSGF_MISC_SR_CORR_AER BIT(18) > +#define MSGF_MISC_SR_UR_DETECT BIT(20) > +#define MSGF_MISC_SR_NON_FATAL_DEV BIT(22) > +#define MSGF_MISC_SR_FATAL_DEV BIT(23) > +#define MSGF_MISC_SR_LINK_DOWN BIT(24) > +#define MSGF_MSIC_SR_LINK_AUTO_BWIDTH BIT(25) > +#define MSGF_MSIC_SR_LINK_BWIDTH BIT(26) > > #define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \ > MSGF_MISC_SR_RXMSG_OVER | \ > @@ -96,9 +101,15 @@ > MSGF_MISC_SR_MASTER_ERR | \ > MSGF_MISC_SR_I_ADDR_ERR | \ > MSGF_MISC_SR_E_ADDR_ERR | \ > + MSGF_MISC_SR_FATAL_AER | \ > + MSGF_MISC_SR_NON_FATAL_AER | \ > + MSGF_MISC_SR_CORR_AER | \ > MSGF_MISC_SR_UR_DETECT | \ > - MSGF_MISC_SR_PCIE_CORE | \ > - MSGF_MISC_SR_PCIE_CORE_ERR) > + MSGF_MISC_SR_NON_FATAL_DEV | \ > + MSGF_MISC_SR_FATAL_DEV | \ > + MSGF_MISC_SR_LINK_DOWN | \ > + MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \ > + MSGF_MSIC_SR_LINK_BWIDTH) > > /* Legacy interrupt status mask bits */ > #define MSGF_LEG_SR_INTA BIT(0) > @@ -291,8 +302,29 @@ static irqreturn_t nwl_pcie_misc_handler(int irq, void *data) > dev_err(pcie->dev, > "In Misc Egress address translation error\n"); > > - if (misc_stat & MSGF_MISC_SR_PCIE_CORE_ERR) > - dev_err(pcie->dev, "PCIe Core error\n"); > + if (misc_stat & MSGF_MISC_SR_FATAL_AER) > + dev_err(pcie->dev, "Fatal Error in AER Capability\n"); > + > + if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER) > + dev_err(pcie->dev, "Non-Fatal Error in AER Capability\n"); > + > + if (misc_stat & MSGF_MISC_SR_CORR_AER) > + dev_err(pcie->dev, "Correctable Error in AER Capability\n"); > + > + if (misc_stat & MSGF_MISC_SR_UR_DETECT) > + dev_err(pcie->dev, "Unsupported request Detected\n"); > + > + if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV) > + dev_err(pcie->dev, "Non-Fatal Error Detected\n"); > + > + if (misc_stat & MSGF_MISC_SR_FATAL_DEV) > + dev_err(pcie->dev, "Fatal Error Detected\n"); > + > + if (misc_stat & MSGF_MSIC_SR_LINK_AUTO_BWIDTH) > + dev_info(pcie->dev, "Link Autonomous Bandwidth Management Status bit set\n"); > + > + if (misc_stat & MSGF_MSIC_SR_LINK_BWIDTH) > + dev_info(pcie->dev, "Link Bandwidth Management Status bit set\n"); > > /* Clear misc interrupt status */ > nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS); > -- > 2.1.1 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-pci" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html
WARNING: multiple messages have this Message-ID (diff)
From: helgaas@kernel.org (Bjorn Helgaas) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/3] PCI: Xilinx NWL PCIe: Expanding PCIe core errors and printing event occurred. Date: Tue, 13 Sep 2016 10:18:05 -0500 [thread overview] Message-ID: <20160913151805.GD27748@localhost> (raw) In-Reply-To: <1472553558-27215-1-git-send-email-bharatku@xilinx.com> On Tue, Aug 30, 2016 at 04:09:16PM +0530, Bharat Kumar Gogada wrote: > The current driver prints pcie core error, for all core events. > Instead of just printing PCIe core error, now adding prints to show > individual core events occurred. > > Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> I applied the first two patches to pci/host-xilinx for v4.9, thanks! I'd like to work on the third one a little more, as I mentioned in my response to it. > --- > drivers/pci/host/pcie-xilinx-nwl.c | 48 +++++++++++++++++++++++++++++++------- > 1 file changed, 40 insertions(+), 8 deletions(-) > > diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c > index 3479d30..86c1834 100644 > --- a/drivers/pci/host/pcie-xilinx-nwl.c > +++ b/drivers/pci/host/pcie-xilinx-nwl.c > @@ -85,10 +85,15 @@ > #define MSGF_MISC_SR_MASTER_ERR BIT(5) > #define MSGF_MISC_SR_I_ADDR_ERR BIT(6) > #define MSGF_MISC_SR_E_ADDR_ERR BIT(7) > -#define MSGF_MISC_SR_UR_DETECT BIT(20) > - > -#define MSGF_MISC_SR_PCIE_CORE GENMASK(18, 16) > -#define MSGF_MISC_SR_PCIE_CORE_ERR GENMASK(31, 22) > +#define MSGF_MISC_SR_FATAL_AER BIT(16) > +#define MSGF_MISC_SR_NON_FATAL_AER BIT(17) > +#define MSGF_MISC_SR_CORR_AER BIT(18) > +#define MSGF_MISC_SR_UR_DETECT BIT(20) > +#define MSGF_MISC_SR_NON_FATAL_DEV BIT(22) > +#define MSGF_MISC_SR_FATAL_DEV BIT(23) > +#define MSGF_MISC_SR_LINK_DOWN BIT(24) > +#define MSGF_MSIC_SR_LINK_AUTO_BWIDTH BIT(25) > +#define MSGF_MSIC_SR_LINK_BWIDTH BIT(26) > > #define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \ > MSGF_MISC_SR_RXMSG_OVER | \ > @@ -96,9 +101,15 @@ > MSGF_MISC_SR_MASTER_ERR | \ > MSGF_MISC_SR_I_ADDR_ERR | \ > MSGF_MISC_SR_E_ADDR_ERR | \ > + MSGF_MISC_SR_FATAL_AER | \ > + MSGF_MISC_SR_NON_FATAL_AER | \ > + MSGF_MISC_SR_CORR_AER | \ > MSGF_MISC_SR_UR_DETECT | \ > - MSGF_MISC_SR_PCIE_CORE | \ > - MSGF_MISC_SR_PCIE_CORE_ERR) > + MSGF_MISC_SR_NON_FATAL_DEV | \ > + MSGF_MISC_SR_FATAL_DEV | \ > + MSGF_MISC_SR_LINK_DOWN | \ > + MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \ > + MSGF_MSIC_SR_LINK_BWIDTH) > > /* Legacy interrupt status mask bits */ > #define MSGF_LEG_SR_INTA BIT(0) > @@ -291,8 +302,29 @@ static irqreturn_t nwl_pcie_misc_handler(int irq, void *data) > dev_err(pcie->dev, > "In Misc Egress address translation error\n"); > > - if (misc_stat & MSGF_MISC_SR_PCIE_CORE_ERR) > - dev_err(pcie->dev, "PCIe Core error\n"); > + if (misc_stat & MSGF_MISC_SR_FATAL_AER) > + dev_err(pcie->dev, "Fatal Error in AER Capability\n"); > + > + if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER) > + dev_err(pcie->dev, "Non-Fatal Error in AER Capability\n"); > + > + if (misc_stat & MSGF_MISC_SR_CORR_AER) > + dev_err(pcie->dev, "Correctable Error in AER Capability\n"); > + > + if (misc_stat & MSGF_MISC_SR_UR_DETECT) > + dev_err(pcie->dev, "Unsupported request Detected\n"); > + > + if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV) > + dev_err(pcie->dev, "Non-Fatal Error Detected\n"); > + > + if (misc_stat & MSGF_MISC_SR_FATAL_DEV) > + dev_err(pcie->dev, "Fatal Error Detected\n"); > + > + if (misc_stat & MSGF_MSIC_SR_LINK_AUTO_BWIDTH) > + dev_info(pcie->dev, "Link Autonomous Bandwidth Management Status bit set\n"); > + > + if (misc_stat & MSGF_MSIC_SR_LINK_BWIDTH) > + dev_info(pcie->dev, "Link Bandwidth Management Status bit set\n"); > > /* Clear misc interrupt status */ > nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS); > -- > 2.1.1 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-pci" in > the body of a message to majordomo at vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html
next prev parent reply other threads:[~2016-09-13 15:18 UTC|newest] Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-08-30 10:39 [PATCH 1/3] PCI: Xilinx NWL PCIe: Expanding PCIe core errors and printing event occurred Bharat Kumar Gogada 2016-08-30 10:39 ` Bharat Kumar Gogada 2016-08-30 10:39 ` [PATCH 2/3] PCI: Xilinx NWL PCIe: Enabling all MSI interrupts using MSI mask Bharat Kumar Gogada 2016-08-30 10:39 ` Bharat Kumar Gogada 2016-08-30 10:39 ` Bharat Kumar Gogada 2016-08-30 10:39 ` [PATCH 3/3] PCI: Xilinx NWL PCIe: Fix Error for multi function device for legacy interrupts Bharat Kumar Gogada 2016-08-30 10:39 ` Bharat Kumar Gogada 2016-08-30 12:17 ` Marc Zyngier 2016-08-30 12:17 ` Marc Zyngier 2016-08-30 14:13 ` Bharat Kumar Gogada 2016-08-30 14:13 ` Bharat Kumar Gogada 2016-08-30 14:13 ` Bharat Kumar Gogada 2016-08-30 15:02 ` Marc Zyngier 2016-08-30 15:02 ` Marc Zyngier 2016-08-30 15:02 ` Marc Zyngier 2016-08-31 9:56 ` Bharat Kumar Gogada 2016-08-31 9:56 ` Bharat Kumar Gogada 2016-08-31 9:56 ` Bharat Kumar Gogada 2016-08-31 10:56 ` Marc Zyngier 2016-08-31 10:56 ` Marc Zyngier 2016-08-31 10:56 ` Marc Zyngier 2016-09-01 5:19 ` Bharat Kumar Gogada 2016-09-01 5:19 ` Bharat Kumar Gogada 2016-09-01 5:19 ` Bharat Kumar Gogada 2016-09-12 22:02 ` Bjorn Helgaas 2016-09-12 22:02 ` Bjorn Helgaas 2016-09-12 22:02 ` Bjorn Helgaas 2016-09-13 7:41 ` Marc Zyngier 2016-09-13 7:41 ` Marc Zyngier 2016-09-13 7:41 ` Marc Zyngier 2016-09-13 15:05 ` Bjorn Helgaas 2016-09-13 15:05 ` Bjorn Helgaas 2016-09-13 15:05 ` Bjorn Helgaas 2016-09-13 15:34 ` Bjorn Helgaas 2016-09-13 15:34 ` Bjorn Helgaas 2016-09-13 15:34 ` Bjorn Helgaas 2016-09-13 15:50 ` Thomas Petazzoni 2016-09-13 15:50 ` Thomas Petazzoni 2016-09-13 15:50 ` Thomas Petazzoni 2016-09-14 5:34 ` Bharat Kumar Gogada 2016-09-14 5:34 ` Bharat Kumar Gogada 2016-09-14 5:34 ` Bharat Kumar Gogada 2016-09-14 9:55 ` Kishon Vijay Abraham I 2016-09-14 9:55 ` Kishon Vijay Abraham I 2016-09-14 9:55 ` Kishon Vijay Abraham I 2017-03-02 8:46 ` Bharat Kumar Gogada 2017-03-02 8:46 ` Bharat Kumar Gogada 2017-03-02 8:46 ` Bharat Kumar Gogada 2016-09-13 14:32 ` [PATCH 1/3] PCI: Xilinx NWL PCIe: Expanding PCIe core errors and printing event occurred Bjorn Helgaas 2016-09-13 14:32 ` Bjorn Helgaas 2016-09-14 5:26 ` Bharat Kumar Gogada 2016-09-14 5:26 ` Bharat Kumar Gogada 2016-09-14 5:26 ` Bharat Kumar Gogada 2016-09-13 15:18 ` Bjorn Helgaas [this message] 2016-09-13 15:18 ` Bjorn Helgaas 2016-09-14 5:28 ` Bharat Kumar Gogada 2016-09-14 5:28 ` Bharat Kumar Gogada 2016-09-14 5:28 ` Bharat Kumar Gogada
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20160913151805.GD27748@localhost \ --to=helgaas@kernel.org \ --cc=arnd@arndb.de \ --cc=bharat.kumar.gogada@xilinx.com \ --cc=bharatku@xilinx.com \ --cc=bhelgaas@google.com \ --cc=colin.king@canonical.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-pci@vger.kernel.org \ --cc=marc.zyngier@arm.com \ --cc=michal.simek@xilinx.com \ --cc=rgummal@xilinx.com \ --cc=robh@kernel.org \ --cc=soren.brinkmann@xilinx.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.