* [linux dev-4.7 1/3] pinctrl: aspeed: Add SPI pins to G5
@ 2016-09-15 11:13 Joel Stanley
2016-09-15 11:13 ` [linux dev-4.7 2/3] arm: dts: aspeed: Add spi1 pins to g5 device tree Joel Stanley
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Joel Stanley @ 2016-09-15 11:13 UTC (permalink / raw)
To: andrew; +Cc: openbmc
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 89 ++++++++++++++++++++++++++++++
1 file changed, 89 insertions(+)
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
index a0b1d4ee3b5e..6e5b90e62e99 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
@@ -140,6 +140,77 @@ MS_PIN_DECL(D21, GPIOD3, SD2DAT1, GPID1OUT);
FUNC_GROUP_DECL(GPID1, D20, D21);
+#define SYSSPI_DESC SIG_DESC_SET(HW_STRAP1, 13)
+
+#define C18 64
+SIG_EXPR_LIST_DECL_SINGLE(SYSCS, SYSSPI, COND1, SYSSPI_DESC);
+SS_PIN_DECL(C18, GPIOI0, SYSCS);
+
+#define E15 65
+SIG_EXPR_LIST_DECL_SINGLE(SYSCK, SYSSPI, COND1, SYSSPI_DESC);
+SS_PIN_DECL(E15, GPIOI1, SYSCK);
+
+#define B16 66
+SIG_EXPR_LIST_DECL_SINGLE(SYSMOSI, SYSSPI, COND1, SYSSPI_DESC);
+SS_PIN_DECL(B16, GPIOI2, SYSMOSI);
+
+#define C16 67
+SIG_EXPR_LIST_DECL_SINGLE(SYSMISO, SYSSPI, COND1, SYSSPI_DESC);
+SS_PIN_DECL(C16, GPIOI3, SYSMISO);
+
+FUNC_GROUP_DECL(SYSSPI, C18, E15, B16, C16);
+
+#define SPI1_MASTER_DESC { HW_STRAP1, GENMASK(13, 12), 1, 0 }
+#define SPI1_DEBUG_DESC { HW_STRAP1, GENMASK(13, 12), 2, 0 }
+#define SPI1_PASSTHRU_DESC { HW_STRAP1, GENMASK(13, 12), 3, 0 }
+
+#define VB_DESC SIG_DESC_SET(HW_STRAP1, 5)
+
+#define B15 68
+SIG_EXPR_DECL(SPI1CS0, SPI1_MASTER, COND1, SPI1_MASTER_DESC);
+SIG_EXPR_DECL(SPI1CS0, SPI1_DEBUG, COND1, SPI1_DEBUG_DESC);
+SIG_EXPR_DECL(SPI1CS0, SPI1_PASSTHRU, COND1, SPI1_PASSTHRU_DESC);
+SIG_EXPR_LIST_DECL(SPI1CS0, SIG_EXPR_PTR(SPI1CS0, SPI1_MASTER),
+ SIG_EXPR_PTR(SPI1CS0, SPI1_DEBUG),
+ SIG_EXPR_PTR(SPI1CS0, SPI1_PASSTHRU));
+SIG_EXPR_LIST_DECL_SINGLE(VBCS, VGABIOS_ROM, COND1, VB_DESC);
+MS_PIN_DECL(B15, GPIOI4, SPI1CS0, VBCS);
+
+#define C15 69
+SIG_EXPR_DECL(SPI1CK, SPI1_MASTER, COND1, SPI1_MASTER_DESC);
+SIG_EXPR_DECL(SPI1CK, SPI1_DEBUG, COND1, SPI1_DEBUG_DESC);
+SIG_EXPR_DECL(SPI1CK, SPI1_PASSTHRU, COND1, SPI1_PASSTHRU_DESC);
+SIG_EXPR_LIST_DECL(SPI1CK, SIG_EXPR_PTR(SPI1CK, SPI1_MASTER),
+ SIG_EXPR_PTR(SPI1CK, SPI1_DEBUG),
+ SIG_EXPR_PTR(SPI1CK, SPI1_PASSTHRU));
+SIG_EXPR_LIST_DECL_SINGLE(VBCK, VGABIOS_ROM, COND1, VB_DESC);
+MS_PIN_DECL(C15, GPIOI5, SPI1CK, VBCK);
+
+#define A14 70
+SIG_EXPR_DECL(SPI1MOSI, SPI1_MASTER, COND1, SPI1_MASTER_DESC);
+SIG_EXPR_DECL(SPI1MOSI, SPI1_DEBUG, COND1, SPI1_DEBUG_DESC);
+SIG_EXPR_DECL(SPI1MOSI, SPI1_PASSTHRU, COND1, SPI1_PASSTHRU_DESC);
+SIG_EXPR_LIST_DECL(SPI1MOSI, SIG_EXPR_PTR(SPI1MOSI, SPI1_MASTER),
+ SIG_EXPR_PTR(SPI1MOSI, SPI1_DEBUG),
+ SIG_EXPR_PTR(SPI1MOSI, SPI1_PASSTHRU));
+SIG_EXPR_LIST_DECL_SINGLE(VBMOSI, VGABIOS_ROM, COND1, VB_DESC);
+MS_PIN_DECL(A14, GPIOI6, SPI1MOSI, VBMOSI);
+
+#define A15 71
+SIG_EXPR_DECL(SPI1MISO, SPI1_MASTER, COND1, SPI1_MASTER_DESC);
+SIG_EXPR_DECL(SPI1MISO, SPI1_DEBUG, COND1, SPI1_DEBUG_DESC);
+SIG_EXPR_DECL(SPI1MISO, SPI1_PASSTHRU, COND1, SPI1_PASSTHRU_DESC);
+SIG_EXPR_LIST_DECL(SPI1MISO, SIG_EXPR_PTR(SPI1MISO, SPI1_MASTER),
+ SIG_EXPR_PTR(SPI1MISO, SPI1_DEBUG),
+ SIG_EXPR_PTR(SPI1MISO, SPI1_PASSTHRU));
+SIG_EXPR_LIST_DECL_SINGLE(VBMISO, VGABIOS_ROM, COND1, VB_DESC);
+MS_PIN_DECL(A15, GPIOI7, SPI1MISO, VBMISO);
+
+FUNC_GROUP_DECL(SPI1_MASTER, B15, C15, A14, A15);
+FUNC_GROUP_DECL(SPI1_DEBUG, B15, C15, A14, A15);
+FUNC_GROUP_DECL(SPI1_PASSTHRU, B15, C15, A14, A15);
+FUNC_GROUP_DECL(VGABIOS_ROM, B15, C15, A14, A15);
+
#define I2C5_DESC SIG_DESC_SET(SCU90, 18)
#define L3 80
@@ -492,6 +563,8 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
ASPEED_PINCTRL_PIN(A11),
ASPEED_PINCTRL_PIN(A12),
ASPEED_PINCTRL_PIN(A13),
+ ASPEED_PINCTRL_PIN(A14),
+ ASPEED_PINCTRL_PIN(A15),
ASPEED_PINCTRL_PIN(A2),
ASPEED_PINCTRL_PIN(A3),
ASPEED_PINCTRL_PIN(A4),
@@ -501,6 +574,8 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
ASPEED_PINCTRL_PIN(B1),
ASPEED_PINCTRL_PIN(B11),
ASPEED_PINCTRL_PIN(B12),
+ ASPEED_PINCTRL_PIN(B15),
+ ASPEED_PINCTRL_PIN(B16),
ASPEED_PINCTRL_PIN(B2),
ASPEED_PINCTRL_PIN(B3),
ASPEED_PINCTRL_PIN(B4),
@@ -510,6 +585,9 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
ASPEED_PINCTRL_PIN(C11),
ASPEED_PINCTRL_PIN(C12),
ASPEED_PINCTRL_PIN(C14),
+ ASPEED_PINCTRL_PIN(C15),
+ ASPEED_PINCTRL_PIN(C16),
+ ASPEED_PINCTRL_PIN(C18),
ASPEED_PINCTRL_PIN(C2),
ASPEED_PINCTRL_PIN(C3),
ASPEED_PINCTRL_PIN(C4),
@@ -527,6 +605,7 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
ASPEED_PINCTRL_PIN(D9),
ASPEED_PINCTRL_PIN(E10),
ASPEED_PINCTRL_PIN(E12),
+ ASPEED_PINCTRL_PIN(E15),
ASPEED_PINCTRL_PIN(E21),
ASPEED_PINCTRL_PIN(E6),
ASPEED_PINCTRL_PIN(E7),
@@ -581,6 +660,11 @@ static const struct aspeed_pin_group aspeed_g5_groups[] = {
ASPEED_PINCTRL_GROUP(RGMII1),
ASPEED_PINCTRL_GROUP(RMII2),
ASPEED_PINCTRL_GROUP(RGMII2),
+ ASPEED_PINCTRL_GROUP(SPI1_MASTER),
+ ASPEED_PINCTRL_GROUP(SPI1_DEBUG),
+ ASPEED_PINCTRL_GROUP(SPI1_PASSTHRU),
+ ASPEED_PINCTRL_GROUP(VGABIOS_ROM),
+ ASPEED_PINCTRL_GROUP(SYSSPI),
};
static const struct aspeed_pin_function aspeed_g5_functions[] = {
@@ -612,6 +696,11 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = {
ASPEED_PINCTRL_FUNC(RGMII1),
ASPEED_PINCTRL_FUNC(RMII2),
ASPEED_PINCTRL_FUNC(RGMII2),
+ ASPEED_PINCTRL_FUNC(SPI1_MASTER),
+ ASPEED_PINCTRL_FUNC(SPI1_DEBUG),
+ ASPEED_PINCTRL_FUNC(SPI1_PASSTHRU),
+ ASPEED_PINCTRL_FUNC(VGABIOS_ROM),
+ ASPEED_PINCTRL_FUNC(SYSSPI),
};
static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = {
--
2.9.3
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [linux dev-4.7 2/3] arm: dts: aspeed: Add spi1 pins to g5 device tree
2016-09-15 11:13 [linux dev-4.7 1/3] pinctrl: aspeed: Add SPI pins to G5 Joel Stanley
@ 2016-09-15 11:13 ` Joel Stanley
2016-09-16 0:31 ` Andrew Jeffery
2016-09-15 11:13 ` [linux dev-4.7 3/3] arm: dts: aspeed: Add SPI1 master pinmux hog to g5 machines Joel Stanley
2016-09-16 0:28 ` [linux dev-4.7 1/3] pinctrl: aspeed: Add SPI pins to G5 Andrew Jeffery
2 siblings, 1 reply; 8+ messages in thread
From: Joel Stanley @ 2016-09-15 11:13 UTC (permalink / raw)
To: andrew; +Cc: openbmc
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/aspeed-g5.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index f73a2b18e152..e4e43ae3616a 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -201,6 +201,17 @@
function = "RMII2";
groups = "RMII2";
};
+
+ pinctrl_spi1_master_default: spi1_master_default {
+ function = "SPI1_MASTER";
+ groups = "SPI1_MASTER";
+ };
+
+ pinctrl_spi1_passthru_default: spi1_passthru_default {
+ function = "SPI1_PASSTHRU";
+ groups = "SPI1_PASSTHRU";
+ };
+
};
};
--
2.9.3
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [linux dev-4.7 3/3] arm: dts: aspeed: Add SPI1 master pinmux hog to g5 machines
2016-09-15 11:13 [linux dev-4.7 1/3] pinctrl: aspeed: Add SPI pins to G5 Joel Stanley
2016-09-15 11:13 ` [linux dev-4.7 2/3] arm: dts: aspeed: Add spi1 pins to g5 device tree Joel Stanley
@ 2016-09-15 11:13 ` Joel Stanley
2016-09-16 0:39 ` Andrew Jeffery
2016-09-16 0:28 ` [linux dev-4.7 1/3] pinctrl: aspeed: Add SPI pins to G5 Andrew Jeffery
2 siblings, 1 reply; 8+ messages in thread
From: Joel Stanley @ 2016-09-15 11:13 UTC (permalink / raw)
To: andrew; +Cc: openbmc
This is for reuqired for using the PNOR on ast2500 based systems.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
arch/arm/boot/dts/aspeed-ast2500-evb.dts | 5 +++++
arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 5 +++++
2 files changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
index d34e6f15a0cb..a517b4a595b8 100644
--- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
@@ -35,6 +35,11 @@
};
};
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_master_default>;
+};
+
&uart5 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
index fcc880a80ee0..d7db9700172f 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
@@ -36,6 +36,11 @@
};
};
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_master_default>;
+};
+
&uart5 {
status = "okay";
};
--
2.9.3
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [linux dev-4.7 1/3] pinctrl: aspeed: Add SPI pins to G5
2016-09-15 11:13 [linux dev-4.7 1/3] pinctrl: aspeed: Add SPI pins to G5 Joel Stanley
2016-09-15 11:13 ` [linux dev-4.7 2/3] arm: dts: aspeed: Add spi1 pins to g5 device tree Joel Stanley
2016-09-15 11:13 ` [linux dev-4.7 3/3] arm: dts: aspeed: Add SPI1 master pinmux hog to g5 machines Joel Stanley
@ 2016-09-16 0:28 ` Andrew Jeffery
2 siblings, 0 replies; 8+ messages in thread
From: Andrew Jeffery @ 2016-09-16 0:28 UTC (permalink / raw)
To: Joel Stanley; +Cc: openbmc
[-- Attachment #1: Type: text/plain, Size: 6184 bytes --]
On Thu, 2016-09-15 at 20:43 +0930, Joel Stanley wrote:
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
> ---
> drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 89 ++++++++++++++++++++++++++++++
> 1 file changed, 89 insertions(+)
>
> diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
> index a0b1d4ee3b5e..6e5b90e62e99 100644
> --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
> +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
> @@ -140,6 +140,77 @@ MS_PIN_DECL(D21, GPIOD3, SD2DAT1, GPID1OUT);
>
> FUNC_GROUP_DECL(GPID1, D20, D21);
>
> +#define SYSSPI_DESC SIG_DESC_SET(HW_STRAP1, 13)
> +
> +#define C18 64
> +SIG_EXPR_LIST_DECL_SINGLE(SYSCS, SYSSPI, COND1, SYSSPI_DESC);
> +SS_PIN_DECL(C18, GPIOI0, SYSCS);
> +
> +#define E15 65
> +SIG_EXPR_LIST_DECL_SINGLE(SYSCK, SYSSPI, COND1, SYSSPI_DESC);
> +SS_PIN_DECL(E15, GPIOI1, SYSCK);
> +
> +#define B16 66
> +SIG_EXPR_LIST_DECL_SINGLE(SYSMOSI, SYSSPI, COND1, SYSSPI_DESC);
> +SS_PIN_DECL(B16, GPIOI2, SYSMOSI);
> +
> +#define C16 67
> +SIG_EXPR_LIST_DECL_SINGLE(SYSMISO, SYSSPI, COND1, SYSSPI_DESC);
> +SS_PIN_DECL(C16, GPIOI3, SYSMISO);
> +
> +FUNC_GROUP_DECL(SYSSPI, C18, E15, B16, C16);
> +
> +#define SPI1_MASTER_DESC { HW_STRAP1, GENMASK(13, 12), 1, 0 }
> +#define SPI1_DEBUG_DESC { HW_STRAP1, GENMASK(13, 12), 2, 0 }
> +#define SPI1_PASSTHRU_DESC { HW_STRAP1, GENMASK(13, 12), 3, 0 }
> +
> +#define VB_DESC SIG_DESC_SET(HW_STRAP1, 5)
> +
> +#define B15 68
> +SIG_EXPR_DECL(SPI1CS0, SPI1_MASTER, COND1, SPI1_MASTER_DESC);
> +SIG_EXPR_DECL(SPI1CS0, SPI1_DEBUG, COND1, SPI1_DEBUG_DESC);
> +SIG_EXPR_DECL(SPI1CS0, SPI1_PASSTHRU, COND1, SPI1_PASSTHRU_DESC);
> +SIG_EXPR_LIST_DECL(SPI1CS0, SIG_EXPR_PTR(SPI1CS0, SPI1_MASTER),
> + SIG_EXPR_PTR(SPI1CS0, SPI1_DEBUG),
> + SIG_EXPR_PTR(SPI1CS0, SPI1_PASSTHRU));
> +SIG_EXPR_LIST_DECL_SINGLE(VBCS, VGABIOS_ROM, COND1, VB_DESC);
> +MS_PIN_DECL(B15, GPIOI4, SPI1CS0, VBCS);
> +
> +#define C15 69
> +SIG_EXPR_DECL(SPI1CK, SPI1_MASTER, COND1, SPI1_MASTER_DESC);
> +SIG_EXPR_DECL(SPI1CK, SPI1_DEBUG, COND1, SPI1_DEBUG_DESC);
> +SIG_EXPR_DECL(SPI1CK, SPI1_PASSTHRU, COND1, SPI1_PASSTHRU_DESC);
> +SIG_EXPR_LIST_DECL(SPI1CK, SIG_EXPR_PTR(SPI1CK, SPI1_MASTER),
> + SIG_EXPR_PTR(SPI1CK, SPI1_DEBUG),
> + SIG_EXPR_PTR(SPI1CK, SPI1_PASSTHRU));
> +SIG_EXPR_LIST_DECL_SINGLE(VBCK, VGABIOS_ROM, COND1, VB_DESC);
> +MS_PIN_DECL(C15, GPIOI5, SPI1CK, VBCK);
> +
> +#define A14 70
> +SIG_EXPR_DECL(SPI1MOSI, SPI1_MASTER, COND1, SPI1_MASTER_DESC);
> +SIG_EXPR_DECL(SPI1MOSI, SPI1_DEBUG, COND1, SPI1_DEBUG_DESC);
> +SIG_EXPR_DECL(SPI1MOSI, SPI1_PASSTHRU, COND1, SPI1_PASSTHRU_DESC);
> +SIG_EXPR_LIST_DECL(SPI1MOSI, SIG_EXPR_PTR(SPI1MOSI, SPI1_MASTER),
> + SIG_EXPR_PTR(SPI1MOSI, SPI1_DEBUG),
> + SIG_EXPR_PTR(SPI1MOSI, SPI1_PASSTHRU));
> +SIG_EXPR_LIST_DECL_SINGLE(VBMOSI, VGABIOS_ROM, COND1, VB_DESC);
> +MS_PIN_DECL(A14, GPIOI6, SPI1MOSI, VBMOSI);
> +
> +#define A15 71
> +SIG_EXPR_DECL(SPI1MISO, SPI1_MASTER, COND1, SPI1_MASTER_DESC);
> +SIG_EXPR_DECL(SPI1MISO, SPI1_DEBUG, COND1, SPI1_DEBUG_DESC);
> +SIG_EXPR_DECL(SPI1MISO, SPI1_PASSTHRU, COND1, SPI1_PASSTHRU_DESC);
> +SIG_EXPR_LIST_DECL(SPI1MISO, SIG_EXPR_PTR(SPI1MISO, SPI1_MASTER),
> + SIG_EXPR_PTR(SPI1MISO, SPI1_DEBUG),
> + SIG_EXPR_PTR(SPI1MISO, SPI1_PASSTHRU));
> +SIG_EXPR_LIST_DECL_SINGLE(VBMISO, VGABIOS_ROM, COND1, VB_DESC);
> +MS_PIN_DECL(A15, GPIOI7, SPI1MISO, VBMISO);
> +
> +FUNC_GROUP_DECL(SPI1_MASTER, B15, C15, A14, A15);
> +FUNC_GROUP_DECL(SPI1_DEBUG, B15, C15, A14, A15);
> +FUNC_GROUP_DECL(SPI1_PASSTHRU, B15, C15, A14, A15);
> +FUNC_GROUP_DECL(VGABIOS_ROM, B15, C15, A14, A15);
> +
> #define I2C5_DESC SIG_DESC_SET(SCU90, 18)
>
> #define L3 80
> @@ -492,6 +563,8 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
> ASPEED_PINCTRL_PIN(A11),
> ASPEED_PINCTRL_PIN(A12),
> ASPEED_PINCTRL_PIN(A13),
> + ASPEED_PINCTRL_PIN(A14),
> + ASPEED_PINCTRL_PIN(A15),
> ASPEED_PINCTRL_PIN(A2),
> ASPEED_PINCTRL_PIN(A3),
> ASPEED_PINCTRL_PIN(A4),
> @@ -501,6 +574,8 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
> ASPEED_PINCTRL_PIN(B1),
> ASPEED_PINCTRL_PIN(B11),
> ASPEED_PINCTRL_PIN(B12),
> + ASPEED_PINCTRL_PIN(B15),
> + ASPEED_PINCTRL_PIN(B16),
> ASPEED_PINCTRL_PIN(B2),
> ASPEED_PINCTRL_PIN(B3),
> ASPEED_PINCTRL_PIN(B4),
> @@ -510,6 +585,9 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
> ASPEED_PINCTRL_PIN(C11),
> ASPEED_PINCTRL_PIN(C12),
> ASPEED_PINCTRL_PIN(C14),
> + ASPEED_PINCTRL_PIN(C15),
> + ASPEED_PINCTRL_PIN(C16),
> + ASPEED_PINCTRL_PIN(C18),
> ASPEED_PINCTRL_PIN(C2),
> ASPEED_PINCTRL_PIN(C3),
> ASPEED_PINCTRL_PIN(C4),
> @@ -527,6 +605,7 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
> ASPEED_PINCTRL_PIN(D9),
> ASPEED_PINCTRL_PIN(E10),
> ASPEED_PINCTRL_PIN(E12),
> + ASPEED_PINCTRL_PIN(E15),
> ASPEED_PINCTRL_PIN(E21),
> ASPEED_PINCTRL_PIN(E6),
> ASPEED_PINCTRL_PIN(E7),
> @@ -581,6 +660,11 @@ static const struct aspeed_pin_group aspeed_g5_groups[] = {
> ASPEED_PINCTRL_GROUP(RGMII1),
> ASPEED_PINCTRL_GROUP(RMII2),
> ASPEED_PINCTRL_GROUP(RGMII2),
> + ASPEED_PINCTRL_GROUP(SPI1_MASTER),
> + ASPEED_PINCTRL_GROUP(SPI1_DEBUG),
> + ASPEED_PINCTRL_GROUP(SPI1_PASSTHRU),
> + ASPEED_PINCTRL_GROUP(VGABIOS_ROM),
> + ASPEED_PINCTRL_GROUP(SYSSPI),
> };
>
> static const struct aspeed_pin_function aspeed_g5_functions[] = {
> @@ -612,6 +696,11 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = {
> ASPEED_PINCTRL_FUNC(RGMII1),
> ASPEED_PINCTRL_FUNC(RMII2),
> ASPEED_PINCTRL_FUNC(RGMII2),
> + ASPEED_PINCTRL_FUNC(SPI1_MASTER),
> + ASPEED_PINCTRL_FUNC(SPI1_DEBUG),
> + ASPEED_PINCTRL_FUNC(SPI1_PASSTHRU),
> + ASPEED_PINCTRL_FUNC(VGABIOS_ROM),
> + ASPEED_PINCTRL_FUNC(SYSSPI),
> };
>
> static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = {
[-- Attachment #2: This is a digitally signed message part --]
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [linux dev-4.7 2/3] arm: dts: aspeed: Add spi1 pins to g5 device tree
2016-09-15 11:13 ` [linux dev-4.7 2/3] arm: dts: aspeed: Add spi1 pins to g5 device tree Joel Stanley
@ 2016-09-16 0:31 ` Andrew Jeffery
0 siblings, 0 replies; 8+ messages in thread
From: Andrew Jeffery @ 2016-09-16 0:31 UTC (permalink / raw)
To: Joel Stanley; +Cc: openbmc
[-- Attachment #1: Type: text/plain, Size: 1008 bytes --]
On Thu, 2016-09-15 at 20:43 +0930, Joel Stanley wrote:
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> arch/arm/boot/dts/aspeed-g5.dtsi | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
> index f73a2b18e152..e4e43ae3616a 100644
> --- a/arch/arm/boot/dts/aspeed-g5.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
> @@ -201,6 +201,17 @@
> function = "RMII2";
> groups = "RMII2";
> };
> +
> + pinctrl_spi1_master_default: spi1_master_default {
> + function = "SPI1_MASTER";
> + groups = "SPI1_MASTER";
> + };
> +
> + pinctrl_spi1_passthru_default: spi1_passthru_default {
> + function = "SPI1_PASSTHRU";
> + groups = "SPI1_PASSTHRU";
> + };
> +
This looks fine, however I think we should add VGABIOS_ROM and SYSSPI
given you went to the effort of defining them in the driver.
Cheers,
Andrew
> };
> };
>
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [linux dev-4.7 3/3] arm: dts: aspeed: Add SPI1 master pinmux hog to g5 machines
2016-09-15 11:13 ` [linux dev-4.7 3/3] arm: dts: aspeed: Add SPI1 master pinmux hog to g5 machines Joel Stanley
@ 2016-09-16 0:39 ` Andrew Jeffery
2016-09-16 0:51 ` Joel Stanley
0 siblings, 1 reply; 8+ messages in thread
From: Andrew Jeffery @ 2016-09-16 0:39 UTC (permalink / raw)
To: Joel Stanley; +Cc: openbmc
[-- Attachment #1: Type: text/plain, Size: 1523 bytes --]
On Thu, 2016-09-15 at 20:43 +0930, Joel Stanley wrote:
> This is for reuqired for using the PNOR on ast2500 based systems.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Have we sorted out how we're going to deal with the strap register
configuration (given the pinmux driver treats it as read-only)? I don't
see a u-boot issue for it yet.
Cheers,
Andrew
> ---
> arch/arm/boot/dts/aspeed-ast2500-evb.dts | 5 +++++
> arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts | 5 +++++
> 2 files changed, 10 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
> index d34e6f15a0cb..a517b4a595b8 100644
> --- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts
> +++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
> @@ -35,6 +35,11 @@
> };
> };
>
> +&pinctrl {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_spi1_master_default>;
> +};
> +
> &uart5 {
> status = "okay";
> };
> diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
> index fcc880a80ee0..d7db9700172f 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
> @@ -36,6 +36,11 @@
> };
> };
>
> +&pinctrl {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_spi1_master_default>;
> +};
> +
> &uart5 {
> status = "okay";
> };
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [linux dev-4.7 3/3] arm: dts: aspeed: Add SPI1 master pinmux hog to g5 machines
2016-09-16 0:39 ` Andrew Jeffery
@ 2016-09-16 0:51 ` Joel Stanley
2016-09-16 2:22 ` Andrew Jeffery
0 siblings, 1 reply; 8+ messages in thread
From: Joel Stanley @ 2016-09-16 0:51 UTC (permalink / raw)
To: Andrew Jeffery; +Cc: OpenBMC Maillist
On Fri, Sep 16, 2016 at 10:09 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
> On Thu, 2016-09-15 at 20:43 +0930, Joel Stanley wrote:
>> This is for reuqired for using the PNOR on ast2500 based systems.
>>
>> Signed-off-by: Joel Stanley <joel@jms.id.au>
>
> Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
>
> Have we sorted out how we're going to deal with the strap register
> configuration (given the pinmux driver treats it as read-only)? I don't
> see a u-boot issue for it yet.
I've opened https://github.com/openbmc/openbmc/issues/579 as I haven't
decided if we want it do it in u-boot, kernel or somewhere else.
Cheers,
Joel
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [linux dev-4.7 3/3] arm: dts: aspeed: Add SPI1 master pinmux hog to g5 machines
2016-09-16 0:51 ` Joel Stanley
@ 2016-09-16 2:22 ` Andrew Jeffery
0 siblings, 0 replies; 8+ messages in thread
From: Andrew Jeffery @ 2016-09-16 2:22 UTC (permalink / raw)
To: Joel Stanley; +Cc: OpenBMC Maillist
[-- Attachment #1: Type: text/plain, Size: 759 bytes --]
On Fri, 2016-09-16 at 10:21 +0930, Joel Stanley wrote:
> On Fri, Sep 16, 2016 at 10:09 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
> >
> > On Thu, 2016-09-15 at 20:43 +0930, Joel Stanley wrote:
> > >
> > > This is for reuqired for using the PNOR on ast2500 based systems.
> > >
> > > Signed-off-by: Joel Stanley <joel@jms.id.au>
> > Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
> >
> > Have we sorted out how we're going to deal with the strap register
> > configuration (given the pinmux driver treats it as read-only)? I don't
> > see a u-boot issue for it yet.
> I've opened https://github.com/openbmc/openbmc/issues/579 as I haven't
> decided if we want it do it in u-boot, kernel or somewhere else.
Fair enough!
Thanks,
Andrew
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^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2016-09-16 2:22 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-09-15 11:13 [linux dev-4.7 1/3] pinctrl: aspeed: Add SPI pins to G5 Joel Stanley
2016-09-15 11:13 ` [linux dev-4.7 2/3] arm: dts: aspeed: Add spi1 pins to g5 device tree Joel Stanley
2016-09-16 0:31 ` Andrew Jeffery
2016-09-15 11:13 ` [linux dev-4.7 3/3] arm: dts: aspeed: Add SPI1 master pinmux hog to g5 machines Joel Stanley
2016-09-16 0:39 ` Andrew Jeffery
2016-09-16 0:51 ` Joel Stanley
2016-09-16 2:22 ` Andrew Jeffery
2016-09-16 0:28 ` [linux dev-4.7 1/3] pinctrl: aspeed: Add SPI pins to G5 Andrew Jeffery
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