* [PATCH v3] CLK: Add Loongson1C clock support
@ 2016-09-20 15:54 Yang Ling
2016-09-21 8:46 ` Kelvin Cheung
2016-09-23 21:53 ` Stephen Boyd
0 siblings, 2 replies; 3+ messages in thread
From: Yang Ling @ 2016-09-20 15:54 UTC (permalink / raw)
To: mturquette, sboyd, keguang.zhang
Cc: linux-kernel, linux-clk, linux-mips, gnaygnil
This patch adds clock support to Loongson1C SoC.
Signed-off-by: Yang Ling <gnaygnil@gmail.com>
---
V3:
clk: loongson1c: Migrate to clk_hw based OF and registration APIs.
---
V2:
Use loongson1 generic clock interface.
---
drivers/clk/loongson1/Makefile | 1 +
drivers/clk/loongson1/clk-loongson1c.c | 97 ++++++++++++++++++++++++++++++++++
2 files changed, 98 insertions(+)
create mode 100644 drivers/clk/loongson1/clk-loongson1c.c
diff --git a/drivers/clk/loongson1/Makefile b/drivers/clk/loongson1/Makefile
index 5a162a1..b7f6a16 100644
--- a/drivers/clk/loongson1/Makefile
+++ b/drivers/clk/loongson1/Makefile
@@ -1,2 +1,3 @@
obj-y += clk.o
obj-$(CONFIG_LOONGSON1_LS1B) += clk-loongson1b.o
+obj-$(CONFIG_LOONGSON1_LS1C) += clk-loongson1c.o
diff --git a/drivers/clk/loongson1/clk-loongson1c.c b/drivers/clk/loongson1/clk-loongson1c.c
new file mode 100644
index 0000000..3466f73
--- /dev/null
+++ b/drivers/clk/loongson1/clk-loongson1c.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2016 Yang Ling <gnaygnil@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+
+#include <loongson1.h>
+#include "clk.h"
+
+#define OSC (24 * 1000000)
+#define DIV_APB 1
+
+static DEFINE_SPINLOCK(_lock);
+
+static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ u32 pll, rate;
+
+ pll = __raw_readl(LS1X_CLK_PLL_FREQ);
+ rate = ((pll >> 8) & 0xff) + ((pll >> 16) & 0xff);
+ rate *= OSC;
+ rate >>= 2;
+
+ return rate;
+}
+
+static const struct clk_ops ls1x_pll_clk_ops = {
+ .recalc_rate = ls1x_pll_recalc_rate,
+};
+
+static const struct clk_div_table ahb_div_table[] = {
+ [0] = { .val = 0, .div = 2 },
+ [1] = { .val = 1, .div = 4 },
+ [2] = { .val = 2, .div = 3 },
+ [3] = { .val = 3, .div = 3 },
+};
+
+void __init ls1x_clk_init(void)
+{
+ struct clk_hw *hw;
+
+ hw = clk_hw_register_fixed_rate(NULL, "osc_clk", NULL, 0, OSC);
+ clk_hw_register_clkdev(hw, "osc_clk", NULL);
+
+ /* clock derived from 24 MHz OSC clk */
+ hw = clk_hw_register_pll(NULL, "pll_clk", "osc_clk",
+ &ls1x_pll_clk_ops, 0);
+ clk_hw_register_clkdev(hw, "pll_clk", NULL);
+
+ hw = clk_hw_register_divider(NULL, "cpu_clk_div", "pll_clk",
+ CLK_GET_RATE_NOCACHE, LS1X_CLK_PLL_DIV,
+ DIV_CPU_SHIFT, DIV_CPU_WIDTH,
+ CLK_DIVIDER_ONE_BASED |
+ CLK_DIVIDER_ROUND_CLOSEST, &_lock);
+ clk_hw_register_clkdev(hw, "cpu_clk_div", NULL);
+ hw = clk_hw_register_fixed_factor(NULL, "cpu_clk", "cpu_clk_div",
+ 0, 1, 1);
+ clk_hw_register_clkdev(hw, "cpu_clk", NULL);
+
+ hw = clk_hw_register_divider(NULL, "dc_clk_div", "pll_clk",
+ 0, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
+ DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+ clk_hw_register_clkdev(hw, "dc_clk_div", NULL);
+ hw = clk_hw_register_fixed_factor(NULL, "dc_clk", "dc_clk_div",
+ 0, 1, 1);
+ clk_hw_register_clkdev(hw, "dc_clk", NULL);
+
+ hw = clk_hw_register_divider_table(NULL, "ahb_clk_div", "cpu_clk_div",
+ 0, LS1X_CLK_PLL_FREQ, DIV_DDR_SHIFT,
+ DIV_DDR_WIDTH, CLK_DIVIDER_ALLOW_ZERO,
+ ahb_div_table, &_lock);
+ clk_hw_register_clkdev(hw, "ahb_clk_div", NULL);
+ hw = clk_hw_register_fixed_factor(NULL, "ahb_clk", "ahb_clk_div",
+ 0, 1, 1);
+ clk_hw_register_clkdev(hw, "ahb_clk", NULL);
+ clk_hw_register_clkdev(hw, "ls1x-dma", NULL);
+ clk_hw_register_clkdev(hw, "stmmaceth", NULL);
+
+ /* clock derived from AHB clk */
+ hw = clk_hw_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
+ DIV_APB);
+ clk_hw_register_clkdev(hw, "apb_clk", NULL);
+ clk_hw_register_clkdev(hw, "ls1x-ac97", NULL);
+ clk_hw_register_clkdev(hw, "ls1x-i2c", NULL);
+ clk_hw_register_clkdev(hw, "ls1x-nand", NULL);
+ clk_hw_register_clkdev(hw, "ls1x-pwmtimer", NULL);
+ clk_hw_register_clkdev(hw, "ls1x-spi", NULL);
+ clk_hw_register_clkdev(hw, "ls1x-wdt", NULL);
+ clk_hw_register_clkdev(hw, "serial8250", NULL);
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v3] CLK: Add Loongson1C clock support
2016-09-20 15:54 [PATCH v3] CLK: Add Loongson1C clock support Yang Ling
@ 2016-09-21 8:46 ` Kelvin Cheung
2016-09-23 21:53 ` Stephen Boyd
1 sibling, 0 replies; 3+ messages in thread
From: Kelvin Cheung @ 2016-09-21 8:46 UTC (permalink / raw)
To: Yang Ling
Cc: Michael Turquette, Stephen Boyd, linux-kernel, linux-clk, linux-mips
[-- Attachment #1: Type: text/plain, Size: 5259 bytes --]
2016-09-20 23:54 GMT+08:00 Yang Ling <gnaygnil@gmail.com>:
> This patch adds clock support to Loongson1C SoC.
>
> Signed-off-by: Yang Ling <gnaygnil@gmail.com>
>
> ---
> V3:
> clk: loongson1c: Migrate to clk_hw based OF and registration APIs.
> ---
> V2:
> Use loongson1 generic clock interface.
> ---
> drivers/clk/loongson1/Makefile | 1 +
> drivers/clk/loongson1/clk-loongson1c.c | 97
> ++++++++++++++++++++++++++++++++++
> 2 files changed, 98 insertions(+)
> create mode 100644 drivers/clk/loongson1/clk-loongson1c.c
>
> diff --git a/drivers/clk/loongson1/Makefile b/drivers/clk/loongson1/Makefi
> le
> index 5a162a1..b7f6a16 100644
> --- a/drivers/clk/loongson1/Makefile
> +++ b/drivers/clk/loongson1/Makefile
> @@ -1,2 +1,3 @@
> obj-y += clk.o
> obj-$(CONFIG_LOONGSON1_LS1B) += clk-loongson1b.o
> +obj-$(CONFIG_LOONGSON1_LS1C) += clk-loongson1c.o
> diff --git a/drivers/clk/loongson1/clk-loongson1c.c
> b/drivers/clk/loongson1/clk-loongson1c.c
> new file mode 100644
> index 0000000..3466f73
> --- /dev/null
> +++ b/drivers/clk/loongson1/clk-loongson1c.c
> @@ -0,0 +1,97 @@
> +/*
> + * Copyright (c) 2016 Yang Ling <gnaygnil@gmail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> it
> + * under the terms of the GNU General Public License as published by
> the
> + * Free Software Foundation; either version 2 of the License, or (at
> your
> + * option) any later version.
> + */
> +
> +#include <linux/clkdev.h>
> +#include <linux/clk-provider.h>
> +
> +#include <loongson1.h>
> +#include "clk.h"
> +
> +#define OSC (24 * 1000000)
> +#define DIV_APB 1
> +
> +static DEFINE_SPINLOCK(_lock);
> +
> +static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + u32 pll, rate;
> +
> + pll = __raw_readl(LS1X_CLK_PLL_FREQ);
> + rate = ((pll >> 8) & 0xff) + ((pll >> 16) & 0xff);
> + rate *= OSC;
> + rate >>= 2;
> +
> + return rate;
> +}
> +
> +static const struct clk_ops ls1x_pll_clk_ops = {
> + .recalc_rate = ls1x_pll_recalc_rate,
> +};
> +
> +static const struct clk_div_table ahb_div_table[] = {
> + [0] = { .val = 0, .div = 2 },
> + [1] = { .val = 1, .div = 4 },
> + [2] = { .val = 2, .div = 3 },
> + [3] = { .val = 3, .div = 3 },
> +};
> +
> +void __init ls1x_clk_init(void)
> +{
> + struct clk_hw *hw;
> +
> + hw = clk_hw_register_fixed_rate(NULL, "osc_clk", NULL, 0, OSC);
> + clk_hw_register_clkdev(hw, "osc_clk", NULL);
> +
> + /* clock derived from 24 MHz OSC clk */
> + hw = clk_hw_register_pll(NULL, "pll_clk", "osc_clk",
> + &ls1x_pll_clk_ops, 0);
> + clk_hw_register_clkdev(hw, "pll_clk", NULL);
> +
> + hw = clk_hw_register_divider(NULL, "cpu_clk_div", "pll_clk",
> + CLK_GET_RATE_NOCACHE, LS1X_CLK_PLL_DIV,
> + DIV_CPU_SHIFT, DIV_CPU_WIDTH,
> + CLK_DIVIDER_ONE_BASED |
> + CLK_DIVIDER_ROUND_CLOSEST, &_lock);
> + clk_hw_register_clkdev(hw, "cpu_clk_div", NULL);
> + hw = clk_hw_register_fixed_factor(NULL, "cpu_clk", "cpu_clk_div",
> + 0, 1, 1);
> + clk_hw_register_clkdev(hw, "cpu_clk", NULL);
> +
> + hw = clk_hw_register_divider(NULL, "dc_clk_div", "pll_clk",
> + 0, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
> + DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED,
> &_lock);
> + clk_hw_register_clkdev(hw, "dc_clk_div", NULL);
> + hw = clk_hw_register_fixed_factor(NULL, "dc_clk", "dc_clk_div",
> + 0, 1, 1);
> + clk_hw_register_clkdev(hw, "dc_clk", NULL);
> +
> + hw = clk_hw_register_divider_table(NULL, "ahb_clk_div",
> "cpu_clk_div",
> + 0, LS1X_CLK_PLL_FREQ, DIV_DDR_SHIFT,
> + DIV_DDR_WIDTH, CLK_DIVIDER_ALLOW_ZERO,
> + ahb_div_table, &_lock);
> + clk_hw_register_clkdev(hw, "ahb_clk_div", NULL);
> + hw = clk_hw_register_fixed_factor(NULL, "ahb_clk", "ahb_clk_div",
> + 0, 1, 1);
> + clk_hw_register_clkdev(hw, "ahb_clk", NULL);
> + clk_hw_register_clkdev(hw, "ls1x-dma", NULL);
> + clk_hw_register_clkdev(hw, "stmmaceth", NULL);
> +
> + /* clock derived from AHB clk */
> + hw = clk_hw_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0,
> 1,
> + DIV_APB);
> + clk_hw_register_clkdev(hw, "apb_clk", NULL);
> + clk_hw_register_clkdev(hw, "ls1x-ac97", NULL);
> + clk_hw_register_clkdev(hw, "ls1x-i2c", NULL);
> + clk_hw_register_clkdev(hw, "ls1x-nand", NULL);
> + clk_hw_register_clkdev(hw, "ls1x-pwmtimer", NULL);
> + clk_hw_register_clkdev(hw, "ls1x-spi", NULL);
> + clk_hw_register_clkdev(hw, "ls1x-wdt", NULL);
> + clk_hw_register_clkdev(hw, "serial8250", NULL);
> +}
> --
> 1.9.1
>
>
Acked-by: Keguang Zhang <keguang.zhang@gmail.com>
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v3] CLK: Add Loongson1C clock support
2016-09-20 15:54 [PATCH v3] CLK: Add Loongson1C clock support Yang Ling
2016-09-21 8:46 ` Kelvin Cheung
@ 2016-09-23 21:53 ` Stephen Boyd
1 sibling, 0 replies; 3+ messages in thread
From: Stephen Boyd @ 2016-09-23 21:53 UTC (permalink / raw)
To: Yang Ling; +Cc: mturquette, keguang.zhang, linux-kernel, linux-clk, linux-mips
On 09/20, Yang Ling wrote:
> This patch adds clock support to Loongson1C SoC.
>
> Signed-off-by: Yang Ling <gnaygnil@gmail.com>
>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
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2016-09-21 8:46 ` Kelvin Cheung
2016-09-23 21:53 ` Stephen Boyd
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