* Remainder of small cleanups for DCEv6
@ 2016-09-22 16:43 Tom St Denis
[not found] ` <20160922164347.6404-1-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Tom St Denis @ 2016-09-22 16:43 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Small cleanups to sync up DCEv6 with the style of the others
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/3] drm/amd/amdgpu: Remove division from vblank_wait
[not found] ` <20160922164347.6404-1-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
@ 2016-09-22 16:43 ` Tom St Denis
2016-09-22 16:43 ` [PATCH 2/3] drm/amd/amdgpu: Clean up afmt allocation in DCEv6 Tom St Denis
2016-09-22 16:43 ` [PATCH 3/3] drm/amd/amdgpu: Various cleanups for DCEv6 Tom St Denis
2 siblings, 0 replies; 6+ messages in thread
From: Tom St Denis @ 2016-09-22 16:43 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis
Removes division from vblank_wait for DCE v6, v8,
and v10. Was already implemented for v11.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 8 +++++---
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 8 +++++---
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 8 +++++---
3 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 5af418f6d027..8fb16e9ba315 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -221,7 +221,7 @@ static bool dce_v10_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
*/
static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc)
{
- unsigned i = 0;
+ unsigned i = 100;
if (crtc >= adev->mode_info.num_crtc)
return;
@@ -233,14 +233,16 @@ static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc)
* wait for another frame.
*/
while (dce_v10_0_is_in_vblank(adev, crtc)) {
- if (i++ % 100 == 0) {
+ if (i++ == 100) {
+ i = 0;
if (!dce_v10_0_is_counter_moving(adev, crtc))
break;
}
}
while (!dce_v10_0_is_in_vblank(adev, crtc)) {
- if (i++ % 100 == 0) {
+ if (i++ == 100) {
+ i = 0;
if (!dce_v10_0_is_counter_moving(adev, crtc))
break;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 0a6ec8c43ae0..e41d583740b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -146,7 +146,7 @@ static bool dce_v6_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
*/
static void dce_v6_0_vblank_wait(struct amdgpu_device *adev, int crtc)
{
- unsigned i = 0;
+ unsigned i = 100;
if (crtc >= adev->mode_info.num_crtc)
return;
@@ -158,14 +158,16 @@ static void dce_v6_0_vblank_wait(struct amdgpu_device *adev, int crtc)
* wait for another frame.
*/
while (dce_v6_0_is_in_vblank(adev, crtc)) {
- if (i++ % 100 == 0) {
+ if (i++ == 100) {
+ i = 0;
if (!dce_v6_0_is_counter_moving(adev, crtc))
break;
}
}
while (!dce_v6_0_is_in_vblank(adev, crtc)) {
- if (i++ % 100 == 0) {
+ if (i++ == 100) {
+ i = 0;
if (!dce_v6_0_is_counter_moving(adev, crtc))
break;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 4d313aa20096..9ca586c45b69 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -170,7 +170,7 @@ static bool dce_v8_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
*/
static void dce_v8_0_vblank_wait(struct amdgpu_device *adev, int crtc)
{
- unsigned i = 0;
+ unsigned i = 100;
if (crtc >= adev->mode_info.num_crtc)
return;
@@ -182,14 +182,16 @@ static void dce_v8_0_vblank_wait(struct amdgpu_device *adev, int crtc)
* wait for another frame.
*/
while (dce_v8_0_is_in_vblank(adev, crtc)) {
- if (i++ % 100 == 0) {
+ if (i++ == 100) {
+ i = 0;
if (!dce_v8_0_is_counter_moving(adev, crtc))
break;
}
}
while (!dce_v8_0_is_in_vblank(adev, crtc)) {
- if (i++ % 100 == 0) {
+ if (i++ == 100) {
+ i = 0;
if (!dce_v8_0_is_counter_moving(adev, crtc))
break;
}
--
2.10.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/3] drm/amd/amdgpu: Clean up afmt allocation in DCEv6.
[not found] ` <20160922164347.6404-1-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
2016-09-22 16:43 ` [PATCH 1/3] drm/amd/amdgpu: Remove division from vblank_wait Tom St Denis
@ 2016-09-22 16:43 ` Tom St Denis
2016-09-22 16:43 ` [PATCH 3/3] drm/amd/amdgpu: Various cleanups for DCEv6 Tom St Denis
2 siblings, 0 replies; 6+ messages in thread
From: Tom St Denis @ 2016-09-22 16:43 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index e41d583740b5..dce5414f4ae3 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -1424,17 +1424,24 @@ static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable)
static void dce_v6_0_afmt_init(struct amdgpu_device *adev)
{
- int i;
+ int i, j;
for (i = 0; i < adev->mode_info.num_dig; i++)
adev->mode_info.afmt[i] = NULL;
- /* DCE8 has audio blocks tied to DIG encoders */
+ /* DCE6 has audio blocks tied to DIG encoders */
for (i = 0; i < adev->mode_info.num_dig; i++) {
adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
if (adev->mode_info.afmt[i]) {
adev->mode_info.afmt[i]->offset = dig_offsets[i];
adev->mode_info.afmt[i]->id = i;
+ } else {
+ for (j = 0; j < i; j++) {
+ kfree(adev->mode_info.afmt[j]);
+ adev->mode_info.afmt[j] = NULL;
+ }
+ DRM_ERROR("Out of memory allocating afmt table\n");
+ return -ENOMEM;
}
}
}
@@ -2397,7 +2404,9 @@ static int dce_v6_0_sw_init(void *handle)
return -EINVAL;
/* setup afmt */
- dce_v6_0_afmt_init(adev);
+ r = dce_v6_0_afmt_init(adev);
+ if (r)
+ return r;
r = dce_v6_0_audio_init(adev);
if (r)
--
2.10.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/3] drm/amd/amdgpu: Various cleanups for DCEv6
[not found] ` <20160922164347.6404-1-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
2016-09-22 16:43 ` [PATCH 1/3] drm/amd/amdgpu: Remove division from vblank_wait Tom St Denis
2016-09-22 16:43 ` [PATCH 2/3] drm/amd/amdgpu: Clean up afmt allocation in DCEv6 Tom St Denis
@ 2016-09-22 16:43 ` Tom St Denis
[not found] ` <20160922164347.6404-4-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
2 siblings, 1 reply; 6+ messages in thread
From: Tom St Denis @ 2016-09-22 16:43 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 46 ++++++++---------------------------
1 file changed, 10 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index dce5414f4ae3..a4fa30b9924a 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -1474,10 +1474,7 @@ static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable)
u32 vga_control;
vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
- if (enable)
- WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
- else
- WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
+ WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0));
}
static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)
@@ -1486,10 +1483,7 @@ static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)
struct drm_device *dev = crtc->dev;
struct amdgpu_device *adev = dev->dev_private;
- if (enable)
- WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
- else
- WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
+ WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);
}
static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
@@ -1519,8 +1513,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
if (atomic) {
amdgpu_fb = to_amdgpu_framebuffer(fb);
target_fb = fb;
- }
- else {
+ } else {
amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
target_fb = crtc->primary->fb;
}
@@ -1534,9 +1527,9 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
if (unlikely(r != 0))
return r;
- if (atomic)
+ if (atomic) {
fb_location = amdgpu_bo_gpu_offset(abo);
- else {
+ } else {
r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
if (unlikely(r != 0)) {
amdgpu_bo_unreserve(abo);
@@ -1632,8 +1625,9 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
- } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1)
+ } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
+ }
pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
fb_format |= SI_GRPH_PIPE_CONFIG(pipe_config);
@@ -1797,26 +1791,13 @@ static int dce_v6_0_pick_dig_encoder(struct drm_encoder *encoder)
switch (amdgpu_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
- if (dig->linkb)
- return 1;
- else
- return 0;
- break;
+ return dig->linkb ? 1 : 0;
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
- if (dig->linkb)
- return 3;
- else
- return 2;
- break;
+ return dig->linkb ? 3 : 2;
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
- if (dig->linkb)
- return 5;
- else
- return 4;
- break;
+ return dig->linkb ? 5 : 4;
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
return 6;
- break;
default:
DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
return 0;
@@ -2051,7 +2032,6 @@ static void dce_v6_0_cursor_reset(struct drm_crtc *crtc)
amdgpu_crtc->cursor_y);
dce_v6_0_show_cursor(crtc);
-
dce_v6_0_lock_cursor(crtc, false);
}
}
@@ -2372,15 +2352,11 @@ static int dce_v6_0_sw_init(void *handle)
adev->mode_info.mode_config_initialized = true;
adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
-
adev->ddev->mode_config.async_page_flip = true;
-
adev->ddev->mode_config.max_width = 16384;
adev->ddev->mode_config.max_height = 16384;
-
adev->ddev->mode_config.preferred_depth = 24;
adev->ddev->mode_config.prefer_shadow = 1;
-
adev->ddev->mode_config.fb_base = adev->mc.aper_base;
r = amdgpu_modeset_create_props(adev);
@@ -2426,7 +2402,6 @@ static int dce_v6_0_sw_fini(void *handle)
drm_kms_helper_poll_fini(adev->ddev);
dce_v6_0_audio_fini(adev);
-
dce_v6_0_afmt_fini(adev);
drm_mode_config_cleanup(adev->ddev);
@@ -3054,7 +3029,6 @@ static void dce_v6_0_encoder_add(struct amdgpu_device *adev,
}
amdgpu_encoder->enc_priv = NULL;
-
amdgpu_encoder->encoder_enum = encoder_enum;
amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
amdgpu_encoder->devices = supported_device;
--
2.10.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 3/3] drm/amd/amdgpu: Various cleanups for DCEv6
[not found] ` <20160922164347.6404-4-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
@ 2016-09-22 16:56 ` Alex Deucher
2016-09-24 12:31 ` Edward O'Callaghan
1 sibling, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2016-09-22 16:56 UTC (permalink / raw)
To: Tom St Denis; +Cc: Tom St Denis, amd-gfx list
On Thu, Sep 22, 2016 at 12:43 PM, Tom St Denis <tstdenis82@gmail.com> wrote:
> Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 46 ++++++++---------------------------
> 1 file changed, 10 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index dce5414f4ae3..a4fa30b9924a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -1474,10 +1474,7 @@ static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable)
> u32 vga_control;
>
> vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
> - if (enable)
> - WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
> - else
> - WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
> + WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0));
> }
>
> static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)
> @@ -1486,10 +1483,7 @@ static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)
> struct drm_device *dev = crtc->dev;
> struct amdgpu_device *adev = dev->dev_private;
>
> - if (enable)
> - WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
> - else
> - WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
> + WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);
> }
>
> static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
> @@ -1519,8 +1513,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
> if (atomic) {
> amdgpu_fb = to_amdgpu_framebuffer(fb);
> target_fb = fb;
> - }
> - else {
> + } else {
> amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
> target_fb = crtc->primary->fb;
> }
> @@ -1534,9 +1527,9 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
> if (unlikely(r != 0))
> return r;
>
> - if (atomic)
> + if (atomic) {
> fb_location = amdgpu_bo_gpu_offset(abo);
> - else {
> + } else {
> r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
> if (unlikely(r != 0)) {
> amdgpu_bo_unreserve(abo);
> @@ -1632,8 +1625,9 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
> fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
> fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
> fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
> - } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1)
> + } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
> fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
> + }
>
> pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
> fb_format |= SI_GRPH_PIPE_CONFIG(pipe_config);
> @@ -1797,26 +1791,13 @@ static int dce_v6_0_pick_dig_encoder(struct drm_encoder *encoder)
>
> switch (amdgpu_encoder->encoder_id) {
> case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
> - if (dig->linkb)
> - return 1;
> - else
> - return 0;
> - break;
> + return dig->linkb ? 1 : 0;
> case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
> - if (dig->linkb)
> - return 3;
> - else
> - return 2;
> - break;
> + return dig->linkb ? 3 : 2;
> case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
> - if (dig->linkb)
> - return 5;
> - else
> - return 4;
> - break;
> + return dig->linkb ? 5 : 4;
> case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
> return 6;
> - break;
> default:
> DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
> return 0;
> @@ -2051,7 +2032,6 @@ static void dce_v6_0_cursor_reset(struct drm_crtc *crtc)
> amdgpu_crtc->cursor_y);
>
> dce_v6_0_show_cursor(crtc);
> -
> dce_v6_0_lock_cursor(crtc, false);
> }
> }
> @@ -2372,15 +2352,11 @@ static int dce_v6_0_sw_init(void *handle)
> adev->mode_info.mode_config_initialized = true;
>
> adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
> -
> adev->ddev->mode_config.async_page_flip = true;
> -
> adev->ddev->mode_config.max_width = 16384;
> adev->ddev->mode_config.max_height = 16384;
> -
> adev->ddev->mode_config.preferred_depth = 24;
> adev->ddev->mode_config.prefer_shadow = 1;
> -
> adev->ddev->mode_config.fb_base = adev->mc.aper_base;
>
> r = amdgpu_modeset_create_props(adev);
> @@ -2426,7 +2402,6 @@ static int dce_v6_0_sw_fini(void *handle)
> drm_kms_helper_poll_fini(adev->ddev);
>
> dce_v6_0_audio_fini(adev);
> -
> dce_v6_0_afmt_fini(adev);
>
> drm_mode_config_cleanup(adev->ddev);
> @@ -3054,7 +3029,6 @@ static void dce_v6_0_encoder_add(struct amdgpu_device *adev,
> }
>
> amdgpu_encoder->enc_priv = NULL;
> -
> amdgpu_encoder->encoder_enum = encoder_enum;
> amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
> amdgpu_encoder->devices = supported_device;
> --
> 2.10.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 3/3] drm/amd/amdgpu: Various cleanups for DCEv6
[not found] ` <20160922164347.6404-4-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
2016-09-22 16:56 ` Alex Deucher
@ 2016-09-24 12:31 ` Edward O'Callaghan
1 sibling, 0 replies; 6+ messages in thread
From: Edward O'Callaghan @ 2016-09-24 12:31 UTC (permalink / raw)
To: Tom St Denis, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis
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This patch is,
Review-by: Edward O'Callaghan <funfunctor-dczkZgxz+BNUPWh3PAxdjQ@public.gmane.org>
On 09/23/2016 02:43 AM, Tom St Denis wrote:
> Signed-off-by: Tom St Denis <tom.stdenis-5C7GfCeVMHo@public.gmane.org>
> ---
> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 46 ++++++++---------------------------
> 1 file changed, 10 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index dce5414f4ae3..a4fa30b9924a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -1474,10 +1474,7 @@ static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable)
> u32 vga_control;
>
> vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
> - if (enable)
> - WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
> - else
> - WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
> + WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0));
> }
>
> static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)
> @@ -1486,10 +1483,7 @@ static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)
> struct drm_device *dev = crtc->dev;
> struct amdgpu_device *adev = dev->dev_private;
>
> - if (enable)
> - WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
> - else
> - WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
> + WREG32(EVERGREEN_GRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);
> }
>
> static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
> @@ -1519,8 +1513,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
> if (atomic) {
> amdgpu_fb = to_amdgpu_framebuffer(fb);
> target_fb = fb;
> - }
> - else {
> + } else {
> amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
> target_fb = crtc->primary->fb;
> }
> @@ -1534,9 +1527,9 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
> if (unlikely(r != 0))
> return r;
>
> - if (atomic)
> + if (atomic) {
> fb_location = amdgpu_bo_gpu_offset(abo);
> - else {
> + } else {
> r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
> if (unlikely(r != 0)) {
> amdgpu_bo_unreserve(abo);
> @@ -1632,8 +1625,9 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
> fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
> fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
> fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
> - } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1)
> + } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
> fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
> + }
>
> pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
> fb_format |= SI_GRPH_PIPE_CONFIG(pipe_config);
> @@ -1797,26 +1791,13 @@ static int dce_v6_0_pick_dig_encoder(struct drm_encoder *encoder)
>
> switch (amdgpu_encoder->encoder_id) {
> case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
> - if (dig->linkb)
> - return 1;
> - else
> - return 0;
> - break;
> + return dig->linkb ? 1 : 0;
> case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
> - if (dig->linkb)
> - return 3;
> - else
> - return 2;
> - break;
> + return dig->linkb ? 3 : 2;
> case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
> - if (dig->linkb)
> - return 5;
> - else
> - return 4;
> - break;
> + return dig->linkb ? 5 : 4;
> case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
> return 6;
> - break;
> default:
> DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
> return 0;
> @@ -2051,7 +2032,6 @@ static void dce_v6_0_cursor_reset(struct drm_crtc *crtc)
> amdgpu_crtc->cursor_y);
>
> dce_v6_0_show_cursor(crtc);
> -
> dce_v6_0_lock_cursor(crtc, false);
> }
> }
> @@ -2372,15 +2352,11 @@ static int dce_v6_0_sw_init(void *handle)
> adev->mode_info.mode_config_initialized = true;
>
> adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
> -
> adev->ddev->mode_config.async_page_flip = true;
> -
> adev->ddev->mode_config.max_width = 16384;
> adev->ddev->mode_config.max_height = 16384;
> -
> adev->ddev->mode_config.preferred_depth = 24;
> adev->ddev->mode_config.prefer_shadow = 1;
> -
> adev->ddev->mode_config.fb_base = adev->mc.aper_base;
>
> r = amdgpu_modeset_create_props(adev);
> @@ -2426,7 +2402,6 @@ static int dce_v6_0_sw_fini(void *handle)
> drm_kms_helper_poll_fini(adev->ddev);
>
> dce_v6_0_audio_fini(adev);
> -
> dce_v6_0_afmt_fini(adev);
>
> drm_mode_config_cleanup(adev->ddev);
> @@ -3054,7 +3029,6 @@ static void dce_v6_0_encoder_add(struct amdgpu_device *adev,
> }
>
> amdgpu_encoder->enc_priv = NULL;
> -
> amdgpu_encoder->encoder_enum = encoder_enum;
> amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
> amdgpu_encoder->devices = supported_device;
>
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^ permalink raw reply [flat|nested] 6+ messages in thread
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2016-09-22 16:43 Remainder of small cleanups for DCEv6 Tom St Denis
[not found] ` <20160922164347.6404-1-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
2016-09-22 16:43 ` [PATCH 1/3] drm/amd/amdgpu: Remove division from vblank_wait Tom St Denis
2016-09-22 16:43 ` [PATCH 2/3] drm/amd/amdgpu: Clean up afmt allocation in DCEv6 Tom St Denis
2016-09-22 16:43 ` [PATCH 3/3] drm/amd/amdgpu: Various cleanups for DCEv6 Tom St Denis
[not found] ` <20160922164347.6404-4-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
2016-09-22 16:56 ` Alex Deucher
2016-09-24 12:31 ` Edward O'Callaghan
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