* [PATCH] tps65910 erratum SWCZ010
@ 2016-09-23 8:51 Jan Remmet
2016-09-23 8:52 ` [PATCH] regulator: tps65910: Work around silicon " Jan Remmet
2016-09-23 10:34 ` [PATCH] tps65910 erratum SWCZ010 Mark Brown
0 siblings, 2 replies; 5+ messages in thread
From: Jan Remmet @ 2016-09-23 8:51 UTC (permalink / raw)
To: tony; +Cc: lgirdwood, broonie, linux-omap, linux-kernel
SWCZ010 contains two erratas, one already fixed
commit be1c770028b8 ("mfd: tps65910: Work around silicon erratum SWCZ010")
and this one.
Tested on AM335x board with linux-ti v4.4 kernel. Switching cpu_freq
frequently from 300MHz to 1Ghz results in measurable voltage crashes.
This patch fix the issue.
Jan Remmet (1):
regulator: tps65910: Work around silicon erratum SWCZ010
drivers/regulator/tps65910-regulator.c | 6 ++++++
1 file changed, 6 insertions(+)
--
1.9.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] regulator: tps65910: Work around silicon erratum SWCZ010
2016-09-23 8:51 [PATCH] tps65910 erratum SWCZ010 Jan Remmet
@ 2016-09-23 8:52 ` Jan Remmet
2016-09-25 5:59 ` Mark Brown
2016-09-23 10:34 ` [PATCH] tps65910 erratum SWCZ010 Mark Brown
1 sibling, 1 reply; 5+ messages in thread
From: Jan Remmet @ 2016-09-23 8:52 UTC (permalink / raw)
To: tony; +Cc: lgirdwood, broonie, linux-omap, linux-kernel
http://www.ti.com/lit/pdf/SWCZ010:
DCDC o/p voltage can go higher than programmed value
Impact:
VDDI, VDD2, and VIO output programmed voltage level can go higher than
expected or crash, when coming out of PFM to PWM mode or using DVFS.
Description:
When DCDC CLK SYNC bits are 11/01:
* VIO 3-MHz oscillator is the source clock of the digital core and input
clock of VDD1 and VDD2
* Turn-on of VDD1 and VDD2 HSD PFETis synchronized or at a constant
phase shift
* Current pulled though VCC1+VCC2 is Iload(VDD1) + Iload(VDD2)
* The 3 HSD PFET will be turned-on at the same time, causing the highest
possible switching noise on the application. This noise level depends
on the layout, the VBAT level, and the load current. The noise level
increases with improper layout.
When DCDC CLK SYNC bits are 00:
* VIO 3-MHz oscillator is the source clock of digital core
* VDD1 and VDD2 are running on their own 3-MHz oscillator
* Current pulled though VCC1+VCC2 average of Iload(VDD1) + Iload(VDD2)
* The switching noise of the 3 SMPS will be randomly spread over time,
causing lower overall switching noise.
Workaround:
Set DCDCCTRL_REG[1:0]= 00.
Signed-off-by: Jan Remmet <j.remmet@phytec.de>
---
drivers/regulator/tps65910-regulator.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/regulator/tps65910-regulator.c b/drivers/regulator/tps65910-regulator.c
index fb991ec..696116e 100644
--- a/drivers/regulator/tps65910-regulator.c
+++ b/drivers/regulator/tps65910-regulator.c
@@ -1111,6 +1111,12 @@ static int tps65910_probe(struct platform_device *pdev)
pmic->num_regulators = ARRAY_SIZE(tps65910_regs);
pmic->ext_sleep_control = tps65910_ext_sleep_control;
info = tps65910_regs;
+ /* Work around silicon erratum SWCZ010: output programmed
+ * voltage level can go higher than expected or crash
+ * Workaround: use no synchronization of DCDC clocks
+ */
+ tps65910_reg_clear_bits(pmic->mfd, TPS65910_DCDCCTRL,
+ DCDCCTRL_DCDCCKSYNC_MASK);
break;
case TPS65911:
pmic->get_ctrl_reg = &tps65911_get_ctrl_register;
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] tps65910 erratum SWCZ010
2016-09-23 8:51 [PATCH] tps65910 erratum SWCZ010 Jan Remmet
2016-09-23 8:52 ` [PATCH] regulator: tps65910: Work around silicon " Jan Remmet
@ 2016-09-23 10:34 ` Mark Brown
1 sibling, 0 replies; 5+ messages in thread
From: Mark Brown @ 2016-09-23 10:34 UTC (permalink / raw)
To: Jan Remmet; +Cc: tony, lgirdwood, linux-omap, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 513 bytes --]
On Fri, Sep 23, 2016 at 10:51:59AM +0200, Jan Remmet wrote:
> SWCZ010 contains two erratas, one already fixed
> commit be1c770028b8 ("mfd: tps65910: Work around silicon erratum SWCZ010")
> and this one.
Please don't send cover letters for single patches, if there is anything
that needs saying put it in the changelog of the patch or after the ---
if it's administrative stuff. This reduces mail volume and ensures that
any important information is recorded in the changelog rather than being
lost.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 473 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* Applied "regulator: tps65910: Work around silicon erratum SWCZ010" to the regulator tree
2016-09-23 8:52 ` [PATCH] regulator: tps65910: Work around silicon " Jan Remmet
@ 2016-09-25 5:59 ` Mark Brown
0 siblings, 0 replies; 5+ messages in thread
From: Mark Brown @ 2016-09-25 5:59 UTC (permalink / raw)
To: Jan Remmet
Cc: Mark Brown, stable, tony, lgirdwood, broonie, linux-omap,
linux-kernel, linux-kernel
The patch
regulator: tps65910: Work around silicon erratum SWCZ010
has been applied to the regulator tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
>From 8f9165c981fed187bb483de84caf9adf835aefda Mon Sep 17 00:00:00 2001
From: Jan Remmet <j.remmet@phytec.de>
Date: Fri, 23 Sep 2016 10:52:00 +0200
Subject: [PATCH] regulator: tps65910: Work around silicon erratum SWCZ010
http://www.ti.com/lit/pdf/SWCZ010:
DCDC o/p voltage can go higher than programmed value
Impact:
VDDI, VDD2, and VIO output programmed voltage level can go higher than
expected or crash, when coming out of PFM to PWM mode or using DVFS.
Description:
When DCDC CLK SYNC bits are 11/01:
* VIO 3-MHz oscillator is the source clock of the digital core and input
clock of VDD1 and VDD2
* Turn-on of VDD1 and VDD2 HSD PFETis synchronized or at a constant
phase shift
* Current pulled though VCC1+VCC2 is Iload(VDD1) + Iload(VDD2)
* The 3 HSD PFET will be turned-on at the same time, causing the highest
possible switching noise on the application. This noise level depends
on the layout, the VBAT level, and the load current. The noise level
increases with improper layout.
When DCDC CLK SYNC bits are 00:
* VIO 3-MHz oscillator is the source clock of digital core
* VDD1 and VDD2 are running on their own 3-MHz oscillator
* Current pulled though VCC1+VCC2 average of Iload(VDD1) + Iload(VDD2)
* The switching noise of the 3 SMPS will be randomly spread over time,
causing lower overall switching noise.
Workaround:
Set DCDCCTRL_REG[1:0]= 00.
Signed-off-by: Jan Remmet <j.remmet@phytec.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
---
drivers/regulator/tps65910-regulator.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/regulator/tps65910-regulator.c b/drivers/regulator/tps65910-regulator.c
index fb991ec76423..696116ebdf50 100644
--- a/drivers/regulator/tps65910-regulator.c
+++ b/drivers/regulator/tps65910-regulator.c
@@ -1111,6 +1111,12 @@ static int tps65910_probe(struct platform_device *pdev)
pmic->num_regulators = ARRAY_SIZE(tps65910_regs);
pmic->ext_sleep_control = tps65910_ext_sleep_control;
info = tps65910_regs;
+ /* Work around silicon erratum SWCZ010: output programmed
+ * voltage level can go higher than expected or crash
+ * Workaround: use no synchronization of DCDC clocks
+ */
+ tps65910_reg_clear_bits(pmic->mfd, TPS65910_DCDCCTRL,
+ DCDCCTRL_DCDCCKSYNC_MASK);
break;
case TPS65911:
pmic->get_ctrl_reg = &tps65911_get_ctrl_register;
--
2.9.3
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Applied "regulator: tps65910: Work around silicon erratum SWCZ010" to the regulator tree
@ 2016-09-25 5:59 ` Mark Brown
0 siblings, 0 replies; 5+ messages in thread
From: Mark Brown @ 2016-09-25 5:59 UTC (permalink / raw)
To: Jan Remmet; +Cc: Mark Brown, stable, tony, lgirdwood
The patch
regulator: tps65910: Work around silicon erratum SWCZ010
has been applied to the regulator tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
>From 8f9165c981fed187bb483de84caf9adf835aefda Mon Sep 17 00:00:00 2001
From: Jan Remmet <j.remmet@phytec.de>
Date: Fri, 23 Sep 2016 10:52:00 +0200
Subject: [PATCH] regulator: tps65910: Work around silicon erratum SWCZ010
http://www.ti.com/lit/pdf/SWCZ010:
DCDC o/p voltage can go higher than programmed value
Impact:
VDDI, VDD2, and VIO output programmed voltage level can go higher than
expected or crash, when coming out of PFM to PWM mode or using DVFS.
Description:
When DCDC CLK SYNC bits are 11/01:
* VIO 3-MHz oscillator is the source clock of the digital core and input
clock of VDD1 and VDD2
* Turn-on of VDD1 and VDD2 HSD PFETis synchronized or at a constant
phase shift
* Current pulled though VCC1+VCC2 is Iload(VDD1) + Iload(VDD2)
* The 3 HSD PFET will be turned-on at the same time, causing the highest
possible switching noise on the application. This noise level depends
on the layout, the VBAT level, and the load current. The noise level
increases with improper layout.
When DCDC CLK SYNC bits are 00:
* VIO 3-MHz oscillator is the source clock of digital core
* VDD1 and VDD2 are running on their own 3-MHz oscillator
* Current pulled though VCC1+VCC2 average of Iload(VDD1) + Iload(VDD2)
* The switching noise of the 3 SMPS will be randomly spread over time,
causing lower overall switching noise.
Workaround:
Set DCDCCTRL_REG[1:0]= 00.
Signed-off-by: Jan Remmet <j.remmet@phytec.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
---
drivers/regulator/tps65910-regulator.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/regulator/tps65910-regulator.c b/drivers/regulator/tps65910-regulator.c
index fb991ec76423..696116ebdf50 100644
--- a/drivers/regulator/tps65910-regulator.c
+++ b/drivers/regulator/tps65910-regulator.c
@@ -1111,6 +1111,12 @@ static int tps65910_probe(struct platform_device *pdev)
pmic->num_regulators = ARRAY_SIZE(tps65910_regs);
pmic->ext_sleep_control = tps65910_ext_sleep_control;
info = tps65910_regs;
+ /* Work around silicon erratum SWCZ010: output programmed
+ * voltage level can go higher than expected or crash
+ * Workaround: use no synchronization of DCDC clocks
+ */
+ tps65910_reg_clear_bits(pmic->mfd, TPS65910_DCDCCTRL,
+ DCDCCTRL_DCDCCKSYNC_MASK);
break;
case TPS65911:
pmic->get_ctrl_reg = &tps65911_get_ctrl_register;
--
2.9.3
^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2016-09-25 5:59 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-09-23 8:51 [PATCH] tps65910 erratum SWCZ010 Jan Remmet
2016-09-23 8:52 ` [PATCH] regulator: tps65910: Work around silicon " Jan Remmet
2016-09-25 5:59 ` Applied "regulator: tps65910: Work around silicon erratum SWCZ010" to the regulator tree Mark Brown
2016-09-25 5:59 ` Mark Brown
2016-09-23 10:34 ` [PATCH] tps65910 erratum SWCZ010 Mark Brown
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