All of lore.kernel.org
 help / color / mirror / Atom feed
From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 3/9] MIPS: fix iand optimize setup of CP0 registers
Date: Sun, 25 Sep 2016 20:05:26 +0200	[thread overview]
Message-ID: <20160925180532.19800-4-daniel.schwierzeck@gmail.com> (raw)
In-Reply-To: <20160925180532.19800-1-daniel.schwierzeck@gmail.com>

Clear cp0 status while preserving implementation specific bits.
Set bits BEV and ERL as the arch specification requires after
a reset or soft-reset exception.

Extend and fix initialization of watch registers. Check if additional
watch register sets are implemented and initialize them too.

Initialize cp0 count as early as possible to get the most
accurate boot timing.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---

 arch/mips/cpu/start.S            | 74 +++++++++++++++++++++++++++-------------
 arch/mips/include/asm/mipsregs.h |  1 +
 2 files changed, 51 insertions(+), 24 deletions(-)

diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index 6886036..c909ffa 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -34,28 +34,20 @@
 # define STATUS_SET	ST0_KX
 #endif
 
-	/*
-	 * For the moment disable interrupts, mark the kernel mode and
-	 * set ST0_KX so that the CPU does not spit fire when using
-	 * 64-bit addresses.
-	 */
-	.macro	setup_c0_status set clr
-	.set	push
-	mfc0	t0, CP0_STATUS
-	or	t0, ST0_CU0 | \set | 0x1f | \clr
-	xor	t0, 0x1f | \clr
-	mtc0	t0, CP0_STATUS
-	.set	noreorder
-	sll	zero, 3				# ehb
-	.set	pop
-	.endm
-
 	.set noreorder
 
+	.macro init_wr sel
+	MTC0	zero, CP0_WATCHLO,\sel
+	mtc0	t1, CP0_WATCHHI,\sel
+	mfc0	t0, CP0_WATCHHI,\sel
+	bgez	t0, wr_done
+	 nop
+	.endm
+
 ENTRY(_start)
 	/* U-Boot entry point */
 	b	reset
-	 nop
+	 mtc0	zero, CP0_COUNT	# clear cp0 count for most accurate boot timing
 
 #if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
 	/*
@@ -133,17 +125,51 @@ reset:
 	b	3b
 	 nop
 
-	/* Clear watch registers */
-4:	MTC0	zero, CP0_WATCHLO
+	/* Init CP0 Status */
+4:	mfc0	t0, CP0_STATUS
+	and	t0, ST0_IMPL
+	or	t0, ST0_BEV | ST0_ERL | STATUS_SET
+	mtc0	t0, CP0_STATUS
+
+	/*
+	 * Check whether CP0 Config1 is implemented. If not continue
+	 * with legacy Watch register initialization.
+	 */
+	mfc0	t0, CP0_CONFIG
+	bgez	t0, wr_legacy
+	 nop
+
+	/*
+	 * Check WR bit in CP0 Config1 to determine if Watch registers
+	 * are implemented.
+	 */
+	mfc0	t0, CP0_CONFIG, 1
+	andi	t0, (1 << 3)
+	beqz	t0, wr_done
+	 nop
+
+	/* Clear Watch Status bits and disable watch exceptions */
+	li	t1, 0x7		# Clear I, R and W conditions
+	init_wr	0
+	init_wr	1
+	init_wr	2
+	init_wr	3
+	init_wr	4
+	init_wr	5
+	init_wr	6
+	init_wr	7
+	b	wr_done
+	 nop
+
+wr_legacy:
+	MTC0	zero, CP0_WATCHLO
 	mtc0	zero, CP0_WATCHHI
 
-	/* WP(Watch Pending), SW0/1 should be cleared */
+wr_done:
+	/* Clear WP, IV and SW interrupts */
 	mtc0	zero, CP0_CAUSE
 
-	setup_c0_status STATUS_SET 0
-
-	/* Init Timer */
-	mtc0	zero, CP0_COUNT
+	/* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */
 	mtc0	zero, CP0_COMPARE
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 9ab5063..7a9d222 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -299,6 +299,7 @@
 #define	 STATUSF_IP14		(_ULCAST_(1) <<	 6)
 #define	 STATUSB_IP15		7
 #define	 STATUSF_IP15		(_ULCAST_(1) <<	 7)
+#define ST0_IMPL		(_ULCAST_(3) <<	 16)
 #define ST0_CH			0x00040000
 #define ST0_NMI			0x00080000
 #define ST0_SR			0x00100000
-- 
2.9.3

  parent reply	other threads:[~2016-09-25 18:05 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-25 18:05 [U-Boot] [PATCH 0/9] MIPS: improve start.S and add exception support Daniel Schwierzeck
2016-09-25 18:05 ` [U-Boot] [PATCH 1/9] MIPS: make inclusion of ROM exception vectors configurable Daniel Schwierzeck
2016-09-25 18:05 ` [U-Boot] [PATCH 2/9] MIPS: fix ROM exception vectors Daniel Schwierzeck
2016-09-26  7:58   ` Matthew Fortune
2016-09-26 17:45     ` Daniel Schwierzeck
2016-09-26 19:03       ` Matthew Fortune
2016-09-25 18:05 ` Daniel Schwierzeck [this message]
2016-09-25 18:05 ` [U-Boot] [PATCH 4/9] MIPS: factor out code for initial stack and global data Daniel Schwierzeck
2016-09-25 18:05 ` [U-Boot] [PATCH 5/9] MIPS: add possibility to setup initial stack and global data in SRAM Daniel Schwierzeck
2016-09-25 18:05 ` [U-Boot] [PATCH 6/9] MIPS: add asm-offsets for struct pt_regs Daniel Schwierzeck
2016-09-25 18:05 ` [U-Boot] [PATCH 7/9] MIPS: reserve space for exception vectors Daniel Schwierzeck
2016-09-25 18:05 ` [U-Boot] [PATCH 8/9] MIPS: add handling for generic and EJTAG exceptions Daniel Schwierzeck
2016-09-26 10:29   ` Paul Burton
2016-09-26 17:41     ` Daniel Schwierzeck
2016-09-26 18:15       ` Paul Burton
2016-09-25 18:05 ` [U-Boot] [PATCH 9/9] common/board_f: enable initr_trap for MIPS Daniel Schwierzeck
2016-09-27  0:34   ` Simon Glass
2016-09-26  7:52 ` [U-Boot] [PATCH 0/9] MIPS: improve start.S and add exception support Matthew Fortune

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20160925180532.19800-4-daniel.schwierzeck@gmail.com \
    --to=daniel.schwierzeck@gmail.com \
    --cc=u-boot@lists.denx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.