Enable UVD PG for SMU7 and turn on for Tonga

Enable UVD PG for SMU7 and turn on for Tonga

[Tom St Denis]

Patch #1 fixes the UVD powergating function in the smu7 driver
as well as senses vce/uvd features (so we can fix/add vce PG later on).

Patch #2 enables it for tonga.  Tested by reading tile/clk bits during
load/idle.

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[PATCH 1/2] drm/amd/powerplay: Enable UVD powergating for SMU7

[Tom St Denis]

This patch enables detecting VCE/UVD PG features and fixes the
UVD powergate function.

Tested on a Tonga (by reading UVD tile/clk bits during playback/idle).

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 .../gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c    | 12 +++++++++---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c           | 14 ++++++++++++++
 2 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
index 6eb6db199250..0537407db00a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
@@ -149,15 +149,21 @@ int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
 	if (bgate) {
 		cgs_set_clockgating_state(hwmgr->device,
 				AMD_IP_BLOCK_TYPE_UVD,
-				AMD_CG_STATE_GATE);
+				AMD_CG_STATE_UNGATE);
+		cgs_set_powergating_state(hwmgr->device,
+						AMD_IP_BLOCK_TYPE_UVD,
+						AMD_PG_STATE_GATE);
 		smu7_update_uvd_dpm(hwmgr, true);
 		smu7_powerdown_uvd(hwmgr);
 	} else {
 		smu7_powerup_uvd(hwmgr);
-		smu7_update_uvd_dpm(hwmgr, false);
+		cgs_set_powergating_state(hwmgr->device,
+						AMD_IP_BLOCK_TYPE_UVD,
+						AMD_CG_STATE_UNGATE);
 		cgs_set_clockgating_state(hwmgr->device,
 				AMD_IP_BLOCK_TYPE_UVD,
-				AMD_CG_STATE_UNGATE);
+				AMD_CG_STATE_GATE);
+		smu7_update_uvd_dpm(hwmgr, false);
 	}
 
 	return 0;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 508245d49d33..06ab90b97bb8 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -1344,6 +1344,8 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 	struct phm_ppt_v1_information *table_info =
 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
+	struct cgs_system_info sys_info = {0};
+	int result;
 
 	data->dll_default_on = false;
 	data->mclk_dpm0_activity_target = 0xa;
@@ -1431,6 +1433,18 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 	data->pcie_lane_performance.min = 16;
 	data->pcie_lane_power_saving.max = 0;
 	data->pcie_lane_power_saving.min = 16;
+
+	sys_info.size = sizeof(struct cgs_system_info);
+	sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
+	result = cgs_query_system_info(hwmgr->device, &sys_info);
+	if (!result) {
+		if (sys_info.value & AMD_PG_SUPPORT_UVD)
+			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+				      PHM_PlatformCaps_UVDPowerGating);
+		if (sys_info.value & AMD_PG_SUPPORT_VCE)
+			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+				      PHM_PlatformCaps_VCEPowerGating);
+	}
 }
 
 /**
-- 
2.10.0

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[PATCH 2/2] drm/amd/amdgpu: Enable UVD PG on Tonga

[Tom St Denis]

Tested by reading tile/clk bits during load/idle.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index c6bc3df36118..c4394a6b82e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1924,7 +1924,7 @@ static int vi_common_early_init(void *handle)
 		break;
 	case CHIP_TONGA:
 		adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
-		adev->pg_flags = 0;
+		adev->pg_flags = AMD_PG_SUPPORT_UVD;
 		adev->external_rev_id = adev->rev_id + 0x14;
 		break;
 	case CHIP_POLARIS11:
-- 
2.10.0

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RE: Enable UVD PG for SMU7 and turn on for Tonga

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Tom St Denis
> Sent: Friday, September 30, 2016 11:02 AM
> To: amd-gfx@lists.freedesktop.org
> Subject: Enable UVD PG for SMU7 and turn on for Tonga
> 
> Patch #1 fixes the UVD powergating function in the smu7 driver
> as well as senses vce/uvd features (so we can fix/add vce PG later on).
> 
> Patch #2 enables it for tonga.  Tested by reading tile/clk bits during
> load/idle.

Nice!  Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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Re: Enable UVD PG for SMU7 and turn on for Tonga

[StDenis, Tom]

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Thanks.  I'll try it on FIJI next.  Hopefully MGCG isn't needed for at least basic tile power control.


Tom


________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>
Sent: Friday, September 30, 2016 11:10
To: 'Tom St Denis'; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: RE: Enable UVD PG for SMU7 and turn on for Tonga

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org] On Behalf
> Of Tom St Denis
> Sent: Friday, September 30, 2016 11:02 AM
> To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> Subject: Enable UVD PG for SMU7 and turn on for Tonga
>
> Patch #1 fixes the UVD powergating function in the smu7 driver
> as well as senses vce/uvd features (so we can fix/add vce PG later on).
>
> Patch #2 enables it for tonga.  Tested by reading tile/clk bits during
> load/idle.

Nice!  Series is:
Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>
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RE: Enable UVD PG for SMU7 and turn on for Tonga

[Deucher, Alexander]

[-- Attachment #1.1: Type: text/plain, Size: 1979 bytes --]

I'm not sure Fiji supports PG on any blocks.  You may want to double check with the hw teams.

Alex

From: StDenis, Tom
Sent: Friday, September 30, 2016 11:13 AM
To: Deucher, Alexander; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: Enable UVD PG for SMU7 and turn on for Tonga


Thanks.  I'll try it on FIJI next.  Hopefully MGCG isn't needed for at least basic tile power control.



Tom

________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-bounces@lists.freedesktop.org>> on behalf of Deucher, Alexander <Alexander.Deucher@amd.com<mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>>
Sent: Friday, September 30, 2016 11:10
To: 'Tom St Denis'; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32mptlylMvRsHA@public.gmane.orgdesktop.org>
Subject: RE: Enable UVD PG for SMU7 and turn on for Tonga

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org] On Behalf
> Of Tom St Denis
> Sent: Friday, September 30, 2016 11:02 AM
> To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
> Subject: Enable UVD PG for SMU7 and turn on for Tonga
>
> Patch #1 fixes the UVD powergating function in the smu7 driver
> as well as senses vce/uvd features (so we can fix/add vce PG later on).
>
> Patch #2 enables it for tonga.  Tested by reading tile/clk bits during
> load/idle.

Nice!  Series is:
Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org<mailto:alexander.deucher-5C7GfCeVMHo@public.gmane.org>>
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

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