From: Paul Burton <paul.burton@imgtec.com> To: <linux-mips@linux-mips.org>, Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@imgtec.com> Subject: [PATCH v3 08/18] MIPS: Sanitise coherentio semantics Date: Wed, 5 Oct 2016 18:18:14 +0100 [thread overview] Message-ID: <20161005171824.18014-9-paul.burton@imgtec.com> (raw) In-Reply-To: <20161005171824.18014-1-paul.burton@imgtec.com> The coherentio variable has previously been used as a boolean value, indicating whether the user specified that coherent I/O should be enabled or disabled. It failed to take into account the case where the user does not specify any preference, in which case it makes sense that we should default to coherent I/O if the hardware supports it (hw_coherentio is non-zero). Introduce an enum to clarify the 3 different values of coherentio & use it throughout the code, modifying plat_device_is_coherent() & r4k_cache_init() to take into account the default case. Signed-off-by: Paul Burton <paul.burton@imgtec.com> --- Changes in v3: None Changes in v2: None arch/mips/alchemy/common/setup.c | 6 +++--- arch/mips/include/asm/dma-coherence.h | 12 +++++++++--- arch/mips/include/asm/mach-generic/dma-coherence.h | 10 +++++++++- arch/mips/mm/c-r4k.c | 3 ++- arch/mips/mm/dma-default.c | 7 ++++--- arch/mips/mti-malta/malta-setup.c | 4 ++-- arch/mips/pci/pci-alchemy.c | 3 ++- 7 files changed, 31 insertions(+), 14 deletions(-) diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c index 2902138..7faaa6d 100644 --- a/arch/mips/alchemy/common/setup.c +++ b/arch/mips/alchemy/common/setup.c @@ -48,17 +48,17 @@ void __init plat_mem_setup(void) clear_c0_config(1 << 19); /* Clear Config[OD] */ hw_coherentio = 0; - coherentio = 1; + coherentio = IO_COHERENCE_ENABLED; switch (alchemy_get_cputype()) { case ALCHEMY_CPU_AU1000: case ALCHEMY_CPU_AU1500: case ALCHEMY_CPU_AU1100: - coherentio = 0; + coherentio = IO_COHERENCE_DISABLED; break; case ALCHEMY_CPU_AU1200: /* Au1200 AB USB does not support coherent memory */ if (0 == (read_c0_prid() & PRID_REV_MASK)) - coherentio = 0; + coherentio = IO_COHERENCE_DISABLED; break; } diff --git a/arch/mips/include/asm/dma-coherence.h b/arch/mips/include/asm/dma-coherence.h index bc5e85d..4fbce79 100644 --- a/arch/mips/include/asm/dma-coherence.h +++ b/arch/mips/include/asm/dma-coherence.h @@ -9,14 +9,20 @@ #ifndef __ASM_DMA_COHERENCE_H #define __ASM_DMA_COHERENCE_H +enum coherent_io_user_state { + IO_COHERENCE_DEFAULT, + IO_COHERENCE_ENABLED, + IO_COHERENCE_DISABLED, +}; + #ifdef CONFIG_DMA_MAYBE_COHERENT -extern int coherentio; +extern enum coherent_io_user_state coherentio; extern int hw_coherentio; #else #ifdef CONFIG_DMA_COHERENT -#define coherentio 1 +#define coherentio IO_COHERENCE_ENABLED #else -#define coherentio 0 +#define coherentio IO_COHERENCE_DISABLED #endif #define hw_coherentio 0 #endif /* CONFIG_DMA_MAYBE_COHERENT */ diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h index 0f8a354..8484f82 100644 --- a/arch/mips/include/asm/mach-generic/dma-coherence.h +++ b/arch/mips/include/asm/mach-generic/dma-coherence.h @@ -49,7 +49,15 @@ static inline int plat_dma_supported(struct device *dev, u64 mask) static inline int plat_device_is_coherent(struct device *dev) { - return coherentio; + switch (coherentio) { + default: + case IO_COHERENCE_DEFAULT: + return hw_coherentio; + case IO_COHERENCE_ENABLED: + return 1; + case IO_COHERENCE_DISABLED: + return 0; + } } #ifndef plat_post_dma_flush diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 1fc1118..78ac033 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1935,7 +1935,8 @@ void r4k_cache_init(void) __local_flush_icache_user_range = local_r4k_flush_icache_user_range; #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT) - if (coherentio) { + if ((coherentio == IO_COHERENCE_ENABLED) || + ((coherentio == IO_COHERENCE_DEFAULT) && hw_coherentio)) { _dma_cache_wback_inv = (void *)cache_noop; _dma_cache_wback = (void *)cache_noop; _dma_cache_inv = (void *)cache_noop; diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 755259c..8b86c61 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -25,13 +25,14 @@ #include <dma-coherence.h> #ifdef CONFIG_DMA_MAYBE_COHERENT -int coherentio = 0; /* User defined DMA coherency from command line. */ +/* User defined DMA coherency from command line. */ +enum coherent_io_user_state coherentio = IO_COHERENCE_DEFAULT; EXPORT_SYMBOL_GPL(coherentio); int hw_coherentio = 0; /* Actual hardware supported DMA coherency setting. */ static int __init setcoherentio(char *str) { - coherentio = 1; + coherentio = IO_COHERENCE_ENABLED; pr_info("Hardware DMA cache coherency (command line)\n"); return 0; } @@ -39,7 +40,7 @@ early_param("coherentio", setcoherentio); static int __init setnocoherentio(char *str) { - coherentio = 0; + coherentio = IO_COHERENCE_DISABLED; pr_info("Software DMA cache coherency (command line)\n"); return 0; } diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index 7e7364b..f1b60748 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -154,12 +154,12 @@ static void __init plat_setup_iocoherency(void) * coherency instead. */ if (plat_enable_iocoherency()) { - if (coherentio == 0) + if (coherentio == IO_COHERENCE_DISABLED) pr_info("Hardware DMA cache coherency disabled\n"); else pr_info("Hardware DMA cache coherency enabled\n"); } else { - if (coherentio == 1) + if (coherentio == IO_COHERENCE_ENABLED) pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n"); else pr_info("Software DMA cache coherency enabled\n"); diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c index c8994c1..e99ca77 100644 --- a/arch/mips/pci/pci-alchemy.c +++ b/arch/mips/pci/pci-alchemy.c @@ -429,7 +429,8 @@ static int alchemy_pci_probe(struct platform_device *pdev) /* Au1500 revisions older than AD have borked coherent PCI */ if ((alchemy_get_cputype() == ALCHEMY_CPU_AU1500) && - (read_c0_prid() < 0x01030202) && !coherentio) { + (read_c0_prid() < 0x01030202) && + (coherentio == IO_COHERENCE_DISABLED)) { val = __raw_readl(ctx->regs + PCI_REG_CONFIG); val |= PCI_CONFIG_NC; __raw_writel(val, ctx->regs + PCI_REG_CONFIG); -- 2.10.0
WARNING: multiple messages have this Message-ID (diff)
From: Paul Burton <paul.burton@imgtec.com> To: linux-mips@linux-mips.org, Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@imgtec.com> Subject: [PATCH v3 08/18] MIPS: Sanitise coherentio semantics Date: Wed, 5 Oct 2016 18:18:14 +0100 [thread overview] Message-ID: <20161005171824.18014-9-paul.burton@imgtec.com> (raw) Message-ID: <20161005171814.TgIWPsve4uApP49CVeLtBIvdWyfWETSGx6wb79masOA@z> (raw) In-Reply-To: <20161005171824.18014-1-paul.burton@imgtec.com> The coherentio variable has previously been used as a boolean value, indicating whether the user specified that coherent I/O should be enabled or disabled. It failed to take into account the case where the user does not specify any preference, in which case it makes sense that we should default to coherent I/O if the hardware supports it (hw_coherentio is non-zero). Introduce an enum to clarify the 3 different values of coherentio & use it throughout the code, modifying plat_device_is_coherent() & r4k_cache_init() to take into account the default case. Signed-off-by: Paul Burton <paul.burton@imgtec.com> --- Changes in v3: None Changes in v2: None arch/mips/alchemy/common/setup.c | 6 +++--- arch/mips/include/asm/dma-coherence.h | 12 +++++++++--- arch/mips/include/asm/mach-generic/dma-coherence.h | 10 +++++++++- arch/mips/mm/c-r4k.c | 3 ++- arch/mips/mm/dma-default.c | 7 ++++--- arch/mips/mti-malta/malta-setup.c | 4 ++-- arch/mips/pci/pci-alchemy.c | 3 ++- 7 files changed, 31 insertions(+), 14 deletions(-) diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c index 2902138..7faaa6d 100644 --- a/arch/mips/alchemy/common/setup.c +++ b/arch/mips/alchemy/common/setup.c @@ -48,17 +48,17 @@ void __init plat_mem_setup(void) clear_c0_config(1 << 19); /* Clear Config[OD] */ hw_coherentio = 0; - coherentio = 1; + coherentio = IO_COHERENCE_ENABLED; switch (alchemy_get_cputype()) { case ALCHEMY_CPU_AU1000: case ALCHEMY_CPU_AU1500: case ALCHEMY_CPU_AU1100: - coherentio = 0; + coherentio = IO_COHERENCE_DISABLED; break; case ALCHEMY_CPU_AU1200: /* Au1200 AB USB does not support coherent memory */ if (0 == (read_c0_prid() & PRID_REV_MASK)) - coherentio = 0; + coherentio = IO_COHERENCE_DISABLED; break; } diff --git a/arch/mips/include/asm/dma-coherence.h b/arch/mips/include/asm/dma-coherence.h index bc5e85d..4fbce79 100644 --- a/arch/mips/include/asm/dma-coherence.h +++ b/arch/mips/include/asm/dma-coherence.h @@ -9,14 +9,20 @@ #ifndef __ASM_DMA_COHERENCE_H #define __ASM_DMA_COHERENCE_H +enum coherent_io_user_state { + IO_COHERENCE_DEFAULT, + IO_COHERENCE_ENABLED, + IO_COHERENCE_DISABLED, +}; + #ifdef CONFIG_DMA_MAYBE_COHERENT -extern int coherentio; +extern enum coherent_io_user_state coherentio; extern int hw_coherentio; #else #ifdef CONFIG_DMA_COHERENT -#define coherentio 1 +#define coherentio IO_COHERENCE_ENABLED #else -#define coherentio 0 +#define coherentio IO_COHERENCE_DISABLED #endif #define hw_coherentio 0 #endif /* CONFIG_DMA_MAYBE_COHERENT */ diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h index 0f8a354..8484f82 100644 --- a/arch/mips/include/asm/mach-generic/dma-coherence.h +++ b/arch/mips/include/asm/mach-generic/dma-coherence.h @@ -49,7 +49,15 @@ static inline int plat_dma_supported(struct device *dev, u64 mask) static inline int plat_device_is_coherent(struct device *dev) { - return coherentio; + switch (coherentio) { + default: + case IO_COHERENCE_DEFAULT: + return hw_coherentio; + case IO_COHERENCE_ENABLED: + return 1; + case IO_COHERENCE_DISABLED: + return 0; + } } #ifndef plat_post_dma_flush diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 1fc1118..78ac033 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1935,7 +1935,8 @@ void r4k_cache_init(void) __local_flush_icache_user_range = local_r4k_flush_icache_user_range; #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT) - if (coherentio) { + if ((coherentio == IO_COHERENCE_ENABLED) || + ((coherentio == IO_COHERENCE_DEFAULT) && hw_coherentio)) { _dma_cache_wback_inv = (void *)cache_noop; _dma_cache_wback = (void *)cache_noop; _dma_cache_inv = (void *)cache_noop; diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 755259c..8b86c61 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -25,13 +25,14 @@ #include <dma-coherence.h> #ifdef CONFIG_DMA_MAYBE_COHERENT -int coherentio = 0; /* User defined DMA coherency from command line. */ +/* User defined DMA coherency from command line. */ +enum coherent_io_user_state coherentio = IO_COHERENCE_DEFAULT; EXPORT_SYMBOL_GPL(coherentio); int hw_coherentio = 0; /* Actual hardware supported DMA coherency setting. */ static int __init setcoherentio(char *str) { - coherentio = 1; + coherentio = IO_COHERENCE_ENABLED; pr_info("Hardware DMA cache coherency (command line)\n"); return 0; } @@ -39,7 +40,7 @@ early_param("coherentio", setcoherentio); static int __init setnocoherentio(char *str) { - coherentio = 0; + coherentio = IO_COHERENCE_DISABLED; pr_info("Software DMA cache coherency (command line)\n"); return 0; } diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index 7e7364b..f1b60748 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -154,12 +154,12 @@ static void __init plat_setup_iocoherency(void) * coherency instead. */ if (plat_enable_iocoherency()) { - if (coherentio == 0) + if (coherentio == IO_COHERENCE_DISABLED) pr_info("Hardware DMA cache coherency disabled\n"); else pr_info("Hardware DMA cache coherency enabled\n"); } else { - if (coherentio == 1) + if (coherentio == IO_COHERENCE_ENABLED) pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n"); else pr_info("Software DMA cache coherency enabled\n"); diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c index c8994c1..e99ca77 100644 --- a/arch/mips/pci/pci-alchemy.c +++ b/arch/mips/pci/pci-alchemy.c @@ -429,7 +429,8 @@ static int alchemy_pci_probe(struct platform_device *pdev) /* Au1500 revisions older than AD have borked coherent PCI */ if ((alchemy_get_cputype() == ALCHEMY_CPU_AU1500) && - (read_c0_prid() < 0x01030202) && !coherentio) { + (read_c0_prid() < 0x01030202) && + (coherentio == IO_COHERENCE_DISABLED)) { val = __raw_readl(ctx->regs + PCI_REG_CONFIG); val |= PCI_CONFIG_NC; __raw_writel(val, ctx->regs + PCI_REG_CONFIG); -- 2.10.0
next prev parent reply other threads:[~2016-10-05 17:22 UTC|newest] Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-10-05 17:18 [PATCH v3 00/18] MIPS generic kernels, SEAD-3 & Boston support Paul Burton 2016-10-05 17:18 ` Paul Burton 2016-10-05 17:18 ` [PATCH v3 01/18] MIPS: PCI: Use struct list_head lists Paul Burton 2016-10-05 17:18 ` Paul Burton 2016-10-05 17:18 ` [PATCH v3 02/18] MIPS: PCI: Support for CONFIG_PCI_DOMAINS_GENERIC Paul Burton 2016-10-05 17:18 ` Paul Burton 2016-10-05 17:18 ` [PATCH v3 03/18] MIPS: PCI: Make pcibios_set_cache_line_size an initcall Paul Burton 2016-10-05 17:18 ` Paul Burton 2016-10-05 17:18 ` [PATCH v3 04/18] MIPS: PCI: Inline pcibios_assign_all_busses Paul Burton 2016-10-05 17:18 ` Paul Burton 2016-10-05 17:18 ` [PATCH v3 05/18] MIPS: PCI: Split pci.c into pci.c & pci-legacy.c Paul Burton 2016-10-05 17:18 ` Paul Burton 2016-10-05 17:18 ` [PATCH v3 06/18] MIPS: PCI: Introduce CONFIG_PCI_DRIVERS_LEGACY Paul Burton 2016-10-05 17:18 ` Paul Burton 2016-10-05 17:18 ` [PATCH v3 07/18] MIPS: PCI: Support generic drivers Paul Burton 2016-10-05 17:18 ` Paul Burton 2016-10-05 17:18 ` Paul Burton [this message] 2016-10-05 17:18 ` [PATCH v3 08/18] MIPS: Sanitise coherentio semantics Paul Burton 2016-10-05 17:18 ` [PATCH v3 09/18] MIPS: dma-default: Don't check hw_coherentio if device is non-coherent Paul Burton 2016-10-05 17:18 ` Paul Burton 2016-10-05 17:18 ` [PATCH v3 10/18] MIPS: Support per-device DMA coherence Paul Burton 2016-10-05 17:18 ` Paul Burton 2016-10-05 17:18 ` [PATCH v3 11/18] MIPS: Print CM error reports upon bus errors Paul Burton 2016-10-05 17:18 ` Paul Burton 2016-10-05 17:18 ` [PATCH v3 12/18] MIPS: Adjust MIPS64 CAC_BASE to reflect Config.K0 Paul Burton 2016-10-05 17:18 ` Paul Burton 2016-10-05 17:18 ` [PATCH v3 13/18] MIPS: Support generating Flattened Image Trees (.itb) Paul Burton 2016-10-05 17:18 ` Paul Burton 2016-10-05 17:18 ` [PATCH v3 14/18] MIPS: generic: Introduce generic DT-based board support Paul Burton 2016-10-05 17:18 ` Paul Burton 2016-10-05 17:18 ` [PATCH v3 15/18] MIPS: generic: Convert SEAD-3 to a generic board Paul Burton 2016-10-05 17:18 ` Paul Burton 2016-10-05 17:18 ` [PATCH v3 16/18] dt-bindings: Document img,boston-clock binding Paul Burton 2016-10-05 17:18 ` Paul Burton [not found] ` <20161005171824.18014-17-paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org> 2016-10-10 13:01 ` Rob Herring 2016-10-10 13:01 ` Rob Herring 2016-10-11 15:56 ` Paul Burton 2016-10-11 15:56 ` Paul Burton 2016-10-11 16:00 ` Paul Burton 2016-10-11 16:00 ` Paul Burton 2016-10-11 20:06 ` Rob Herring 2016-10-11 21:15 ` Paul Burton 2016-10-19 0:46 ` Stephen Boyd 2016-10-19 0:46 ` Stephen Boyd 2016-10-05 17:18 ` [PATCH v3 17/18] clk: boston: Add a driver for MIPS Boston board clocks Paul Burton 2016-10-05 17:18 ` Paul Burton 2016-10-07 9:50 ` Paul Burton 2016-10-05 17:18 ` [PATCH v3 18/18] MIPS: generic: Support MIPS Boston development boards Paul Burton 2016-10-05 17:18 ` Paul Burton
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