* [PATCH 1/9] PCI: xilinx: Name private struct pointer "xilinx" consistently
@ 2016-10-07 16:28 Bjorn Helgaas
2016-10-07 16:28 ` [PATCH 2/9] PCI: xilinx: Rename accessors Bjorn Helgaas
` (7 more replies)
0 siblings, 8 replies; 9+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:28 UTC (permalink / raw)
To: Michal Simek, Sören Brinkmann; +Cc: linux-pci
Use a device-specific name, "xilinx", for struct xilinx_pcie_port pointers
to hint that this is device-specific information. No functional change
intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pcie-xilinx.c | 204 ++++++++++++++++++++--------------------
1 file changed, 102 insertions(+), 102 deletions(-)
diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index be56803..14e4187 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -118,34 +118,34 @@ struct xilinx_pcie_port {
static DECLARE_BITMAP(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
-static inline u32 pcie_read(struct xilinx_pcie_port *port, u32 reg)
+static inline u32 pcie_read(struct xilinx_pcie_port *xilinx, u32 reg)
{
- return readl(port->reg_base + reg);
+ return readl(xilinx->reg_base + reg);
}
-static inline void pcie_write(struct xilinx_pcie_port *port, u32 val, u32 reg)
+static inline void pcie_write(struct xilinx_pcie_port *xilinx, u32 val, u32 reg)
{
- writel(val, port->reg_base + reg);
+ writel(val, xilinx->reg_base + reg);
}
-static inline bool xilinx_pcie_link_is_up(struct xilinx_pcie_port *port)
+static inline bool xilinx_pcie_link_is_up(struct xilinx_pcie_port *xilinx)
{
- return (pcie_read(port, XILINX_PCIE_REG_PSCR) &
+ return (pcie_read(xilinx, XILINX_PCIE_REG_PSCR) &
XILINX_PCIE_REG_PSCR_LNKUP) ? 1 : 0;
}
/**
* xilinx_pcie_clear_err_interrupts - Clear Error Interrupts
- * @port: PCIe port information
+ * @xilinx: PCIe port information
*/
-static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *port)
+static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *xilinx)
{
- unsigned long val = pcie_read(port, XILINX_PCIE_REG_RPEFR);
+ unsigned long val = pcie_read(xilinx, XILINX_PCIE_REG_RPEFR);
if (val & XILINX_PCIE_RPEFR_ERR_VALID) {
- dev_dbg(port->dev, "Requester ID %lu\n",
+ dev_dbg(xilinx->dev, "Requester ID %lu\n",
val & XILINX_PCIE_RPEFR_REQ_ID);
- pcie_write(port, XILINX_PCIE_RPEFR_ALL_MASK,
+ pcie_write(xilinx, XILINX_PCIE_RPEFR_ALL_MASK,
XILINX_PCIE_REG_RPEFR);
}
}
@@ -159,15 +159,15 @@ static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *port)
*/
static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
{
- struct xilinx_pcie_port *port = bus->sysdata;
+ struct xilinx_pcie_port *xilinx = bus->sysdata;
/* Check if link is up when trying to access downstream ports */
- if (bus->number != port->root_busno)
- if (!xilinx_pcie_link_is_up(port))
+ if (bus->number != xilinx->root_busno)
+ if (!xilinx_pcie_link_is_up(xilinx))
return false;
/* Only one device down on each root port */
- if (bus->number == port->root_busno && devfn > 0)
+ if (bus->number == xilinx->root_busno && devfn > 0)
return false;
return true;
@@ -185,7 +185,7 @@ static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
static void __iomem *xilinx_pcie_map_bus(struct pci_bus *bus,
unsigned int devfn, int where)
{
- struct xilinx_pcie_port *port = bus->sysdata;
+ struct xilinx_pcie_port *xilinx = bus->sysdata;
int relbus;
if (!xilinx_pcie_valid_device(bus, devfn))
@@ -194,7 +194,7 @@ static void __iomem *xilinx_pcie_map_bus(struct pci_bus *bus,
relbus = (bus->number << ECAM_BUS_NUM_SHIFT) |
(devfn << ECAM_DEV_NUM_SHIFT);
- return port->reg_base + relbus + where;
+ return xilinx->reg_base + relbus + where;
}
/* PCIe operations */
@@ -213,14 +213,14 @@ static struct pci_ops xilinx_pcie_ops = {
static void xilinx_pcie_destroy_msi(unsigned int irq)
{
struct msi_desc *msi;
- struct xilinx_pcie_port *port;
+ struct xilinx_pcie_port *xilinx;
struct irq_data *d = irq_get_irq_data(irq);
irq_hw_number_t hwirq = irqd_to_hwirq(d);
if (!test_bit(hwirq, msi_irq_in_use)) {
msi = irq_get_msi_desc(irq);
- port = msi_desc_to_pci_sysdata(msi);
- dev_err(port->dev, "Trying to free unused MSI#%d\n", irq);
+ xilinx = msi_desc_to_pci_sysdata(msi);
+ dev_err(xilinx->dev, "Trying to free unused MSI#%d\n", irq);
} else {
clear_bit(hwirq, msi_irq_in_use);
}
@@ -228,11 +228,11 @@ static void xilinx_pcie_destroy_msi(unsigned int irq)
/**
* xilinx_pcie_assign_msi - Allocate MSI number
- * @port: PCIe port structure
+ * @xilinx: PCIe port structure
*
* Return: A valid IRQ on success and error value on failure.
*/
-static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port)
+static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *xilinx)
{
int pos;
@@ -269,23 +269,23 @@ static int xilinx_pcie_msi_setup_irq(struct msi_controller *chip,
struct pci_dev *pdev,
struct msi_desc *desc)
{
- struct xilinx_pcie_port *port = pdev->bus->sysdata;
+ struct xilinx_pcie_port *xilinx = pdev->bus->sysdata;
unsigned int irq;
int hwirq;
struct msi_msg msg;
phys_addr_t msg_addr;
- hwirq = xilinx_pcie_assign_msi(port);
+ hwirq = xilinx_pcie_assign_msi(xilinx);
if (hwirq < 0)
return hwirq;
- irq = irq_create_mapping(port->msi_domain, hwirq);
+ irq = irq_create_mapping(xilinx->msi_domain, hwirq);
if (!irq)
return -EINVAL;
irq_set_msi_desc(irq, desc);
- msg_addr = virt_to_phys((void *)port->msi_pages);
+ msg_addr = virt_to_phys((void *)xilinx->msi_pages);
msg.address_hi = 0;
msg.address_lo = msg_addr;
@@ -335,16 +335,16 @@ static const struct irq_domain_ops msi_domain_ops = {
/**
* xilinx_pcie_enable_msi - Enable MSI support
- * @port: PCIe port information
+ * @xilinx: PCIe port information
*/
-static void xilinx_pcie_enable_msi(struct xilinx_pcie_port *port)
+static void xilinx_pcie_enable_msi(struct xilinx_pcie_port *xilinx)
{
phys_addr_t msg_addr;
- port->msi_pages = __get_free_pages(GFP_KERNEL, 0);
- msg_addr = virt_to_phys((void *)port->msi_pages);
- pcie_write(port, 0x0, XILINX_PCIE_REG_MSIBASE1);
- pcie_write(port, msg_addr, XILINX_PCIE_REG_MSIBASE2);
+ xilinx->msi_pages = __get_free_pages(GFP_KERNEL, 0);
+ msg_addr = virt_to_phys((void *)xilinx->msi_pages);
+ pcie_write(xilinx, 0x0, XILINX_PCIE_REG_MSIBASE1);
+ pcie_write(xilinx, msg_addr, XILINX_PCIE_REG_MSIBASE2);
}
/* INTx Functions */
@@ -382,85 +382,85 @@ static const struct irq_domain_ops intx_domain_ops = {
*/
static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
{
- struct xilinx_pcie_port *port = (struct xilinx_pcie_port *)data;
+ struct xilinx_pcie_port *xilinx = (struct xilinx_pcie_port *)data;
u32 val, mask, status, msi_data;
/* Read interrupt decode and mask registers */
- val = pcie_read(port, XILINX_PCIE_REG_IDR);
- mask = pcie_read(port, XILINX_PCIE_REG_IMR);
+ val = pcie_read(xilinx, XILINX_PCIE_REG_IDR);
+ mask = pcie_read(xilinx, XILINX_PCIE_REG_IMR);
status = val & mask;
if (!status)
return IRQ_NONE;
if (status & XILINX_PCIE_INTR_LINK_DOWN)
- dev_warn(port->dev, "Link Down\n");
+ dev_warn(xilinx->dev, "Link Down\n");
if (status & XILINX_PCIE_INTR_ECRC_ERR)
- dev_warn(port->dev, "ECRC failed\n");
+ dev_warn(xilinx->dev, "ECRC failed\n");
if (status & XILINX_PCIE_INTR_STR_ERR)
- dev_warn(port->dev, "Streaming error\n");
+ dev_warn(xilinx->dev, "Streaming error\n");
if (status & XILINX_PCIE_INTR_HOT_RESET)
- dev_info(port->dev, "Hot reset\n");
+ dev_info(xilinx->dev, "Hot reset\n");
if (status & XILINX_PCIE_INTR_CFG_TIMEOUT)
- dev_warn(port->dev, "ECAM access timeout\n");
+ dev_warn(xilinx->dev, "ECAM access timeout\n");
if (status & XILINX_PCIE_INTR_CORRECTABLE) {
- dev_warn(port->dev, "Correctable error message\n");
- xilinx_pcie_clear_err_interrupts(port);
+ dev_warn(xilinx->dev, "Correctable error message\n");
+ xilinx_pcie_clear_err_interrupts(xilinx);
}
if (status & XILINX_PCIE_INTR_NONFATAL) {
- dev_warn(port->dev, "Non fatal error message\n");
- xilinx_pcie_clear_err_interrupts(port);
+ dev_warn(xilinx->dev, "Non fatal error message\n");
+ xilinx_pcie_clear_err_interrupts(xilinx);
}
if (status & XILINX_PCIE_INTR_FATAL) {
- dev_warn(port->dev, "Fatal error message\n");
- xilinx_pcie_clear_err_interrupts(port);
+ dev_warn(xilinx->dev, "Fatal error message\n");
+ xilinx_pcie_clear_err_interrupts(xilinx);
}
if (status & XILINX_PCIE_INTR_INTX) {
/* INTx interrupt received */
- val = pcie_read(port, XILINX_PCIE_REG_RPIFR1);
+ val = pcie_read(xilinx, XILINX_PCIE_REG_RPIFR1);
/* Check whether interrupt valid */
if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
- dev_warn(port->dev, "RP Intr FIFO1 read error\n");
+ dev_warn(xilinx->dev, "RP Intr FIFO1 read error\n");
goto error;
}
if (!(val & XILINX_PCIE_RPIFR1_MSI_INTR)) {
/* Clear interrupt FIFO register 1 */
- pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
+ pcie_write(xilinx, XILINX_PCIE_RPIFR1_ALL_MASK,
XILINX_PCIE_REG_RPIFR1);
/* Handle INTx Interrupt */
val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1;
- generic_handle_irq(irq_find_mapping(port->leg_domain,
+ generic_handle_irq(irq_find_mapping(xilinx->leg_domain,
val));
}
}
if (status & XILINX_PCIE_INTR_MSI) {
/* MSI Interrupt */
- val = pcie_read(port, XILINX_PCIE_REG_RPIFR1);
+ val = pcie_read(xilinx, XILINX_PCIE_REG_RPIFR1);
if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
- dev_warn(port->dev, "RP Intr FIFO1 read error\n");
+ dev_warn(xilinx->dev, "RP Intr FIFO1 read error\n");
goto error;
}
if (val & XILINX_PCIE_RPIFR1_MSI_INTR) {
- msi_data = pcie_read(port, XILINX_PCIE_REG_RPIFR2) &
+ msi_data = pcie_read(xilinx, XILINX_PCIE_REG_RPIFR2) &
XILINX_PCIE_RPIFR2_MSG_DATA;
/* Clear interrupt FIFO register 1 */
- pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
+ pcie_write(xilinx, XILINX_PCIE_RPIFR1_ALL_MASK,
XILINX_PCIE_REG_RPIFR1);
if (IS_ENABLED(CONFIG_PCI_MSI)) {
@@ -471,48 +471,48 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
}
if (status & XILINX_PCIE_INTR_SLV_UNSUPP)
- dev_warn(port->dev, "Slave unsupported request\n");
+ dev_warn(xilinx->dev, "Slave unsupported request\n");
if (status & XILINX_PCIE_INTR_SLV_UNEXP)
- dev_warn(port->dev, "Slave unexpected completion\n");
+ dev_warn(xilinx->dev, "Slave unexpected completion\n");
if (status & XILINX_PCIE_INTR_SLV_COMPL)
- dev_warn(port->dev, "Slave completion timeout\n");
+ dev_warn(xilinx->dev, "Slave completion timeout\n");
if (status & XILINX_PCIE_INTR_SLV_ERRP)
- dev_warn(port->dev, "Slave Error Poison\n");
+ dev_warn(xilinx->dev, "Slave Error Poison\n");
if (status & XILINX_PCIE_INTR_SLV_CMPABT)
- dev_warn(port->dev, "Slave Completer Abort\n");
+ dev_warn(xilinx->dev, "Slave Completer Abort\n");
if (status & XILINX_PCIE_INTR_SLV_ILLBUR)
- dev_warn(port->dev, "Slave Illegal Burst\n");
+ dev_warn(xilinx->dev, "Slave Illegal Burst\n");
if (status & XILINX_PCIE_INTR_MST_DECERR)
- dev_warn(port->dev, "Master decode error\n");
+ dev_warn(xilinx->dev, "Master decode error\n");
if (status & XILINX_PCIE_INTR_MST_SLVERR)
- dev_warn(port->dev, "Master slave error\n");
+ dev_warn(xilinx->dev, "Master slave error\n");
if (status & XILINX_PCIE_INTR_MST_ERRP)
- dev_warn(port->dev, "Master error poison\n");
+ dev_warn(xilinx->dev, "Master error poison\n");
error:
/* Clear the Interrupt Decode register */
- pcie_write(port, status, XILINX_PCIE_REG_IDR);
+ pcie_write(xilinx, status, XILINX_PCIE_REG_IDR);
return IRQ_HANDLED;
}
/**
* xilinx_pcie_init_irq_domain - Initialize IRQ domain
- * @port: PCIe port information
+ * @xilinx: PCIe port information
*
* Return: '0' on success and error value on failure
*/
-static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)
+static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *xilinx)
{
- struct device *dev = port->dev;
+ struct device *dev = xilinx->dev;
struct device_node *node = dev->of_node;
struct device_node *pcie_intc_node;
@@ -523,26 +523,26 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)
return -ENODEV;
}
- port->leg_domain = irq_domain_add_linear(pcie_intc_node, 4,
+ xilinx->leg_domain = irq_domain_add_linear(pcie_intc_node, 4,
&intx_domain_ops,
- port);
- if (!port->leg_domain) {
+ xilinx);
+ if (!xilinx->leg_domain) {
dev_err(dev, "Failed to get a INTx IRQ domain\n");
return -ENODEV;
}
/* Setup MSI */
if (IS_ENABLED(CONFIG_PCI_MSI)) {
- port->msi_domain = irq_domain_add_linear(node,
+ xilinx->msi_domain = irq_domain_add_linear(node,
XILINX_NUM_MSI_IRQS,
&msi_domain_ops,
&xilinx_pcie_msi_chip);
- if (!port->msi_domain) {
+ if (!xilinx->msi_domain) {
dev_err(dev, "Failed to get a MSI IRQ domain\n");
return -ENODEV;
}
- xilinx_pcie_enable_msi(port);
+ xilinx_pcie_enable_msi(xilinx);
}
return 0;
@@ -550,42 +550,42 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)
/**
* xilinx_pcie_init_port - Initialize hardware
- * @port: PCIe port information
+ * @xilinx: PCIe port information
*/
-static void xilinx_pcie_init_port(struct xilinx_pcie_port *port)
+static void xilinx_pcie_init_port(struct xilinx_pcie_port *xilinx)
{
- if (xilinx_pcie_link_is_up(port))
- dev_info(port->dev, "PCIe Link is UP\n");
+ if (xilinx_pcie_link_is_up(xilinx))
+ dev_info(xilinx->dev, "PCIe Link is UP\n");
else
- dev_info(port->dev, "PCIe Link is DOWN\n");
+ dev_info(xilinx->dev, "PCIe Link is DOWN\n");
/* Disable all interrupts */
- pcie_write(port, ~XILINX_PCIE_IDR_ALL_MASK,
+ pcie_write(xilinx, ~XILINX_PCIE_IDR_ALL_MASK,
XILINX_PCIE_REG_IMR);
/* Clear pending interrupts */
- pcie_write(port, pcie_read(port, XILINX_PCIE_REG_IDR) &
+ pcie_write(xilinx, pcie_read(xilinx, XILINX_PCIE_REG_IDR) &
XILINX_PCIE_IMR_ALL_MASK,
XILINX_PCIE_REG_IDR);
/* Enable all interrupts */
- pcie_write(port, XILINX_PCIE_IMR_ALL_MASK, XILINX_PCIE_REG_IMR);
+ pcie_write(xilinx, XILINX_PCIE_IMR_ALL_MASK, XILINX_PCIE_REG_IMR);
/* Enable the Bridge enable bit */
- pcie_write(port, pcie_read(port, XILINX_PCIE_REG_RPSC) |
+ pcie_write(xilinx, pcie_read(xilinx, XILINX_PCIE_REG_RPSC) |
XILINX_PCIE_REG_RPSC_BEN,
XILINX_PCIE_REG_RPSC);
}
/**
* xilinx_pcie_parse_dt - Parse Device tree
- * @port: PCIe port information
+ * @xilinx: PCIe port information
*
* Return: '0' on success and error value on failure
*/
-static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *port)
+static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *xilinx)
{
- struct device *dev = port->dev;
+ struct device *dev = xilinx->dev;
struct device_node *node = dev->of_node;
struct resource regs;
const char *type;
@@ -603,16 +603,16 @@ static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *port)
return err;
}
- port->reg_base = devm_ioremap_resource(dev, ®s);
- if (IS_ERR(port->reg_base))
- return PTR_ERR(port->reg_base);
+ xilinx->reg_base = devm_ioremap_resource(dev, ®s);
+ if (IS_ERR(xilinx->reg_base))
+ return PTR_ERR(xilinx->reg_base);
- port->irq = irq_of_parse_and_map(node, 0);
- err = devm_request_irq(dev, port->irq, xilinx_pcie_intr_handler,
+ xilinx->irq = irq_of_parse_and_map(node, 0);
+ err = devm_request_irq(dev, xilinx->irq, xilinx_pcie_intr_handler,
IRQF_SHARED | IRQF_NO_THREAD,
- "xilinx-pcie", port);
+ "xilinx-pcie", xilinx);
if (err) {
- dev_err(dev, "unable to request irq %d\n", port->irq);
+ dev_err(dev, "unable to request irq %d\n", xilinx->irq);
return err;
}
@@ -627,7 +627,7 @@ static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *port)
*/
static int xilinx_pcie_probe(struct platform_device *pdev)
{
- struct xilinx_pcie_port *port;
+ struct xilinx_pcie_port *xilinx;
struct device *dev = &pdev->dev;
struct pci_bus *bus;
int err;
@@ -637,21 +637,21 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
if (!dev->of_node)
return -ENODEV;
- port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
- if (!port)
+ xilinx = devm_kzalloc(dev, sizeof(*xilinx), GFP_KERNEL);
+ if (!xilinx)
return -ENOMEM;
- port->dev = dev;
+ xilinx->dev = dev;
- err = xilinx_pcie_parse_dt(port);
+ err = xilinx_pcie_parse_dt(xilinx);
if (err) {
dev_err(dev, "Parsing DT failed\n");
return err;
}
- xilinx_pcie_init_port(port);
+ xilinx_pcie_init_port(xilinx);
- err = xilinx_pcie_init_irq_domain(port);
+ err = xilinx_pcie_init_irq_domain(xilinx);
if (err) {
dev_err(dev, "Failed creating IRQ Domain\n");
return err;
@@ -669,14 +669,14 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
goto error;
bus = pci_create_root_bus(&pdev->dev, 0,
- &xilinx_pcie_ops, port, &res);
+ &xilinx_pcie_ops, xilinx, &res);
if (!bus) {
err = -ENOMEM;
goto error;
}
#ifdef CONFIG_PCI_MSI
- xilinx_pcie_msi_chip.dev = port->dev;
+ xilinx_pcie_msi_chip.dev = xilinx->dev;
bus->msi = &xilinx_pcie_msi_chip;
#endif
pci_scan_child_bus(bus);
@@ -685,7 +685,7 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
#endif
pci_bus_add_devices(bus);
- platform_set_drvdata(pdev, port);
+ platform_set_drvdata(pdev, xilinx);
return 0;
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/9] PCI: xilinx: Rename accessors
2016-10-07 16:28 [PATCH 1/9] PCI: xilinx: Name private struct pointer "xilinx" consistently Bjorn Helgaas
@ 2016-10-07 16:28 ` Bjorn Helgaas
2016-10-07 16:29 ` [PATCH 3/9] PCI: xilinx: Swap order of xilinx_writel() reg/val arguments Bjorn Helgaas
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:28 UTC (permalink / raw)
To: Michal Simek, Sören Brinkmann; +Cc: linux-pci
Rename pcie_read() to xilinx_readl() and pcie_write() to xilinx_writel()
for consistency with other drivers. No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pcie-xilinx.c | 38 +++++++++++++++++++-------------------
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index 14e4187..f8e4c22 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -118,19 +118,19 @@ struct xilinx_pcie_port {
static DECLARE_BITMAP(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
-static inline u32 pcie_read(struct xilinx_pcie_port *xilinx, u32 reg)
+static inline u32 xilinx_readl(struct xilinx_pcie_port *xilinx, u32 reg)
{
return readl(xilinx->reg_base + reg);
}
-static inline void pcie_write(struct xilinx_pcie_port *xilinx, u32 val, u32 reg)
+static inline void xilinx_writel(struct xilinx_pcie_port *xilinx, u32 val, u32 reg)
{
writel(val, xilinx->reg_base + reg);
}
static inline bool xilinx_pcie_link_is_up(struct xilinx_pcie_port *xilinx)
{
- return (pcie_read(xilinx, XILINX_PCIE_REG_PSCR) &
+ return (xilinx_readl(xilinx, XILINX_PCIE_REG_PSCR) &
XILINX_PCIE_REG_PSCR_LNKUP) ? 1 : 0;
}
@@ -140,12 +140,12 @@ static inline bool xilinx_pcie_link_is_up(struct xilinx_pcie_port *xilinx)
*/
static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *xilinx)
{
- unsigned long val = pcie_read(xilinx, XILINX_PCIE_REG_RPEFR);
+ unsigned long val = xilinx_readl(xilinx, XILINX_PCIE_REG_RPEFR);
if (val & XILINX_PCIE_RPEFR_ERR_VALID) {
dev_dbg(xilinx->dev, "Requester ID %lu\n",
val & XILINX_PCIE_RPEFR_REQ_ID);
- pcie_write(xilinx, XILINX_PCIE_RPEFR_ALL_MASK,
+ xilinx_writel(xilinx, XILINX_PCIE_RPEFR_ALL_MASK,
XILINX_PCIE_REG_RPEFR);
}
}
@@ -343,8 +343,8 @@ static void xilinx_pcie_enable_msi(struct xilinx_pcie_port *xilinx)
xilinx->msi_pages = __get_free_pages(GFP_KERNEL, 0);
msg_addr = virt_to_phys((void *)xilinx->msi_pages);
- pcie_write(xilinx, 0x0, XILINX_PCIE_REG_MSIBASE1);
- pcie_write(xilinx, msg_addr, XILINX_PCIE_REG_MSIBASE2);
+ xilinx_writel(xilinx, 0x0, XILINX_PCIE_REG_MSIBASE1);
+ xilinx_writel(xilinx, msg_addr, XILINX_PCIE_REG_MSIBASE2);
}
/* INTx Functions */
@@ -386,8 +386,8 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
u32 val, mask, status, msi_data;
/* Read interrupt decode and mask registers */
- val = pcie_read(xilinx, XILINX_PCIE_REG_IDR);
- mask = pcie_read(xilinx, XILINX_PCIE_REG_IMR);
+ val = xilinx_readl(xilinx, XILINX_PCIE_REG_IDR);
+ mask = xilinx_readl(xilinx, XILINX_PCIE_REG_IMR);
status = val & mask;
if (!status)
@@ -425,7 +425,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
if (status & XILINX_PCIE_INTR_INTX) {
/* INTx interrupt received */
- val = pcie_read(xilinx, XILINX_PCIE_REG_RPIFR1);
+ val = xilinx_readl(xilinx, XILINX_PCIE_REG_RPIFR1);
/* Check whether interrupt valid */
if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
@@ -435,7 +435,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
if (!(val & XILINX_PCIE_RPIFR1_MSI_INTR)) {
/* Clear interrupt FIFO register 1 */
- pcie_write(xilinx, XILINX_PCIE_RPIFR1_ALL_MASK,
+ xilinx_writel(xilinx, XILINX_PCIE_RPIFR1_ALL_MASK,
XILINX_PCIE_REG_RPIFR1);
/* Handle INTx Interrupt */
@@ -448,7 +448,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
if (status & XILINX_PCIE_INTR_MSI) {
/* MSI Interrupt */
- val = pcie_read(xilinx, XILINX_PCIE_REG_RPIFR1);
+ val = xilinx_readl(xilinx, XILINX_PCIE_REG_RPIFR1);
if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
dev_warn(xilinx->dev, "RP Intr FIFO1 read error\n");
@@ -456,11 +456,11 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
}
if (val & XILINX_PCIE_RPIFR1_MSI_INTR) {
- msi_data = pcie_read(xilinx, XILINX_PCIE_REG_RPIFR2) &
+ msi_data = xilinx_readl(xilinx, XILINX_PCIE_REG_RPIFR2) &
XILINX_PCIE_RPIFR2_MSG_DATA;
/* Clear interrupt FIFO register 1 */
- pcie_write(xilinx, XILINX_PCIE_RPIFR1_ALL_MASK,
+ xilinx_writel(xilinx, XILINX_PCIE_RPIFR1_ALL_MASK,
XILINX_PCIE_REG_RPIFR1);
if (IS_ENABLED(CONFIG_PCI_MSI)) {
@@ -499,7 +499,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
error:
/* Clear the Interrupt Decode register */
- pcie_write(xilinx, status, XILINX_PCIE_REG_IDR);
+ xilinx_writel(xilinx, status, XILINX_PCIE_REG_IDR);
return IRQ_HANDLED;
}
@@ -560,19 +560,19 @@ static void xilinx_pcie_init_port(struct xilinx_pcie_port *xilinx)
dev_info(xilinx->dev, "PCIe Link is DOWN\n");
/* Disable all interrupts */
- pcie_write(xilinx, ~XILINX_PCIE_IDR_ALL_MASK,
+ xilinx_writel(xilinx, ~XILINX_PCIE_IDR_ALL_MASK,
XILINX_PCIE_REG_IMR);
/* Clear pending interrupts */
- pcie_write(xilinx, pcie_read(xilinx, XILINX_PCIE_REG_IDR) &
+ xilinx_writel(xilinx, xilinx_readl(xilinx, XILINX_PCIE_REG_IDR) &
XILINX_PCIE_IMR_ALL_MASK,
XILINX_PCIE_REG_IDR);
/* Enable all interrupts */
- pcie_write(xilinx, XILINX_PCIE_IMR_ALL_MASK, XILINX_PCIE_REG_IMR);
+ xilinx_writel(xilinx, XILINX_PCIE_IMR_ALL_MASK, XILINX_PCIE_REG_IMR);
/* Enable the Bridge enable bit */
- pcie_write(xilinx, pcie_read(xilinx, XILINX_PCIE_REG_RPSC) |
+ xilinx_writel(xilinx, xilinx_readl(xilinx, XILINX_PCIE_REG_RPSC) |
XILINX_PCIE_REG_RPSC_BEN,
XILINX_PCIE_REG_RPSC);
}
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/9] PCI: xilinx: Swap order of xilinx_writel() reg/val arguments
2016-10-07 16:28 [PATCH 1/9] PCI: xilinx: Name private struct pointer "xilinx" consistently Bjorn Helgaas
2016-10-07 16:28 ` [PATCH 2/9] PCI: xilinx: Rename accessors Bjorn Helgaas
@ 2016-10-07 16:29 ` Bjorn Helgaas
2016-10-07 16:29 ` [PATCH 4/9] PCI: xilinx: Add local struct device pointers Bjorn Helgaas
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:29 UTC (permalink / raw)
To: Michal Simek, Sören Brinkmann; +Cc: linux-pci
Swap order of xilinx_writel() arguments to match the "dev, pos, val"
order used by pci_write_config_word() and other drivers. No functional
change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pcie-xilinx.c | 39 +++++++++++++++++++--------------------
1 file changed, 19 insertions(+), 20 deletions(-)
diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index f8e4c22..b840737 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -123,7 +123,8 @@ static inline u32 xilinx_readl(struct xilinx_pcie_port *xilinx, u32 reg)
return readl(xilinx->reg_base + reg);
}
-static inline void xilinx_writel(struct xilinx_pcie_port *xilinx, u32 val, u32 reg)
+static inline void xilinx_writel(struct xilinx_pcie_port *xilinx, u32 reg,
+ u32 val)
{
writel(val, xilinx->reg_base + reg);
}
@@ -145,8 +146,8 @@ static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *xilinx)
if (val & XILINX_PCIE_RPEFR_ERR_VALID) {
dev_dbg(xilinx->dev, "Requester ID %lu\n",
val & XILINX_PCIE_RPEFR_REQ_ID);
- xilinx_writel(xilinx, XILINX_PCIE_RPEFR_ALL_MASK,
- XILINX_PCIE_REG_RPEFR);
+ xilinx_writel(xilinx, XILINX_PCIE_REG_RPEFR,
+ XILINX_PCIE_RPEFR_ALL_MASK);
}
}
@@ -343,8 +344,8 @@ static void xilinx_pcie_enable_msi(struct xilinx_pcie_port *xilinx)
xilinx->msi_pages = __get_free_pages(GFP_KERNEL, 0);
msg_addr = virt_to_phys((void *)xilinx->msi_pages);
- xilinx_writel(xilinx, 0x0, XILINX_PCIE_REG_MSIBASE1);
- xilinx_writel(xilinx, msg_addr, XILINX_PCIE_REG_MSIBASE2);
+ xilinx_writel(xilinx, XILINX_PCIE_REG_MSIBASE1, 0);
+ xilinx_writel(xilinx, XILINX_PCIE_REG_MSIBASE2, msg_addr);
}
/* INTx Functions */
@@ -435,8 +436,8 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
if (!(val & XILINX_PCIE_RPIFR1_MSI_INTR)) {
/* Clear interrupt FIFO register 1 */
- xilinx_writel(xilinx, XILINX_PCIE_RPIFR1_ALL_MASK,
- XILINX_PCIE_REG_RPIFR1);
+ xilinx_writel(xilinx, XILINX_PCIE_REG_RPIFR1,
+ XILINX_PCIE_RPIFR1_ALL_MASK);
/* Handle INTx Interrupt */
val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
@@ -460,8 +461,8 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
XILINX_PCIE_RPIFR2_MSG_DATA;
/* Clear interrupt FIFO register 1 */
- xilinx_writel(xilinx, XILINX_PCIE_RPIFR1_ALL_MASK,
- XILINX_PCIE_REG_RPIFR1);
+ xilinx_writel(xilinx, XILINX_PCIE_REG_RPIFR1,
+ XILINX_PCIE_RPIFR1_ALL_MASK);
if (IS_ENABLED(CONFIG_PCI_MSI)) {
/* Handle MSI Interrupt */
@@ -499,8 +500,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
error:
/* Clear the Interrupt Decode register */
- xilinx_writel(xilinx, status, XILINX_PCIE_REG_IDR);
-
+ xilinx_writel(xilinx, XILINX_PCIE_REG_IDR, status);
return IRQ_HANDLED;
}
@@ -560,21 +560,20 @@ static void xilinx_pcie_init_port(struct xilinx_pcie_port *xilinx)
dev_info(xilinx->dev, "PCIe Link is DOWN\n");
/* Disable all interrupts */
- xilinx_writel(xilinx, ~XILINX_PCIE_IDR_ALL_MASK,
- XILINX_PCIE_REG_IMR);
+ xilinx_writel(xilinx, XILINX_PCIE_REG_IMR, ~XILINX_PCIE_IDR_ALL_MASK);
/* Clear pending interrupts */
- xilinx_writel(xilinx, xilinx_readl(xilinx, XILINX_PCIE_REG_IDR) &
- XILINX_PCIE_IMR_ALL_MASK,
- XILINX_PCIE_REG_IDR);
+ xilinx_writel(xilinx, XILINX_PCIE_REG_IDR,
+ xilinx_readl(xilinx, XILINX_PCIE_REG_IDR) &
+ XILINX_PCIE_IMR_ALL_MASK);
/* Enable all interrupts */
- xilinx_writel(xilinx, XILINX_PCIE_IMR_ALL_MASK, XILINX_PCIE_REG_IMR);
+ xilinx_writel(xilinx, XILINX_PCIE_REG_IMR, XILINX_PCIE_IMR_ALL_MASK);
/* Enable the Bridge enable bit */
- xilinx_writel(xilinx, xilinx_readl(xilinx, XILINX_PCIE_REG_RPSC) |
- XILINX_PCIE_REG_RPSC_BEN,
- XILINX_PCIE_REG_RPSC);
+ xilinx_writel(xilinx, XILINX_PCIE_REG_RPSC,
+ xilinx_readl(xilinx, XILINX_PCIE_REG_RPSC) |
+ XILINX_PCIE_REG_RPSC_BEN);
}
/**
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 4/9] PCI: xilinx: Add local struct device pointers
2016-10-07 16:28 [PATCH 1/9] PCI: xilinx: Name private struct pointer "xilinx" consistently Bjorn Helgaas
2016-10-07 16:28 ` [PATCH 2/9] PCI: xilinx: Rename accessors Bjorn Helgaas
2016-10-07 16:29 ` [PATCH 3/9] PCI: xilinx: Swap order of xilinx_writel() reg/val arguments Bjorn Helgaas
@ 2016-10-07 16:29 ` Bjorn Helgaas
2016-10-07 16:29 ` [PATCH 5/9] PCI: xilinx: Remove unused platform data Bjorn Helgaas
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:29 UTC (permalink / raw)
To: Michal Simek, Sören Brinkmann; +Cc: linux-pci
Use a local "struct device *dev" for brevity and consistency with other
drivers. No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pcie-xilinx.c | 47 +++++++++++++++++++++-------------------
1 file changed, 25 insertions(+), 22 deletions(-)
diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index b840737..44a2652 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -384,6 +384,7 @@ static const struct irq_domain_ops intx_domain_ops = {
static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
{
struct xilinx_pcie_port *xilinx = (struct xilinx_pcie_port *)data;
+ struct device *dev = xilinx->dev;
u32 val, mask, status, msi_data;
/* Read interrupt decode and mask registers */
@@ -395,32 +396,32 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
return IRQ_NONE;
if (status & XILINX_PCIE_INTR_LINK_DOWN)
- dev_warn(xilinx->dev, "Link Down\n");
+ dev_warn(dev, "Link Down\n");
if (status & XILINX_PCIE_INTR_ECRC_ERR)
- dev_warn(xilinx->dev, "ECRC failed\n");
+ dev_warn(dev, "ECRC failed\n");
if (status & XILINX_PCIE_INTR_STR_ERR)
- dev_warn(xilinx->dev, "Streaming error\n");
+ dev_warn(dev, "Streaming error\n");
if (status & XILINX_PCIE_INTR_HOT_RESET)
- dev_info(xilinx->dev, "Hot reset\n");
+ dev_info(dev, "Hot reset\n");
if (status & XILINX_PCIE_INTR_CFG_TIMEOUT)
- dev_warn(xilinx->dev, "ECAM access timeout\n");
+ dev_warn(dev, "ECAM access timeout\n");
if (status & XILINX_PCIE_INTR_CORRECTABLE) {
- dev_warn(xilinx->dev, "Correctable error message\n");
+ dev_warn(dev, "Correctable error message\n");
xilinx_pcie_clear_err_interrupts(xilinx);
}
if (status & XILINX_PCIE_INTR_NONFATAL) {
- dev_warn(xilinx->dev, "Non fatal error message\n");
+ dev_warn(dev, "Non fatal error message\n");
xilinx_pcie_clear_err_interrupts(xilinx);
}
if (status & XILINX_PCIE_INTR_FATAL) {
- dev_warn(xilinx->dev, "Fatal error message\n");
+ dev_warn(dev, "Fatal error message\n");
xilinx_pcie_clear_err_interrupts(xilinx);
}
@@ -430,7 +431,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
/* Check whether interrupt valid */
if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
- dev_warn(xilinx->dev, "RP Intr FIFO1 read error\n");
+ dev_warn(dev, "RP Intr FIFO1 read error\n");
goto error;
}
@@ -452,7 +453,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
val = xilinx_readl(xilinx, XILINX_PCIE_REG_RPIFR1);
if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
- dev_warn(xilinx->dev, "RP Intr FIFO1 read error\n");
+ dev_warn(dev, "RP Intr FIFO1 read error\n");
goto error;
}
@@ -472,31 +473,31 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
}
if (status & XILINX_PCIE_INTR_SLV_UNSUPP)
- dev_warn(xilinx->dev, "Slave unsupported request\n");
+ dev_warn(dev, "Slave unsupported request\n");
if (status & XILINX_PCIE_INTR_SLV_UNEXP)
- dev_warn(xilinx->dev, "Slave unexpected completion\n");
+ dev_warn(dev, "Slave unexpected completion\n");
if (status & XILINX_PCIE_INTR_SLV_COMPL)
- dev_warn(xilinx->dev, "Slave completion timeout\n");
+ dev_warn(dev, "Slave completion timeout\n");
if (status & XILINX_PCIE_INTR_SLV_ERRP)
- dev_warn(xilinx->dev, "Slave Error Poison\n");
+ dev_warn(dev, "Slave Error Poison\n");
if (status & XILINX_PCIE_INTR_SLV_CMPABT)
- dev_warn(xilinx->dev, "Slave Completer Abort\n");
+ dev_warn(dev, "Slave Completer Abort\n");
if (status & XILINX_PCIE_INTR_SLV_ILLBUR)
- dev_warn(xilinx->dev, "Slave Illegal Burst\n");
+ dev_warn(dev, "Slave Illegal Burst\n");
if (status & XILINX_PCIE_INTR_MST_DECERR)
- dev_warn(xilinx->dev, "Master decode error\n");
+ dev_warn(dev, "Master decode error\n");
if (status & XILINX_PCIE_INTR_MST_SLVERR)
- dev_warn(xilinx->dev, "Master slave error\n");
+ dev_warn(dev, "Master slave error\n");
if (status & XILINX_PCIE_INTR_MST_ERRP)
- dev_warn(xilinx->dev, "Master error poison\n");
+ dev_warn(dev, "Master error poison\n");
error:
/* Clear the Interrupt Decode register */
@@ -554,10 +555,12 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *xilinx)
*/
static void xilinx_pcie_init_port(struct xilinx_pcie_port *xilinx)
{
+ struct device *dev = xilinx->dev;
+
if (xilinx_pcie_link_is_up(xilinx))
- dev_info(xilinx->dev, "PCIe Link is UP\n");
+ dev_info(dev, "PCIe Link is UP\n");
else
- dev_info(xilinx->dev, "PCIe Link is DOWN\n");
+ dev_info(dev, "PCIe Link is DOWN\n");
/* Disable all interrupts */
xilinx_writel(xilinx, XILINX_PCIE_REG_IMR, ~XILINX_PCIE_IDR_ALL_MASK);
@@ -626,8 +629,8 @@ static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *xilinx)
*/
static int xilinx_pcie_probe(struct platform_device *pdev)
{
- struct xilinx_pcie_port *xilinx;
struct device *dev = &pdev->dev;
+ struct xilinx_pcie_port *xilinx;
struct pci_bus *bus;
int err;
resource_size_t iobase = 0;
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 5/9] PCI: xilinx: Remove unused platform data
2016-10-07 16:28 [PATCH 1/9] PCI: xilinx: Name private struct pointer "xilinx" consistently Bjorn Helgaas
` (2 preceding siblings ...)
2016-10-07 16:29 ` [PATCH 4/9] PCI: xilinx: Add local struct device pointers Bjorn Helgaas
@ 2016-10-07 16:29 ` Bjorn Helgaas
2016-10-07 16:29 ` [PATCH 6/9] PCI: xilinx-nwl: Name private struct pointer "nwl" consistently Bjorn Helgaas
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:29 UTC (permalink / raw)
To: Michal Simek, Sören Brinkmann; +Cc: linux-pci
The xilinx driver never uses the platform drvdata pointer, so don't
bother setting it. No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pcie-xilinx.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index 44a2652..08ec61b 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -687,8 +687,6 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
#endif
pci_bus_add_devices(bus);
- platform_set_drvdata(pdev, xilinx);
-
return 0;
error:
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 6/9] PCI: xilinx-nwl: Name private struct pointer "nwl" consistently
2016-10-07 16:28 [PATCH 1/9] PCI: xilinx: Name private struct pointer "xilinx" consistently Bjorn Helgaas
` (3 preceding siblings ...)
2016-10-07 16:29 ` [PATCH 5/9] PCI: xilinx: Remove unused platform data Bjorn Helgaas
@ 2016-10-07 16:29 ` Bjorn Helgaas
2016-10-07 16:29 ` [PATCH 7/9] PCI: xilinx-nwl: Swap order of nwl_bridge_writel() reg/val arguments Bjorn Helgaas
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:29 UTC (permalink / raw)
To: Michal Simek, Sören Brinkmann; +Cc: linux-pci
Use a device-specific name, "nwl", for struct nwl_pcie pointers
to hint that this is device-specific information. No functional change
intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pcie-xilinx-nwl.c | 318 ++++++++++++++++++------------------
1 file changed, 159 insertions(+), 159 deletions(-)
diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c
index 67eae41..2c72c73 100644
--- a/drivers/pci/host/pcie-xilinx-nwl.c
+++ b/drivers/pci/host/pcie-xilinx-nwl.c
@@ -186,57 +186,57 @@ struct nwl_pcie {
struct irq_domain *legacy_irq_domain;
};
-static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)
+static inline u32 nwl_bridge_readl(struct nwl_pcie *nwl, u32 off)
{
- return readl(pcie->breg_base + off);
+ return readl(nwl->breg_base + off);
}
-static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)
+static inline void nwl_bridge_writel(struct nwl_pcie *nwl, u32 val, u32 off)
{
- writel(val, pcie->breg_base + off);
+ writel(val, nwl->breg_base + off);
}
-static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
+static bool nwl_pcie_link_up(struct nwl_pcie *nwl)
{
- if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
+ if (readl(nwl->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
return true;
return false;
}
-static bool nwl_phy_link_up(struct nwl_pcie *pcie)
+static bool nwl_phy_link_up(struct nwl_pcie *nwl)
{
- if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)
+ if (readl(nwl->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)
return true;
return false;
}
-static int nwl_wait_for_link(struct nwl_pcie *pcie)
+static int nwl_wait_for_link(struct nwl_pcie *nwl)
{
int retries;
/* check if the link is up or not */
for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
- if (nwl_phy_link_up(pcie))
+ if (nwl_phy_link_up(nwl))
return 0;
usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
}
- dev_err(pcie->dev, "PHY link never came up\n");
+ dev_err(nwl->dev, "PHY link never came up\n");
return -ETIMEDOUT;
}
static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
{
- struct nwl_pcie *pcie = bus->sysdata;
+ struct nwl_pcie *nwl = bus->sysdata;
/* Check link before accessing downstream ports */
- if (bus->number != pcie->root_busno) {
- if (!nwl_pcie_link_up(pcie))
+ if (bus->number != nwl->root_busno) {
+ if (!nwl_pcie_link_up(nwl))
return false;
}
/* Only one device down on each root port */
- if (bus->number == pcie->root_busno && devfn > 0)
+ if (bus->number == nwl->root_busno && devfn > 0)
return false;
return true;
@@ -255,7 +255,7 @@ static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
int where)
{
- struct nwl_pcie *pcie = bus->sysdata;
+ struct nwl_pcie *nwl = bus->sysdata;
int relbus;
if (!nwl_pcie_valid_device(bus, devfn))
@@ -264,7 +264,7 @@ static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
relbus = (bus->number << ECAM_BUS_LOC_SHIFT) |
(devfn << ECAM_DEV_LOC_SHIFT);
- return pcie->ecam_base + relbus + where;
+ return nwl->ecam_base + relbus + where;
}
/* PCIe operations */
@@ -276,58 +276,58 @@ static struct pci_ops nwl_pcie_ops = {
static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
{
- struct nwl_pcie *pcie = data;
+ struct nwl_pcie *nwl = data;
u32 misc_stat;
/* Checking for misc interrupts */
- misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
+ misc_stat = nwl_bridge_readl(nwl, MSGF_MISC_STATUS) &
MSGF_MISC_SR_MASKALL;
if (!misc_stat)
return IRQ_NONE;
if (misc_stat & MSGF_MISC_SR_RXMSG_OVER)
- dev_err(pcie->dev, "Received Message FIFO Overflow\n");
+ dev_err(nwl->dev, "Received Message FIFO Overflow\n");
if (misc_stat & MSGF_MISC_SR_SLAVE_ERR)
- dev_err(pcie->dev, "Slave error\n");
+ dev_err(nwl->dev, "Slave error\n");
if (misc_stat & MSGF_MISC_SR_MASTER_ERR)
- dev_err(pcie->dev, "Master error\n");
+ dev_err(nwl->dev, "Master error\n");
if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR)
- dev_err(pcie->dev,
+ dev_err(nwl->dev,
"In Misc Ingress address translation error\n");
if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR)
- dev_err(pcie->dev,
+ dev_err(nwl->dev,
"In Misc Egress address translation error\n");
if (misc_stat & MSGF_MISC_SR_FATAL_AER)
- dev_err(pcie->dev, "Fatal Error in AER Capability\n");
+ dev_err(nwl->dev, "Fatal Error in AER Capability\n");
if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER)
- dev_err(pcie->dev, "Non-Fatal Error in AER Capability\n");
+ dev_err(nwl->dev, "Non-Fatal Error in AER Capability\n");
if (misc_stat & MSGF_MISC_SR_CORR_AER)
- dev_err(pcie->dev, "Correctable Error in AER Capability\n");
+ dev_err(nwl->dev, "Correctable Error in AER Capability\n");
if (misc_stat & MSGF_MISC_SR_UR_DETECT)
- dev_err(pcie->dev, "Unsupported request Detected\n");
+ dev_err(nwl->dev, "Unsupported request Detected\n");
if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV)
- dev_err(pcie->dev, "Non-Fatal Error Detected\n");
+ dev_err(nwl->dev, "Non-Fatal Error Detected\n");
if (misc_stat & MSGF_MISC_SR_FATAL_DEV)
- dev_err(pcie->dev, "Fatal Error Detected\n");
+ dev_err(nwl->dev, "Fatal Error Detected\n");
if (misc_stat & MSGF_MSIC_SR_LINK_AUTO_BWIDTH)
- dev_info(pcie->dev, "Link Autonomous Bandwidth Management Status bit set\n");
+ dev_info(nwl->dev, "Link Autonomous Bandwidth Management Status bit set\n");
if (misc_stat & MSGF_MSIC_SR_LINK_BWIDTH)
- dev_info(pcie->dev, "Link Bandwidth Management Status bit set\n");
+ dev_info(nwl->dev, "Link Bandwidth Management Status bit set\n");
/* Clear misc interrupt status */
- nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);
+ nwl_bridge_writel(nwl, misc_stat, MSGF_MISC_STATUS);
return IRQ_HANDLED;
}
@@ -335,18 +335,18 @@ static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
static void nwl_pcie_leg_handler(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
- struct nwl_pcie *pcie;
+ struct nwl_pcie *nwl;
unsigned long status;
u32 bit;
u32 virq;
chained_irq_enter(chip, desc);
- pcie = irq_desc_get_handler_data(desc);
+ nwl = irq_desc_get_handler_data(desc);
- while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
+ while ((status = nwl_bridge_readl(nwl, MSGF_LEG_STATUS) &
MSGF_LEG_SR_MASKALL) != 0) {
for_each_set_bit(bit, &status, INTX_NUM) {
- virq = irq_find_mapping(pcie->legacy_irq_domain,
+ virq = irq_find_mapping(nwl->legacy_irq_domain,
bit + 1);
if (virq)
generic_handle_irq(virq);
@@ -356,18 +356,18 @@ static void nwl_pcie_leg_handler(struct irq_desc *desc)
chained_irq_exit(chip, desc);
}
-static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)
+static void nwl_pcie_handle_msi_irq(struct nwl_pcie *nwl, u32 status_reg)
{
struct nwl_msi *msi;
unsigned long status;
u32 bit;
u32 virq;
- msi = &pcie->msi;
+ msi = &nwl->msi;
- while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {
+ while ((status = nwl_bridge_readl(nwl, status_reg)) != 0) {
for_each_set_bit(bit, &status, 32) {
- nwl_bridge_writel(pcie, 1 << bit, status_reg);
+ nwl_bridge_writel(nwl, 1 << bit, status_reg);
virq = irq_find_mapping(msi->dev_domain, bit);
if (virq)
generic_handle_irq(virq);
@@ -378,20 +378,20 @@ static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)
static void nwl_pcie_msi_handler_high(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
- struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
+ struct nwl_pcie *nwl = irq_desc_get_handler_data(desc);
chained_irq_enter(chip, desc);
- nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI);
+ nwl_pcie_handle_msi_irq(nwl, MSGF_MSI_STATUS_HI);
chained_irq_exit(chip, desc);
}
static void nwl_pcie_msi_handler_low(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
- struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
+ struct nwl_pcie *nwl = irq_desc_get_handler_data(desc);
chained_irq_enter(chip, desc);
- nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO);
+ nwl_pcie_handle_msi_irq(nwl, MSGF_MSI_STATUS_LO);
chained_irq_exit(chip, desc);
}
@@ -427,8 +427,8 @@ static struct msi_domain_info nwl_msi_domain_info = {
static void nwl_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
{
- struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
- phys_addr_t msi_addr = pcie->phys_pcie_reg_base;
+ struct nwl_pcie *nwl = irq_data_get_irq_chip_data(data);
+ phys_addr_t msi_addr = nwl->phys_pcie_reg_base;
msg->address_lo = lower_32_bits(msi_addr);
msg->address_hi = upper_32_bits(msi_addr);
@@ -450,8 +450,8 @@ static struct irq_chip nwl_irq_chip = {
static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs, void *args)
{
- struct nwl_pcie *pcie = domain->host_data;
- struct nwl_msi *msi = &pcie->msi;
+ struct nwl_pcie *nwl = domain->host_data;
+ struct nwl_msi *msi = &nwl->msi;
int bit;
int i;
@@ -478,8 +478,8 @@ static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs)
{
struct irq_data *data = irq_domain_get_irq_data(domain, virq);
- struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
- struct nwl_msi *msi = &pcie->msi;
+ struct nwl_pcie *nwl = irq_data_get_irq_chip_data(data);
+ struct nwl_msi *msi = &nwl->msi;
mutex_lock(&msi->lock);
bitmap_clear(msi->bitmap, data->hwirq, nr_irqs);
@@ -491,23 +491,23 @@ static const struct irq_domain_ops dev_msi_domain_ops = {
.free = nwl_irq_domain_free,
};
-static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)
+static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *nwl)
{
#ifdef CONFIG_PCI_MSI
- struct fwnode_handle *fwnode = of_node_to_fwnode(pcie->dev->of_node);
- struct nwl_msi *msi = &pcie->msi;
+ struct fwnode_handle *fwnode = of_node_to_fwnode(nwl->dev->of_node);
+ struct nwl_msi *msi = &nwl->msi;
msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR,
- &dev_msi_domain_ops, pcie);
+ &dev_msi_domain_ops, nwl);
if (!msi->dev_domain) {
- dev_err(pcie->dev, "failed to create dev IRQ domain\n");
+ dev_err(nwl->dev, "failed to create dev IRQ domain\n");
return -ENOMEM;
}
msi->msi_domain = pci_msi_create_irq_domain(fwnode,
&nwl_msi_domain_info,
msi->dev_domain);
if (!msi->msi_domain) {
- dev_err(pcie->dev, "failed to create msi IRQ domain\n");
+ dev_err(nwl->dev, "failed to create msi IRQ domain\n");
irq_domain_remove(msi->dev_domain);
return -ENOMEM;
}
@@ -515,35 +515,35 @@ static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)
return 0;
}
-static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)
+static int nwl_pcie_init_irq_domain(struct nwl_pcie *nwl)
{
- struct device_node *node = pcie->dev->of_node;
+ struct device_node *node = nwl->dev->of_node;
struct device_node *legacy_intc_node;
legacy_intc_node = of_get_next_child(node, NULL);
if (!legacy_intc_node) {
- dev_err(pcie->dev, "No legacy intc node found\n");
+ dev_err(nwl->dev, "No legacy intc node found\n");
return -EINVAL;
}
- pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node,
+ nwl->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node,
INTX_NUM,
&legacy_domain_ops,
- pcie);
+ nwl);
- if (!pcie->legacy_irq_domain) {
- dev_err(pcie->dev, "failed to create IRQ domain\n");
+ if (!nwl->legacy_irq_domain) {
+ dev_err(nwl->dev, "failed to create IRQ domain\n");
return -ENOMEM;
}
- nwl_pcie_init_msi_irq_domain(pcie);
+ nwl_pcie_init_msi_irq_domain(nwl);
return 0;
}
-static int nwl_pcie_enable_msi(struct nwl_pcie *pcie, struct pci_bus *bus)
+static int nwl_pcie_enable_msi(struct nwl_pcie *nwl, struct pci_bus *bus)
{
- struct platform_device *pdev = to_platform_device(pcie->dev);
- struct nwl_msi *msi = &pcie->msi;
+ struct platform_device *pdev = to_platform_device(nwl->dev);
+ struct nwl_msi *msi = &nwl->msi;
unsigned long base;
int ret;
int size = BITS_TO_LONGS(INT_PCI_MSI_NR) * sizeof(long);
@@ -563,7 +563,7 @@ static int nwl_pcie_enable_msi(struct nwl_pcie *pcie, struct pci_bus *bus)
}
irq_set_chained_handler_and_data(msi->irq_msi1,
- nwl_pcie_msi_handler_high, pcie);
+ nwl_pcie_msi_handler_high, nwl);
/* Get msi_0 IRQ number */
msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0");
@@ -574,50 +574,50 @@ static int nwl_pcie_enable_msi(struct nwl_pcie *pcie, struct pci_bus *bus)
}
irq_set_chained_handler_and_data(msi->irq_msi0,
- nwl_pcie_msi_handler_low, pcie);
+ nwl_pcie_msi_handler_low, nwl);
/* Check for msii_present bit */
- ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;
+ ret = nwl_bridge_readl(nwl, I_MSII_CAPABILITIES) & MSII_PRESENT;
if (!ret) {
- dev_err(pcie->dev, "MSI not present\n");
+ dev_err(nwl->dev, "MSI not present\n");
ret = -EIO;
goto err;
}
/* Enable MSII */
- nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
+ nwl_bridge_writel(nwl, nwl_bridge_readl(nwl, I_MSII_CONTROL) |
MSII_ENABLE, I_MSII_CONTROL);
/* Enable MSII status */
- nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
+ nwl_bridge_writel(nwl, nwl_bridge_readl(nwl, I_MSII_CONTROL) |
MSII_STATUS_ENABLE, I_MSII_CONTROL);
/* setup AFI/FPCI range */
- base = pcie->phys_pcie_reg_base;
- nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);
- nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);
+ base = nwl->phys_pcie_reg_base;
+ nwl_bridge_writel(nwl, lower_32_bits(base), I_MSII_BASE_LO);
+ nwl_bridge_writel(nwl, upper_32_bits(base), I_MSII_BASE_HI);
/*
* For high range MSI interrupts: disable, clear any pending,
* and enable
*/
- nwl_bridge_writel(pcie, (u32)~MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
+ nwl_bridge_writel(nwl, (u32)~MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
- nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) &
+ nwl_bridge_writel(nwl, nwl_bridge_readl(nwl, MSGF_MSI_STATUS_HI) &
MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI);
- nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
+ nwl_bridge_writel(nwl, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
/*
* For low range MSI interrupts: disable, clear any pending,
* and enable
*/
- nwl_bridge_writel(pcie, (u32)~MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
+ nwl_bridge_writel(nwl, (u32)~MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
- nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &
+ nwl_bridge_writel(nwl, nwl_bridge_readl(nwl, MSGF_MSI_STATUS_LO) &
MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO);
- nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
+ nwl_bridge_writel(nwl, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
return 0;
err:
@@ -626,163 +626,163 @@ err:
return ret;
}
-static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
+static int nwl_pcie_bridge_init(struct nwl_pcie *nwl)
{
- struct platform_device *pdev = to_platform_device(pcie->dev);
+ struct platform_device *pdev = to_platform_device(nwl->dev);
u32 breg_val, ecam_val, first_busno = 0;
int err;
- breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
+ breg_val = nwl_bridge_readl(nwl, E_BREG_CAPABILITIES) & BREG_PRESENT;
if (!breg_val) {
- dev_err(pcie->dev, "BREG is not present\n");
+ dev_err(nwl->dev, "BREG is not present\n");
return breg_val;
}
/* Write bridge_off to breg base */
- nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),
+ nwl_bridge_writel(nwl, lower_32_bits(nwl->phys_breg_base),
E_BREG_BASE_LO);
- nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),
+ nwl_bridge_writel(nwl, upper_32_bits(nwl->phys_breg_base),
E_BREG_BASE_HI);
/* Enable BREG */
- nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,
+ nwl_bridge_writel(nwl, ~BREG_ENABLE_FORCE & BREG_ENABLE,
E_BREG_CONTROL);
/* Disable DMA channel registers */
- nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |
+ nwl_bridge_writel(nwl, nwl_bridge_readl(nwl, BRCFG_PCIE_RX0) |
CFG_DMA_REG_BAR, BRCFG_PCIE_RX0);
/* Enable Ingress subtractive decode translation */
- nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);
+ nwl_bridge_writel(nwl, SET_ISUB_CONTROL, I_ISUB_CONTROL);
/* Enable msg filtering details */
- nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,
+ nwl_bridge_writel(nwl, CFG_ENABLE_MSG_FILTER_MASK,
BRCFG_PCIE_RX_MSG_FILTER);
- err = nwl_wait_for_link(pcie);
+ err = nwl_wait_for_link(nwl);
if (err)
return err;
- ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;
+ ecam_val = nwl_bridge_readl(nwl, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;
if (!ecam_val) {
- dev_err(pcie->dev, "ECAM is not present\n");
+ dev_err(nwl->dev, "ECAM is not present\n");
return ecam_val;
}
/* Enable ECAM */
- nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
+ nwl_bridge_writel(nwl, nwl_bridge_readl(nwl, E_ECAM_CONTROL) |
E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
- nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
- (pcie->ecam_value << E_ECAM_SIZE_SHIFT),
+ nwl_bridge_writel(nwl, nwl_bridge_readl(nwl, E_ECAM_CONTROL) |
+ (nwl->ecam_value << E_ECAM_SIZE_SHIFT),
E_ECAM_CONTROL);
- nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
+ nwl_bridge_writel(nwl, lower_32_bits(nwl->phys_ecam_base),
E_ECAM_BASE_LO);
- nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
+ nwl_bridge_writel(nwl, upper_32_bits(nwl->phys_ecam_base),
E_ECAM_BASE_HI);
/* Get bus range */
- ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);
- pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;
+ ecam_val = nwl_bridge_readl(nwl, E_ECAM_CONTROL);
+ nwl->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;
/* Write primary, secondary and subordinate bus numbers */
ecam_val = first_busno;
ecam_val |= (first_busno + 1) << 8;
- ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT);
- writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS));
+ ecam_val |= (nwl->last_busno << E_ECAM_SIZE_SHIFT);
+ writel(ecam_val, (nwl->ecam_base + PCI_PRIMARY_BUS));
- if (nwl_pcie_link_up(pcie))
- dev_info(pcie->dev, "Link is UP\n");
+ if (nwl_pcie_link_up(nwl))
+ dev_info(nwl->dev, "Link is UP\n");
else
- dev_info(pcie->dev, "Link is DOWN\n");
+ dev_info(nwl->dev, "Link is DOWN\n");
/* Get misc IRQ number */
- pcie->irq_misc = platform_get_irq_byname(pdev, "misc");
- if (pcie->irq_misc < 0) {
+ nwl->irq_misc = platform_get_irq_byname(pdev, "misc");
+ if (nwl->irq_misc < 0) {
dev_err(&pdev->dev, "failed to get misc IRQ %d\n",
- pcie->irq_misc);
+ nwl->irq_misc);
return -EINVAL;
}
- err = devm_request_irq(pcie->dev, pcie->irq_misc,
+ err = devm_request_irq(nwl->dev, nwl->irq_misc,
nwl_pcie_misc_handler, IRQF_SHARED,
- "nwl_pcie:misc", pcie);
+ "nwl_pcie:misc", nwl);
if (err) {
- dev_err(pcie->dev, "fail to register misc IRQ#%d\n",
- pcie->irq_misc);
+ dev_err(nwl->dev, "fail to register misc IRQ#%d\n",
+ nwl->irq_misc);
return err;
}
/* Disable all misc interrupts */
- nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
+ nwl_bridge_writel(nwl, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
/* Clear pending misc interrupts */
- nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
+ nwl_bridge_writel(nwl, nwl_bridge_readl(nwl, MSGF_MISC_STATUS) &
MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS);
/* Enable all misc interrupts */
- nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
+ nwl_bridge_writel(nwl, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
/* Disable all legacy interrupts */
- nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
+ nwl_bridge_writel(nwl, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
/* Clear pending legacy interrupts */
- nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
+ nwl_bridge_writel(nwl, nwl_bridge_readl(nwl, MSGF_LEG_STATUS) &
MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);
/* Enable all legacy interrupts */
- nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
+ nwl_bridge_writel(nwl, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
/* Enable the bridge config interrupt */
- nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |
+ nwl_bridge_writel(nwl, nwl_bridge_readl(nwl, BRCFG_INTERRUPT) |
BRCFG_INTERRUPT_MASK, BRCFG_INTERRUPT);
return 0;
}
-static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
+static int nwl_pcie_parse_dt(struct nwl_pcie *nwl,
struct platform_device *pdev)
{
- struct device_node *node = pcie->dev->of_node;
+ struct device_node *node = nwl->dev->of_node;
struct resource *res;
const char *type;
/* Check for device type */
type = of_get_property(node, "device_type", NULL);
if (!type || strcmp(type, "pci")) {
- dev_err(pcie->dev, "invalid \"device_type\" %s\n", type);
+ dev_err(nwl->dev, "invalid \"device_type\" %s\n", type);
return -EINVAL;
}
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
- pcie->breg_base = devm_ioremap_resource(pcie->dev, res);
- if (IS_ERR(pcie->breg_base))
- return PTR_ERR(pcie->breg_base);
- pcie->phys_breg_base = res->start;
+ nwl->breg_base = devm_ioremap_resource(nwl->dev, res);
+ if (IS_ERR(nwl->breg_base))
+ return PTR_ERR(nwl->breg_base);
+ nwl->phys_breg_base = res->start;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg");
- pcie->pcireg_base = devm_ioremap_resource(pcie->dev, res);
- if (IS_ERR(pcie->pcireg_base))
- return PTR_ERR(pcie->pcireg_base);
- pcie->phys_pcie_reg_base = res->start;
+ nwl->pcireg_base = devm_ioremap_resource(nwl->dev, res);
+ if (IS_ERR(nwl->pcireg_base))
+ return PTR_ERR(nwl->pcireg_base);
+ nwl->phys_pcie_reg_base = res->start;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
- pcie->ecam_base = devm_ioremap_resource(pcie->dev, res);
- if (IS_ERR(pcie->ecam_base))
- return PTR_ERR(pcie->ecam_base);
- pcie->phys_ecam_base = res->start;
+ nwl->ecam_base = devm_ioremap_resource(nwl->dev, res);
+ if (IS_ERR(nwl->ecam_base))
+ return PTR_ERR(nwl->ecam_base);
+ nwl->phys_ecam_base = res->start;
/* Get intx IRQ number */
- pcie->irq_intx = platform_get_irq_byname(pdev, "intx");
- if (pcie->irq_intx < 0) {
+ nwl->irq_intx = platform_get_irq_byname(pdev, "intx");
+ if (nwl->irq_intx < 0) {
dev_err(&pdev->dev, "failed to get intx IRQ %d\n",
- pcie->irq_intx);
+ nwl->irq_intx);
return -EINVAL;
}
- irq_set_chained_handler_and_data(pcie->irq_intx,
- nwl_pcie_leg_handler, pcie);
+ irq_set_chained_handler_and_data(nwl->irq_intx,
+ nwl_pcie_leg_handler, nwl);
return 0;
}
@@ -795,57 +795,57 @@ static const struct of_device_id nwl_pcie_of_match[] = {
static int nwl_pcie_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
- struct nwl_pcie *pcie;
+ struct nwl_pcie *nwl;
struct pci_bus *bus;
struct pci_bus *child;
int err;
resource_size_t iobase = 0;
LIST_HEAD(res);
- pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
- if (!pcie)
+ nwl = devm_kzalloc(&pdev->dev, sizeof(*nwl), GFP_KERNEL);
+ if (!nwl)
return -ENOMEM;
- pcie->dev = &pdev->dev;
- pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;
+ nwl->dev = &pdev->dev;
+ nwl->ecam_value = NWL_ECAM_VALUE_DEFAULT;
- err = nwl_pcie_parse_dt(pcie, pdev);
+ err = nwl_pcie_parse_dt(nwl, pdev);
if (err) {
- dev_err(pcie->dev, "Parsing DT failed\n");
+ dev_err(nwl->dev, "Parsing DT failed\n");
return err;
}
- err = nwl_pcie_bridge_init(pcie);
+ err = nwl_pcie_bridge_init(nwl);
if (err) {
- dev_err(pcie->dev, "HW Initialization failed\n");
+ dev_err(nwl->dev, "HW Initialization failed\n");
return err;
}
err = of_pci_get_host_bridge_resources(node, 0, 0xff, &res, &iobase);
if (err) {
- dev_err(pcie->dev, "Getting bridge resources failed\n");
+ dev_err(nwl->dev, "Getting bridge resources failed\n");
return err;
}
- err = devm_request_pci_bus_resources(pcie->dev, &res);
+ err = devm_request_pci_bus_resources(nwl->dev, &res);
if (err)
goto error;
- err = nwl_pcie_init_irq_domain(pcie);
+ err = nwl_pcie_init_irq_domain(nwl);
if (err) {
- dev_err(pcie->dev, "Failed creating IRQ Domain\n");
+ dev_err(nwl->dev, "Failed creating IRQ Domain\n");
goto error;
}
- bus = pci_create_root_bus(&pdev->dev, pcie->root_busno,
- &nwl_pcie_ops, pcie, &res);
+ bus = pci_create_root_bus(&pdev->dev, nwl->root_busno,
+ &nwl_pcie_ops, nwl, &res);
if (!bus) {
err = -ENOMEM;
goto error;
}
if (IS_ENABLED(CONFIG_PCI_MSI)) {
- err = nwl_pcie_enable_msi(pcie, bus);
+ err = nwl_pcie_enable_msi(nwl, bus);
if (err < 0) {
dev_err(&pdev->dev,
"failed to enable MSI support: %d\n", err);
@@ -857,7 +857,7 @@ static int nwl_pcie_probe(struct platform_device *pdev)
list_for_each_entry(child, &bus->children, node)
pcie_bus_configure_settings(child);
pci_bus_add_devices(bus);
- platform_set_drvdata(pdev, pcie);
+ platform_set_drvdata(pdev, nwl);
return 0;
error:
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 7/9] PCI: xilinx-nwl: Swap order of nwl_bridge_writel() reg/val arguments
2016-10-07 16:28 [PATCH 1/9] PCI: xilinx: Name private struct pointer "xilinx" consistently Bjorn Helgaas
` (4 preceding siblings ...)
2016-10-07 16:29 ` [PATCH 6/9] PCI: xilinx-nwl: Name private struct pointer "nwl" consistently Bjorn Helgaas
@ 2016-10-07 16:29 ` Bjorn Helgaas
2016-10-07 16:29 ` [PATCH 8/9] PCI: xilinx-nwl: Add local struct device pointers Bjorn Helgaas
2016-10-07 16:29 ` [PATCH 9/9] PCI: xilinx-nwl: Remove unused platform data Bjorn Helgaas
7 siblings, 0 replies; 9+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:29 UTC (permalink / raw)
To: Michal Simek, Sören Brinkmann; +Cc: linux-pci
Swap order of nwl_bridge_writel() arguments to match the "dev, pos, val"
order used by pci_write_config_word() and other drivers. No functional
change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pcie-xilinx-nwl.c | 107 +++++++++++++++++++-----------------
1 file changed, 57 insertions(+), 50 deletions(-)
diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c
index 2c72c73..2403865 100644
--- a/drivers/pci/host/pcie-xilinx-nwl.c
+++ b/drivers/pci/host/pcie-xilinx-nwl.c
@@ -186,12 +186,12 @@ struct nwl_pcie {
struct irq_domain *legacy_irq_domain;
};
-static inline u32 nwl_bridge_readl(struct nwl_pcie *nwl, u32 off)
+static u32 nwl_bridge_readl(struct nwl_pcie *nwl, u32 off)
{
return readl(nwl->breg_base + off);
}
-static inline void nwl_bridge_writel(struct nwl_pcie *nwl, u32 val, u32 off)
+static void nwl_bridge_writel(struct nwl_pcie *nwl, u32 off, u32 val)
{
writel(val, nwl->breg_base + off);
}
@@ -327,7 +327,7 @@ static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
dev_info(nwl->dev, "Link Bandwidth Management Status bit set\n");
/* Clear misc interrupt status */
- nwl_bridge_writel(nwl, misc_stat, MSGF_MISC_STATUS);
+ nwl_bridge_writel(nwl, MSGF_MISC_STATUS, misc_stat);
return IRQ_HANDLED;
}
@@ -367,7 +367,7 @@ static void nwl_pcie_handle_msi_irq(struct nwl_pcie *nwl, u32 status_reg)
while ((status = nwl_bridge_readl(nwl, status_reg)) != 0) {
for_each_set_bit(bit, &status, 32) {
- nwl_bridge_writel(nwl, 1 << bit, status_reg);
+ nwl_bridge_writel(nwl, status_reg, 1 << bit);
virq = irq_find_mapping(msi->dev_domain, bit);
if (virq)
generic_handle_irq(virq);
@@ -585,40 +585,43 @@ static int nwl_pcie_enable_msi(struct nwl_pcie *nwl, struct pci_bus *bus)
}
/* Enable MSII */
- nwl_bridge_writel(nwl, nwl_bridge_readl(nwl, I_MSII_CONTROL) |
- MSII_ENABLE, I_MSII_CONTROL);
+ nwl_bridge_writel(nwl, I_MSII_CONTROL,
+ nwl_bridge_readl(nwl, I_MSII_CONTROL) |
+ MSII_ENABLE);
/* Enable MSII status */
- nwl_bridge_writel(nwl, nwl_bridge_readl(nwl, I_MSII_CONTROL) |
- MSII_STATUS_ENABLE, I_MSII_CONTROL);
+ nwl_bridge_writel(nwl, I_MSII_CONTROL,
+ nwl_bridge_readl(nwl, I_MSII_CONTROL) |
+ MSII_STATUS_ENABLE);
/* setup AFI/FPCI range */
base = nwl->phys_pcie_reg_base;
- nwl_bridge_writel(nwl, lower_32_bits(base), I_MSII_BASE_LO);
- nwl_bridge_writel(nwl, upper_32_bits(base), I_MSII_BASE_HI);
+ nwl_bridge_writel(nwl, I_MSII_BASE_LO, lower_32_bits(base));
+ nwl_bridge_writel(nwl, I_MSII_BASE_HI, upper_32_bits(base));
/*
* For high range MSI interrupts: disable, clear any pending,
* and enable
*/
- nwl_bridge_writel(nwl, (u32)~MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
+ nwl_bridge_writel(nwl, MSGF_MSI_MASK_HI, (u32)~MSGF_MSI_SR_HI_MASK);
- nwl_bridge_writel(nwl, nwl_bridge_readl(nwl, MSGF_MSI_STATUS_HI) &
- MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI);
+ nwl_bridge_writel(nwl, MSGF_MSI_STATUS_HI,
+ nwl_bridge_readl(nwl, MSGF_MSI_STATUS_HI) &
+ MSGF_MSI_SR_HI_MASK);
- nwl_bridge_writel(nwl, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
+ nwl_bridge_writel(nwl, MSGF_MSI_MASK_HI, MSGF_MSI_SR_HI_MASK);
/*
* For low range MSI interrupts: disable, clear any pending,
* and enable
*/
- nwl_bridge_writel(nwl, (u32)~MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
+ nwl_bridge_writel(nwl, MSGF_MSI_MASK_LO, (u32)~MSGF_MSI_SR_LO_MASK);
- nwl_bridge_writel(nwl, nwl_bridge_readl(nwl, MSGF_MSI_STATUS_LO) &
- MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO);
-
- nwl_bridge_writel(nwl, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
+ nwl_bridge_writel(nwl, MSGF_MSI_STATUS_LO,
+ nwl_bridge_readl(nwl, MSGF_MSI_STATUS_LO) &
+ MSGF_MSI_SR_LO_MASK);
+ nwl_bridge_writel(nwl, MSGF_MSI_MASK_LO, MSGF_MSI_SR_LO_MASK);
return 0;
err:
kfree(msi->bitmap);
@@ -639,25 +642,26 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *nwl)
}
/* Write bridge_off to breg base */
- nwl_bridge_writel(nwl, lower_32_bits(nwl->phys_breg_base),
- E_BREG_BASE_LO);
- nwl_bridge_writel(nwl, upper_32_bits(nwl->phys_breg_base),
- E_BREG_BASE_HI);
+ nwl_bridge_writel(nwl, E_BREG_BASE_LO,
+ lower_32_bits(nwl->phys_breg_base));
+ nwl_bridge_writel(nwl, E_BREG_BASE_HI,
+ upper_32_bits(nwl->phys_breg_base));
/* Enable BREG */
- nwl_bridge_writel(nwl, ~BREG_ENABLE_FORCE & BREG_ENABLE,
- E_BREG_CONTROL);
+ nwl_bridge_writel(nwl, E_BREG_CONTROL,
+ ~BREG_ENABLE_FORCE & BREG_ENABLE);
/* Disable DMA channel registers */
- nwl_bridge_writel(nwl, nwl_bridge_readl(nwl, BRCFG_PCIE_RX0) |
- CFG_DMA_REG_BAR, BRCFG_PCIE_RX0);
+ nwl_bridge_writel(nwl, BRCFG_PCIE_RX0,
+ nwl_bridge_readl(nwl, BRCFG_PCIE_RX0) |
+ CFG_DMA_REG_BAR);
/* Enable Ingress subtractive decode translation */
- nwl_bridge_writel(nwl, SET_ISUB_CONTROL, I_ISUB_CONTROL);
+ nwl_bridge_writel(nwl, I_ISUB_CONTROL, SET_ISUB_CONTROL);
/* Enable msg filtering details */
- nwl_bridge_writel(nwl, CFG_ENABLE_MSG_FILTER_MASK,
- BRCFG_PCIE_RX_MSG_FILTER);
+ nwl_bridge_writel(nwl, BRCFG_PCIE_RX_MSG_FILTER,
+ CFG_ENABLE_MSG_FILTER_MASK);
err = nwl_wait_for_link(nwl);
if (err)
@@ -670,17 +674,18 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *nwl)
}
/* Enable ECAM */
- nwl_bridge_writel(nwl, nwl_bridge_readl(nwl, E_ECAM_CONTROL) |
- E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
+ nwl_bridge_writel(nwl, E_ECAM_CONTROL,
+ nwl_bridge_readl(nwl, E_ECAM_CONTROL) |
+ E_ECAM_CR_ENABLE);
- nwl_bridge_writel(nwl, nwl_bridge_readl(nwl, E_ECAM_CONTROL) |
- (nwl->ecam_value << E_ECAM_SIZE_SHIFT),
- E_ECAM_CONTROL);
+ nwl_bridge_writel(nwl, E_ECAM_CONTROL,
+ nwl_bridge_readl(nwl, E_ECAM_CONTROL) |
+ (nwl->ecam_value << E_ECAM_SIZE_SHIFT));
- nwl_bridge_writel(nwl, lower_32_bits(nwl->phys_ecam_base),
- E_ECAM_BASE_LO);
- nwl_bridge_writel(nwl, upper_32_bits(nwl->phys_ecam_base),
- E_ECAM_BASE_HI);
+ nwl_bridge_writel(nwl, E_ECAM_BASE_LO,
+ lower_32_bits(nwl->phys_ecam_base));
+ nwl_bridge_writel(nwl, E_ECAM_BASE_HI,
+ upper_32_bits(nwl->phys_ecam_base));
/* Get bus range */
ecam_val = nwl_bridge_readl(nwl, E_ECAM_CONTROL);
@@ -714,30 +719,32 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *nwl)
}
/* Disable all misc interrupts */
- nwl_bridge_writel(nwl, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
+ nwl_bridge_writel(nwl, MSGF_MISC_MASK, (u32)~MSGF_MISC_SR_MASKALL);
/* Clear pending misc interrupts */
- nwl_bridge_writel(nwl, nwl_bridge_readl(nwl, MSGF_MISC_STATUS) &
- MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS);
+ nwl_bridge_writel(nwl, MSGF_MISC_STATUS,
+ nwl_bridge_readl(nwl, MSGF_MISC_STATUS) &
+ MSGF_MISC_SR_MASKALL);
/* Enable all misc interrupts */
- nwl_bridge_writel(nwl, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
+ nwl_bridge_writel(nwl, MSGF_MISC_MASK, MSGF_MISC_SR_MASKALL);
/* Disable all legacy interrupts */
- nwl_bridge_writel(nwl, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
+ nwl_bridge_writel(nwl, MSGF_LEG_MASK, (u32)~MSGF_LEG_SR_MASKALL);
/* Clear pending legacy interrupts */
- nwl_bridge_writel(nwl, nwl_bridge_readl(nwl, MSGF_LEG_STATUS) &
- MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);
+ nwl_bridge_writel(nwl, MSGF_LEG_STATUS,
+ nwl_bridge_readl(nwl, MSGF_LEG_STATUS) &
+ MSGF_LEG_SR_MASKALL);
/* Enable all legacy interrupts */
- nwl_bridge_writel(nwl, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
+ nwl_bridge_writel(nwl, MSGF_LEG_MASK, MSGF_LEG_SR_MASKALL);
/* Enable the bridge config interrupt */
- nwl_bridge_writel(nwl, nwl_bridge_readl(nwl, BRCFG_INTERRUPT) |
- BRCFG_INTERRUPT_MASK, BRCFG_INTERRUPT);
-
+ nwl_bridge_writel(nwl, BRCFG_INTERRUPT,
+ nwl_bridge_readl(nwl, BRCFG_INTERRUPT) |
+ BRCFG_INTERRUPT_MASK);
return 0;
}
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 8/9] PCI: xilinx-nwl: Add local struct device pointers
2016-10-07 16:28 [PATCH 1/9] PCI: xilinx: Name private struct pointer "xilinx" consistently Bjorn Helgaas
` (5 preceding siblings ...)
2016-10-07 16:29 ` [PATCH 7/9] PCI: xilinx-nwl: Swap order of nwl_bridge_writel() reg/val arguments Bjorn Helgaas
@ 2016-10-07 16:29 ` Bjorn Helgaas
2016-10-07 16:29 ` [PATCH 9/9] PCI: xilinx-nwl: Remove unused platform data Bjorn Helgaas
7 siblings, 0 replies; 9+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:29 UTC (permalink / raw)
To: Michal Simek, Sören Brinkmann; +Cc: linux-pci
Use a local "struct device *dev" for brevity and consistency with other
drivers. No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pcie-xilinx-nwl.c | 108 ++++++++++++++++++------------------
1 file changed, 54 insertions(+), 54 deletions(-)
diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c
index 2403865..63b6174 100644
--- a/drivers/pci/host/pcie-xilinx-nwl.c
+++ b/drivers/pci/host/pcie-xilinx-nwl.c
@@ -277,6 +277,7 @@ static struct pci_ops nwl_pcie_ops = {
static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
{
struct nwl_pcie *nwl = data;
+ struct device *dev = nwl->dev;
u32 misc_stat;
/* Checking for misc interrupts */
@@ -286,45 +287,43 @@ static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
return IRQ_NONE;
if (misc_stat & MSGF_MISC_SR_RXMSG_OVER)
- dev_err(nwl->dev, "Received Message FIFO Overflow\n");
+ dev_err(dev, "Received Message FIFO Overflow\n");
if (misc_stat & MSGF_MISC_SR_SLAVE_ERR)
- dev_err(nwl->dev, "Slave error\n");
+ dev_err(dev, "Slave error\n");
if (misc_stat & MSGF_MISC_SR_MASTER_ERR)
- dev_err(nwl->dev, "Master error\n");
+ dev_err(dev, "Master error\n");
if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR)
- dev_err(nwl->dev,
- "In Misc Ingress address translation error\n");
+ dev_err(dev, "In Misc Ingress address translation error\n");
if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR)
- dev_err(nwl->dev,
- "In Misc Egress address translation error\n");
+ dev_err(dev, "In Misc Egress address translation error\n");
if (misc_stat & MSGF_MISC_SR_FATAL_AER)
- dev_err(nwl->dev, "Fatal Error in AER Capability\n");
+ dev_err(dev, "Fatal Error in AER Capability\n");
if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER)
- dev_err(nwl->dev, "Non-Fatal Error in AER Capability\n");
+ dev_err(dev, "Non-Fatal Error in AER Capability\n");
if (misc_stat & MSGF_MISC_SR_CORR_AER)
- dev_err(nwl->dev, "Correctable Error in AER Capability\n");
+ dev_err(dev, "Correctable Error in AER Capability\n");
if (misc_stat & MSGF_MISC_SR_UR_DETECT)
- dev_err(nwl->dev, "Unsupported request Detected\n");
+ dev_err(dev, "Unsupported request Detected\n");
if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV)
- dev_err(nwl->dev, "Non-Fatal Error Detected\n");
+ dev_err(dev, "Non-Fatal Error Detected\n");
if (misc_stat & MSGF_MISC_SR_FATAL_DEV)
- dev_err(nwl->dev, "Fatal Error Detected\n");
+ dev_err(dev, "Fatal Error Detected\n");
if (misc_stat & MSGF_MSIC_SR_LINK_AUTO_BWIDTH)
- dev_info(nwl->dev, "Link Autonomous Bandwidth Management Status bit set\n");
+ dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n");
if (misc_stat & MSGF_MSIC_SR_LINK_BWIDTH)
- dev_info(nwl->dev, "Link Bandwidth Management Status bit set\n");
+ dev_info(dev, "Link Bandwidth Management Status bit set\n");
/* Clear misc interrupt status */
nwl_bridge_writel(nwl, MSGF_MISC_STATUS, misc_stat);
@@ -494,20 +493,21 @@ static const struct irq_domain_ops dev_msi_domain_ops = {
static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *nwl)
{
#ifdef CONFIG_PCI_MSI
- struct fwnode_handle *fwnode = of_node_to_fwnode(nwl->dev->of_node);
+ struct device *dev = nwl->dev;
+ struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
struct nwl_msi *msi = &nwl->msi;
msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR,
&dev_msi_domain_ops, nwl);
if (!msi->dev_domain) {
- dev_err(nwl->dev, "failed to create dev IRQ domain\n");
+ dev_err(dev, "failed to create dev IRQ domain\n");
return -ENOMEM;
}
msi->msi_domain = pci_msi_create_irq_domain(fwnode,
&nwl_msi_domain_info,
msi->dev_domain);
if (!msi->msi_domain) {
- dev_err(nwl->dev, "failed to create msi IRQ domain\n");
+ dev_err(dev, "failed to create msi IRQ domain\n");
irq_domain_remove(msi->dev_domain);
return -ENOMEM;
}
@@ -517,12 +517,13 @@ static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *nwl)
static int nwl_pcie_init_irq_domain(struct nwl_pcie *nwl)
{
- struct device_node *node = nwl->dev->of_node;
+ struct device *dev = nwl->dev;
+ struct device_node *node = dev->of_node;
struct device_node *legacy_intc_node;
legacy_intc_node = of_get_next_child(node, NULL);
if (!legacy_intc_node) {
- dev_err(nwl->dev, "No legacy intc node found\n");
+ dev_err(dev, "No legacy intc node found\n");
return -EINVAL;
}
@@ -532,7 +533,7 @@ static int nwl_pcie_init_irq_domain(struct nwl_pcie *nwl)
nwl);
if (!nwl->legacy_irq_domain) {
- dev_err(nwl->dev, "failed to create IRQ domain\n");
+ dev_err(dev, "failed to create IRQ domain\n");
return -ENOMEM;
}
@@ -542,7 +543,8 @@ static int nwl_pcie_init_irq_domain(struct nwl_pcie *nwl)
static int nwl_pcie_enable_msi(struct nwl_pcie *nwl, struct pci_bus *bus)
{
- struct platform_device *pdev = to_platform_device(nwl->dev);
+ struct device *dev = nwl->dev;
+ struct platform_device *pdev = to_platform_device(dev);
struct nwl_msi *msi = &nwl->msi;
unsigned long base;
int ret;
@@ -557,7 +559,7 @@ static int nwl_pcie_enable_msi(struct nwl_pcie *nwl, struct pci_bus *bus)
/* Get msi_1 IRQ number */
msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1");
if (msi->irq_msi1 < 0) {
- dev_err(&pdev->dev, "failed to get IRQ#%d\n", msi->irq_msi1);
+ dev_err(dev, "failed to get IRQ#%d\n", msi->irq_msi1);
ret = -EINVAL;
goto err;
}
@@ -568,7 +570,7 @@ static int nwl_pcie_enable_msi(struct nwl_pcie *nwl, struct pci_bus *bus)
/* Get msi_0 IRQ number */
msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0");
if (msi->irq_msi0 < 0) {
- dev_err(&pdev->dev, "failed to get IRQ#%d\n", msi->irq_msi0);
+ dev_err(dev, "failed to get IRQ#%d\n", msi->irq_msi0);
ret = -EINVAL;
goto err;
}
@@ -579,7 +581,7 @@ static int nwl_pcie_enable_msi(struct nwl_pcie *nwl, struct pci_bus *bus)
/* Check for msii_present bit */
ret = nwl_bridge_readl(nwl, I_MSII_CAPABILITIES) & MSII_PRESENT;
if (!ret) {
- dev_err(nwl->dev, "MSI not present\n");
+ dev_err(dev, "MSI not present\n");
ret = -EIO;
goto err;
}
@@ -631,13 +633,14 @@ err:
static int nwl_pcie_bridge_init(struct nwl_pcie *nwl)
{
- struct platform_device *pdev = to_platform_device(nwl->dev);
+ struct device *dev = nwl->dev;
+ struct platform_device *pdev = to_platform_device(dev);
u32 breg_val, ecam_val, first_busno = 0;
int err;
breg_val = nwl_bridge_readl(nwl, E_BREG_CAPABILITIES) & BREG_PRESENT;
if (!breg_val) {
- dev_err(nwl->dev, "BREG is not present\n");
+ dev_err(dev, "BREG is not present\n");
return breg_val;
}
@@ -669,7 +672,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *nwl)
ecam_val = nwl_bridge_readl(nwl, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;
if (!ecam_val) {
- dev_err(nwl->dev, "ECAM is not present\n");
+ dev_err(dev, "ECAM is not present\n");
return ecam_val;
}
@@ -697,24 +700,22 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *nwl)
writel(ecam_val, (nwl->ecam_base + PCI_PRIMARY_BUS));
if (nwl_pcie_link_up(nwl))
- dev_info(nwl->dev, "Link is UP\n");
+ dev_info(dev, "Link is UP\n");
else
- dev_info(nwl->dev, "Link is DOWN\n");
+ dev_info(dev, "Link is DOWN\n");
/* Get misc IRQ number */
nwl->irq_misc = platform_get_irq_byname(pdev, "misc");
if (nwl->irq_misc < 0) {
- dev_err(&pdev->dev, "failed to get misc IRQ %d\n",
- nwl->irq_misc);
+ dev_err(dev, "failed to get misc IRQ %d\n", nwl->irq_misc);
return -EINVAL;
}
- err = devm_request_irq(nwl->dev, nwl->irq_misc,
+ err = devm_request_irq(dev, nwl->irq_misc,
nwl_pcie_misc_handler, IRQF_SHARED,
"nwl_pcie:misc", nwl);
if (err) {
- dev_err(nwl->dev, "fail to register misc IRQ#%d\n",
- nwl->irq_misc);
+ dev_err(dev, "fail to register misc IRQ#%d\n", nwl->irq_misc);
return err;
}
@@ -751,31 +752,32 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *nwl)
static int nwl_pcie_parse_dt(struct nwl_pcie *nwl,
struct platform_device *pdev)
{
- struct device_node *node = nwl->dev->of_node;
+ struct device *dev = nwl->dev;
+ struct device_node *node = dev->of_node;
struct resource *res;
const char *type;
/* Check for device type */
type = of_get_property(node, "device_type", NULL);
if (!type || strcmp(type, "pci")) {
- dev_err(nwl->dev, "invalid \"device_type\" %s\n", type);
+ dev_err(dev, "invalid \"device_type\" %s\n", type);
return -EINVAL;
}
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
- nwl->breg_base = devm_ioremap_resource(nwl->dev, res);
+ nwl->breg_base = devm_ioremap_resource(dev, res);
if (IS_ERR(nwl->breg_base))
return PTR_ERR(nwl->breg_base);
nwl->phys_breg_base = res->start;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg");
- nwl->pcireg_base = devm_ioremap_resource(nwl->dev, res);
+ nwl->pcireg_base = devm_ioremap_resource(dev, res);
if (IS_ERR(nwl->pcireg_base))
return PTR_ERR(nwl->pcireg_base);
nwl->phys_pcie_reg_base = res->start;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
- nwl->ecam_base = devm_ioremap_resource(nwl->dev, res);
+ nwl->ecam_base = devm_ioremap_resource(dev, res);
if (IS_ERR(nwl->ecam_base))
return PTR_ERR(nwl->ecam_base);
nwl->phys_ecam_base = res->start;
@@ -783,14 +785,12 @@ static int nwl_pcie_parse_dt(struct nwl_pcie *nwl,
/* Get intx IRQ number */
nwl->irq_intx = platform_get_irq_byname(pdev, "intx");
if (nwl->irq_intx < 0) {
- dev_err(&pdev->dev, "failed to get intx IRQ %d\n",
- nwl->irq_intx);
+ dev_err(dev, "failed to get intx IRQ %d\n", nwl->irq_intx);
return -EINVAL;
}
irq_set_chained_handler_and_data(nwl->irq_intx,
nwl_pcie_leg_handler, nwl);
-
return 0;
}
@@ -801,7 +801,8 @@ static const struct of_device_id nwl_pcie_of_match[] = {
static int nwl_pcie_probe(struct platform_device *pdev)
{
- struct device_node *node = pdev->dev.of_node;
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->of_node;
struct nwl_pcie *nwl;
struct pci_bus *bus;
struct pci_bus *child;
@@ -809,42 +810,42 @@ static int nwl_pcie_probe(struct platform_device *pdev)
resource_size_t iobase = 0;
LIST_HEAD(res);
- nwl = devm_kzalloc(&pdev->dev, sizeof(*nwl), GFP_KERNEL);
+ nwl = devm_kzalloc(dev, sizeof(*nwl), GFP_KERNEL);
if (!nwl)
return -ENOMEM;
- nwl->dev = &pdev->dev;
+ nwl->dev = dev;
nwl->ecam_value = NWL_ECAM_VALUE_DEFAULT;
err = nwl_pcie_parse_dt(nwl, pdev);
if (err) {
- dev_err(nwl->dev, "Parsing DT failed\n");
+ dev_err(dev, "Parsing DT failed\n");
return err;
}
err = nwl_pcie_bridge_init(nwl);
if (err) {
- dev_err(nwl->dev, "HW Initialization failed\n");
+ dev_err(dev, "HW Initialization failed\n");
return err;
}
err = of_pci_get_host_bridge_resources(node, 0, 0xff, &res, &iobase);
if (err) {
- dev_err(nwl->dev, "Getting bridge resources failed\n");
+ dev_err(dev, "Getting bridge resources failed\n");
return err;
}
- err = devm_request_pci_bus_resources(nwl->dev, &res);
+ err = devm_request_pci_bus_resources(dev, &res);
if (err)
goto error;
err = nwl_pcie_init_irq_domain(nwl);
if (err) {
- dev_err(nwl->dev, "Failed creating IRQ Domain\n");
+ dev_err(dev, "Failed creating IRQ Domain\n");
goto error;
}
- bus = pci_create_root_bus(&pdev->dev, nwl->root_busno,
+ bus = pci_create_root_bus(dev, nwl->root_busno,
&nwl_pcie_ops, nwl, &res);
if (!bus) {
err = -ENOMEM;
@@ -854,8 +855,7 @@ static int nwl_pcie_probe(struct platform_device *pdev)
if (IS_ENABLED(CONFIG_PCI_MSI)) {
err = nwl_pcie_enable_msi(nwl, bus);
if (err < 0) {
- dev_err(&pdev->dev,
- "failed to enable MSI support: %d\n", err);
+ dev_err(dev, "failed to enable MSI support: %d\n", err);
goto error;
}
}
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 9/9] PCI: xilinx-nwl: Remove unused platform data
2016-10-07 16:28 [PATCH 1/9] PCI: xilinx: Name private struct pointer "xilinx" consistently Bjorn Helgaas
` (6 preceding siblings ...)
2016-10-07 16:29 ` [PATCH 8/9] PCI: xilinx-nwl: Add local struct device pointers Bjorn Helgaas
@ 2016-10-07 16:29 ` Bjorn Helgaas
7 siblings, 0 replies; 9+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:29 UTC (permalink / raw)
To: Michal Simek, Sören Brinkmann; +Cc: linux-pci
The xilinx-nwl driver never uses the platform drvdata pointer, so don't
bother setting it. No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pcie-xilinx-nwl.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c
index 63b6174..ea0265e 100644
--- a/drivers/pci/host/pcie-xilinx-nwl.c
+++ b/drivers/pci/host/pcie-xilinx-nwl.c
@@ -864,7 +864,6 @@ static int nwl_pcie_probe(struct platform_device *pdev)
list_for_each_entry(child, &bus->children, node)
pcie_bus_configure_settings(child);
pci_bus_add_devices(bus);
- platform_set_drvdata(pdev, nwl);
return 0;
error:
^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2016-10-07 16:29 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-10-07 16:28 [PATCH 1/9] PCI: xilinx: Name private struct pointer "xilinx" consistently Bjorn Helgaas
2016-10-07 16:28 ` [PATCH 2/9] PCI: xilinx: Rename accessors Bjorn Helgaas
2016-10-07 16:29 ` [PATCH 3/9] PCI: xilinx: Swap order of xilinx_writel() reg/val arguments Bjorn Helgaas
2016-10-07 16:29 ` [PATCH 4/9] PCI: xilinx: Add local struct device pointers Bjorn Helgaas
2016-10-07 16:29 ` [PATCH 5/9] PCI: xilinx: Remove unused platform data Bjorn Helgaas
2016-10-07 16:29 ` [PATCH 6/9] PCI: xilinx-nwl: Name private struct pointer "nwl" consistently Bjorn Helgaas
2016-10-07 16:29 ` [PATCH 7/9] PCI: xilinx-nwl: Swap order of nwl_bridge_writel() reg/val arguments Bjorn Helgaas
2016-10-07 16:29 ` [PATCH 8/9] PCI: xilinx-nwl: Add local struct device pointers Bjorn Helgaas
2016-10-07 16:29 ` [PATCH 9/9] PCI: xilinx-nwl: Remove unused platform data Bjorn Helgaas
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.