* [PATCH 1/8] PCI: exynos: Name private struct pointer "exynos" consistently
@ 2016-10-07 16:35 Bjorn Helgaas
2016-10-07 16:35 ` [PATCH 2/8] PCI: exynos: Pass device-specific struct to internal functions Bjorn Helgaas
` (7 more replies)
0 siblings, 8 replies; 11+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:35 UTC (permalink / raw)
To: Jingoo Han, Krzysztof Kozlowski, Kukjin Kim; +Cc: linux-pci, linux-samsung-soc
Use a device-specific name, "exynos", for struct exynos_pcie pointers
to hint that this is device-specific information. No functional change
intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pci-exynos.c | 272 ++++++++++++++++++++---------------------
1 file changed, 135 insertions(+), 137 deletions(-)
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index f559b49..05eb246 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -102,221 +102,221 @@ struct exynos_pcie {
#define PCIE_PHY_TRSV3_PD_TSV (0x1 << 7)
#define PCIE_PHY_TRSV3_LVCC 0x31c
-static inline void exynos_elb_writel(struct exynos_pcie *pcie, u32 val, u32 reg)
+static void exynos_elb_writel(struct exynos_pcie *exynos, u32 val, u32 reg)
{
- writel(val, pcie->elbi_base + reg);
+ writel(val, exynos->elbi_base + reg);
}
-static inline u32 exynos_elb_readl(struct exynos_pcie *pcie, u32 reg)
+static u32 exynos_elb_readl(struct exynos_pcie *exynos, u32 reg)
{
- return readl(pcie->elbi_base + reg);
+ return readl(exynos->elbi_base + reg);
}
-static inline void exynos_phy_writel(struct exynos_pcie *pcie, u32 val, u32 reg)
+static void exynos_phy_writel(struct exynos_pcie *exynos, u32 val, u32 reg)
{
- writel(val, pcie->phy_base + reg);
+ writel(val, exynos->phy_base + reg);
}
-static inline u32 exynos_phy_readl(struct exynos_pcie *pcie, u32 reg)
+static u32 exynos_phy_readl(struct exynos_pcie *exynos, u32 reg)
{
- return readl(pcie->phy_base + reg);
+ return readl(exynos->phy_base + reg);
}
-static inline void exynos_blk_writel(struct exynos_pcie *pcie, u32 val, u32 reg)
+static void exynos_blk_writel(struct exynos_pcie *exynos, u32 val, u32 reg)
{
- writel(val, pcie->block_base + reg);
+ writel(val, exynos->block_base + reg);
}
-static inline u32 exynos_blk_readl(struct exynos_pcie *pcie, u32 reg)
+static u32 exynos_blk_readl(struct exynos_pcie *exynos, u32 reg)
{
- return readl(pcie->block_base + reg);
+ return readl(exynos->block_base + reg);
}
static void exynos_pcie_sideband_dbi_w_mode(struct pcie_port *pp, bool on)
{
u32 val;
- struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ struct exynos_pcie *exynos = to_exynos_pcie(pp);
if (on) {
- val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC);
+ val = exynos_elb_readl(exynos, PCIE_ELBI_SLV_AWMISC);
val |= PCIE_ELBI_SLV_DBI_ENABLE;
- exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC);
+ exynos_elb_writel(exynos, val, PCIE_ELBI_SLV_AWMISC);
} else {
- val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC);
+ val = exynos_elb_readl(exynos, PCIE_ELBI_SLV_AWMISC);
val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
- exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC);
+ exynos_elb_writel(exynos, val, PCIE_ELBI_SLV_AWMISC);
}
}
static void exynos_pcie_sideband_dbi_r_mode(struct pcie_port *pp, bool on)
{
u32 val;
- struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ struct exynos_pcie *exynos = to_exynos_pcie(pp);
if (on) {
- val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC);
+ val = exynos_elb_readl(exynos, PCIE_ELBI_SLV_ARMISC);
val |= PCIE_ELBI_SLV_DBI_ENABLE;
- exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC);
+ exynos_elb_writel(exynos, val, PCIE_ELBI_SLV_ARMISC);
} else {
- val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC);
+ val = exynos_elb_readl(exynos, PCIE_ELBI_SLV_ARMISC);
val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
- exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC);
+ exynos_elb_writel(exynos, val, PCIE_ELBI_SLV_ARMISC);
}
}
static void exynos_pcie_assert_core_reset(struct pcie_port *pp)
{
u32 val;
- struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ struct exynos_pcie *exynos = to_exynos_pcie(pp);
- val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET);
+ val = exynos_elb_readl(exynos, PCIE_CORE_RESET);
val &= ~PCIE_CORE_RESET_ENABLE;
- exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET);
- exynos_elb_writel(exynos_pcie, 0, PCIE_PWR_RESET);
- exynos_elb_writel(exynos_pcie, 0, PCIE_STICKY_RESET);
- exynos_elb_writel(exynos_pcie, 0, PCIE_NONSTICKY_RESET);
+ exynos_elb_writel(exynos, val, PCIE_CORE_RESET);
+ exynos_elb_writel(exynos, 0, PCIE_PWR_RESET);
+ exynos_elb_writel(exynos, 0, PCIE_STICKY_RESET);
+ exynos_elb_writel(exynos, 0, PCIE_NONSTICKY_RESET);
}
static void exynos_pcie_deassert_core_reset(struct pcie_port *pp)
{
u32 val;
- struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ struct exynos_pcie *exynos = to_exynos_pcie(pp);
- val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET);
+ val = exynos_elb_readl(exynos, PCIE_CORE_RESET);
val |= PCIE_CORE_RESET_ENABLE;
- exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET);
- exynos_elb_writel(exynos_pcie, 1, PCIE_STICKY_RESET);
- exynos_elb_writel(exynos_pcie, 1, PCIE_NONSTICKY_RESET);
- exynos_elb_writel(exynos_pcie, 1, PCIE_APP_INIT_RESET);
- exynos_elb_writel(exynos_pcie, 0, PCIE_APP_INIT_RESET);
- exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_MAC_RESET);
+ exynos_elb_writel(exynos, val, PCIE_CORE_RESET);
+ exynos_elb_writel(exynos, 1, PCIE_STICKY_RESET);
+ exynos_elb_writel(exynos, 1, PCIE_NONSTICKY_RESET);
+ exynos_elb_writel(exynos, 1, PCIE_APP_INIT_RESET);
+ exynos_elb_writel(exynos, 0, PCIE_APP_INIT_RESET);
+ exynos_blk_writel(exynos, 1, PCIE_PHY_MAC_RESET);
}
static void exynos_pcie_assert_phy_reset(struct pcie_port *pp)
{
- struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ struct exynos_pcie *exynos = to_exynos_pcie(pp);
- exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_MAC_RESET);
- exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_GLOBAL_RESET);
+ exynos_blk_writel(exynos, 0, PCIE_PHY_MAC_RESET);
+ exynos_blk_writel(exynos, 1, PCIE_PHY_GLOBAL_RESET);
}
static void exynos_pcie_deassert_phy_reset(struct pcie_port *pp)
{
- struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ struct exynos_pcie *exynos = to_exynos_pcie(pp);
- exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_GLOBAL_RESET);
- exynos_elb_writel(exynos_pcie, 1, PCIE_PWR_RESET);
- exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET);
- exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_CMN_REG);
- exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSVREG_RESET);
- exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSV_RESET);
+ exynos_blk_writel(exynos, 0, PCIE_PHY_GLOBAL_RESET);
+ exynos_elb_writel(exynos, 1, PCIE_PWR_RESET);
+ exynos_blk_writel(exynos, 0, PCIE_PHY_COMMON_RESET);
+ exynos_blk_writel(exynos, 0, PCIE_PHY_CMN_REG);
+ exynos_blk_writel(exynos, 0, PCIE_PHY_TRSVREG_RESET);
+ exynos_blk_writel(exynos, 0, PCIE_PHY_TRSV_RESET);
}
static void exynos_pcie_power_on_phy(struct pcie_port *pp)
{
u32 val;
- struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ struct exynos_pcie *exynos = to_exynos_pcie(pp);
- val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER);
+ val = exynos_phy_readl(exynos, PCIE_PHY_COMMON_POWER);
val &= ~PCIE_PHY_COMMON_PD_CMN;
- exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER);
+ exynos_phy_writel(exynos, val, PCIE_PHY_COMMON_POWER);
- val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER);
+ val = exynos_phy_readl(exynos, PCIE_PHY_TRSV0_POWER);
val &= ~PCIE_PHY_TRSV0_PD_TSV;
- exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER);
+ exynos_phy_writel(exynos, val, PCIE_PHY_TRSV0_POWER);
- val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER);
+ val = exynos_phy_readl(exynos, PCIE_PHY_TRSV1_POWER);
val &= ~PCIE_PHY_TRSV1_PD_TSV;
- exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER);
+ exynos_phy_writel(exynos, val, PCIE_PHY_TRSV1_POWER);
- val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER);
+ val = exynos_phy_readl(exynos, PCIE_PHY_TRSV2_POWER);
val &= ~PCIE_PHY_TRSV2_PD_TSV;
- exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER);
+ exynos_phy_writel(exynos, val, PCIE_PHY_TRSV2_POWER);
- val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER);
+ val = exynos_phy_readl(exynos, PCIE_PHY_TRSV3_POWER);
val &= ~PCIE_PHY_TRSV3_PD_TSV;
- exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER);
+ exynos_phy_writel(exynos, val, PCIE_PHY_TRSV3_POWER);
}
static void exynos_pcie_power_off_phy(struct pcie_port *pp)
{
u32 val;
- struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ struct exynos_pcie *exynos = to_exynos_pcie(pp);
- val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER);
+ val = exynos_phy_readl(exynos, PCIE_PHY_COMMON_POWER);
val |= PCIE_PHY_COMMON_PD_CMN;
- exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER);
+ exynos_phy_writel(exynos, val, PCIE_PHY_COMMON_POWER);
- val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER);
+ val = exynos_phy_readl(exynos, PCIE_PHY_TRSV0_POWER);
val |= PCIE_PHY_TRSV0_PD_TSV;
- exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER);
+ exynos_phy_writel(exynos, val, PCIE_PHY_TRSV0_POWER);
- val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER);
+ val = exynos_phy_readl(exynos, PCIE_PHY_TRSV1_POWER);
val |= PCIE_PHY_TRSV1_PD_TSV;
- exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER);
+ exynos_phy_writel(exynos, val, PCIE_PHY_TRSV1_POWER);
- val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER);
+ val = exynos_phy_readl(exynos, PCIE_PHY_TRSV2_POWER);
val |= PCIE_PHY_TRSV2_PD_TSV;
- exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER);
+ exynos_phy_writel(exynos, val, PCIE_PHY_TRSV2_POWER);
- val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER);
+ val = exynos_phy_readl(exynos, PCIE_PHY_TRSV3_POWER);
val |= PCIE_PHY_TRSV3_PD_TSV;
- exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER);
+ exynos_phy_writel(exynos, val, PCIE_PHY_TRSV3_POWER);
}
static void exynos_pcie_init_phy(struct pcie_port *pp)
{
- struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ struct exynos_pcie *exynos = to_exynos_pcie(pp);
/* DCC feedback control off */
- exynos_phy_writel(exynos_pcie, 0x29, PCIE_PHY_DCC_FEEDBACK);
+ exynos_phy_writel(exynos, 0x29, PCIE_PHY_DCC_FEEDBACK);
/* set TX/RX impedance */
- exynos_phy_writel(exynos_pcie, 0xd5, PCIE_PHY_IMPEDANCE);
+ exynos_phy_writel(exynos, 0xd5, PCIE_PHY_IMPEDANCE);
/* set 50Mhz PHY clock */
- exynos_phy_writel(exynos_pcie, 0x14, PCIE_PHY_PLL_DIV_0);
- exynos_phy_writel(exynos_pcie, 0x12, PCIE_PHY_PLL_DIV_1);
+ exynos_phy_writel(exynos, 0x14, PCIE_PHY_PLL_DIV_0);
+ exynos_phy_writel(exynos, 0x12, PCIE_PHY_PLL_DIV_1);
/* set TX Differential output for lane 0 */
- exynos_phy_writel(exynos_pcie, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
+ exynos_phy_writel(exynos, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
/* set TX Pre-emphasis Level Control for lane 0 to minimum */
- exynos_phy_writel(exynos_pcie, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
+ exynos_phy_writel(exynos, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
/* set RX clock and data recovery bandwidth */
- exynos_phy_writel(exynos_pcie, 0xe7, PCIE_PHY_PLL_BIAS);
- exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV0_RXCDR);
- exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV1_RXCDR);
- exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV2_RXCDR);
- exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV3_RXCDR);
+ exynos_phy_writel(exynos, 0xe7, PCIE_PHY_PLL_BIAS);
+ exynos_phy_writel(exynos, 0x82, PCIE_PHY_TRSV0_RXCDR);
+ exynos_phy_writel(exynos, 0x82, PCIE_PHY_TRSV1_RXCDR);
+ exynos_phy_writel(exynos, 0x82, PCIE_PHY_TRSV2_RXCDR);
+ exynos_phy_writel(exynos, 0x82, PCIE_PHY_TRSV3_RXCDR);
/* change TX Pre-emphasis Level Control for lanes */
- exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
- exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
- exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
- exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
+ exynos_phy_writel(exynos, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
+ exynos_phy_writel(exynos, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
+ exynos_phy_writel(exynos, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
+ exynos_phy_writel(exynos, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
/* set LVCC */
- exynos_phy_writel(exynos_pcie, 0x20, PCIE_PHY_TRSV0_LVCC);
- exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV1_LVCC);
- exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV2_LVCC);
- exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV3_LVCC);
+ exynos_phy_writel(exynos, 0x20, PCIE_PHY_TRSV0_LVCC);
+ exynos_phy_writel(exynos, 0xa0, PCIE_PHY_TRSV1_LVCC);
+ exynos_phy_writel(exynos, 0xa0, PCIE_PHY_TRSV2_LVCC);
+ exynos_phy_writel(exynos, 0xa0, PCIE_PHY_TRSV3_LVCC);
}
static void exynos_pcie_assert_reset(struct pcie_port *pp)
{
- struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ struct exynos_pcie *exynos = to_exynos_pcie(pp);
- if (exynos_pcie->reset_gpio >= 0)
- devm_gpio_request_one(pp->dev, exynos_pcie->reset_gpio,
+ if (exynos->reset_gpio >= 0)
+ devm_gpio_request_one(pp->dev, exynos->reset_gpio,
GPIOF_OUT_INIT_HIGH, "RESET");
}
static int exynos_pcie_establish_link(struct pcie_port *pp)
{
- struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ struct exynos_pcie *exynos = to_exynos_pcie(pp);
u32 val;
if (dw_pcie_link_up(pp)) {
@@ -338,9 +338,9 @@ static int exynos_pcie_establish_link(struct pcie_port *pp)
exynos_pcie_init_phy(pp);
/* pulse for common reset */
- exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_COMMON_RESET);
+ exynos_blk_writel(exynos, 1, PCIE_PHY_COMMON_RESET);
udelay(500);
- exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET);
+ exynos_blk_writel(exynos, 0, PCIE_PHY_COMMON_RESET);
/* de-assert core reset */
exynos_pcie_deassert_core_reset(pp);
@@ -352,15 +352,15 @@ static int exynos_pcie_establish_link(struct pcie_port *pp)
exynos_pcie_assert_reset(pp);
/* assert LTSSM enable */
- exynos_elb_writel(exynos_pcie, PCIE_ELBI_LTSSM_ENABLE,
+ exynos_elb_writel(exynos, PCIE_ELBI_LTSSM_ENABLE,
PCIE_APP_LTSSM_ENABLE);
/* check if the link is up or not */
if (!dw_pcie_wait_for_link(pp))
return 0;
- while (exynos_phy_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED) == 0) {
- val = exynos_blk_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED);
+ while (exynos_phy_readl(exynos, PCIE_PHY_PLL_LOCKED) == 0) {
+ val = exynos_blk_readl(exynos, PCIE_PHY_PLL_LOCKED);
dev_info(pp->dev, "PLL Locked: 0x%x\n", val);
}
/* power off phy */
@@ -372,21 +372,21 @@ static int exynos_pcie_establish_link(struct pcie_port *pp)
static void exynos_pcie_clear_irq_pulse(struct pcie_port *pp)
{
u32 val;
- struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ struct exynos_pcie *exynos = to_exynos_pcie(pp);
- val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_PULSE);
- exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_PULSE);
+ val = exynos_elb_readl(exynos, PCIE_IRQ_PULSE);
+ exynos_elb_writel(exynos, val, PCIE_IRQ_PULSE);
}
static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp)
{
u32 val;
- struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ struct exynos_pcie *exynos = to_exynos_pcie(pp);
/* enable INTX interrupt */
val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
IRQ_INTC_ASSERT | IRQ_INTD_ASSERT;
- exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_PULSE);
+ exynos_elb_writel(exynos, val, PCIE_IRQ_EN_PULSE);
}
static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
@@ -407,14 +407,14 @@ static irqreturn_t exynos_pcie_msi_irq_handler(int irq, void *arg)
static void exynos_pcie_msi_init(struct pcie_port *pp)
{
u32 val;
- struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ struct exynos_pcie *exynos = to_exynos_pcie(pp);
dw_pcie_msi_init(pp);
/* enable MSI interrupt */
- val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_EN_LEVEL);
+ val = exynos_elb_readl(exynos, PCIE_IRQ_EN_LEVEL);
val |= IRQ_MSI_ENABLE;
- exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_LEVEL);
+ exynos_elb_writel(exynos, val, PCIE_IRQ_EN_LEVEL);
}
static void exynos_pcie_enable_interrupts(struct pcie_port *pp)
@@ -466,8 +466,8 @@ static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
static int exynos_pcie_link_up(struct pcie_port *pp)
{
- struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
- u32 val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_RDLH_LINKUP);
+ struct exynos_pcie *exynos = to_exynos_pcie(pp);
+ u32 val = exynos_elb_readl(exynos, PCIE_ELBI_RDLH_LINKUP);
if (val == PCIE_ELBI_LTSSM_ENABLE)
return 1;
@@ -538,7 +538,7 @@ static int __init exynos_add_pcie_port(struct pcie_port *pp,
static int __init exynos_pcie_probe(struct platform_device *pdev)
{
- struct exynos_pcie *exynos_pcie;
+ struct exynos_pcie *exynos;
struct pcie_port *pp;
struct device_node *np = pdev->dev.of_node;
struct resource *elbi_base;
@@ -546,54 +546,52 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
struct resource *block_base;
int ret;
- exynos_pcie = devm_kzalloc(&pdev->dev, sizeof(*exynos_pcie),
- GFP_KERNEL);
- if (!exynos_pcie)
+ exynos = devm_kzalloc(&pdev->dev, sizeof(*exynos), GFP_KERNEL);
+ if (!exynos)
return -ENOMEM;
- pp = &exynos_pcie->pp;
-
+ pp = &exynos->pp;
pp->dev = &pdev->dev;
- exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
+ exynos->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
- exynos_pcie->clk = devm_clk_get(&pdev->dev, "pcie");
- if (IS_ERR(exynos_pcie->clk)) {
+ exynos->clk = devm_clk_get(&pdev->dev, "pcie");
+ if (IS_ERR(exynos->clk)) {
dev_err(&pdev->dev, "Failed to get pcie rc clock\n");
- return PTR_ERR(exynos_pcie->clk);
+ return PTR_ERR(exynos->clk);
}
- ret = clk_prepare_enable(exynos_pcie->clk);
+ ret = clk_prepare_enable(exynos->clk);
if (ret)
return ret;
- exynos_pcie->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
- if (IS_ERR(exynos_pcie->bus_clk)) {
+ exynos->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
+ if (IS_ERR(exynos->bus_clk)) {
dev_err(&pdev->dev, "Failed to get pcie bus clock\n");
- ret = PTR_ERR(exynos_pcie->bus_clk);
+ ret = PTR_ERR(exynos->bus_clk);
goto fail_clk;
}
- ret = clk_prepare_enable(exynos_pcie->bus_clk);
+ ret = clk_prepare_enable(exynos->bus_clk);
if (ret)
goto fail_clk;
elbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- exynos_pcie->elbi_base = devm_ioremap_resource(&pdev->dev, elbi_base);
- if (IS_ERR(exynos_pcie->elbi_base)) {
- ret = PTR_ERR(exynos_pcie->elbi_base);
+ exynos->elbi_base = devm_ioremap_resource(&pdev->dev, elbi_base);
+ if (IS_ERR(exynos->elbi_base)) {
+ ret = PTR_ERR(exynos->elbi_base);
goto fail_bus_clk;
}
phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- exynos_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy_base);
- if (IS_ERR(exynos_pcie->phy_base)) {
- ret = PTR_ERR(exynos_pcie->phy_base);
+ exynos->phy_base = devm_ioremap_resource(&pdev->dev, phy_base);
+ if (IS_ERR(exynos->phy_base)) {
+ ret = PTR_ERR(exynos->phy_base);
goto fail_bus_clk;
}
block_base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
- exynos_pcie->block_base = devm_ioremap_resource(&pdev->dev, block_base);
- if (IS_ERR(exynos_pcie->block_base)) {
- ret = PTR_ERR(exynos_pcie->block_base);
+ exynos->block_base = devm_ioremap_resource(&pdev->dev, block_base);
+ if (IS_ERR(exynos->block_base)) {
+ ret = PTR_ERR(exynos->block_base);
goto fail_bus_clk;
}
@@ -601,22 +599,22 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
if (ret < 0)
goto fail_bus_clk;
- platform_set_drvdata(pdev, exynos_pcie);
+ platform_set_drvdata(pdev, exynos);
return 0;
fail_bus_clk:
- clk_disable_unprepare(exynos_pcie->bus_clk);
+ clk_disable_unprepare(exynos->bus_clk);
fail_clk:
- clk_disable_unprepare(exynos_pcie->clk);
+ clk_disable_unprepare(exynos->clk);
return ret;
}
static int __exit exynos_pcie_remove(struct platform_device *pdev)
{
- struct exynos_pcie *exynos_pcie = platform_get_drvdata(pdev);
+ struct exynos_pcie *exynos = platform_get_drvdata(pdev);
- clk_disable_unprepare(exynos_pcie->bus_clk);
- clk_disable_unprepare(exynos_pcie->clk);
+ clk_disable_unprepare(exynos->bus_clk);
+ clk_disable_unprepare(exynos->clk);
return 0;
}
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/8] PCI: exynos: Pass device-specific struct to internal functions
2016-10-07 16:35 [PATCH 1/8] PCI: exynos: Name private struct pointer "exynos" consistently Bjorn Helgaas
@ 2016-10-07 16:35 ` Bjorn Helgaas
2016-10-07 16:35 ` [PATCH 3/8] PCI: exynos: Reorder struct exynos_pcie Bjorn Helgaas
` (6 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:35 UTC (permalink / raw)
To: Jingoo Han, Krzysztof Kozlowski, Kukjin Kim; +Cc: linux-pci, linux-samsung-soc
Only interfaces used from outside the driver, e.g., those called by the
DesignWare core, need to accept pointers to the generic struct pcie_port.
Internal interfaces can accept pointers to the device-specific struct,
which makes them more straightforward. No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pci-exynos.c | 130 ++++++++++++++++++-----------------------
1 file changed, 56 insertions(+), 74 deletions(-)
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index 05eb246..fa0784d 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -132,10 +132,9 @@ static u32 exynos_blk_readl(struct exynos_pcie *exynos, u32 reg)
return readl(exynos->block_base + reg);
}
-static void exynos_pcie_sideband_dbi_w_mode(struct pcie_port *pp, bool on)
+static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *exynos, bool on)
{
u32 val;
- struct exynos_pcie *exynos = to_exynos_pcie(pp);
if (on) {
val = exynos_elb_readl(exynos, PCIE_ELBI_SLV_AWMISC);
@@ -148,10 +147,9 @@ static void exynos_pcie_sideband_dbi_w_mode(struct pcie_port *pp, bool on)
}
}
-static void exynos_pcie_sideband_dbi_r_mode(struct pcie_port *pp, bool on)
+static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *exynos, bool on)
{
u32 val;
- struct exynos_pcie *exynos = to_exynos_pcie(pp);
if (on) {
val = exynos_elb_readl(exynos, PCIE_ELBI_SLV_ARMISC);
@@ -164,10 +162,9 @@ static void exynos_pcie_sideband_dbi_r_mode(struct pcie_port *pp, bool on)
}
}
-static void exynos_pcie_assert_core_reset(struct pcie_port *pp)
+static void exynos_pcie_assert_core_reset(struct exynos_pcie *exynos)
{
u32 val;
- struct exynos_pcie *exynos = to_exynos_pcie(pp);
val = exynos_elb_readl(exynos, PCIE_CORE_RESET);
val &= ~PCIE_CORE_RESET_ENABLE;
@@ -177,10 +174,9 @@ static void exynos_pcie_assert_core_reset(struct pcie_port *pp)
exynos_elb_writel(exynos, 0, PCIE_NONSTICKY_RESET);
}
-static void exynos_pcie_deassert_core_reset(struct pcie_port *pp)
+static void exynos_pcie_deassert_core_reset(struct exynos_pcie *exynos)
{
u32 val;
- struct exynos_pcie *exynos = to_exynos_pcie(pp);
val = exynos_elb_readl(exynos, PCIE_CORE_RESET);
val |= PCIE_CORE_RESET_ENABLE;
@@ -193,18 +189,14 @@ static void exynos_pcie_deassert_core_reset(struct pcie_port *pp)
exynos_blk_writel(exynos, 1, PCIE_PHY_MAC_RESET);
}
-static void exynos_pcie_assert_phy_reset(struct pcie_port *pp)
+static void exynos_pcie_assert_phy_reset(struct exynos_pcie *exynos)
{
- struct exynos_pcie *exynos = to_exynos_pcie(pp);
-
exynos_blk_writel(exynos, 0, PCIE_PHY_MAC_RESET);
exynos_blk_writel(exynos, 1, PCIE_PHY_GLOBAL_RESET);
}
-static void exynos_pcie_deassert_phy_reset(struct pcie_port *pp)
+static void exynos_pcie_deassert_phy_reset(struct exynos_pcie *exynos)
{
- struct exynos_pcie *exynos = to_exynos_pcie(pp);
-
exynos_blk_writel(exynos, 0, PCIE_PHY_GLOBAL_RESET);
exynos_elb_writel(exynos, 1, PCIE_PWR_RESET);
exynos_blk_writel(exynos, 0, PCIE_PHY_COMMON_RESET);
@@ -213,10 +205,9 @@ static void exynos_pcie_deassert_phy_reset(struct pcie_port *pp)
exynos_blk_writel(exynos, 0, PCIE_PHY_TRSV_RESET);
}
-static void exynos_pcie_power_on_phy(struct pcie_port *pp)
+static void exynos_pcie_power_on_phy(struct exynos_pcie *exynos)
{
u32 val;
- struct exynos_pcie *exynos = to_exynos_pcie(pp);
val = exynos_phy_readl(exynos, PCIE_PHY_COMMON_POWER);
val &= ~PCIE_PHY_COMMON_PD_CMN;
@@ -239,10 +230,9 @@ static void exynos_pcie_power_on_phy(struct pcie_port *pp)
exynos_phy_writel(exynos, val, PCIE_PHY_TRSV3_POWER);
}
-static void exynos_pcie_power_off_phy(struct pcie_port *pp)
+static void exynos_pcie_power_off_phy(struct exynos_pcie *exynos)
{
u32 val;
- struct exynos_pcie *exynos = to_exynos_pcie(pp);
val = exynos_phy_readl(exynos, PCIE_PHY_COMMON_POWER);
val |= PCIE_PHY_COMMON_PD_CMN;
@@ -265,10 +255,8 @@ static void exynos_pcie_power_off_phy(struct pcie_port *pp)
exynos_phy_writel(exynos, val, PCIE_PHY_TRSV3_POWER);
}
-static void exynos_pcie_init_phy(struct pcie_port *pp)
+static void exynos_pcie_init_phy(struct exynos_pcie *exynos)
{
- struct exynos_pcie *exynos = to_exynos_pcie(pp);
-
/* DCC feedback control off */
exynos_phy_writel(exynos, 0x29, PCIE_PHY_DCC_FEEDBACK);
@@ -305,18 +293,18 @@ static void exynos_pcie_init_phy(struct pcie_port *pp)
exynos_phy_writel(exynos, 0xa0, PCIE_PHY_TRSV3_LVCC);
}
-static void exynos_pcie_assert_reset(struct pcie_port *pp)
+static void exynos_pcie_assert_reset(struct exynos_pcie *exynos)
{
- struct exynos_pcie *exynos = to_exynos_pcie(pp);
+ struct pcie_port *pp = &exynos->pp;
if (exynos->reset_gpio >= 0)
devm_gpio_request_one(pp->dev, exynos->reset_gpio,
GPIOF_OUT_INIT_HIGH, "RESET");
}
-static int exynos_pcie_establish_link(struct pcie_port *pp)
+static int exynos_pcie_establish_link(struct exynos_pcie *exynos)
{
- struct exynos_pcie *exynos = to_exynos_pcie(pp);
+ struct pcie_port *pp = &exynos->pp;
u32 val;
if (dw_pcie_link_up(pp)) {
@@ -324,32 +312,20 @@ static int exynos_pcie_establish_link(struct pcie_port *pp)
return 0;
}
- /* assert reset signals */
- exynos_pcie_assert_core_reset(pp);
- exynos_pcie_assert_phy_reset(pp);
-
- /* de-assert phy reset */
- exynos_pcie_deassert_phy_reset(pp);
-
- /* power on phy */
- exynos_pcie_power_on_phy(pp);
-
- /* initialize phy */
- exynos_pcie_init_phy(pp);
+ exynos_pcie_assert_core_reset(exynos);
+ exynos_pcie_assert_phy_reset(exynos);
+ exynos_pcie_deassert_phy_reset(exynos);
+ exynos_pcie_power_on_phy(exynos);
+ exynos_pcie_init_phy(exynos);
/* pulse for common reset */
exynos_blk_writel(exynos, 1, PCIE_PHY_COMMON_RESET);
udelay(500);
exynos_blk_writel(exynos, 0, PCIE_PHY_COMMON_RESET);
- /* de-assert core reset */
- exynos_pcie_deassert_core_reset(pp);
-
- /* setup root complex */
+ exynos_pcie_deassert_core_reset(exynos);
dw_pcie_setup_rc(pp);
-
- /* assert reset signal */
- exynos_pcie_assert_reset(pp);
+ exynos_pcie_assert_reset(exynos);
/* assert LTSSM enable */
exynos_elb_writel(exynos, PCIE_ELBI_LTSSM_ENABLE,
@@ -363,25 +339,21 @@ static int exynos_pcie_establish_link(struct pcie_port *pp)
val = exynos_blk_readl(exynos, PCIE_PHY_PLL_LOCKED);
dev_info(pp->dev, "PLL Locked: 0x%x\n", val);
}
- /* power off phy */
- exynos_pcie_power_off_phy(pp);
-
+ exynos_pcie_power_off_phy(exynos);
return -ETIMEDOUT;
}
-static void exynos_pcie_clear_irq_pulse(struct pcie_port *pp)
+static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *exynos)
{
u32 val;
- struct exynos_pcie *exynos = to_exynos_pcie(pp);
val = exynos_elb_readl(exynos, PCIE_IRQ_PULSE);
exynos_elb_writel(exynos, val, PCIE_IRQ_PULSE);
}
-static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp)
+static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *exynos)
{
u32 val;
- struct exynos_pcie *exynos = to_exynos_pcie(pp);
/* enable INTX interrupt */
val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
@@ -391,23 +363,24 @@ static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp)
static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
{
- struct pcie_port *pp = arg;
+ struct exynos_pcie *exynos = arg;
- exynos_pcie_clear_irq_pulse(pp);
+ exynos_pcie_clear_irq_pulse(exynos);
return IRQ_HANDLED;
}
static irqreturn_t exynos_pcie_msi_irq_handler(int irq, void *arg)
{
- struct pcie_port *pp = arg;
+ struct exynos_pcie *exynos = arg;
+ struct pcie_port *pp = &exynos->pp;
return dw_handle_msi_irq(pp);
}
-static void exynos_pcie_msi_init(struct pcie_port *pp)
+static void exynos_pcie_msi_init(struct exynos_pcie *exynos)
{
+ struct pcie_port *pp = &exynos->pp;
u32 val;
- struct exynos_pcie *exynos = to_exynos_pcie(pp);
dw_pcie_msi_init(pp);
@@ -417,58 +390,64 @@ static void exynos_pcie_msi_init(struct pcie_port *pp)
exynos_elb_writel(exynos, val, PCIE_IRQ_EN_LEVEL);
}
-static void exynos_pcie_enable_interrupts(struct pcie_port *pp)
+static void exynos_pcie_enable_interrupts(struct exynos_pcie *exynos)
{
- exynos_pcie_enable_irq_pulse(pp);
+ exynos_pcie_enable_irq_pulse(exynos);
if (IS_ENABLED(CONFIG_PCI_MSI))
- exynos_pcie_msi_init(pp);
+ exynos_pcie_msi_init(exynos);
}
static inline u32 exynos_pcie_readl_rc(struct pcie_port *pp, u32 reg)
{
+ struct exynos_pcie *exynos = to_exynos_pcie(pp);
u32 val;
- exynos_pcie_sideband_dbi_r_mode(pp, true);
+ exynos_pcie_sideband_dbi_r_mode(exynos, true);
val = readl(pp->dbi_base + reg);
- exynos_pcie_sideband_dbi_r_mode(pp, false);
+ exynos_pcie_sideband_dbi_r_mode(exynos, false);
return val;
}
static inline void exynos_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val)
{
- exynos_pcie_sideband_dbi_w_mode(pp, true);
+ struct exynos_pcie *exynos = to_exynos_pcie(pp);
+
+ exynos_pcie_sideband_dbi_w_mode(exynos, true);
writel(val, pp->dbi_base + reg);
- exynos_pcie_sideband_dbi_w_mode(pp, false);
+ exynos_pcie_sideband_dbi_w_mode(exynos, false);
}
static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
u32 *val)
{
+ struct exynos_pcie *exynos = to_exynos_pcie(pp);
int ret;
- exynos_pcie_sideband_dbi_r_mode(pp, true);
+ exynos_pcie_sideband_dbi_r_mode(exynos, true);
ret = dw_pcie_cfg_read(pp->dbi_base + where, size, val);
- exynos_pcie_sideband_dbi_r_mode(pp, false);
+ exynos_pcie_sideband_dbi_r_mode(exynos, false);
return ret;
}
static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
u32 val)
{
+ struct exynos_pcie *exynos = to_exynos_pcie(pp);
int ret;
- exynos_pcie_sideband_dbi_w_mode(pp, true);
+ exynos_pcie_sideband_dbi_w_mode(exynos, true);
ret = dw_pcie_cfg_write(pp->dbi_base + where, size, val);
- exynos_pcie_sideband_dbi_w_mode(pp, false);
+ exynos_pcie_sideband_dbi_w_mode(exynos, false);
return ret;
}
static int exynos_pcie_link_up(struct pcie_port *pp)
{
struct exynos_pcie *exynos = to_exynos_pcie(pp);
- u32 val = exynos_elb_readl(exynos, PCIE_ELBI_RDLH_LINKUP);
+ u32 val;
+ val = exynos_elb_readl(exynos, PCIE_ELBI_RDLH_LINKUP);
if (val == PCIE_ELBI_LTSSM_ENABLE)
return 1;
@@ -477,8 +456,10 @@ static int exynos_pcie_link_up(struct pcie_port *pp)
static void exynos_pcie_host_init(struct pcie_port *pp)
{
- exynos_pcie_establish_link(pp);
- exynos_pcie_enable_interrupts(pp);
+ struct exynos_pcie *exynos = to_exynos_pcie(pp);
+
+ exynos_pcie_establish_link(exynos);
+ exynos_pcie_enable_interrupts(exynos);
}
static struct pcie_host_ops exynos_pcie_host_ops = {
@@ -490,9 +471,10 @@ static struct pcie_host_ops exynos_pcie_host_ops = {
.host_init = exynos_pcie_host_init,
};
-static int __init exynos_add_pcie_port(struct pcie_port *pp,
+static int __init exynos_add_pcie_port(struct exynos_pcie *exynos,
struct platform_device *pdev)
{
+ struct pcie_port *pp = &exynos->pp;
int ret;
pp->irq = platform_get_irq(pdev, 1);
@@ -501,7 +483,7 @@ static int __init exynos_add_pcie_port(struct pcie_port *pp,
return -ENODEV;
}
ret = devm_request_irq(&pdev->dev, pp->irq, exynos_pcie_irq_handler,
- IRQF_SHARED, "exynos-pcie", pp);
+ IRQF_SHARED, "exynos-pcie", exynos);
if (ret) {
dev_err(&pdev->dev, "failed to request irq\n");
return ret;
@@ -517,7 +499,7 @@ static int __init exynos_add_pcie_port(struct pcie_port *pp,
ret = devm_request_irq(&pdev->dev, pp->msi_irq,
exynos_pcie_msi_irq_handler,
IRQF_SHARED | IRQF_NO_THREAD,
- "exynos-pcie", pp);
+ "exynos-pcie", exynos);
if (ret) {
dev_err(&pdev->dev, "failed to request msi irq\n");
return ret;
@@ -595,7 +577,7 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
goto fail_bus_clk;
}
- ret = exynos_add_pcie_port(pp, pdev);
+ ret = exynos_add_pcie_port(exynos, pdev);
if (ret < 0)
goto fail_bus_clk;
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 3/8] PCI: exynos: Reorder struct exynos_pcie
2016-10-07 16:35 [PATCH 1/8] PCI: exynos: Name private struct pointer "exynos" consistently Bjorn Helgaas
2016-10-07 16:35 ` [PATCH 2/8] PCI: exynos: Pass device-specific struct to internal functions Bjorn Helgaas
@ 2016-10-07 16:35 ` Bjorn Helgaas
2016-10-07 16:35 ` [PATCH 4/8] PCI: exynos: Reorder accessor functions Bjorn Helgaas
` (5 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:35 UTC (permalink / raw)
To: Jingoo Han, Krzysztof Kozlowski, Kukjin Kim; +Cc: linux-pci, linux-samsung-soc
Reorder struct exynos_pcie to put generic fields first. No functional
change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pci-exynos.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index fa0784d..c7b0809 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -29,13 +29,13 @@
#define to_exynos_pcie(x) container_of(x, struct exynos_pcie, pp)
struct exynos_pcie {
- void __iomem *elbi_base;
- void __iomem *phy_base;
- void __iomem *block_base;
+ struct pcie_port pp;
+ void __iomem *elbi_base; /* DT 0th resource */
+ void __iomem *phy_base; /* DT 1st resource */
+ void __iomem *block_base; /* DT 2nd resource */
int reset_gpio;
struct clk *clk;
struct clk *bus_clk;
- struct pcie_port pp;
};
/* PCIe ELBI registers */
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 4/8] PCI: exynos: Reorder accessor functions
2016-10-07 16:35 [PATCH 1/8] PCI: exynos: Name private struct pointer "exynos" consistently Bjorn Helgaas
2016-10-07 16:35 ` [PATCH 2/8] PCI: exynos: Pass device-specific struct to internal functions Bjorn Helgaas
2016-10-07 16:35 ` [PATCH 3/8] PCI: exynos: Reorder struct exynos_pcie Bjorn Helgaas
@ 2016-10-07 16:35 ` Bjorn Helgaas
2016-10-07 16:36 ` [PATCH 5/8] PCI: exynos: Swap order of exynos_elb_writel() reg/val arguments Bjorn Helgaas
` (4 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:35 UTC (permalink / raw)
To: Jingoo Han, Krzysztof Kozlowski, Kukjin Kim; +Cc: linux-pci, linux-samsung-soc
Reorder the accessors so the reader is first, as most other drivers do. No
functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pci-exynos.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index c7b0809..5f54ab5 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -102,19 +102,14 @@ struct exynos_pcie {
#define PCIE_PHY_TRSV3_PD_TSV (0x1 << 7)
#define PCIE_PHY_TRSV3_LVCC 0x31c
-static void exynos_elb_writel(struct exynos_pcie *exynos, u32 val, u32 reg)
-{
- writel(val, exynos->elbi_base + reg);
-}
-
static u32 exynos_elb_readl(struct exynos_pcie *exynos, u32 reg)
{
return readl(exynos->elbi_base + reg);
}
-static void exynos_phy_writel(struct exynos_pcie *exynos, u32 val, u32 reg)
+static void exynos_elb_writel(struct exynos_pcie *exynos, u32 val, u32 reg)
{
- writel(val, exynos->phy_base + reg);
+ writel(val, exynos->elbi_base + reg);
}
static u32 exynos_phy_readl(struct exynos_pcie *exynos, u32 reg)
@@ -122,9 +117,9 @@ static u32 exynos_phy_readl(struct exynos_pcie *exynos, u32 reg)
return readl(exynos->phy_base + reg);
}
-static void exynos_blk_writel(struct exynos_pcie *exynos, u32 val, u32 reg)
+static void exynos_phy_writel(struct exynos_pcie *exynos, u32 val, u32 reg)
{
- writel(val, exynos->block_base + reg);
+ writel(val, exynos->phy_base + reg);
}
static u32 exynos_blk_readl(struct exynos_pcie *exynos, u32 reg)
@@ -132,6 +127,11 @@ static u32 exynos_blk_readl(struct exynos_pcie *exynos, u32 reg)
return readl(exynos->block_base + reg);
}
+static void exynos_blk_writel(struct exynos_pcie *exynos, u32 val, u32 reg)
+{
+ writel(val, exynos->block_base + reg);
+}
+
static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *exynos, bool on)
{
u32 val;
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 5/8] PCI: exynos: Swap order of exynos_elb_writel() reg/val arguments
2016-10-07 16:35 [PATCH 1/8] PCI: exynos: Name private struct pointer "exynos" consistently Bjorn Helgaas
` (2 preceding siblings ...)
2016-10-07 16:35 ` [PATCH 4/8] PCI: exynos: Reorder accessor functions Bjorn Helgaas
@ 2016-10-07 16:36 ` Bjorn Helgaas
2016-10-07 16:36 ` [PATCH 6/8] PCI: exynos: Swap order of exynos_phy_writel() " Bjorn Helgaas
` (3 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:36 UTC (permalink / raw)
To: Jingoo Han, Krzysztof Kozlowski, Kukjin Kim; +Cc: linux-pci, linux-samsung-soc
Swap order of exynos_elb_writel() arguments to match the "dev, pos, val"
order used by pci_write_config_word() and other drivers. No functional
change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pci-exynos.c | 40 ++++++++++++++++++++--------------------
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index 5f54ab5..eb50b1a 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -107,7 +107,7 @@ static u32 exynos_elb_readl(struct exynos_pcie *exynos, u32 reg)
return readl(exynos->elbi_base + reg);
}
-static void exynos_elb_writel(struct exynos_pcie *exynos, u32 val, u32 reg)
+static void exynos_elb_writel(struct exynos_pcie *exynos, u32 reg, u32 val)
{
writel(val, exynos->elbi_base + reg);
}
@@ -139,11 +139,11 @@ static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *exynos, bool on)
if (on) {
val = exynos_elb_readl(exynos, PCIE_ELBI_SLV_AWMISC);
val |= PCIE_ELBI_SLV_DBI_ENABLE;
- exynos_elb_writel(exynos, val, PCIE_ELBI_SLV_AWMISC);
+ exynos_elb_writel(exynos, PCIE_ELBI_SLV_AWMISC, val);
} else {
val = exynos_elb_readl(exynos, PCIE_ELBI_SLV_AWMISC);
val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
- exynos_elb_writel(exynos, val, PCIE_ELBI_SLV_AWMISC);
+ exynos_elb_writel(exynos, PCIE_ELBI_SLV_AWMISC, val);
}
}
@@ -154,11 +154,11 @@ static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *exynos, bool on)
if (on) {
val = exynos_elb_readl(exynos, PCIE_ELBI_SLV_ARMISC);
val |= PCIE_ELBI_SLV_DBI_ENABLE;
- exynos_elb_writel(exynos, val, PCIE_ELBI_SLV_ARMISC);
+ exynos_elb_writel(exynos, PCIE_ELBI_SLV_ARMISC, val);
} else {
val = exynos_elb_readl(exynos, PCIE_ELBI_SLV_ARMISC);
val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
- exynos_elb_writel(exynos, val, PCIE_ELBI_SLV_ARMISC);
+ exynos_elb_writel(exynos, PCIE_ELBI_SLV_ARMISC, val);
}
}
@@ -168,10 +168,10 @@ static void exynos_pcie_assert_core_reset(struct exynos_pcie *exynos)
val = exynos_elb_readl(exynos, PCIE_CORE_RESET);
val &= ~PCIE_CORE_RESET_ENABLE;
- exynos_elb_writel(exynos, val, PCIE_CORE_RESET);
- exynos_elb_writel(exynos, 0, PCIE_PWR_RESET);
- exynos_elb_writel(exynos, 0, PCIE_STICKY_RESET);
- exynos_elb_writel(exynos, 0, PCIE_NONSTICKY_RESET);
+ exynos_elb_writel(exynos, PCIE_CORE_RESET, val);
+ exynos_elb_writel(exynos, PCIE_PWR_RESET, 0);
+ exynos_elb_writel(exynos, PCIE_STICKY_RESET, 0);
+ exynos_elb_writel(exynos, PCIE_NONSTICKY_RESET, 0);
}
static void exynos_pcie_deassert_core_reset(struct exynos_pcie *exynos)
@@ -181,11 +181,11 @@ static void exynos_pcie_deassert_core_reset(struct exynos_pcie *exynos)
val = exynos_elb_readl(exynos, PCIE_CORE_RESET);
val |= PCIE_CORE_RESET_ENABLE;
- exynos_elb_writel(exynos, val, PCIE_CORE_RESET);
- exynos_elb_writel(exynos, 1, PCIE_STICKY_RESET);
- exynos_elb_writel(exynos, 1, PCIE_NONSTICKY_RESET);
- exynos_elb_writel(exynos, 1, PCIE_APP_INIT_RESET);
- exynos_elb_writel(exynos, 0, PCIE_APP_INIT_RESET);
+ exynos_elb_writel(exynos, PCIE_CORE_RESET, val);
+ exynos_elb_writel(exynos, PCIE_STICKY_RESET, 1);
+ exynos_elb_writel(exynos, PCIE_NONSTICKY_RESET, 1);
+ exynos_elb_writel(exynos, PCIE_APP_INIT_RESET, 1);
+ exynos_elb_writel(exynos, PCIE_APP_INIT_RESET, 0);
exynos_blk_writel(exynos, 1, PCIE_PHY_MAC_RESET);
}
@@ -198,7 +198,7 @@ static void exynos_pcie_assert_phy_reset(struct exynos_pcie *exynos)
static void exynos_pcie_deassert_phy_reset(struct exynos_pcie *exynos)
{
exynos_blk_writel(exynos, 0, PCIE_PHY_GLOBAL_RESET);
- exynos_elb_writel(exynos, 1, PCIE_PWR_RESET);
+ exynos_elb_writel(exynos, PCIE_PWR_RESET, 1);
exynos_blk_writel(exynos, 0, PCIE_PHY_COMMON_RESET);
exynos_blk_writel(exynos, 0, PCIE_PHY_CMN_REG);
exynos_blk_writel(exynos, 0, PCIE_PHY_TRSVREG_RESET);
@@ -328,8 +328,8 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos)
exynos_pcie_assert_reset(exynos);
/* assert LTSSM enable */
- exynos_elb_writel(exynos, PCIE_ELBI_LTSSM_ENABLE,
- PCIE_APP_LTSSM_ENABLE);
+ exynos_elb_writel(exynos, PCIE_APP_LTSSM_ENABLE,
+ PCIE_ELBI_LTSSM_ENABLE);
/* check if the link is up or not */
if (!dw_pcie_wait_for_link(pp))
@@ -348,7 +348,7 @@ static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *exynos)
u32 val;
val = exynos_elb_readl(exynos, PCIE_IRQ_PULSE);
- exynos_elb_writel(exynos, val, PCIE_IRQ_PULSE);
+ exynos_elb_writel(exynos, PCIE_IRQ_PULSE, val);
}
static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *exynos)
@@ -358,7 +358,7 @@ static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *exynos)
/* enable INTX interrupt */
val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
IRQ_INTC_ASSERT | IRQ_INTD_ASSERT;
- exynos_elb_writel(exynos, val, PCIE_IRQ_EN_PULSE);
+ exynos_elb_writel(exynos, PCIE_IRQ_EN_PULSE, val);
}
static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
@@ -387,7 +387,7 @@ static void exynos_pcie_msi_init(struct exynos_pcie *exynos)
/* enable MSI interrupt */
val = exynos_elb_readl(exynos, PCIE_IRQ_EN_LEVEL);
val |= IRQ_MSI_ENABLE;
- exynos_elb_writel(exynos, val, PCIE_IRQ_EN_LEVEL);
+ exynos_elb_writel(exynos, PCIE_IRQ_EN_LEVEL, val);
}
static void exynos_pcie_enable_interrupts(struct exynos_pcie *exynos)
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 6/8] PCI: exynos: Swap order of exynos_phy_writel() reg/val arguments
2016-10-07 16:35 [PATCH 1/8] PCI: exynos: Name private struct pointer "exynos" consistently Bjorn Helgaas
` (3 preceding siblings ...)
2016-10-07 16:36 ` [PATCH 5/8] PCI: exynos: Swap order of exynos_elb_writel() reg/val arguments Bjorn Helgaas
@ 2016-10-07 16:36 ` Bjorn Helgaas
2016-10-07 16:36 ` [PATCH 7/8] PCI: exynos: Swap order of exynos_blk_writel() " Bjorn Helgaas
` (2 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:36 UTC (permalink / raw)
To: Jingoo Han, Krzysztof Kozlowski, Kukjin Kim; +Cc: linux-pci, linux-samsung-soc
Swap order of exynos_phy_writel() arguments to match the "dev, pos, val"
order used by pci_write_config_word() and other drivers. No functional
change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pci-exynos.c | 60 +++++++++++++++++++++--------------------
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index eb50b1a..463cbd6 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -117,7 +117,7 @@ static u32 exynos_phy_readl(struct exynos_pcie *exynos, u32 reg)
return readl(exynos->phy_base + reg);
}
-static void exynos_phy_writel(struct exynos_pcie *exynos, u32 val, u32 reg)
+static void exynos_phy_writel(struct exynos_pcie *exynos, u32 reg, u32 val)
{
writel(val, exynos->phy_base + reg);
}
@@ -211,23 +211,23 @@ static void exynos_pcie_power_on_phy(struct exynos_pcie *exynos)
val = exynos_phy_readl(exynos, PCIE_PHY_COMMON_POWER);
val &= ~PCIE_PHY_COMMON_PD_CMN;
- exynos_phy_writel(exynos, val, PCIE_PHY_COMMON_POWER);
+ exynos_phy_writel(exynos, PCIE_PHY_COMMON_POWER, val);
val = exynos_phy_readl(exynos, PCIE_PHY_TRSV0_POWER);
val &= ~PCIE_PHY_TRSV0_PD_TSV;
- exynos_phy_writel(exynos, val, PCIE_PHY_TRSV0_POWER);
+ exynos_phy_writel(exynos, PCIE_PHY_TRSV0_POWER, val);
val = exynos_phy_readl(exynos, PCIE_PHY_TRSV1_POWER);
val &= ~PCIE_PHY_TRSV1_PD_TSV;
- exynos_phy_writel(exynos, val, PCIE_PHY_TRSV1_POWER);
+ exynos_phy_writel(exynos, PCIE_PHY_TRSV1_POWER, val);
val = exynos_phy_readl(exynos, PCIE_PHY_TRSV2_POWER);
val &= ~PCIE_PHY_TRSV2_PD_TSV;
- exynos_phy_writel(exynos, val, PCIE_PHY_TRSV2_POWER);
+ exynos_phy_writel(exynos, PCIE_PHY_TRSV2_POWER, val);
val = exynos_phy_readl(exynos, PCIE_PHY_TRSV3_POWER);
val &= ~PCIE_PHY_TRSV3_PD_TSV;
- exynos_phy_writel(exynos, val, PCIE_PHY_TRSV3_POWER);
+ exynos_phy_writel(exynos, PCIE_PHY_TRSV3_POWER, val);
}
static void exynos_pcie_power_off_phy(struct exynos_pcie *exynos)
@@ -236,61 +236,61 @@ static void exynos_pcie_power_off_phy(struct exynos_pcie *exynos)
val = exynos_phy_readl(exynos, PCIE_PHY_COMMON_POWER);
val |= PCIE_PHY_COMMON_PD_CMN;
- exynos_phy_writel(exynos, val, PCIE_PHY_COMMON_POWER);
+ exynos_phy_writel(exynos, PCIE_PHY_COMMON_POWER, val);
val = exynos_phy_readl(exynos, PCIE_PHY_TRSV0_POWER);
val |= PCIE_PHY_TRSV0_PD_TSV;
- exynos_phy_writel(exynos, val, PCIE_PHY_TRSV0_POWER);
+ exynos_phy_writel(exynos, PCIE_PHY_TRSV0_POWER, val);
val = exynos_phy_readl(exynos, PCIE_PHY_TRSV1_POWER);
val |= PCIE_PHY_TRSV1_PD_TSV;
- exynos_phy_writel(exynos, val, PCIE_PHY_TRSV1_POWER);
+ exynos_phy_writel(exynos, PCIE_PHY_TRSV1_POWER, val);
val = exynos_phy_readl(exynos, PCIE_PHY_TRSV2_POWER);
val |= PCIE_PHY_TRSV2_PD_TSV;
- exynos_phy_writel(exynos, val, PCIE_PHY_TRSV2_POWER);
+ exynos_phy_writel(exynos, PCIE_PHY_TRSV2_POWER, val);
val = exynos_phy_readl(exynos, PCIE_PHY_TRSV3_POWER);
val |= PCIE_PHY_TRSV3_PD_TSV;
- exynos_phy_writel(exynos, val, PCIE_PHY_TRSV3_POWER);
+ exynos_phy_writel(exynos, PCIE_PHY_TRSV3_POWER, val);
}
static void exynos_pcie_init_phy(struct exynos_pcie *exynos)
{
/* DCC feedback control off */
- exynos_phy_writel(exynos, 0x29, PCIE_PHY_DCC_FEEDBACK);
+ exynos_phy_writel(exynos, PCIE_PHY_DCC_FEEDBACK, 0x29);
/* set TX/RX impedance */
- exynos_phy_writel(exynos, 0xd5, PCIE_PHY_IMPEDANCE);
+ exynos_phy_writel(exynos, PCIE_PHY_IMPEDANCE, 0xd5);
/* set 50Mhz PHY clock */
- exynos_phy_writel(exynos, 0x14, PCIE_PHY_PLL_DIV_0);
- exynos_phy_writel(exynos, 0x12, PCIE_PHY_PLL_DIV_1);
+ exynos_phy_writel(exynos, PCIE_PHY_PLL_DIV_0, 0x14);
+ exynos_phy_writel(exynos, PCIE_PHY_PLL_DIV_1, 0x12);
/* set TX Differential output for lane 0 */
- exynos_phy_writel(exynos, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
+ exynos_phy_writel(exynos, PCIE_PHY_TRSV0_DRV_LVL, 0x7f);
/* set TX Pre-emphasis Level Control for lane 0 to minimum */
- exynos_phy_writel(exynos, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
+ exynos_phy_writel(exynos, PCIE_PHY_TRSV0_EMP_LVL, 0x0);
/* set RX clock and data recovery bandwidth */
- exynos_phy_writel(exynos, 0xe7, PCIE_PHY_PLL_BIAS);
- exynos_phy_writel(exynos, 0x82, PCIE_PHY_TRSV0_RXCDR);
- exynos_phy_writel(exynos, 0x82, PCIE_PHY_TRSV1_RXCDR);
- exynos_phy_writel(exynos, 0x82, PCIE_PHY_TRSV2_RXCDR);
- exynos_phy_writel(exynos, 0x82, PCIE_PHY_TRSV3_RXCDR);
+ exynos_phy_writel(exynos, PCIE_PHY_PLL_BIAS, 0xe7);
+ exynos_phy_writel(exynos, PCIE_PHY_TRSV0_RXCDR, 0x82);
+ exynos_phy_writel(exynos, PCIE_PHY_TRSV1_RXCDR, 0x82);
+ exynos_phy_writel(exynos, PCIE_PHY_TRSV2_RXCDR, 0x82);
+ exynos_phy_writel(exynos, PCIE_PHY_TRSV3_RXCDR, 0x82);
/* change TX Pre-emphasis Level Control for lanes */
- exynos_phy_writel(exynos, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
- exynos_phy_writel(exynos, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
- exynos_phy_writel(exynos, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
- exynos_phy_writel(exynos, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
+ exynos_phy_writel(exynos, PCIE_PHY_TRSV0_EMP_LVL, 0x39);
+ exynos_phy_writel(exynos, PCIE_PHY_TRSV1_EMP_LVL, 0x39);
+ exynos_phy_writel(exynos, PCIE_PHY_TRSV2_EMP_LVL, 0x39);
+ exynos_phy_writel(exynos, PCIE_PHY_TRSV3_EMP_LVL, 0x39);
/* set LVCC */
- exynos_phy_writel(exynos, 0x20, PCIE_PHY_TRSV0_LVCC);
- exynos_phy_writel(exynos, 0xa0, PCIE_PHY_TRSV1_LVCC);
- exynos_phy_writel(exynos, 0xa0, PCIE_PHY_TRSV2_LVCC);
- exynos_phy_writel(exynos, 0xa0, PCIE_PHY_TRSV3_LVCC);
+ exynos_phy_writel(exynos, PCIE_PHY_TRSV0_LVCC, 0x20);
+ exynos_phy_writel(exynos, PCIE_PHY_TRSV1_LVCC, 0xa0);
+ exynos_phy_writel(exynos, PCIE_PHY_TRSV2_LVCC, 0xa0);
+ exynos_phy_writel(exynos, PCIE_PHY_TRSV3_LVCC, 0xa0);
}
static void exynos_pcie_assert_reset(struct exynos_pcie *exynos)
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 7/8] PCI: exynos: Swap order of exynos_blk_writel() reg/val arguments
2016-10-07 16:35 [PATCH 1/8] PCI: exynos: Name private struct pointer "exynos" consistently Bjorn Helgaas
` (4 preceding siblings ...)
2016-10-07 16:36 ` [PATCH 6/8] PCI: exynos: Swap order of exynos_phy_writel() " Bjorn Helgaas
@ 2016-10-07 16:36 ` Bjorn Helgaas
2016-10-07 16:36 ` [PATCH 8/8] PCI: exynos: Add local struct device pointers Bjorn Helgaas
2016-10-08 19:41 ` [PATCH 1/8] PCI: exynos: Name private struct pointer "exynos" consistently Krzysztof Kozlowski
7 siblings, 0 replies; 11+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:36 UTC (permalink / raw)
To: Jingoo Han, Krzysztof Kozlowski, Kukjin Kim; +Cc: linux-pci, linux-samsung-soc
Swap order of exynos_blk_writel() arguments to match the "dev, pos, val"
order used by pci_write_config_word() and other drivers. No functional
change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pci-exynos.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index 463cbd6..4fb3ce7 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -127,7 +127,7 @@ static u32 exynos_blk_readl(struct exynos_pcie *exynos, u32 reg)
return readl(exynos->block_base + reg);
}
-static void exynos_blk_writel(struct exynos_pcie *exynos, u32 val, u32 reg)
+static void exynos_blk_writel(struct exynos_pcie *exynos, u32 reg, u32 val)
{
writel(val, exynos->block_base + reg);
}
@@ -186,23 +186,23 @@ static void exynos_pcie_deassert_core_reset(struct exynos_pcie *exynos)
exynos_elb_writel(exynos, PCIE_NONSTICKY_RESET, 1);
exynos_elb_writel(exynos, PCIE_APP_INIT_RESET, 1);
exynos_elb_writel(exynos, PCIE_APP_INIT_RESET, 0);
- exynos_blk_writel(exynos, 1, PCIE_PHY_MAC_RESET);
+ exynos_blk_writel(exynos, PCIE_PHY_MAC_RESET, 1);
}
static void exynos_pcie_assert_phy_reset(struct exynos_pcie *exynos)
{
- exynos_blk_writel(exynos, 0, PCIE_PHY_MAC_RESET);
- exynos_blk_writel(exynos, 1, PCIE_PHY_GLOBAL_RESET);
+ exynos_blk_writel(exynos, PCIE_PHY_MAC_RESET, 0);
+ exynos_blk_writel(exynos, PCIE_PHY_GLOBAL_RESET, 1);
}
static void exynos_pcie_deassert_phy_reset(struct exynos_pcie *exynos)
{
- exynos_blk_writel(exynos, 0, PCIE_PHY_GLOBAL_RESET);
+ exynos_blk_writel(exynos, PCIE_PHY_GLOBAL_RESET, 0);
exynos_elb_writel(exynos, PCIE_PWR_RESET, 1);
- exynos_blk_writel(exynos, 0, PCIE_PHY_COMMON_RESET);
- exynos_blk_writel(exynos, 0, PCIE_PHY_CMN_REG);
- exynos_blk_writel(exynos, 0, PCIE_PHY_TRSVREG_RESET);
- exynos_blk_writel(exynos, 0, PCIE_PHY_TRSV_RESET);
+ exynos_blk_writel(exynos, PCIE_PHY_COMMON_RESET, 0);
+ exynos_blk_writel(exynos, PCIE_PHY_CMN_REG, 0);
+ exynos_blk_writel(exynos, PCIE_PHY_TRSVREG_RESET, 0);
+ exynos_blk_writel(exynos, PCIE_PHY_TRSV_RESET, 0);
}
static void exynos_pcie_power_on_phy(struct exynos_pcie *exynos)
@@ -319,9 +319,9 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos)
exynos_pcie_init_phy(exynos);
/* pulse for common reset */
- exynos_blk_writel(exynos, 1, PCIE_PHY_COMMON_RESET);
+ exynos_blk_writel(exynos, PCIE_PHY_COMMON_RESET, 1);
udelay(500);
- exynos_blk_writel(exynos, 0, PCIE_PHY_COMMON_RESET);
+ exynos_blk_writel(exynos, PCIE_PHY_COMMON_RESET, 0);
exynos_pcie_deassert_core_reset(exynos);
dw_pcie_setup_rc(pp);
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 8/8] PCI: exynos: Add local struct device pointers
2016-10-07 16:35 [PATCH 1/8] PCI: exynos: Name private struct pointer "exynos" consistently Bjorn Helgaas
` (5 preceding siblings ...)
2016-10-07 16:36 ` [PATCH 7/8] PCI: exynos: Swap order of exynos_blk_writel() " Bjorn Helgaas
@ 2016-10-07 16:36 ` Bjorn Helgaas
2016-10-08 19:41 ` [PATCH 1/8] PCI: exynos: Name private struct pointer "exynos" consistently Krzysztof Kozlowski
7 siblings, 0 replies; 11+ messages in thread
From: Bjorn Helgaas @ 2016-10-07 16:36 UTC (permalink / raw)
To: Jingoo Han, Krzysztof Kozlowski, Kukjin Kim; +Cc: linux-pci, linux-samsung-soc
Use a local "struct device *dev" for brevity and consistency with other
drivers. No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/host/pci-exynos.c | 44 ++++++++++++++++++++++-------------------
1 file changed, 24 insertions(+), 20 deletions(-)
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index 4fb3ce7..0e3cdc4 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -296,19 +296,21 @@ static void exynos_pcie_init_phy(struct exynos_pcie *exynos)
static void exynos_pcie_assert_reset(struct exynos_pcie *exynos)
{
struct pcie_port *pp = &exynos->pp;
+ struct device *dev = pp->dev;
if (exynos->reset_gpio >= 0)
- devm_gpio_request_one(pp->dev, exynos->reset_gpio,
+ devm_gpio_request_one(dev, exynos->reset_gpio,
GPIOF_OUT_INIT_HIGH, "RESET");
}
static int exynos_pcie_establish_link(struct exynos_pcie *exynos)
{
struct pcie_port *pp = &exynos->pp;
+ struct device *dev = pp->dev;
u32 val;
if (dw_pcie_link_up(pp)) {
- dev_err(pp->dev, "Link already up\n");
+ dev_err(dev, "Link already up\n");
return 0;
}
@@ -337,7 +339,7 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos)
while (exynos_phy_readl(exynos, PCIE_PHY_PLL_LOCKED) == 0) {
val = exynos_blk_readl(exynos, PCIE_PHY_PLL_LOCKED);
- dev_info(pp->dev, "PLL Locked: 0x%x\n", val);
+ dev_info(dev, "PLL Locked: 0x%x\n", val);
}
exynos_pcie_power_off_phy(exynos);
return -ETIMEDOUT;
@@ -475,33 +477,34 @@ static int __init exynos_add_pcie_port(struct exynos_pcie *exynos,
struct platform_device *pdev)
{
struct pcie_port *pp = &exynos->pp;
+ struct device *dev = pp->dev;
int ret;
pp->irq = platform_get_irq(pdev, 1);
if (!pp->irq) {
- dev_err(&pdev->dev, "failed to get irq\n");
+ dev_err(dev, "failed to get irq\n");
return -ENODEV;
}
- ret = devm_request_irq(&pdev->dev, pp->irq, exynos_pcie_irq_handler,
+ ret = devm_request_irq(dev, pp->irq, exynos_pcie_irq_handler,
IRQF_SHARED, "exynos-pcie", exynos);
if (ret) {
- dev_err(&pdev->dev, "failed to request irq\n");
+ dev_err(dev, "failed to request irq\n");
return ret;
}
if (IS_ENABLED(CONFIG_PCI_MSI)) {
pp->msi_irq = platform_get_irq(pdev, 0);
if (!pp->msi_irq) {
- dev_err(&pdev->dev, "failed to get msi irq\n");
+ dev_err(dev, "failed to get msi irq\n");
return -ENODEV;
}
- ret = devm_request_irq(&pdev->dev, pp->msi_irq,
+ ret = devm_request_irq(dev, pp->msi_irq,
exynos_pcie_msi_irq_handler,
IRQF_SHARED | IRQF_NO_THREAD,
"exynos-pcie", exynos);
if (ret) {
- dev_err(&pdev->dev, "failed to request msi irq\n");
+ dev_err(dev, "failed to request msi irq\n");
return ret;
}
}
@@ -511,7 +514,7 @@ static int __init exynos_add_pcie_port(struct exynos_pcie *exynos,
ret = dw_pcie_host_init(pp);
if (ret) {
- dev_err(&pdev->dev, "failed to initialize host\n");
+ dev_err(dev, "failed to initialize host\n");
return ret;
}
@@ -520,35 +523,36 @@ static int __init exynos_add_pcie_port(struct exynos_pcie *exynos,
static int __init exynos_pcie_probe(struct platform_device *pdev)
{
+ struct device *dev = &pdev->dev;
struct exynos_pcie *exynos;
struct pcie_port *pp;
- struct device_node *np = pdev->dev.of_node;
+ struct device_node *np = dev->of_node;
struct resource *elbi_base;
struct resource *phy_base;
struct resource *block_base;
int ret;
- exynos = devm_kzalloc(&pdev->dev, sizeof(*exynos), GFP_KERNEL);
+ exynos = devm_kzalloc(dev, sizeof(*exynos), GFP_KERNEL);
if (!exynos)
return -ENOMEM;
pp = &exynos->pp;
- pp->dev = &pdev->dev;
+ pp->dev = dev;
exynos->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
- exynos->clk = devm_clk_get(&pdev->dev, "pcie");
+ exynos->clk = devm_clk_get(dev, "pcie");
if (IS_ERR(exynos->clk)) {
- dev_err(&pdev->dev, "Failed to get pcie rc clock\n");
+ dev_err(dev, "Failed to get pcie rc clock\n");
return PTR_ERR(exynos->clk);
}
ret = clk_prepare_enable(exynos->clk);
if (ret)
return ret;
- exynos->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
+ exynos->bus_clk = devm_clk_get(dev, "pcie_bus");
if (IS_ERR(exynos->bus_clk)) {
- dev_err(&pdev->dev, "Failed to get pcie bus clock\n");
+ dev_err(dev, "Failed to get pcie bus clock\n");
ret = PTR_ERR(exynos->bus_clk);
goto fail_clk;
}
@@ -557,21 +561,21 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
goto fail_clk;
elbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- exynos->elbi_base = devm_ioremap_resource(&pdev->dev, elbi_base);
+ exynos->elbi_base = devm_ioremap_resource(dev, elbi_base);
if (IS_ERR(exynos->elbi_base)) {
ret = PTR_ERR(exynos->elbi_base);
goto fail_bus_clk;
}
phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- exynos->phy_base = devm_ioremap_resource(&pdev->dev, phy_base);
+ exynos->phy_base = devm_ioremap_resource(dev, phy_base);
if (IS_ERR(exynos->phy_base)) {
ret = PTR_ERR(exynos->phy_base);
goto fail_bus_clk;
}
block_base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
- exynos->block_base = devm_ioremap_resource(&pdev->dev, block_base);
+ exynos->block_base = devm_ioremap_resource(dev, block_base);
if (IS_ERR(exynos->block_base)) {
ret = PTR_ERR(exynos->block_base);
goto fail_bus_clk;
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 1/8] PCI: exynos: Name private struct pointer "exynos" consistently
2016-10-07 16:35 [PATCH 1/8] PCI: exynos: Name private struct pointer "exynos" consistently Bjorn Helgaas
` (6 preceding siblings ...)
2016-10-07 16:36 ` [PATCH 8/8] PCI: exynos: Add local struct device pointers Bjorn Helgaas
@ 2016-10-08 19:41 ` Krzysztof Kozlowski
2016-10-10 13:36 ` Bjorn Helgaas
7 siblings, 1 reply; 11+ messages in thread
From: Krzysztof Kozlowski @ 2016-10-08 19:41 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Jingoo Han, Krzysztof Kozlowski, Kukjin Kim, linux-pci,
linux-samsung-soc
On Fri, Oct 07, 2016 at 11:35:26AM -0500, Bjorn Helgaas wrote:
> Use a device-specific name, "exynos", for struct exynos_pcie pointers
> to hint that this is device-specific information.
I don't get it. "exynos_pcie" is already a exynos-device-specific name.
There are a lot of changes but I don't see the real reason/benefit. What
was your intention?
> No functional change
> intended.
Oh, but there is. Inline disappeared in first functions. Although I
don't mind but this should be seprate from trivial rename.
Best regards,
Krzysztof
>
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> ---
> drivers/pci/host/pci-exynos.c | 272 ++++++++++++++++++++---------------------
> 1 file changed, 135 insertions(+), 137 deletions(-)
>
> diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
> index f559b49..05eb246 100644
> --- a/drivers/pci/host/pci-exynos.c
> +++ b/drivers/pci/host/pci-exynos.c
> @@ -102,221 +102,221 @@ struct exynos_pcie {
> #define PCIE_PHY_TRSV3_PD_TSV (0x1 << 7)
> #define PCIE_PHY_TRSV3_LVCC 0x31c
>
> -static inline void exynos_elb_writel(struct exynos_pcie *pcie, u32 val, u32 reg)
> +static void exynos_elb_writel(struct exynos_pcie *exynos, u32 val, u32 reg)
> {
> - writel(val, pcie->elbi_base + reg);
> + writel(val, exynos->elbi_base + reg);
> }
>
> -static inline u32 exynos_elb_readl(struct exynos_pcie *pcie, u32 reg)
> +static u32 exynos_elb_readl(struct exynos_pcie *exynos, u32 reg)
> {
> - return readl(pcie->elbi_base + reg);
> + return readl(exynos->elbi_base + reg);
> }
>
> -static inline void exynos_phy_writel(struct exynos_pcie *pcie, u32 val, u32 reg)
> +static void exynos_phy_writel(struct exynos_pcie *exynos, u32 val, u32 reg)
> {
> - writel(val, pcie->phy_base + reg);
> + writel(val, exynos->phy_base + reg);
> }
>
> -static inline u32 exynos_phy_readl(struct exynos_pcie *pcie, u32 reg)
> +static u32 exynos_phy_readl(struct exynos_pcie *exynos, u32 reg)
> {
> - return readl(pcie->phy_base + reg);
> + return readl(exynos->phy_base + reg);
> }
>
> -static inline void exynos_blk_writel(struct exynos_pcie *pcie, u32 val, u32 reg)
> +static void exynos_blk_writel(struct exynos_pcie *exynos, u32 val, u32 reg)
> {
> - writel(val, pcie->block_base + reg);
> + writel(val, exynos->block_base + reg);
> }
>
> -static inline u32 exynos_blk_readl(struct exynos_pcie *pcie, u32 reg)
> +static u32 exynos_blk_readl(struct exynos_pcie *exynos, u32 reg)
> {
> - return readl(pcie->block_base + reg);
> + return readl(exynos->block_base + reg);
> }
>
> static void exynos_pcie_sideband_dbi_w_mode(struct pcie_port *pp, bool on)
> {
> u32 val;
> - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> + struct exynos_pcie *exynos = to_exynos_pcie(pp);
>
> if (on) {
> - val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC);
> + val = exynos_elb_readl(exynos, PCIE_ELBI_SLV_AWMISC);
> val |= PCIE_ELBI_SLV_DBI_ENABLE;
> - exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC);
> + exynos_elb_writel(exynos, val, PCIE_ELBI_SLV_AWMISC);
> } else {
> - val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC);
> + val = exynos_elb_readl(exynos, PCIE_ELBI_SLV_AWMISC);
> val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
> - exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC);
> + exynos_elb_writel(exynos, val, PCIE_ELBI_SLV_AWMISC);
> }
> }
>
> static void exynos_pcie_sideband_dbi_r_mode(struct pcie_port *pp, bool on)
> {
> u32 val;
> - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> + struct exynos_pcie *exynos = to_exynos_pcie(pp);
>
> if (on) {
> - val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC);
> + val = exynos_elb_readl(exynos, PCIE_ELBI_SLV_ARMISC);
> val |= PCIE_ELBI_SLV_DBI_ENABLE;
> - exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC);
> + exynos_elb_writel(exynos, val, PCIE_ELBI_SLV_ARMISC);
> } else {
> - val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC);
> + val = exynos_elb_readl(exynos, PCIE_ELBI_SLV_ARMISC);
> val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
> - exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC);
> + exynos_elb_writel(exynos, val, PCIE_ELBI_SLV_ARMISC);
> }
> }
>
> static void exynos_pcie_assert_core_reset(struct pcie_port *pp)
> {
> u32 val;
> - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> + struct exynos_pcie *exynos = to_exynos_pcie(pp);
>
> - val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET);
> + val = exynos_elb_readl(exynos, PCIE_CORE_RESET);
> val &= ~PCIE_CORE_RESET_ENABLE;
> - exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET);
> - exynos_elb_writel(exynos_pcie, 0, PCIE_PWR_RESET);
> - exynos_elb_writel(exynos_pcie, 0, PCIE_STICKY_RESET);
> - exynos_elb_writel(exynos_pcie, 0, PCIE_NONSTICKY_RESET);
> + exynos_elb_writel(exynos, val, PCIE_CORE_RESET);
> + exynos_elb_writel(exynos, 0, PCIE_PWR_RESET);
> + exynos_elb_writel(exynos, 0, PCIE_STICKY_RESET);
> + exynos_elb_writel(exynos, 0, PCIE_NONSTICKY_RESET);
> }
>
> static void exynos_pcie_deassert_core_reset(struct pcie_port *pp)
> {
> u32 val;
> - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> + struct exynos_pcie *exynos = to_exynos_pcie(pp);
>
> - val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET);
> + val = exynos_elb_readl(exynos, PCIE_CORE_RESET);
> val |= PCIE_CORE_RESET_ENABLE;
>
> - exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET);
> - exynos_elb_writel(exynos_pcie, 1, PCIE_STICKY_RESET);
> - exynos_elb_writel(exynos_pcie, 1, PCIE_NONSTICKY_RESET);
> - exynos_elb_writel(exynos_pcie, 1, PCIE_APP_INIT_RESET);
> - exynos_elb_writel(exynos_pcie, 0, PCIE_APP_INIT_RESET);
> - exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_MAC_RESET);
> + exynos_elb_writel(exynos, val, PCIE_CORE_RESET);
> + exynos_elb_writel(exynos, 1, PCIE_STICKY_RESET);
> + exynos_elb_writel(exynos, 1, PCIE_NONSTICKY_RESET);
> + exynos_elb_writel(exynos, 1, PCIE_APP_INIT_RESET);
> + exynos_elb_writel(exynos, 0, PCIE_APP_INIT_RESET);
> + exynos_blk_writel(exynos, 1, PCIE_PHY_MAC_RESET);
> }
>
> static void exynos_pcie_assert_phy_reset(struct pcie_port *pp)
> {
> - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> + struct exynos_pcie *exynos = to_exynos_pcie(pp);
>
> - exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_MAC_RESET);
> - exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_GLOBAL_RESET);
> + exynos_blk_writel(exynos, 0, PCIE_PHY_MAC_RESET);
> + exynos_blk_writel(exynos, 1, PCIE_PHY_GLOBAL_RESET);
> }
>
> static void exynos_pcie_deassert_phy_reset(struct pcie_port *pp)
> {
> - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> + struct exynos_pcie *exynos = to_exynos_pcie(pp);
>
> - exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_GLOBAL_RESET);
> - exynos_elb_writel(exynos_pcie, 1, PCIE_PWR_RESET);
> - exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET);
> - exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_CMN_REG);
> - exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSVREG_RESET);
> - exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSV_RESET);
> + exynos_blk_writel(exynos, 0, PCIE_PHY_GLOBAL_RESET);
> + exynos_elb_writel(exynos, 1, PCIE_PWR_RESET);
> + exynos_blk_writel(exynos, 0, PCIE_PHY_COMMON_RESET);
> + exynos_blk_writel(exynos, 0, PCIE_PHY_CMN_REG);
> + exynos_blk_writel(exynos, 0, PCIE_PHY_TRSVREG_RESET);
> + exynos_blk_writel(exynos, 0, PCIE_PHY_TRSV_RESET);
> }
>
> static void exynos_pcie_power_on_phy(struct pcie_port *pp)
> {
> u32 val;
> - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> + struct exynos_pcie *exynos = to_exynos_pcie(pp);
>
> - val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER);
> + val = exynos_phy_readl(exynos, PCIE_PHY_COMMON_POWER);
> val &= ~PCIE_PHY_COMMON_PD_CMN;
> - exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER);
> + exynos_phy_writel(exynos, val, PCIE_PHY_COMMON_POWER);
>
> - val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER);
> + val = exynos_phy_readl(exynos, PCIE_PHY_TRSV0_POWER);
> val &= ~PCIE_PHY_TRSV0_PD_TSV;
> - exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER);
> + exynos_phy_writel(exynos, val, PCIE_PHY_TRSV0_POWER);
>
> - val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER);
> + val = exynos_phy_readl(exynos, PCIE_PHY_TRSV1_POWER);
> val &= ~PCIE_PHY_TRSV1_PD_TSV;
> - exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER);
> + exynos_phy_writel(exynos, val, PCIE_PHY_TRSV1_POWER);
>
> - val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER);
> + val = exynos_phy_readl(exynos, PCIE_PHY_TRSV2_POWER);
> val &= ~PCIE_PHY_TRSV2_PD_TSV;
> - exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER);
> + exynos_phy_writel(exynos, val, PCIE_PHY_TRSV2_POWER);
>
> - val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER);
> + val = exynos_phy_readl(exynos, PCIE_PHY_TRSV3_POWER);
> val &= ~PCIE_PHY_TRSV3_PD_TSV;
> - exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER);
> + exynos_phy_writel(exynos, val, PCIE_PHY_TRSV3_POWER);
> }
>
> static void exynos_pcie_power_off_phy(struct pcie_port *pp)
> {
> u32 val;
> - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> + struct exynos_pcie *exynos = to_exynos_pcie(pp);
>
> - val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER);
> + val = exynos_phy_readl(exynos, PCIE_PHY_COMMON_POWER);
> val |= PCIE_PHY_COMMON_PD_CMN;
> - exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER);
> + exynos_phy_writel(exynos, val, PCIE_PHY_COMMON_POWER);
>
> - val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER);
> + val = exynos_phy_readl(exynos, PCIE_PHY_TRSV0_POWER);
> val |= PCIE_PHY_TRSV0_PD_TSV;
> - exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER);
> + exynos_phy_writel(exynos, val, PCIE_PHY_TRSV0_POWER);
>
> - val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER);
> + val = exynos_phy_readl(exynos, PCIE_PHY_TRSV1_POWER);
> val |= PCIE_PHY_TRSV1_PD_TSV;
> - exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER);
> + exynos_phy_writel(exynos, val, PCIE_PHY_TRSV1_POWER);
>
> - val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER);
> + val = exynos_phy_readl(exynos, PCIE_PHY_TRSV2_POWER);
> val |= PCIE_PHY_TRSV2_PD_TSV;
> - exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER);
> + exynos_phy_writel(exynos, val, PCIE_PHY_TRSV2_POWER);
>
> - val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER);
> + val = exynos_phy_readl(exynos, PCIE_PHY_TRSV3_POWER);
> val |= PCIE_PHY_TRSV3_PD_TSV;
> - exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER);
> + exynos_phy_writel(exynos, val, PCIE_PHY_TRSV3_POWER);
> }
>
> static void exynos_pcie_init_phy(struct pcie_port *pp)
> {
> - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> + struct exynos_pcie *exynos = to_exynos_pcie(pp);
>
> /* DCC feedback control off */
> - exynos_phy_writel(exynos_pcie, 0x29, PCIE_PHY_DCC_FEEDBACK);
> + exynos_phy_writel(exynos, 0x29, PCIE_PHY_DCC_FEEDBACK);
>
> /* set TX/RX impedance */
> - exynos_phy_writel(exynos_pcie, 0xd5, PCIE_PHY_IMPEDANCE);
> + exynos_phy_writel(exynos, 0xd5, PCIE_PHY_IMPEDANCE);
>
> /* set 50Mhz PHY clock */
> - exynos_phy_writel(exynos_pcie, 0x14, PCIE_PHY_PLL_DIV_0);
> - exynos_phy_writel(exynos_pcie, 0x12, PCIE_PHY_PLL_DIV_1);
> + exynos_phy_writel(exynos, 0x14, PCIE_PHY_PLL_DIV_0);
> + exynos_phy_writel(exynos, 0x12, PCIE_PHY_PLL_DIV_1);
>
> /* set TX Differential output for lane 0 */
> - exynos_phy_writel(exynos_pcie, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
> + exynos_phy_writel(exynos, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
>
> /* set TX Pre-emphasis Level Control for lane 0 to minimum */
> - exynos_phy_writel(exynos_pcie, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
> + exynos_phy_writel(exynos, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
>
> /* set RX clock and data recovery bandwidth */
> - exynos_phy_writel(exynos_pcie, 0xe7, PCIE_PHY_PLL_BIAS);
> - exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV0_RXCDR);
> - exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV1_RXCDR);
> - exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV2_RXCDR);
> - exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV3_RXCDR);
> + exynos_phy_writel(exynos, 0xe7, PCIE_PHY_PLL_BIAS);
> + exynos_phy_writel(exynos, 0x82, PCIE_PHY_TRSV0_RXCDR);
> + exynos_phy_writel(exynos, 0x82, PCIE_PHY_TRSV1_RXCDR);
> + exynos_phy_writel(exynos, 0x82, PCIE_PHY_TRSV2_RXCDR);
> + exynos_phy_writel(exynos, 0x82, PCIE_PHY_TRSV3_RXCDR);
>
> /* change TX Pre-emphasis Level Control for lanes */
> - exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
> - exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
> - exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
> - exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
> + exynos_phy_writel(exynos, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
> + exynos_phy_writel(exynos, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
> + exynos_phy_writel(exynos, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
> + exynos_phy_writel(exynos, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
>
> /* set LVCC */
> - exynos_phy_writel(exynos_pcie, 0x20, PCIE_PHY_TRSV0_LVCC);
> - exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV1_LVCC);
> - exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV2_LVCC);
> - exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV3_LVCC);
> + exynos_phy_writel(exynos, 0x20, PCIE_PHY_TRSV0_LVCC);
> + exynos_phy_writel(exynos, 0xa0, PCIE_PHY_TRSV1_LVCC);
> + exynos_phy_writel(exynos, 0xa0, PCIE_PHY_TRSV2_LVCC);
> + exynos_phy_writel(exynos, 0xa0, PCIE_PHY_TRSV3_LVCC);
> }
>
> static void exynos_pcie_assert_reset(struct pcie_port *pp)
> {
> - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> + struct exynos_pcie *exynos = to_exynos_pcie(pp);
>
> - if (exynos_pcie->reset_gpio >= 0)
> - devm_gpio_request_one(pp->dev, exynos_pcie->reset_gpio,
> + if (exynos->reset_gpio >= 0)
> + devm_gpio_request_one(pp->dev, exynos->reset_gpio,
> GPIOF_OUT_INIT_HIGH, "RESET");
> }
>
> static int exynos_pcie_establish_link(struct pcie_port *pp)
> {
> - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> + struct exynos_pcie *exynos = to_exynos_pcie(pp);
> u32 val;
>
> if (dw_pcie_link_up(pp)) {
> @@ -338,9 +338,9 @@ static int exynos_pcie_establish_link(struct pcie_port *pp)
> exynos_pcie_init_phy(pp);
>
> /* pulse for common reset */
> - exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_COMMON_RESET);
> + exynos_blk_writel(exynos, 1, PCIE_PHY_COMMON_RESET);
> udelay(500);
> - exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET);
> + exynos_blk_writel(exynos, 0, PCIE_PHY_COMMON_RESET);
>
> /* de-assert core reset */
> exynos_pcie_deassert_core_reset(pp);
> @@ -352,15 +352,15 @@ static int exynos_pcie_establish_link(struct pcie_port *pp)
> exynos_pcie_assert_reset(pp);
>
> /* assert LTSSM enable */
> - exynos_elb_writel(exynos_pcie, PCIE_ELBI_LTSSM_ENABLE,
> + exynos_elb_writel(exynos, PCIE_ELBI_LTSSM_ENABLE,
> PCIE_APP_LTSSM_ENABLE);
>
> /* check if the link is up or not */
> if (!dw_pcie_wait_for_link(pp))
> return 0;
>
> - while (exynos_phy_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED) == 0) {
> - val = exynos_blk_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED);
> + while (exynos_phy_readl(exynos, PCIE_PHY_PLL_LOCKED) == 0) {
> + val = exynos_blk_readl(exynos, PCIE_PHY_PLL_LOCKED);
> dev_info(pp->dev, "PLL Locked: 0x%x\n", val);
> }
> /* power off phy */
> @@ -372,21 +372,21 @@ static int exynos_pcie_establish_link(struct pcie_port *pp)
> static void exynos_pcie_clear_irq_pulse(struct pcie_port *pp)
> {
> u32 val;
> - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> + struct exynos_pcie *exynos = to_exynos_pcie(pp);
>
> - val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_PULSE);
> - exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_PULSE);
> + val = exynos_elb_readl(exynos, PCIE_IRQ_PULSE);
> + exynos_elb_writel(exynos, val, PCIE_IRQ_PULSE);
> }
>
> static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp)
> {
> u32 val;
> - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> + struct exynos_pcie *exynos = to_exynos_pcie(pp);
>
> /* enable INTX interrupt */
> val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
> IRQ_INTC_ASSERT | IRQ_INTD_ASSERT;
> - exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_PULSE);
> + exynos_elb_writel(exynos, val, PCIE_IRQ_EN_PULSE);
> }
>
> static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
> @@ -407,14 +407,14 @@ static irqreturn_t exynos_pcie_msi_irq_handler(int irq, void *arg)
> static void exynos_pcie_msi_init(struct pcie_port *pp)
> {
> u32 val;
> - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> + struct exynos_pcie *exynos = to_exynos_pcie(pp);
>
> dw_pcie_msi_init(pp);
>
> /* enable MSI interrupt */
> - val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_EN_LEVEL);
> + val = exynos_elb_readl(exynos, PCIE_IRQ_EN_LEVEL);
> val |= IRQ_MSI_ENABLE;
> - exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_LEVEL);
> + exynos_elb_writel(exynos, val, PCIE_IRQ_EN_LEVEL);
> }
>
> static void exynos_pcie_enable_interrupts(struct pcie_port *pp)
> @@ -466,8 +466,8 @@ static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
>
> static int exynos_pcie_link_up(struct pcie_port *pp)
> {
> - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> - u32 val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_RDLH_LINKUP);
> + struct exynos_pcie *exynos = to_exynos_pcie(pp);
> + u32 val = exynos_elb_readl(exynos, PCIE_ELBI_RDLH_LINKUP);
>
> if (val == PCIE_ELBI_LTSSM_ENABLE)
> return 1;
> @@ -538,7 +538,7 @@ static int __init exynos_add_pcie_port(struct pcie_port *pp,
>
> static int __init exynos_pcie_probe(struct platform_device *pdev)
> {
> - struct exynos_pcie *exynos_pcie;
> + struct exynos_pcie *exynos;
> struct pcie_port *pp;
> struct device_node *np = pdev->dev.of_node;
> struct resource *elbi_base;
> @@ -546,54 +546,52 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
> struct resource *block_base;
> int ret;
>
> - exynos_pcie = devm_kzalloc(&pdev->dev, sizeof(*exynos_pcie),
> - GFP_KERNEL);
> - if (!exynos_pcie)
> + exynos = devm_kzalloc(&pdev->dev, sizeof(*exynos), GFP_KERNEL);
> + if (!exynos)
> return -ENOMEM;
>
> - pp = &exynos_pcie->pp;
> -
> + pp = &exynos->pp;
> pp->dev = &pdev->dev;
>
> - exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
> + exynos->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
>
> - exynos_pcie->clk = devm_clk_get(&pdev->dev, "pcie");
> - if (IS_ERR(exynos_pcie->clk)) {
> + exynos->clk = devm_clk_get(&pdev->dev, "pcie");
> + if (IS_ERR(exynos->clk)) {
> dev_err(&pdev->dev, "Failed to get pcie rc clock\n");
> - return PTR_ERR(exynos_pcie->clk);
> + return PTR_ERR(exynos->clk);
> }
> - ret = clk_prepare_enable(exynos_pcie->clk);
> + ret = clk_prepare_enable(exynos->clk);
> if (ret)
> return ret;
>
> - exynos_pcie->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
> - if (IS_ERR(exynos_pcie->bus_clk)) {
> + exynos->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
> + if (IS_ERR(exynos->bus_clk)) {
> dev_err(&pdev->dev, "Failed to get pcie bus clock\n");
> - ret = PTR_ERR(exynos_pcie->bus_clk);
> + ret = PTR_ERR(exynos->bus_clk);
> goto fail_clk;
> }
> - ret = clk_prepare_enable(exynos_pcie->bus_clk);
> + ret = clk_prepare_enable(exynos->bus_clk);
> if (ret)
> goto fail_clk;
>
> elbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> - exynos_pcie->elbi_base = devm_ioremap_resource(&pdev->dev, elbi_base);
> - if (IS_ERR(exynos_pcie->elbi_base)) {
> - ret = PTR_ERR(exynos_pcie->elbi_base);
> + exynos->elbi_base = devm_ioremap_resource(&pdev->dev, elbi_base);
> + if (IS_ERR(exynos->elbi_base)) {
> + ret = PTR_ERR(exynos->elbi_base);
> goto fail_bus_clk;
> }
>
> phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> - exynos_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy_base);
> - if (IS_ERR(exynos_pcie->phy_base)) {
> - ret = PTR_ERR(exynos_pcie->phy_base);
> + exynos->phy_base = devm_ioremap_resource(&pdev->dev, phy_base);
> + if (IS_ERR(exynos->phy_base)) {
> + ret = PTR_ERR(exynos->phy_base);
> goto fail_bus_clk;
> }
>
> block_base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
> - exynos_pcie->block_base = devm_ioremap_resource(&pdev->dev, block_base);
> - if (IS_ERR(exynos_pcie->block_base)) {
> - ret = PTR_ERR(exynos_pcie->block_base);
> + exynos->block_base = devm_ioremap_resource(&pdev->dev, block_base);
> + if (IS_ERR(exynos->block_base)) {
> + ret = PTR_ERR(exynos->block_base);
> goto fail_bus_clk;
> }
>
> @@ -601,22 +599,22 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
> if (ret < 0)
> goto fail_bus_clk;
>
> - platform_set_drvdata(pdev, exynos_pcie);
> + platform_set_drvdata(pdev, exynos);
> return 0;
>
> fail_bus_clk:
> - clk_disable_unprepare(exynos_pcie->bus_clk);
> + clk_disable_unprepare(exynos->bus_clk);
> fail_clk:
> - clk_disable_unprepare(exynos_pcie->clk);
> + clk_disable_unprepare(exynos->clk);
> return ret;
> }
>
> static int __exit exynos_pcie_remove(struct platform_device *pdev)
> {
> - struct exynos_pcie *exynos_pcie = platform_get_drvdata(pdev);
> + struct exynos_pcie *exynos = platform_get_drvdata(pdev);
>
> - clk_disable_unprepare(exynos_pcie->bus_clk);
> - clk_disable_unprepare(exynos_pcie->clk);
> + clk_disable_unprepare(exynos->bus_clk);
> + clk_disable_unprepare(exynos->clk);
>
> return 0;
> }
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/8] PCI: exynos: Name private struct pointer "exynos" consistently
2016-10-08 19:41 ` [PATCH 1/8] PCI: exynos: Name private struct pointer "exynos" consistently Krzysztof Kozlowski
@ 2016-10-10 13:36 ` Bjorn Helgaas
2016-10-10 16:49 ` Krzysztof Kozlowski
0 siblings, 1 reply; 11+ messages in thread
From: Bjorn Helgaas @ 2016-10-10 13:36 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Helgaas, Jingoo Han, Krzysztof Kozlowski, Kukjin Kim,
linux-pci, linux-samsung-soc
Hi Krzysztof,
Thanks a lot for taking the time to look these over.
On Sat, Oct 08, 2016 at 10:41:44PM +0300, Krzysztof Kozlowski wrote:
> On Fri, Oct 07, 2016 at 11:35:26AM -0500, Bjorn Helgaas wrote:
> > Use a device-specific name, "exynos", for struct exynos_pcie pointers
> > to hint that this is device-specific information.
>
> I don't get it. "exynos_pcie" is already a exynos-device-specific name.
> There are a lot of changes but I don't see the real reason/benefit. What
> was your intention?
I'm looking across all the drivers in drivers/pci/host/, not just
exynos. Many of them used "pcie" as name for pointers to the
device-specific struct, leading to things like "pcie->lut" or
"pcie->breg_base". These *look* like they should be sort of generic,
but in fact they are device-specific.
My idea was to replace that "pcie" name with something
device-specific, and I started with the simplest possible name, e.g.,
"exynos". Others pointed out that that for SoCs, that is often not
enough specific enough, and something like "exynos_pcie" is more
appropriate.
In the specific case of exynos, it already uses "exynos_pcie" in most
cases, so I tweaked this patch to use it in the few remaining places
where it didn't (the register accessor functions).
> > No functional change
> > intended.
>
> Oh, but there is. Inline disappeared in first functions. Although I
> don't mind but this should be seprate from trivial rename.
I didn't think of "inline" as a functional change, but I split it out
into its own patch. I'm embarrassed at how much churn this turned out
to be, so I didn't want to add more patches than I had to, but I did
split it out for you.
I repushed the branch.
> > Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> > ---
> > drivers/pci/host/pci-exynos.c | 272 ++++++++++++++++++++---------------------
> > 1 file changed, 135 insertions(+), 137 deletions(-)
> >
> > diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
> > index f559b49..05eb246 100644
> > --- a/drivers/pci/host/pci-exynos.c
> > +++ b/drivers/pci/host/pci-exynos.c
> > @@ -102,221 +102,221 @@ struct exynos_pcie {
> > #define PCIE_PHY_TRSV3_PD_TSV (0x1 << 7)
> > #define PCIE_PHY_TRSV3_LVCC 0x31c
> >
> > -static inline void exynos_elb_writel(struct exynos_pcie *pcie, u32 val, u32 reg)
> > +static void exynos_elb_writel(struct exynos_pcie *exynos, u32 val, u32 reg)
> > {
> > - writel(val, pcie->elbi_base + reg);
> > + writel(val, exynos->elbi_base + reg);
> > }
> >
> > -static inline u32 exynos_elb_readl(struct exynos_pcie *pcie, u32 reg)
> > +static u32 exynos_elb_readl(struct exynos_pcie *exynos, u32 reg)
> > {
> > - return readl(pcie->elbi_base + reg);
> > + return readl(exynos->elbi_base + reg);
> > }
> >
> > -static inline void exynos_phy_writel(struct exynos_pcie *pcie, u32 val, u32 reg)
> > +static void exynos_phy_writel(struct exynos_pcie *exynos, u32 val, u32 reg)
> > {
> > - writel(val, pcie->phy_base + reg);
> > + writel(val, exynos->phy_base + reg);
> > }
> >
> > -static inline u32 exynos_phy_readl(struct exynos_pcie *pcie, u32 reg)
> > +static u32 exynos_phy_readl(struct exynos_pcie *exynos, u32 reg)
> > {
> > - return readl(pcie->phy_base + reg);
> > + return readl(exynos->phy_base + reg);
> > }
> >
> > -static inline void exynos_blk_writel(struct exynos_pcie *pcie, u32 val, u32 reg)
> > +static void exynos_blk_writel(struct exynos_pcie *exynos, u32 val, u32 reg)
> > {
> > - writel(val, pcie->block_base + reg);
> > + writel(val, exynos->block_base + reg);
> > }
> >
> > -static inline u32 exynos_blk_readl(struct exynos_pcie *pcie, u32 reg)
> > +static u32 exynos_blk_readl(struct exynos_pcie *exynos, u32 reg)
> > {
> > - return readl(pcie->block_base + reg);
> > + return readl(exynos->block_base + reg);
> > }
> >
> > static void exynos_pcie_sideband_dbi_w_mode(struct pcie_port *pp, bool on)
> > {
> > u32 val;
> > - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> > + struct exynos_pcie *exynos = to_exynos_pcie(pp);
> >
> > if (on) {
> > - val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC);
> > + val = exynos_elb_readl(exynos, PCIE_ELBI_SLV_AWMISC);
> > val |= PCIE_ELBI_SLV_DBI_ENABLE;
> > - exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC);
> > + exynos_elb_writel(exynos, val, PCIE_ELBI_SLV_AWMISC);
> > } else {
> > - val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC);
> > + val = exynos_elb_readl(exynos, PCIE_ELBI_SLV_AWMISC);
> > val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
> > - exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC);
> > + exynos_elb_writel(exynos, val, PCIE_ELBI_SLV_AWMISC);
> > }
> > }
> >
> > static void exynos_pcie_sideband_dbi_r_mode(struct pcie_port *pp, bool on)
> > {
> > u32 val;
> > - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> > + struct exynos_pcie *exynos = to_exynos_pcie(pp);
> >
> > if (on) {
> > - val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC);
> > + val = exynos_elb_readl(exynos, PCIE_ELBI_SLV_ARMISC);
> > val |= PCIE_ELBI_SLV_DBI_ENABLE;
> > - exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC);
> > + exynos_elb_writel(exynos, val, PCIE_ELBI_SLV_ARMISC);
> > } else {
> > - val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC);
> > + val = exynos_elb_readl(exynos, PCIE_ELBI_SLV_ARMISC);
> > val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
> > - exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC);
> > + exynos_elb_writel(exynos, val, PCIE_ELBI_SLV_ARMISC);
> > }
> > }
> >
> > static void exynos_pcie_assert_core_reset(struct pcie_port *pp)
> > {
> > u32 val;
> > - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> > + struct exynos_pcie *exynos = to_exynos_pcie(pp);
> >
> > - val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET);
> > + val = exynos_elb_readl(exynos, PCIE_CORE_RESET);
> > val &= ~PCIE_CORE_RESET_ENABLE;
> > - exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET);
> > - exynos_elb_writel(exynos_pcie, 0, PCIE_PWR_RESET);
> > - exynos_elb_writel(exynos_pcie, 0, PCIE_STICKY_RESET);
> > - exynos_elb_writel(exynos_pcie, 0, PCIE_NONSTICKY_RESET);
> > + exynos_elb_writel(exynos, val, PCIE_CORE_RESET);
> > + exynos_elb_writel(exynos, 0, PCIE_PWR_RESET);
> > + exynos_elb_writel(exynos, 0, PCIE_STICKY_RESET);
> > + exynos_elb_writel(exynos, 0, PCIE_NONSTICKY_RESET);
> > }
> >
> > static void exynos_pcie_deassert_core_reset(struct pcie_port *pp)
> > {
> > u32 val;
> > - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> > + struct exynos_pcie *exynos = to_exynos_pcie(pp);
> >
> > - val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET);
> > + val = exynos_elb_readl(exynos, PCIE_CORE_RESET);
> > val |= PCIE_CORE_RESET_ENABLE;
> >
> > - exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET);
> > - exynos_elb_writel(exynos_pcie, 1, PCIE_STICKY_RESET);
> > - exynos_elb_writel(exynos_pcie, 1, PCIE_NONSTICKY_RESET);
> > - exynos_elb_writel(exynos_pcie, 1, PCIE_APP_INIT_RESET);
> > - exynos_elb_writel(exynos_pcie, 0, PCIE_APP_INIT_RESET);
> > - exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_MAC_RESET);
> > + exynos_elb_writel(exynos, val, PCIE_CORE_RESET);
> > + exynos_elb_writel(exynos, 1, PCIE_STICKY_RESET);
> > + exynos_elb_writel(exynos, 1, PCIE_NONSTICKY_RESET);
> > + exynos_elb_writel(exynos, 1, PCIE_APP_INIT_RESET);
> > + exynos_elb_writel(exynos, 0, PCIE_APP_INIT_RESET);
> > + exynos_blk_writel(exynos, 1, PCIE_PHY_MAC_RESET);
> > }
> >
> > static void exynos_pcie_assert_phy_reset(struct pcie_port *pp)
> > {
> > - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> > + struct exynos_pcie *exynos = to_exynos_pcie(pp);
> >
> > - exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_MAC_RESET);
> > - exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_GLOBAL_RESET);
> > + exynos_blk_writel(exynos, 0, PCIE_PHY_MAC_RESET);
> > + exynos_blk_writel(exynos, 1, PCIE_PHY_GLOBAL_RESET);
> > }
> >
> > static void exynos_pcie_deassert_phy_reset(struct pcie_port *pp)
> > {
> > - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> > + struct exynos_pcie *exynos = to_exynos_pcie(pp);
> >
> > - exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_GLOBAL_RESET);
> > - exynos_elb_writel(exynos_pcie, 1, PCIE_PWR_RESET);
> > - exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET);
> > - exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_CMN_REG);
> > - exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSVREG_RESET);
> > - exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSV_RESET);
> > + exynos_blk_writel(exynos, 0, PCIE_PHY_GLOBAL_RESET);
> > + exynos_elb_writel(exynos, 1, PCIE_PWR_RESET);
> > + exynos_blk_writel(exynos, 0, PCIE_PHY_COMMON_RESET);
> > + exynos_blk_writel(exynos, 0, PCIE_PHY_CMN_REG);
> > + exynos_blk_writel(exynos, 0, PCIE_PHY_TRSVREG_RESET);
> > + exynos_blk_writel(exynos, 0, PCIE_PHY_TRSV_RESET);
> > }
> >
> > static void exynos_pcie_power_on_phy(struct pcie_port *pp)
> > {
> > u32 val;
> > - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> > + struct exynos_pcie *exynos = to_exynos_pcie(pp);
> >
> > - val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER);
> > + val = exynos_phy_readl(exynos, PCIE_PHY_COMMON_POWER);
> > val &= ~PCIE_PHY_COMMON_PD_CMN;
> > - exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER);
> > + exynos_phy_writel(exynos, val, PCIE_PHY_COMMON_POWER);
> >
> > - val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER);
> > + val = exynos_phy_readl(exynos, PCIE_PHY_TRSV0_POWER);
> > val &= ~PCIE_PHY_TRSV0_PD_TSV;
> > - exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER);
> > + exynos_phy_writel(exynos, val, PCIE_PHY_TRSV0_POWER);
> >
> > - val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER);
> > + val = exynos_phy_readl(exynos, PCIE_PHY_TRSV1_POWER);
> > val &= ~PCIE_PHY_TRSV1_PD_TSV;
> > - exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER);
> > + exynos_phy_writel(exynos, val, PCIE_PHY_TRSV1_POWER);
> >
> > - val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER);
> > + val = exynos_phy_readl(exynos, PCIE_PHY_TRSV2_POWER);
> > val &= ~PCIE_PHY_TRSV2_PD_TSV;
> > - exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER);
> > + exynos_phy_writel(exynos, val, PCIE_PHY_TRSV2_POWER);
> >
> > - val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER);
> > + val = exynos_phy_readl(exynos, PCIE_PHY_TRSV3_POWER);
> > val &= ~PCIE_PHY_TRSV3_PD_TSV;
> > - exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER);
> > + exynos_phy_writel(exynos, val, PCIE_PHY_TRSV3_POWER);
> > }
> >
> > static void exynos_pcie_power_off_phy(struct pcie_port *pp)
> > {
> > u32 val;
> > - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> > + struct exynos_pcie *exynos = to_exynos_pcie(pp);
> >
> > - val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER);
> > + val = exynos_phy_readl(exynos, PCIE_PHY_COMMON_POWER);
> > val |= PCIE_PHY_COMMON_PD_CMN;
> > - exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER);
> > + exynos_phy_writel(exynos, val, PCIE_PHY_COMMON_POWER);
> >
> > - val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER);
> > + val = exynos_phy_readl(exynos, PCIE_PHY_TRSV0_POWER);
> > val |= PCIE_PHY_TRSV0_PD_TSV;
> > - exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER);
> > + exynos_phy_writel(exynos, val, PCIE_PHY_TRSV0_POWER);
> >
> > - val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER);
> > + val = exynos_phy_readl(exynos, PCIE_PHY_TRSV1_POWER);
> > val |= PCIE_PHY_TRSV1_PD_TSV;
> > - exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER);
> > + exynos_phy_writel(exynos, val, PCIE_PHY_TRSV1_POWER);
> >
> > - val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER);
> > + val = exynos_phy_readl(exynos, PCIE_PHY_TRSV2_POWER);
> > val |= PCIE_PHY_TRSV2_PD_TSV;
> > - exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER);
> > + exynos_phy_writel(exynos, val, PCIE_PHY_TRSV2_POWER);
> >
> > - val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER);
> > + val = exynos_phy_readl(exynos, PCIE_PHY_TRSV3_POWER);
> > val |= PCIE_PHY_TRSV3_PD_TSV;
> > - exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER);
> > + exynos_phy_writel(exynos, val, PCIE_PHY_TRSV3_POWER);
> > }
> >
> > static void exynos_pcie_init_phy(struct pcie_port *pp)
> > {
> > - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> > + struct exynos_pcie *exynos = to_exynos_pcie(pp);
> >
> > /* DCC feedback control off */
> > - exynos_phy_writel(exynos_pcie, 0x29, PCIE_PHY_DCC_FEEDBACK);
> > + exynos_phy_writel(exynos, 0x29, PCIE_PHY_DCC_FEEDBACK);
> >
> > /* set TX/RX impedance */
> > - exynos_phy_writel(exynos_pcie, 0xd5, PCIE_PHY_IMPEDANCE);
> > + exynos_phy_writel(exynos, 0xd5, PCIE_PHY_IMPEDANCE);
> >
> > /* set 50Mhz PHY clock */
> > - exynos_phy_writel(exynos_pcie, 0x14, PCIE_PHY_PLL_DIV_0);
> > - exynos_phy_writel(exynos_pcie, 0x12, PCIE_PHY_PLL_DIV_1);
> > + exynos_phy_writel(exynos, 0x14, PCIE_PHY_PLL_DIV_0);
> > + exynos_phy_writel(exynos, 0x12, PCIE_PHY_PLL_DIV_1);
> >
> > /* set TX Differential output for lane 0 */
> > - exynos_phy_writel(exynos_pcie, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
> > + exynos_phy_writel(exynos, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
> >
> > /* set TX Pre-emphasis Level Control for lane 0 to minimum */
> > - exynos_phy_writel(exynos_pcie, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
> > + exynos_phy_writel(exynos, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
> >
> > /* set RX clock and data recovery bandwidth */
> > - exynos_phy_writel(exynos_pcie, 0xe7, PCIE_PHY_PLL_BIAS);
> > - exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV0_RXCDR);
> > - exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV1_RXCDR);
> > - exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV2_RXCDR);
> > - exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV3_RXCDR);
> > + exynos_phy_writel(exynos, 0xe7, PCIE_PHY_PLL_BIAS);
> > + exynos_phy_writel(exynos, 0x82, PCIE_PHY_TRSV0_RXCDR);
> > + exynos_phy_writel(exynos, 0x82, PCIE_PHY_TRSV1_RXCDR);
> > + exynos_phy_writel(exynos, 0x82, PCIE_PHY_TRSV2_RXCDR);
> > + exynos_phy_writel(exynos, 0x82, PCIE_PHY_TRSV3_RXCDR);
> >
> > /* change TX Pre-emphasis Level Control for lanes */
> > - exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
> > - exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
> > - exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
> > - exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
> > + exynos_phy_writel(exynos, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
> > + exynos_phy_writel(exynos, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
> > + exynos_phy_writel(exynos, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
> > + exynos_phy_writel(exynos, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
> >
> > /* set LVCC */
> > - exynos_phy_writel(exynos_pcie, 0x20, PCIE_PHY_TRSV0_LVCC);
> > - exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV1_LVCC);
> > - exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV2_LVCC);
> > - exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV3_LVCC);
> > + exynos_phy_writel(exynos, 0x20, PCIE_PHY_TRSV0_LVCC);
> > + exynos_phy_writel(exynos, 0xa0, PCIE_PHY_TRSV1_LVCC);
> > + exynos_phy_writel(exynos, 0xa0, PCIE_PHY_TRSV2_LVCC);
> > + exynos_phy_writel(exynos, 0xa0, PCIE_PHY_TRSV3_LVCC);
> > }
> >
> > static void exynos_pcie_assert_reset(struct pcie_port *pp)
> > {
> > - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> > + struct exynos_pcie *exynos = to_exynos_pcie(pp);
> >
> > - if (exynos_pcie->reset_gpio >= 0)
> > - devm_gpio_request_one(pp->dev, exynos_pcie->reset_gpio,
> > + if (exynos->reset_gpio >= 0)
> > + devm_gpio_request_one(pp->dev, exynos->reset_gpio,
> > GPIOF_OUT_INIT_HIGH, "RESET");
> > }
> >
> > static int exynos_pcie_establish_link(struct pcie_port *pp)
> > {
> > - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> > + struct exynos_pcie *exynos = to_exynos_pcie(pp);
> > u32 val;
> >
> > if (dw_pcie_link_up(pp)) {
> > @@ -338,9 +338,9 @@ static int exynos_pcie_establish_link(struct pcie_port *pp)
> > exynos_pcie_init_phy(pp);
> >
> > /* pulse for common reset */
> > - exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_COMMON_RESET);
> > + exynos_blk_writel(exynos, 1, PCIE_PHY_COMMON_RESET);
> > udelay(500);
> > - exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET);
> > + exynos_blk_writel(exynos, 0, PCIE_PHY_COMMON_RESET);
> >
> > /* de-assert core reset */
> > exynos_pcie_deassert_core_reset(pp);
> > @@ -352,15 +352,15 @@ static int exynos_pcie_establish_link(struct pcie_port *pp)
> > exynos_pcie_assert_reset(pp);
> >
> > /* assert LTSSM enable */
> > - exynos_elb_writel(exynos_pcie, PCIE_ELBI_LTSSM_ENABLE,
> > + exynos_elb_writel(exynos, PCIE_ELBI_LTSSM_ENABLE,
> > PCIE_APP_LTSSM_ENABLE);
> >
> > /* check if the link is up or not */
> > if (!dw_pcie_wait_for_link(pp))
> > return 0;
> >
> > - while (exynos_phy_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED) == 0) {
> > - val = exynos_blk_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED);
> > + while (exynos_phy_readl(exynos, PCIE_PHY_PLL_LOCKED) == 0) {
> > + val = exynos_blk_readl(exynos, PCIE_PHY_PLL_LOCKED);
> > dev_info(pp->dev, "PLL Locked: 0x%x\n", val);
> > }
> > /* power off phy */
> > @@ -372,21 +372,21 @@ static int exynos_pcie_establish_link(struct pcie_port *pp)
> > static void exynos_pcie_clear_irq_pulse(struct pcie_port *pp)
> > {
> > u32 val;
> > - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> > + struct exynos_pcie *exynos = to_exynos_pcie(pp);
> >
> > - val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_PULSE);
> > - exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_PULSE);
> > + val = exynos_elb_readl(exynos, PCIE_IRQ_PULSE);
> > + exynos_elb_writel(exynos, val, PCIE_IRQ_PULSE);
> > }
> >
> > static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp)
> > {
> > u32 val;
> > - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> > + struct exynos_pcie *exynos = to_exynos_pcie(pp);
> >
> > /* enable INTX interrupt */
> > val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
> > IRQ_INTC_ASSERT | IRQ_INTD_ASSERT;
> > - exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_PULSE);
> > + exynos_elb_writel(exynos, val, PCIE_IRQ_EN_PULSE);
> > }
> >
> > static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
> > @@ -407,14 +407,14 @@ static irqreturn_t exynos_pcie_msi_irq_handler(int irq, void *arg)
> > static void exynos_pcie_msi_init(struct pcie_port *pp)
> > {
> > u32 val;
> > - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> > + struct exynos_pcie *exynos = to_exynos_pcie(pp);
> >
> > dw_pcie_msi_init(pp);
> >
> > /* enable MSI interrupt */
> > - val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_EN_LEVEL);
> > + val = exynos_elb_readl(exynos, PCIE_IRQ_EN_LEVEL);
> > val |= IRQ_MSI_ENABLE;
> > - exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_LEVEL);
> > + exynos_elb_writel(exynos, val, PCIE_IRQ_EN_LEVEL);
> > }
> >
> > static void exynos_pcie_enable_interrupts(struct pcie_port *pp)
> > @@ -466,8 +466,8 @@ static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
> >
> > static int exynos_pcie_link_up(struct pcie_port *pp)
> > {
> > - struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> > - u32 val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_RDLH_LINKUP);
> > + struct exynos_pcie *exynos = to_exynos_pcie(pp);
> > + u32 val = exynos_elb_readl(exynos, PCIE_ELBI_RDLH_LINKUP);
> >
> > if (val == PCIE_ELBI_LTSSM_ENABLE)
> > return 1;
> > @@ -538,7 +538,7 @@ static int __init exynos_add_pcie_port(struct pcie_port *pp,
> >
> > static int __init exynos_pcie_probe(struct platform_device *pdev)
> > {
> > - struct exynos_pcie *exynos_pcie;
> > + struct exynos_pcie *exynos;
> > struct pcie_port *pp;
> > struct device_node *np = pdev->dev.of_node;
> > struct resource *elbi_base;
> > @@ -546,54 +546,52 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
> > struct resource *block_base;
> > int ret;
> >
> > - exynos_pcie = devm_kzalloc(&pdev->dev, sizeof(*exynos_pcie),
> > - GFP_KERNEL);
> > - if (!exynos_pcie)
> > + exynos = devm_kzalloc(&pdev->dev, sizeof(*exynos), GFP_KERNEL);
> > + if (!exynos)
> > return -ENOMEM;
> >
> > - pp = &exynos_pcie->pp;
> > -
> > + pp = &exynos->pp;
> > pp->dev = &pdev->dev;
> >
> > - exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
> > + exynos->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
> >
> > - exynos_pcie->clk = devm_clk_get(&pdev->dev, "pcie");
> > - if (IS_ERR(exynos_pcie->clk)) {
> > + exynos->clk = devm_clk_get(&pdev->dev, "pcie");
> > + if (IS_ERR(exynos->clk)) {
> > dev_err(&pdev->dev, "Failed to get pcie rc clock\n");
> > - return PTR_ERR(exynos_pcie->clk);
> > + return PTR_ERR(exynos->clk);
> > }
> > - ret = clk_prepare_enable(exynos_pcie->clk);
> > + ret = clk_prepare_enable(exynos->clk);
> > if (ret)
> > return ret;
> >
> > - exynos_pcie->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
> > - if (IS_ERR(exynos_pcie->bus_clk)) {
> > + exynos->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
> > + if (IS_ERR(exynos->bus_clk)) {
> > dev_err(&pdev->dev, "Failed to get pcie bus clock\n");
> > - ret = PTR_ERR(exynos_pcie->bus_clk);
> > + ret = PTR_ERR(exynos->bus_clk);
> > goto fail_clk;
> > }
> > - ret = clk_prepare_enable(exynos_pcie->bus_clk);
> > + ret = clk_prepare_enable(exynos->bus_clk);
> > if (ret)
> > goto fail_clk;
> >
> > elbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > - exynos_pcie->elbi_base = devm_ioremap_resource(&pdev->dev, elbi_base);
> > - if (IS_ERR(exynos_pcie->elbi_base)) {
> > - ret = PTR_ERR(exynos_pcie->elbi_base);
> > + exynos->elbi_base = devm_ioremap_resource(&pdev->dev, elbi_base);
> > + if (IS_ERR(exynos->elbi_base)) {
> > + ret = PTR_ERR(exynos->elbi_base);
> > goto fail_bus_clk;
> > }
> >
> > phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> > - exynos_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy_base);
> > - if (IS_ERR(exynos_pcie->phy_base)) {
> > - ret = PTR_ERR(exynos_pcie->phy_base);
> > + exynos->phy_base = devm_ioremap_resource(&pdev->dev, phy_base);
> > + if (IS_ERR(exynos->phy_base)) {
> > + ret = PTR_ERR(exynos->phy_base);
> > goto fail_bus_clk;
> > }
> >
> > block_base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
> > - exynos_pcie->block_base = devm_ioremap_resource(&pdev->dev, block_base);
> > - if (IS_ERR(exynos_pcie->block_base)) {
> > - ret = PTR_ERR(exynos_pcie->block_base);
> > + exynos->block_base = devm_ioremap_resource(&pdev->dev, block_base);
> > + if (IS_ERR(exynos->block_base)) {
> > + ret = PTR_ERR(exynos->block_base);
> > goto fail_bus_clk;
> > }
> >
> > @@ -601,22 +599,22 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
> > if (ret < 0)
> > goto fail_bus_clk;
> >
> > - platform_set_drvdata(pdev, exynos_pcie);
> > + platform_set_drvdata(pdev, exynos);
> > return 0;
> >
> > fail_bus_clk:
> > - clk_disable_unprepare(exynos_pcie->bus_clk);
> > + clk_disable_unprepare(exynos->bus_clk);
> > fail_clk:
> > - clk_disable_unprepare(exynos_pcie->clk);
> > + clk_disable_unprepare(exynos->clk);
> > return ret;
> > }
> >
> > static int __exit exynos_pcie_remove(struct platform_device *pdev)
> > {
> > - struct exynos_pcie *exynos_pcie = platform_get_drvdata(pdev);
> > + struct exynos_pcie *exynos = platform_get_drvdata(pdev);
> >
> > - clk_disable_unprepare(exynos_pcie->bus_clk);
> > - clk_disable_unprepare(exynos_pcie->clk);
> > + clk_disable_unprepare(exynos->bus_clk);
> > + clk_disable_unprepare(exynos->clk);
> >
> > return 0;
> > }
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at http://vger.kernel.org/majordomo-info.html
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/8] PCI: exynos: Name private struct pointer "exynos" consistently
2016-10-10 13:36 ` Bjorn Helgaas
@ 2016-10-10 16:49 ` Krzysztof Kozlowski
0 siblings, 0 replies; 11+ messages in thread
From: Krzysztof Kozlowski @ 2016-10-10 16:49 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Krzysztof Kozlowski, Bjorn Helgaas, Jingoo Han,
Krzysztof Kozlowski, Kukjin Kim, linux-pci, linux-samsung-soc
On Mon, Oct 10, 2016 at 08:36:44AM -0500, Bjorn Helgaas wrote:
> Hi Krzysztof,
>
> Thanks a lot for taking the time to look these over.
>
> On Sat, Oct 08, 2016 at 10:41:44PM +0300, Krzysztof Kozlowski wrote:
> > On Fri, Oct 07, 2016 at 11:35:26AM -0500, Bjorn Helgaas wrote:
> > > Use a device-specific name, "exynos", for struct exynos_pcie pointers
> > > to hint that this is device-specific information.
> >
> > I don't get it. "exynos_pcie" is already a exynos-device-specific name.
> > There are a lot of changes but I don't see the real reason/benefit. What
> > was your intention?
>
> I'm looking across all the drivers in drivers/pci/host/, not just
> exynos. Many of them used "pcie" as name for pointers to the
> device-specific struct, leading to things like "pcie->lut" or
> "pcie->breg_base". These *look* like they should be sort of generic,
> but in fact they are device-specific.
>
> My idea was to replace that "pcie" name with something
> device-specific, and I started with the simplest possible name, e.g.,
> "exynos". Others pointed out that that for SoCs, that is often not
> enough specific enough, and something like "exynos_pcie" is more
> appropriate.
>
> In the specific case of exynos, it already uses "exynos_pcie" in most
> cases, so I tweaked this patch to use it in the few remaining places
> where it didn't (the register accessor functions).
Thanks for clarification, I am fine with it.
> > > No functional change
> > > intended.
> >
> > Oh, but there is. Inline disappeared in first functions. Although I
> > don't mind but this should be seprate from trivial rename.
>
> I didn't think of "inline" as a functional change, but I split it out
> into its own patch. I'm embarrassed at how much churn this turned out
> to be, so I didn't want to add more patches than I had to, but I did
> split it out for you.
>
> I repushed the branch.
Thanks,
Krzysztof
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2016-10-10 16:49 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-10-07 16:35 [PATCH 1/8] PCI: exynos: Name private struct pointer "exynos" consistently Bjorn Helgaas
2016-10-07 16:35 ` [PATCH 2/8] PCI: exynos: Pass device-specific struct to internal functions Bjorn Helgaas
2016-10-07 16:35 ` [PATCH 3/8] PCI: exynos: Reorder struct exynos_pcie Bjorn Helgaas
2016-10-07 16:35 ` [PATCH 4/8] PCI: exynos: Reorder accessor functions Bjorn Helgaas
2016-10-07 16:36 ` [PATCH 5/8] PCI: exynos: Swap order of exynos_elb_writel() reg/val arguments Bjorn Helgaas
2016-10-07 16:36 ` [PATCH 6/8] PCI: exynos: Swap order of exynos_phy_writel() " Bjorn Helgaas
2016-10-07 16:36 ` [PATCH 7/8] PCI: exynos: Swap order of exynos_blk_writel() " Bjorn Helgaas
2016-10-07 16:36 ` [PATCH 8/8] PCI: exynos: Add local struct device pointers Bjorn Helgaas
2016-10-08 19:41 ` [PATCH 1/8] PCI: exynos: Name private struct pointer "exynos" consistently Krzysztof Kozlowski
2016-10-10 13:36 ` Bjorn Helgaas
2016-10-10 16:49 ` Krzysztof Kozlowski
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