[U-Boot] [PATCH v2 0/3] am335x-icev2: Ethernet support

[U-Boot] [PATCH v2 0/3] am335x-icev2: Ethernet support

[Roger Quadros]

Hi,

am335x-icev2 has 2 Ethernet ports that can be used either as CPSW ethernet (RMII mode)
or PRUSS ethernet (MII mode) using jumpers placed next to the port on the board.

As a different PHY clock is required for RMII mode vs MII mode, we detect the jumper
setting and set the PHY clock frequency accordingly.

Tested with CPSW in RMII mode.

cheers,m
-roger

Changelog:
v2:
 - removed unnecessary patch 1.

Mugunthan V N (1):
  driver: net: cpsw: add support for RGMII id mode support and RMII
    clock source selection

Roger Quadros (2):
  board: am335x-icev2: add ethernet phy mode detection logic
  board: am335x: Always set eth/eth1addr environment variable

 board/ti/am335x/board.c | 154 +++++++++++++++++++++++++++++++++++++----------
 drivers/net/cpsw.c      | 157 +++++++++++++++++++++++++++++++++++++++++++-----
 include/cpsw.h          |   1 +
 3 files changed, 265 insertions(+), 47 deletions(-)

-- 
2.7.4

[U-Boot] [PATCH v2 1/3] driver: net: cpsw: add support for RGMII id mode support and RMII clock source selection

[Roger Quadros]

From: Mugunthan V N <mugunthanvnm@ti.com>

cpsw driver supports only selection of phy mode in control module
but control module has more setting like RGMII ID mode selection,
RMII clock source selection. So ported to cpsw-phy-sel driver
from kernel to u-boot.

[Lokesh Vutla]
- Update for am43xx variants.
- Use DT data to configure external chip clock for RMII mode.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 drivers/net/cpsw.c | 157 ++++++++++++++++++++++++++++++++++++++++++++++++-----
 include/cpsw.h     |   1 +
 2 files changed, 144 insertions(+), 14 deletions(-)

diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index 81ccc61..c1dc221 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -225,6 +225,18 @@ struct cpdma_chan {
 	void			*hdp, *cp, *rxfree;
 };
 
+/* AM33xx SoC specific definitions for the CONTROL port */
+#define AM33XX_GMII_SEL_MODE_MII	0
+#define AM33XX_GMII_SEL_MODE_RMII	1
+#define AM33XX_GMII_SEL_MODE_RGMII	2
+
+#define AM33XX_GMII_SEL_RGMII1_IDMODE	BIT(4)
+#define AM33XX_GMII_SEL_RGMII2_IDMODE	BIT(5)
+#define AM33XX_GMII_SEL_RMII1_IO_CLK_EN	BIT(6)
+#define AM33XX_GMII_SEL_RMII2_IO_CLK_EN	BIT(7)
+
+#define GMII_SEL_MODE_MASK		0x3
+
 #define desc_write(desc, fld, val)	__raw_writel((u32)(val), &(desc)->fld)
 #define desc_read(desc, fld)		__raw_readl(&(desc)->fld)
 #define desc_read_ptr(desc, fld)	((void *)__raw_readl(&(desc)->fld))
@@ -1150,12 +1162,129 @@ static inline fdt_addr_t cpsw_get_addr_by_node(const void *fdt, int node)
 						  false);
 }
 
+static void cpsw_gmii_sel_am3352(struct cpsw_priv *priv,
+				 phy_interface_t phy_mode)
+{
+	u32 reg;
+	u32 mask;
+	u32 mode = 0;
+	bool rgmii_id = false;
+	int slave = priv->data.active_slave;
+
+	reg = readl(priv->data.gmii_sel);
+
+	switch (phy_mode) {
+	case PHY_INTERFACE_MODE_RMII:
+		mode = AM33XX_GMII_SEL_MODE_RMII;
+		break;
+
+	case PHY_INTERFACE_MODE_RGMII:
+		mode = AM33XX_GMII_SEL_MODE_RGMII;
+		break;
+	case PHY_INTERFACE_MODE_RGMII_ID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		mode = AM33XX_GMII_SEL_MODE_RGMII;
+		rgmii_id = true;
+		break;
+
+	case PHY_INTERFACE_MODE_MII:
+	default:
+		mode = AM33XX_GMII_SEL_MODE_MII;
+		break;
+	};
+
+	mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6);
+	mode <<= slave * 2;
+
+	if (priv->data.rmii_clock_external) {
+		if (slave == 0)
+			mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN;
+		else
+			mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN;
+	}
+
+	if (rgmii_id) {
+		if (slave == 0)
+			mode |= AM33XX_GMII_SEL_RGMII1_IDMODE;
+		else
+			mode |= AM33XX_GMII_SEL_RGMII2_IDMODE;
+	}
+
+	reg &= ~mask;
+	reg |= mode;
+
+	writel(reg, priv->data.gmii_sel);
+}
+
+static void cpsw_gmii_sel_dra7xx(struct cpsw_priv *priv,
+				 phy_interface_t phy_mode)
+{
+	u32 reg;
+	u32 mask;
+	u32 mode = 0;
+	int slave = priv->data.active_slave;
+
+	reg = readl(priv->data.gmii_sel);
+
+	switch (phy_mode) {
+	case PHY_INTERFACE_MODE_RMII:
+		mode = AM33XX_GMII_SEL_MODE_RMII;
+		break;
+
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		mode = AM33XX_GMII_SEL_MODE_RGMII;
+		break;
+
+	case PHY_INTERFACE_MODE_MII:
+	default:
+		mode = AM33XX_GMII_SEL_MODE_MII;
+		break;
+	};
+
+	switch (slave) {
+	case 0:
+		mask = GMII_SEL_MODE_MASK;
+		break;
+	case 1:
+		mask = GMII_SEL_MODE_MASK << 4;
+		mode <<= 4;
+		break;
+	default:
+		dev_err(priv->dev, "invalid slave number...\n");
+		return;
+	}
+
+	if (priv->data.rmii_clock_external)
+		dev_err(priv->dev, "RMII External clock is not supported\n");
+
+	reg &= ~mask;
+	reg |= mode;
+
+	writel(reg, priv->data.gmii_sel);
+}
+
+static void cpsw_phy_sel(struct cpsw_priv *priv, const char *compat,
+			 phy_interface_t phy_mode)
+{
+	if (!strcmp(compat, "ti,am3352-cpsw-phy-sel"))
+		cpsw_gmii_sel_am3352(priv, phy_mode);
+	if (!strcmp(compat, "ti,am43xx-cpsw-phy-sel"))
+		cpsw_gmii_sel_am3352(priv, phy_mode);
+	else if (!strcmp(compat, "ti,dra7xx-cpsw-phy-sel"))
+		cpsw_gmii_sel_dra7xx(priv, phy_mode);
+}
+
 static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
 {
 	struct eth_pdata *pdata = dev_get_platdata(dev);
 	struct cpsw_priv *priv = dev_get_priv(dev);
 	struct gpio_desc *mode_gpios;
 	const char *phy_mode;
+	const char *phy_sel_compat = NULL;
 	const void *fdt = gd->fdt_blob;
 	int node = dev->of_offset;
 	int subnode;
@@ -1271,6 +1400,17 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
 				error("Not able to get gmii_sel reg address\n");
 				return -ENOENT;
 			}
+
+			if (fdt_get_property(fdt, subnode, "rmii-clock-ext",
+					     NULL))
+				priv->data.rmii_clock_external = true;
+
+			phy_sel_compat = fdt_getprop(fdt, subnode, "compatible",
+						     NULL);
+			if (!phy_sel_compat) {
+				error("Not able to get gmii_sel compatible\n");
+				return -ENOENT;
+			}
 		}
 	}
 
@@ -1293,20 +1433,9 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
 		debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
 		return -EINVAL;
 	}
-	switch (pdata->phy_interface) {
-	case PHY_INTERFACE_MODE_MII:
-		writel(MII_MODE_ENABLE, priv->data.gmii_sel);
-		break;
-	case PHY_INTERFACE_MODE_RMII:
-		writel(RMII_MODE_ENABLE, priv->data.gmii_sel);
-		break;
-	case PHY_INTERFACE_MODE_RGMII:
-	case PHY_INTERFACE_MODE_RGMII_ID:
-	case PHY_INTERFACE_MODE_RGMII_RXID:
-	case PHY_INTERFACE_MODE_RGMII_TXID:
-		writel(RGMII_MODE_ENABLE, priv->data.gmii_sel);
-		break;
-	}
+
+	/* Select phy interface in control module */
+	cpsw_phy_sel(priv, phy_sel_compat, pdata->phy_interface);
 
 	return 0;
 }
diff --git a/include/cpsw.h b/include/cpsw.h
index 257d12a..f135e7b 100644
--- a/include/cpsw.h
+++ b/include/cpsw.h
@@ -48,6 +48,7 @@ struct cpsw_platform_data {
 	void	(*control)(int enabled);
 	u32	host_port_num;
 	u32	active_slave;
+	bool	rmii_clock_external;
 	u8	version;
 };
 
-- 
2.7.4

[U-Boot] [PATCH v2 1/3] driver: net: cpsw: add support for RGMII id mode support and RMII clock source selection

[Tom Rini]

On Wed, Aug 24, 2016 at 03:35:49PM +0300, Roger Quadros wrote:

> From: Mugunthan V N <mugunthanvnm@ti.com>
> 
> cpsw driver supports only selection of phy mode in control module
> but control module has more setting like RGMII ID mode selection,
> RMII clock source selection. So ported to cpsw-phy-sel driver
> from kernel to u-boot.
> 
> [Lokesh Vutla]
> - Update for am43xx variants.
> - Use DT data to configure external chip clock for RMII mode.
> 
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> Signed-off-by: Roger Quadros <rogerq@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 1/3] driver: net: cpsw: add support for RGMII id mode support and RMII clock source selection

[Tom Rini]

On Wed, Aug 24, 2016 at 03:35:49PM +0300, Roger Quadros wrote:

> From: Mugunthan V N <mugunthanvnm@ti.com>
> 
> cpsw driver supports only selection of phy mode in control module
> but control module has more setting like RGMII ID mode selection,
> RMII clock source selection. So ported to cpsw-phy-sel driver
> from kernel to u-boot.
> 
> [Lokesh Vutla]
> - Update for am43xx variants.
> - Use DT data to configure external chip clock for RMII mode.
> 
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> Signed-off-by: Roger Quadros <rogerq@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 1/3] driver: net: cpsw: add support for RGMII id mode support and RMII clock source selection

[Roger Quadros]

Joe,

On 02/09/16 17:53, Tom Rini wrote:
> On Wed, Aug 24, 2016 at 03:35:49PM +0300, Roger Quadros wrote:
> 
>> From: Mugunthan V N <mugunthanvnm@ti.com>
>>
>> cpsw driver supports only selection of phy mode in control module
>> but control module has more setting like RGMII ID mode selection,
>> RMII clock source selection. So ported to cpsw-phy-sel driver
>> from kernel to u-boot.
>>
>> [Lokesh Vutla]
>> - Update for am43xx variants.
>> - Use DT data to configure external chip clock for RMII mode.
>>
>> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
>> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
>> Signed-off-by: Roger Quadros <rogerq@ti.com>
> 
> Reviewed-by: Tom Rini <trini@konsulko.com>
> 
Seems like you have missed this patch and picked the remaining two in this series.

cheers,
-roger

[U-Boot] [PATCH v2 1/3] driver: net: cpsw: add support for RGMII id mode support and RMII clock source selection

[Joe Hershberger]

Hi Roger,

On Fri, Oct 14, 2016 at 7:24 AM, Roger Quadros <rogerq@ti.com> wrote:
> Joe,
>
> On 02/09/16 17:53, Tom Rini wrote:
>> On Wed, Aug 24, 2016 at 03:35:49PM +0300, Roger Quadros wrote:
>>
>>> From: Mugunthan V N <mugunthanvnm@ti.com>
>>>
>>> cpsw driver supports only selection of phy mode in control module
>>> but control module has more setting like RGMII ID mode selection,
>>> RMII clock source selection. So ported to cpsw-phy-sel driver
>>> from kernel to u-boot.
>>>
>>> [Lokesh Vutla]
>>> - Update for am43xx variants.
>>> - Use DT data to configure external chip clock for RMII mode.
>>>
>>> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
>>> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
>>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>>
>> Reviewed-by: Tom Rini <trini@konsulko.com>
>>
> Seems like you have missed this patch and picked the remaining two in this series.

Mugunthan sent this patch also - as he was the author, I used his.

https://patchwork.ozlabs.org/patch/681802/

Cheers,
-Joe

[U-Boot] [PATCH v2 2/3] board: am335x-icev2: add ethernet phy mode detection logic

[Roger Quadros]

Both ethernet ports can be used as CPSW ethernet (RMII mode)
or PRU ethernet (MII mode) by setting the jumper near the port.
Read the jumper value and set the pinmux, external mux and
PHY clock accordingly.

As jumper line is overridden by PHY RX_DV pin immediately
after bootstrap (power-up/reset), we have to use GPIO edge
detection to capture the jumper line status.

As u-boot doesn't provide any infrastructure for GPIO edge
detection, we directly access the GPIO registers.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 board/ti/am335x/board.c | 82 ++++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 75 insertions(+), 7 deletions(-)

diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 56f4984..bf3b539 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -46,12 +46,23 @@ DECLARE_GLOBAL_DATA_PTR;
 #define GPIO_MUX_MII_CTRL	GPIO_TO_PIN(3, 10)
 #define GPIO_FET_SWITCH_CTRL	GPIO_TO_PIN(0, 7)
 #define GPIO_PHY_RESET		GPIO_TO_PIN(2, 5)
+#define GPIO_ETH0_MODE		GPIO_TO_PIN(0, 11)
+#define GPIO_ETH1_MODE		GPIO_TO_PIN(1, 26)
 
 #if defined(CONFIG_SPL_BUILD) || \
 	(defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 #endif
 
+#define GPIO0_RISINGDETECT	(AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
+#define GPIO1_RISINGDETECT	(AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
+
+#define GPIO0_IRQSTATUS1	(AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
+#define GPIO1_IRQSTATUS1	(AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
+
+#define GPIO0_IRQSTATUSRAW	(AM33XX_GPIO0_BASE + 0x024)
+#define GPIO1_IRQSTATUSRAW	(AM33XX_GPIO1_BASE + 0x024)
+
 /*
  * Read header information from EEPROM into global structure.
  */
@@ -491,9 +502,9 @@ void sdram_init(void)
 }
 #endif
 
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+#if !defined(CONFIG_SPL_BUILD) || \
 	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
-static void request_and_set_gpio(int gpio, char *name)
+static void request_and_set_gpio(int gpio, char *name, int val)
 {
 	int ret;
 
@@ -509,7 +520,7 @@ static void request_and_set_gpio(int gpio, char *name)
 		goto err_free_gpio;
 	}
 
-	gpio_set_value(gpio, 1);
+	gpio_set_value(gpio, val);
 
 	return;
 
@@ -517,7 +528,8 @@ err_free_gpio:
 	gpio_free(gpio);
 }
 
-#define REQUEST_AND_SET_GPIO(N)	request_and_set_gpio(N, #N);
+#define REQUEST_AND_SET_GPIO(N)	request_and_set_gpio(N, #N, 1);
+#define REQUEST_AND_CLR_GPIO(N)	request_and_set_gpio(N, #N, 0);
 
 /**
  * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
@@ -547,20 +559,76 @@ int board_init(void)
 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
 	gpmc_init();
 #endif
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD))
-	int rv;
 
+#if !defined(CONFIG_SPL_BUILD) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 	if (board_is_icev2()) {
+		int rv;
+		u32 reg;
+
 		REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
-		REQUEST_AND_SET_GPIO(GPIO_MUX_MII_CTRL);
+		/* Make J19 status available on GPIO1_26 */
+		REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
+
 		REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
+		/*
+		 * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
+		 * jumpers near the port. Read the jumper value and set
+		 * the pinmux, external mux and PHY clock accordingly.
+		 * As jumper line is overridden by PHY RX_DV pin immediately
+		 * after bootstrap (power-up/reset), we need to sample
+		 * it during PHY reset using GPIO rising edge detection.
+		 */
 		REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
+		/* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
+		reg = readl(GPIO0_RISINGDETECT) | BIT(11);
+		writel(reg, GPIO0_RISINGDETECT);
+		reg = readl(GPIO1_RISINGDETECT) | BIT(26);
+		writel(reg, GPIO1_RISINGDETECT);
+		/* Reset PHYs to capture the Jumper setting */
+		gpio_set_value(GPIO_PHY_RESET, 0);
+		udelay(2);	/* PHY datasheet states 1uS min. */
+		gpio_set_value(GPIO_PHY_RESET, 1);
+
+		reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
+		if (reg) {
+			writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
+			/* RMII mode */
+			printf("ETH0, CPSW\n");
+		} else {
+			/* MII mode */
+			printf("ETH0, PRU\n");
+			cdce913_data.pdiv3 = 4;	/* 25MHz PHY clk */
+		}
+
+		reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
+		if (reg) {
+			writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
+			/* RMII mode */
+			printf("ETH1, CPSW\n");
+			gpio_set_value(GPIO_MUX_MII_CTRL, 1);
+		} else {
+			/* MII mode */
+			printf("ETH1, PRU\n");
+			cdce913_data.pdiv2 = 4;	/* 25MHz PHY clk */
+		}
+
+		/* disable rising edge IRQs */
+		reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
+		writel(reg, GPIO0_RISINGDETECT);
+		reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
+		writel(reg, GPIO1_RISINGDETECT);
 
 		rv = setup_clock_synthesizer(&cdce913_data);
 		if (rv) {
 			printf("Clock synthesizer setup failed %d\n", rv);
 			return rv;
 		}
+
+		/* reset PHYs */
+		gpio_set_value(GPIO_PHY_RESET, 0);
+		udelay(2);	/* PHY datasheet states 1uS min. */
+		gpio_set_value(GPIO_PHY_RESET, 1);
 	}
 #endif
 
-- 
2.7.4

[U-Boot] [PATCH v2 2/3] board: am335x-icev2: add ethernet phy mode detection logic

[Tom Rini]

On Wed, Aug 24, 2016 at 03:35:50PM +0300, Roger Quadros wrote:

> Both ethernet ports can be used as CPSW ethernet (RMII mode)
> or PRU ethernet (MII mode) by setting the jumper near the port.
> Read the jumper value and set the pinmux, external mux and
> PHY clock accordingly.
> 
> As jumper line is overridden by PHY RX_DV pin immediately
> after bootstrap (power-up/reset), we have to use GPIO edge
> detection to capture the jumper line status.
> 
> As u-boot doesn't provide any infrastructure for GPIO edge
> detection, we directly access the GPIO registers.
> 
> Signed-off-by: Roger Quadros <rogerq@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 2/3] board: am335x-icev2: add ethernet phy mode detection logic

[Tom Rini]

On Wed, Aug 24, 2016 at 03:35:50PM +0300, Roger Quadros wrote:

> Both ethernet ports can be used as CPSW ethernet (RMII mode)
> or PRU ethernet (MII mode) by setting the jumper near the port.
> Read the jumper value and set the pinmux, external mux and
> PHY clock accordingly.
> 
> As jumper line is overridden by PHY RX_DV pin immediately
> after bootstrap (power-up/reset), we have to use GPIO edge
> detection to capture the jumper line status.
> 
> As u-boot doesn't provide any infrastructure for GPIO edge
> detection, we directly access the GPIO registers.
> 
> Signed-off-by: Roger Quadros <rogerq@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 2/3] board: am335x-icev2: add ethernet phy mode detection logic

[Joe Hershberger]

On Wed, Aug 24, 2016 at 2:35 PM, Roger Quadros <rogerq@ti.com> wrote:
> Both ethernet ports can be used as CPSW ethernet (RMII mode)
> or PRU ethernet (MII mode) by setting the jumper near the port.
> Read the jumper value and set the pinmux, external mux and
> PHY clock accordingly.
>
> As jumper line is overridden by PHY RX_DV pin immediately
> after bootstrap (power-up/reset), we have to use GPIO edge
> detection to capture the jumper line status.
>
> As u-boot doesn't provide any infrastructure for GPIO edge
> detection, we directly access the GPIO registers.
>
> Signed-off-by: Roger Quadros <rogerq@ti.com>

Acked-by: Joe Hershberger <joe.hershberger@ni.com>

[U-Boot] board: am335x-icev2: add ethernet phy mode detection logic

[Joe Hershberger]

Hi Roger,

https://patchwork.ozlabs.org/patch/662258/ was applied to u-boot-net.git.

Thanks!
-Joe

[U-Boot] [PATCH v2 3/3] board: am335x: Always set eth/eth1addr environment variable

[Roger Quadros]

Ethernet ports might be used in the kernel even if CPSW driver
is disabled at u-boot. So always set ethaddr and eth1addr
environment variable from efuse.

Retain usbnet_devaddr as it is required for SPL USB eth boot.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 board/ti/am335x/board.c | 72 +++++++++++++++++++++++++++++++------------------
 1 file changed, 46 insertions(+), 26 deletions(-)

diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index bf3b539..1e1622a 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -49,10 +49,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define GPIO_ETH0_MODE		GPIO_TO_PIN(0, 11)
 #define GPIO_ETH1_MODE		GPIO_TO_PIN(1, 26)
 
-#if defined(CONFIG_SPL_BUILD) || \
-	(defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-#endif
 
 #define GPIO0_RISINGDETECT	(AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
 #define GPIO1_RISINGDETECT	(AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
@@ -638,6 +635,11 @@ int board_init(void)
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
+#if !defined(CONFIG_SPL_BUILD)
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+#endif
+
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 	int rc;
 	char *name = NULL;
@@ -651,6 +653,39 @@ int board_late_init(void)
 	set_board_info_env(name);
 #endif
 
+#if !defined(CONFIG_SPL_BUILD)
+	/* try reading mac address from efuse */
+	mac_lo = readl(&cdev->macid0l);
+	mac_hi = readl(&cdev->macid0h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+	if (!getenv("ethaddr")) {
+		printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+		if (is_valid_ethaddr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+	}
+
+	mac_lo = readl(&cdev->macid1l);
+	mac_hi = readl(&cdev->macid1h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+	if (!getenv("eth1addr")) {
+		if (is_valid_ethaddr(mac_addr))
+			eth_setenv_enetaddr("eth1addr", mac_addr);
+	}
+#endif
+
 	return 0;
 }
 #endif
@@ -719,11 +754,15 @@ static struct cpsw_platform_data cpsw_data = {
 int board_eth_init(bd_t *bis)
 {
 	int rv, n = 0;
+#if defined(CONFIG_USB_ETHER) && \
+	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
 	uint8_t mac_addr[6];
 	uint32_t mac_hi, mac_lo;
-	__maybe_unused struct ti_am_eeprom *header;
 
-	/* try reading mac address from efuse */
+	/*
+	 * use efuse mac address for USB ethernet as we know that
+	 * both CPSW and USB ethernet will never be active at the same time
+	 */
 	mac_lo = readl(&cdev->macid0l);
 	mac_hi = readl(&cdev->macid0h);
 	mac_addr[0] = mac_hi & 0xFF;
@@ -732,32 +771,13 @@ int board_eth_init(bd_t *bis)
 	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 	mac_addr[4] = mac_lo & 0xFF;
 	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+#endif
+
 
 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
-	if (!getenv("ethaddr")) {
-		printf("<ethaddr> not set. Validating first E-fuse MAC\n");
-
-		if (is_valid_ethaddr(mac_addr))
-			eth_setenv_enetaddr("ethaddr", mac_addr);
-	}
 
 #ifdef CONFIG_DRIVER_TI_CPSW
-
-	mac_lo = readl(&cdev->macid1l);
-	mac_hi = readl(&cdev->macid1h);
-	mac_addr[0] = mac_hi & 0xFF;
-	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
-	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
-	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
-	mac_addr[4] = mac_lo & 0xFF;
-	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
-	if (!getenv("eth1addr")) {
-		if (is_valid_ethaddr(mac_addr))
-			eth_setenv_enetaddr("eth1addr", mac_addr);
-	}
-
 	if (read_eeprom() < 0)
 		puts("Could not get board ID.\n");
 
-- 
2.7.4

[U-Boot] [PATCH v2 3/3] board: am335x: Always set eth/eth1addr environment variable

[Tom Rini]

On Wed, Aug 24, 2016 at 03:35:51PM +0300, Roger Quadros wrote:

> Ethernet ports might be used in the kernel even if CPSW driver
> is disabled at u-boot. So always set ethaddr and eth1addr
> environment variable from efuse.
> 
> Retain usbnet_devaddr as it is required for SPL USB eth boot.
> 
> Signed-off-by: Roger Quadros <rogerq@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 3/3] board: am335x: Always set eth/eth1addr environment variable

[Tom Rini]

On Wed, Aug 24, 2016 at 03:35:51PM +0300, Roger Quadros wrote:

> Ethernet ports might be used in the kernel even if CPSW driver
> is disabled at u-boot. So always set ethaddr and eth1addr
> environment variable from efuse.
> 
> Retain usbnet_devaddr as it is required for SPL USB eth boot.
> 
> Signed-off-by: Roger Quadros <rogerq@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 3/3] board: am335x: Always set eth/eth1addr environment variable

[Joe Hershberger]

On Wed, Aug 24, 2016 at 2:35 PM, Roger Quadros <rogerq@ti.com> wrote:
> Ethernet ports might be used in the kernel even if CPSW driver
> is disabled at u-boot. So always set ethaddr and eth1addr
> environment variable from efuse.
>
> Retain usbnet_devaddr as it is required for SPL USB eth boot.
>
> Signed-off-by: Roger Quadros <rogerq@ti.com>

Acked-by: Joe Hershberger <joe.hershberger@ni.com>

[U-Boot] board: am335x: Always set eth/eth1addr environment variable

[Joe Hershberger]

Hi Roger,

https://patchwork.ozlabs.org/patch/662259/ was applied to u-boot-net.git.

Thanks!
-Joe