* [PATCH 1/2] drm/i915/gen9: fix watermarks when using the pipe scaler
@ 2016-10-07 20:28 ` Paulo Zanoni
0 siblings, 0 replies; 7+ messages in thread
From: Paulo Zanoni @ 2016-10-07 20:28 UTC (permalink / raw)
To: intel-gfx; +Cc: dhinakaran.pandiyan, stable, Paulo Zanoni
Luckily, the necessary adjustments for when we're using the scaler are
exactly the same as the ones needed on ILK+, so just reuse the
function we already have.
v2: Invert the patch order so stable backports get easier.
Cc: stable@vger.kernel.org
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fe6c1c6..000b033 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3470,12 +3470,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
return 0;
}
-static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
-{
- /* TODO: Take into account the scalers once we support them */
- return config->base.adjusted_mode.crtc_clock;
-}
-
/*
* The max latency should be 257 (max the punit can code is 255 and we add 2us
* for the read latency) and cpp should always be <= 8, so that
@@ -3526,7 +3520,7 @@ static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cst
* Adjusted plane pixel rate is just the pipe's adjusted pixel rate
* with additional adjustments for plane-specific scaling.
*/
- adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
+ adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
downscale_amount = skl_plane_downscale_amount(pstate);
pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
@@ -3742,11 +3736,11 @@ skl_compute_linetime_wm(struct intel_crtc_state *cstate)
if (!cstate->base.active)
return 0;
- if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
+ if (WARN_ON(ilk_pipe_pixel_rate(cstate) == 0))
return 0;
return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
- skl_pipe_pixel_rate(cstate));
+ ilk_pipe_pixel_rate(cstate));
}
static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 2/2] drm/i915/gen9: don't call ilk_pipe_pixel_rate() twice on the same function
2016-10-07 20:28 ` Paulo Zanoni
(?)
@ 2016-10-07 20:28 ` Paulo Zanoni
-1 siblings, 0 replies; 7+ messages in thread
From: Paulo Zanoni @ 2016-10-07 20:28 UTC (permalink / raw)
To: intel-gfx; +Cc: dhinakaran.pandiyan, Paulo Zanoni
We used to call skl_pipe_pixel_rate(), which used to be a single
one-line return, but now we're calling ilk_pipe_pixel_rate() which is
not as simple, so it's better to just call it once and store the
computed value for reuse.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 000b033..62d730d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3733,14 +3733,18 @@ skl_compute_wm_level(const struct drm_i915_private *dev_priv,
static uint32_t
skl_compute_linetime_wm(struct intel_crtc_state *cstate)
{
+ uint32_t pixel_rate;
+
if (!cstate->base.active)
return 0;
- if (WARN_ON(ilk_pipe_pixel_rate(cstate) == 0))
+ pixel_rate = ilk_pipe_pixel_rate(cstate);
+
+ if (WARN_ON(pixel_rate == 0))
return 0;
return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
- ilk_pipe_pixel_rate(cstate));
+ pixel_rate);
}
static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [Intel-gfx] [PATCH 1/2] drm/i915/gen9: fix watermarks when using the pipe scaler
2016-10-07 20:28 ` Paulo Zanoni
@ 2016-10-10 9:01 ` Jani Nikula
-1 siblings, 0 replies; 7+ messages in thread
From: Jani Nikula @ 2016-10-10 9:01 UTC (permalink / raw)
To: Paulo Zanoni, intel-gfx; +Cc: dhinakaran.pandiyan, stable, Paulo Zanoni
On Fri, 07 Oct 2016, Paulo Zanoni <paulo.r.zanoni@intel.com> wrote:
> Luckily, the necessary adjustments for when we're using the scaler are
> exactly the same as the ones needed on ILK+, so just reuse the
> function we already have.
>
> v2: Invert the patch order so stable backports get easier.
Replied to the other set first... this order is fine too, with or
without cc: stable on the other one.
BR,
Jani.
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 12 +++---------
> 1 file changed, 3 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index fe6c1c6..000b033 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3470,12 +3470,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> return 0;
> }
>
> -static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
> -{
> - /* TODO: Take into account the scalers once we support them */
> - return config->base.adjusted_mode.crtc_clock;
> -}
> -
> /*
> * The max latency should be 257 (max the punit can code is 255 and we add 2us
> * for the read latency) and cpp should always be <= 8, so that
> @@ -3526,7 +3520,7 @@ static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cst
> * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
> * with additional adjustments for plane-specific scaling.
> */
> - adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
> + adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
> downscale_amount = skl_plane_downscale_amount(pstate);
>
> pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
> @@ -3742,11 +3736,11 @@ skl_compute_linetime_wm(struct intel_crtc_state *cstate)
> if (!cstate->base.active)
> return 0;
>
> - if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
> + if (WARN_ON(ilk_pipe_pixel_rate(cstate) == 0))
> return 0;
>
> return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
> - skl_pipe_pixel_rate(cstate));
> + ilk_pipe_pixel_rate(cstate));
> }
>
> static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH 1/2] drm/i915/gen9: fix watermarks when using the pipe scaler
@ 2016-10-10 9:01 ` Jani Nikula
0 siblings, 0 replies; 7+ messages in thread
From: Jani Nikula @ 2016-10-10 9:01 UTC (permalink / raw)
To: intel-gfx; +Cc: dhinakaran.pandiyan, stable, Paulo Zanoni
On Fri, 07 Oct 2016, Paulo Zanoni <paulo.r.zanoni@intel.com> wrote:
> Luckily, the necessary adjustments for when we're using the scaler are
> exactly the same as the ones needed on ILK+, so just reuse the
> function we already have.
>
> v2: Invert the patch order so stable backports get easier.
Replied to the other set first... this order is fine too, with or
without cc: stable on the other one.
BR,
Jani.
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 12 +++---------
> 1 file changed, 3 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index fe6c1c6..000b033 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3470,12 +3470,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> return 0;
> }
>
> -static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
> -{
> - /* TODO: Take into account the scalers once we support them */
> - return config->base.adjusted_mode.crtc_clock;
> -}
> -
> /*
> * The max latency should be 257 (max the punit can code is 255 and we add 2us
> * for the read latency) and cpp should always be <= 8, so that
> @@ -3526,7 +3520,7 @@ static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cst
> * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
> * with additional adjustments for plane-specific scaling.
> */
> - adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
> + adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
> downscale_amount = skl_plane_downscale_amount(pstate);
>
> pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
> @@ -3742,11 +3736,11 @@ skl_compute_linetime_wm(struct intel_crtc_state *cstate)
> if (!cstate->base.active)
> return 0;
>
> - if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
> + if (WARN_ON(ilk_pipe_pixel_rate(cstate) == 0))
> return 0;
>
> return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
> - skl_pipe_pixel_rate(cstate));
> + ilk_pipe_pixel_rate(cstate));
> }
>
> static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915/gen9: fix watermarks when using the pipe scaler
2016-10-07 20:28 ` Paulo Zanoni
` (2 preceding siblings ...)
(?)
@ 2016-10-10 13:50 ` Patchwork
-1 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2016-10-10 13:50 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/gen9: fix watermarks when using the pipe scaler
URL : https://patchwork.freedesktop.org/series/13465/
State : warning
== Summary ==
Series 13465v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/13465/revisions/1/mbox/
Test kms_psr_sink_crc:
Subgroup psr_basic:
dmesg-warn -> PASS (fi-skl-6700hq)
Test vgem_basic:
Subgroup unload:
pass -> SKIP (fi-ilk-650)
pass -> SKIP (fi-skl-6700hq)
skip -> PASS (fi-bdw-5557u)
pass -> SKIP (fi-skl-6260u)
skip -> PASS (fi-byt-n2820)
skip -> PASS (fi-skl-6700k)
fi-bdw-5557u total:248 pass:232 dwarn:0 dfail:0 fail:0 skip:16
fi-bsw-n3050 total:248 pass:204 dwarn:0 dfail:0 fail:0 skip:44
fi-bxt-t5700 total:248 pass:217 dwarn:0 dfail:0 fail:0 skip:31
fi-byt-j1900 total:248 pass:214 dwarn:1 dfail:0 fail:1 skip:32
fi-byt-n2820 total:248 pass:211 dwarn:0 dfail:0 fail:1 skip:36
fi-hsw-4770 total:248 pass:224 dwarn:0 dfail:0 fail:0 skip:24
fi-hsw-4770r total:248 pass:224 dwarn:0 dfail:0 fail:0 skip:24
fi-ilk-650 total:248 pass:184 dwarn:0 dfail:0 fail:2 skip:62
fi-ivb-3520m total:248 pass:221 dwarn:0 dfail:0 fail:0 skip:27
fi-ivb-3770 total:248 pass:207 dwarn:0 dfail:0 fail:0 skip:41
fi-kbl-7200u total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26
fi-skl-6260u total:248 pass:232 dwarn:0 dfail:0 fail:0 skip:16
fi-skl-6700hq total:248 pass:224 dwarn:0 dfail:0 fail:0 skip:24
fi-skl-6700k total:248 pass:222 dwarn:1 dfail:0 fail:0 skip:25
fi-skl-6770hq total:248 pass:231 dwarn:1 dfail:0 fail:1 skip:15
fi-snb-2520m total:248 pass:211 dwarn:0 dfail:0 fail:0 skip:37
fi-snb-2600 total:248 pass:209 dwarn:0 dfail:0 fail:0 skip:39
Results at /archive/results/CI_IGT_test/Patchwork_2655/
f35ed31aea66b3230c366fcba5f3456ae2cb956e drm-intel-nightly: 2016y-10m-10d-11h-28m-51s UTC integration manifest
1cee613 drm/i915/gen9: don't call ilk_pipe_pixel_rate() twice on the same function
3fa3b0b drm/i915/gen9: fix watermarks when using the pipe scaler
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [Intel-gfx] [PATCH 1/2] drm/i915/gen9: fix watermarks when using the pipe scaler
2016-10-07 20:28 ` Paulo Zanoni
` (3 preceding siblings ...)
(?)
@ 2016-10-17 21:33 ` Matt Roper
-1 siblings, 0 replies; 7+ messages in thread
From: Matt Roper @ 2016-10-17 21:33 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: intel-gfx, dhinakaran.pandiyan, stable
On Fri, Oct 07, 2016 at 05:28:57PM -0300, Paulo Zanoni wrote:
> Luckily, the necessary adjustments for when we're using the scaler are
> exactly the same as the ones needed on ILK+, so just reuse the
> function we already have.
>
> v2: Invert the patch order so stable backports get easier.
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
I thought there was a patch floating around to fix this back before I
went on break a couple months ago, but I can't find it now, so this
looks good.
For both patches:
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 12 +++---------
> 1 file changed, 3 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index fe6c1c6..000b033 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3470,12 +3470,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> return 0;
> }
>
> -static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
> -{
> - /* TODO: Take into account the scalers once we support them */
> - return config->base.adjusted_mode.crtc_clock;
> -}
> -
> /*
> * The max latency should be 257 (max the punit can code is 255 and we add 2us
> * for the read latency) and cpp should always be <= 8, so that
> @@ -3526,7 +3520,7 @@ static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cst
> * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
> * with additional adjustments for plane-specific scaling.
> */
> - adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
> + adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
> downscale_amount = skl_plane_downscale_amount(pstate);
>
> pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
> @@ -3742,11 +3736,11 @@ skl_compute_linetime_wm(struct intel_crtc_state *cstate)
> if (!cstate->base.active)
> return 0;
>
> - if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
> + if (WARN_ON(ilk_pipe_pixel_rate(cstate) == 0))
> return 0;
>
> return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
> - skl_pipe_pixel_rate(cstate));
> + ilk_pipe_pixel_rate(cstate));
> }
>
> static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 7+ messages in thread