* [PATCH 1/2] drm/i915/gvt: add ACPI and 64BIT dependencies
@ 2016-10-21 15:25 Arnd Bergmann
2016-10-21 15:25 ` Arnd Bergmann
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Arnd Bergmann @ 2016-10-21 15:25 UTC (permalink / raw)
To: Daniel Vetter, Jani Nikula
Cc: Zhi Wang, Zhenyu Wang, Arnd Bergmann, David Airlie, Chris Wilson,
Joonas Lahtinen, Tvrtko Ursulin, Andreas Ziegler, intel-gfx,
dri-devel, linux-kernel
The newly added gvt code produces lots of serious warnings and errors
when either built on 32-bit x86, or built with ACPI disabled, e.g.
drivers/gpu/drm/i915/gvt/gtt.c: In function ‘read_pte64’:
drivers/gpu/drm/i915/gvt/gtt.c:277:2: error: left shift count >= width of type [-Werror]
drivers/gpu/drm/i915/gvt/gtt.c: In function ‘gen8_gtt_get_pfn’:
drivers/gpu/drm/i915/gvt/gtt.c:360:3: error: left shift count >= width of type [-Werror]
drivers/gpu/drm/i915/gvt/opregion.c: In function ‘intel_gvt_init_opregion’:
drivers/gpu/drm/i915/gvt/opregion.c:183:2: error: implicit declaration of function ‘acpi_os_ioremap’ [-Werror=implicit-function-declaration]
This avoids the problems by simply disallowing those configurations
in Kconfig. I'm sure it's possible to make the code more portable
and support building GVT without those options, but it might not be
useful to do so.
Fixes: 4d60c5fd3f87 ("drm/i915/gvt: vGPU PCI configuration space virtualization")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
If the code is meant to work on 32-bit and non-ACPI kernels, please
treat this as a bug report and disregard the patch.
---
drivers/gpu/drm/i915/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 6d4194288d11..1b9308284dde 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -84,6 +84,7 @@ config DRM_I915_USERPTR
config DRM_I915_GVT
bool "Enable Intel GVT-g graphics virtualization host support"
depends on DRM_I915
+ depends on 64BIT && ACPI
default n
help
Choose this option if you want to enable Intel GVT-g graphics
--
2.9.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/2] drm/i915/gvt: fix compilation
2016-10-21 15:25 [PATCH 1/2] drm/i915/gvt: add ACPI and 64BIT dependencies Arnd Bergmann
@ 2016-10-21 15:25 ` Arnd Bergmann
2016-10-21 16:47 ` ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915/gvt: add ACPI and 64BIT dependencies Patchwork
2016-10-22 5:06 ` Zhenyu Wang
2 siblings, 0 replies; 8+ messages in thread
From: Arnd Bergmann @ 2016-10-21 15:25 UTC (permalink / raw)
To: Daniel Vetter, Jani Nikula
Cc: Zhi Wang, Zhenyu Wang, Arnd Bergmann, David Airlie, Chris Wilson,
igvt-g-dev, intel-gfx, dri-devel, linux-kernel
Two functions in the newly added gvt render code are obviously
broken, as they reference a variable without initialization and
don't reference another variable at all:
drivers/gpu/drm/i915/gvt/render.c: In function ‘intel_gvt_load_render_mmio’:
drivers/gpu/drm/i915/gvt/render.c:148:13: error: ‘offset.reg’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
drivers/gpu/drm/i915/gvt/render.c: In function ‘intel_gvt_restore_render_mmio’:
drivers/gpu/drm/i915/gvt/render.c:185:13: error: ‘offset.reg’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
This is probably not a correct fix, but it gets us a clean build
by removing the unused arrays and initializing the offset variable
to something that potentially might be correct.
Fixes: 178657139307 ("drm/i915/gvt: vGPU context switch")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/gpu/drm/i915/gvt/render.c | 25 +++----------------------
1 file changed, 3 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c
index feebb65ba641..79e112288065 100644
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -147,29 +147,20 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id)
{
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
i915_reg_t offset, l3_offset;
- u32 regs[] = {
- [RCS] = 0xc800,
- [VCS] = 0xc900,
- [VCS2] = 0xca00,
- [BCS] = 0xcc00,
- [VECS] = 0xcb00,
- };
int i;
- if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
- return;
-
if (!IS_SKYLAKE(dev_priv))
return;
for (i = 0; i < 64; i++) {
+ offset.reg = i * 4;
gen9_render_mocs[ring_id][i] = I915_READ(offset);
I915_WRITE(offset, vgpu_vreg(vgpu, offset));
POSTING_READ(offset);
- offset.reg += 4;
}
if (ring_id == RCS) {
+ offset.reg = 64 * 4;
l3_offset.reg = 0xb020;
for (i = 0; i < 32; i++) {
gen9_render_mocs_L3[i] = I915_READ(l3_offset);
@@ -184,26 +175,16 @@ static void restore_mocs(struct intel_vgpu *vgpu, int ring_id)
{
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
i915_reg_t offset, l3_offset;
- u32 regs[] = {
- [RCS] = 0xc800,
- [VCS] = 0xc900,
- [VCS2] = 0xca00,
- [BCS] = 0xcc00,
- [VECS] = 0xcb00,
- };
int i;
- if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
- return;
-
if (!IS_SKYLAKE(dev_priv))
return;
for (i = 0; i < 64; i++) {
+ offset.reg = i * 4;
vgpu_vreg(vgpu, offset) = I915_READ(offset);
I915_WRITE(offset, gen9_render_mocs[ring_id][i]);
POSTING_READ(offset);
- offset.reg += 4;
}
if (ring_id == RCS) {
--
2.9.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/2] drm/i915/gvt: fix compilation
@ 2016-10-21 15:25 ` Arnd Bergmann
0 siblings, 0 replies; 8+ messages in thread
From: Arnd Bergmann @ 2016-10-21 15:25 UTC (permalink / raw)
To: Daniel Vetter, Jani Nikula
Cc: dri-devel, Arnd Bergmann, David Airlie, intel-gfx, linux-kernel,
igvt-g-dev
Two functions in the newly added gvt render code are obviously
broken, as they reference a variable without initialization and
don't reference another variable at all:
drivers/gpu/drm/i915/gvt/render.c: In function ‘intel_gvt_load_render_mmio’:
drivers/gpu/drm/i915/gvt/render.c:148:13: error: ‘offset.reg’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
drivers/gpu/drm/i915/gvt/render.c: In function ‘intel_gvt_restore_render_mmio’:
drivers/gpu/drm/i915/gvt/render.c:185:13: error: ‘offset.reg’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
This is probably not a correct fix, but it gets us a clean build
by removing the unused arrays and initializing the offset variable
to something that potentially might be correct.
Fixes: 178657139307 ("drm/i915/gvt: vGPU context switch")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/gpu/drm/i915/gvt/render.c | 25 +++----------------------
1 file changed, 3 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c
index feebb65ba641..79e112288065 100644
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -147,29 +147,20 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id)
{
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
i915_reg_t offset, l3_offset;
- u32 regs[] = {
- [RCS] = 0xc800,
- [VCS] = 0xc900,
- [VCS2] = 0xca00,
- [BCS] = 0xcc00,
- [VECS] = 0xcb00,
- };
int i;
- if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
- return;
-
if (!IS_SKYLAKE(dev_priv))
return;
for (i = 0; i < 64; i++) {
+ offset.reg = i * 4;
gen9_render_mocs[ring_id][i] = I915_READ(offset);
I915_WRITE(offset, vgpu_vreg(vgpu, offset));
POSTING_READ(offset);
- offset.reg += 4;
}
if (ring_id == RCS) {
+ offset.reg = 64 * 4;
l3_offset.reg = 0xb020;
for (i = 0; i < 32; i++) {
gen9_render_mocs_L3[i] = I915_READ(l3_offset);
@@ -184,26 +175,16 @@ static void restore_mocs(struct intel_vgpu *vgpu, int ring_id)
{
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
i915_reg_t offset, l3_offset;
- u32 regs[] = {
- [RCS] = 0xc800,
- [VCS] = 0xc900,
- [VCS2] = 0xca00,
- [BCS] = 0xcc00,
- [VECS] = 0xcb00,
- };
int i;
- if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
- return;
-
if (!IS_SKYLAKE(dev_priv))
return;
for (i = 0; i < 64; i++) {
+ offset.reg = i * 4;
vgpu_vreg(vgpu, offset) = I915_READ(offset);
I915_WRITE(offset, gen9_render_mocs[ring_id][i]);
POSTING_READ(offset);
- offset.reg += 4;
}
if (ring_id == RCS) {
--
2.9.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915/gvt: add ACPI and 64BIT dependencies
2016-10-21 15:25 [PATCH 1/2] drm/i915/gvt: add ACPI and 64BIT dependencies Arnd Bergmann
2016-10-21 15:25 ` Arnd Bergmann
@ 2016-10-21 16:47 ` Patchwork
2016-10-22 5:06 ` Zhenyu Wang
2 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2016-10-21 16:47 UTC (permalink / raw)
To: Arnd Bergmann; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/gvt: add ACPI and 64BIT dependencies
URL : https://patchwork.freedesktop.org/series/14170/
State : warning
== Summary ==
Series 14170v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/14170/revisions/1/mbox/
Test drv_module_reload_basic:
dmesg-warn -> PASS (fi-skl-6700hq)
dmesg-warn -> PASS (fi-skl-6770hq)
Test gem_exec_suspend:
Subgroup basic-s3:
pass -> DMESG-WARN (fi-skl-6700hq)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass -> DMESG-WARN (fi-skl-6700hq)
Subgroup suspend-read-crc-pipe-b:
pass -> DMESG-WARN (fi-skl-6700hq)
Subgroup suspend-read-crc-pipe-c:
pass -> DMESG-WARN (fi-skl-6700hq)
fi-bdw-5557u total:246 pass:231 dwarn:0 dfail:0 fail:0 skip:15
fi-bsw-n3050 total:246 pass:204 dwarn:0 dfail:0 fail:0 skip:42
fi-bxt-t5700 total:246 pass:216 dwarn:0 dfail:0 fail:0 skip:30
fi-byt-j1900 total:246 pass:215 dwarn:0 dfail:0 fail:0 skip:31
fi-byt-n2820 total:246 pass:211 dwarn:0 dfail:0 fail:0 skip:35
fi-hsw-4770 total:246 pass:224 dwarn:0 dfail:0 fail:0 skip:22
fi-hsw-4770r total:246 pass:224 dwarn:0 dfail:0 fail:0 skip:22
fi-ilk-650 total:246 pass:185 dwarn:0 dfail:0 fail:1 skip:60
fi-ivb-3520m total:246 pass:221 dwarn:0 dfail:0 fail:0 skip:25
fi-ivb-3770 total:246 pass:221 dwarn:0 dfail:0 fail:0 skip:25
fi-kbl-7200u total:246 pass:222 dwarn:0 dfail:0 fail:0 skip:24
fi-skl-6260u total:246 pass:232 dwarn:0 dfail:0 fail:0 skip:14
fi-skl-6700hq total:246 pass:219 dwarn:4 dfail:0 fail:0 skip:23
fi-skl-6700k total:246 pass:222 dwarn:1 dfail:0 fail:0 skip:23
fi-skl-6770hq total:246 pass:232 dwarn:0 dfail:0 fail:0 skip:14
fi-snb-2520m total:246 pass:210 dwarn:0 dfail:0 fail:0 skip:36
fi-snb-2600 total:246 pass:209 dwarn:0 dfail:0 fail:0 skip:37
Results at /archive/results/CI_IGT_test/Patchwork_2791/
45ce7992e2d3211009c035db41745e1f12bbf6e8 drm-intel-nightly: 2016y-10m-21d-14h-52m-49s UTC integration manifest
fe71f2c drm/i915/gvt: fix compilation
7b89fe9 drm/i915/gvt: add ACPI and 64BIT dependencies
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] drm/i915/gvt: add ACPI and 64BIT dependencies
2016-10-21 15:25 [PATCH 1/2] drm/i915/gvt: add ACPI and 64BIT dependencies Arnd Bergmann
@ 2016-10-22 5:06 ` Zhenyu Wang
2016-10-21 16:47 ` ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915/gvt: add ACPI and 64BIT dependencies Patchwork
2016-10-22 5:06 ` Zhenyu Wang
2 siblings, 0 replies; 8+ messages in thread
From: Zhenyu Wang @ 2016-10-22 5:06 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Daniel Vetter, Jani Nikula, Zhi Wang, Zhenyu Wang, David Airlie,
Chris Wilson, Joonas Lahtinen, Tvrtko Ursulin, Andreas Ziegler,
intel-gfx, dri-devel, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 2211 bytes --]
On 2016.10.21 17:25:49 +0200, Arnd Bergmann wrote:
> The newly added gvt code produces lots of serious warnings and errors
> when either built on 32-bit x86, or built with ACPI disabled, e.g.
>
> drivers/gpu/drm/i915/gvt/gtt.c: In function ???read_pte64???:
> drivers/gpu/drm/i915/gvt/gtt.c:277:2: error: left shift count >= width of type [-Werror]
> drivers/gpu/drm/i915/gvt/gtt.c: In function ???gen8_gtt_get_pfn???:
> drivers/gpu/drm/i915/gvt/gtt.c:360:3: error: left shift count >= width of type [-Werror]
> drivers/gpu/drm/i915/gvt/opregion.c: In function ???intel_gvt_init_opregion???:
> drivers/gpu/drm/i915/gvt/opregion.c:183:2: error: implicit declaration of function ???acpi_os_ioremap??? [-Werror=implicit-function-declaration]
>
> This avoids the problems by simply disallowing those configurations
> in Kconfig. I'm sure it's possible to make the code more portable
> and support building GVT without those options, but it might not be
> useful to do so.
>
> Fixes: 4d60c5fd3f87 ("drm/i915/gvt: vGPU PCI configuration space virtualization")
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> If the code is meant to work on 32-bit and non-ACPI kernels, please
> treat this as a bug report and disregard the patch.
> ---
Thanks, Arnd. We have to depend on 64bit now and not require for ACPI,
as we used one acpi function for opregion mem map which is not necessary,
so I queued one 64bit dependence and another to remove acpi dependence for Daniel.
> drivers/gpu/drm/i915/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
> index 6d4194288d11..1b9308284dde 100644
> --- a/drivers/gpu/drm/i915/Kconfig
> +++ b/drivers/gpu/drm/i915/Kconfig
> @@ -84,6 +84,7 @@ config DRM_I915_USERPTR
> config DRM_I915_GVT
> bool "Enable Intel GVT-g graphics virtualization host support"
> depends on DRM_I915
> + depends on 64BIT && ACPI
> default n
> help
> Choose this option if you want to enable Intel GVT-g graphics
> --
> 2.9.0
>
--
Open Source Technology Center, Intel ltd.
$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 163 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] drm/i915/gvt: add ACPI and 64BIT dependencies
@ 2016-10-22 5:06 ` Zhenyu Wang
0 siblings, 0 replies; 8+ messages in thread
From: Zhenyu Wang @ 2016-10-22 5:06 UTC (permalink / raw)
To: Arnd Bergmann
Cc: dri-devel, Tvrtko Ursulin, intel-gfx, Joonas Lahtinen,
linux-kernel, Daniel Vetter, Zhi Wang, Andreas Ziegler
[-- Attachment #1.1: Type: text/plain, Size: 2211 bytes --]
On 2016.10.21 17:25:49 +0200, Arnd Bergmann wrote:
> The newly added gvt code produces lots of serious warnings and errors
> when either built on 32-bit x86, or built with ACPI disabled, e.g.
>
> drivers/gpu/drm/i915/gvt/gtt.c: In function ???read_pte64???:
> drivers/gpu/drm/i915/gvt/gtt.c:277:2: error: left shift count >= width of type [-Werror]
> drivers/gpu/drm/i915/gvt/gtt.c: In function ???gen8_gtt_get_pfn???:
> drivers/gpu/drm/i915/gvt/gtt.c:360:3: error: left shift count >= width of type [-Werror]
> drivers/gpu/drm/i915/gvt/opregion.c: In function ???intel_gvt_init_opregion???:
> drivers/gpu/drm/i915/gvt/opregion.c:183:2: error: implicit declaration of function ???acpi_os_ioremap??? [-Werror=implicit-function-declaration]
>
> This avoids the problems by simply disallowing those configurations
> in Kconfig. I'm sure it's possible to make the code more portable
> and support building GVT without those options, but it might not be
> useful to do so.
>
> Fixes: 4d60c5fd3f87 ("drm/i915/gvt: vGPU PCI configuration space virtualization")
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> If the code is meant to work on 32-bit and non-ACPI kernels, please
> treat this as a bug report and disregard the patch.
> ---
Thanks, Arnd. We have to depend on 64bit now and not require for ACPI,
as we used one acpi function for opregion mem map which is not necessary,
so I queued one 64bit dependence and another to remove acpi dependence for Daniel.
> drivers/gpu/drm/i915/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
> index 6d4194288d11..1b9308284dde 100644
> --- a/drivers/gpu/drm/i915/Kconfig
> +++ b/drivers/gpu/drm/i915/Kconfig
> @@ -84,6 +84,7 @@ config DRM_I915_USERPTR
> config DRM_I915_GVT
> bool "Enable Intel GVT-g graphics virtualization host support"
> depends on DRM_I915
> + depends on 64BIT && ACPI
> default n
> help
> Choose this option if you want to enable Intel GVT-g graphics
> --
> 2.9.0
>
--
Open Source Technology Center, Intel ltd.
$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 163 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] drm/i915/gvt: fix compilation
2016-10-21 15:25 ` Arnd Bergmann
@ 2016-10-22 5:09 ` Zhenyu Wang
-1 siblings, 0 replies; 8+ messages in thread
From: Zhenyu Wang @ 2016-10-22 5:09 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Daniel Vetter, Jani Nikula, Zhi Wang, Zhenyu Wang, David Airlie,
Chris Wilson, igvt-g-dev, intel-gfx, dri-devel, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 3980 bytes --]
On 2016.10.21 17:25:50 +0200, Arnd Bergmann wrote:
> Two functions in the newly added gvt render code are obviously
> broken, as they reference a variable without initialization and
> don't reference another variable at all:
>
> drivers/gpu/drm/i915/gvt/render.c: In function ???intel_gvt_load_render_mmio???:
> drivers/gpu/drm/i915/gvt/render.c:148:13: error: ???offset.reg??? may be used uninitialized in this function [-Werror=maybe-uninitialized]
> drivers/gpu/drm/i915/gvt/render.c: In function ???intel_gvt_restore_render_mmio???:
> drivers/gpu/drm/i915/gvt/render.c:185:13: error: ???offset.reg??? may be used uninitialized in this function [-Werror=maybe-uninitialized]
>
> This is probably not a correct fix, but it gets us a clean build
> by removing the unused arrays and initializing the offset variable
> to something that potentially might be correct.
>
> Fixes: 178657139307 ("drm/i915/gvt: vGPU context switch")
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
I think the correct fix is like
diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c
index feebb65..cc23c3f 100644
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -162,6 +162,7 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id)
if (!IS_SKYLAKE(dev_priv))
return;
+ offset.reg = regs[ring_id];
for (i = 0; i < 64; i++) {
gen9_render_mocs[ring_id][i] = I915_READ(offset);
I915_WRITE(offset, vgpu_vreg(vgpu, offset));
@@ -199,6 +200,7 @@ static void restore_mocs(struct intel_vgpu *vgpu, int ring_id)
if (!IS_SKYLAKE(dev_priv))
return;
+ offset.reg = regs[ring_id];
for (i = 0; i < 64; i++) {
vgpu_vreg(vgpu, offset) = I915_READ(offset);
I915_WRITE(offset, gen9_render_mocs[ring_id][i]);
Thanks for pointing this out, it's a mistake during our code preparation for upstream.
I'll queue this up.
> drivers/gpu/drm/i915/gvt/render.c | 25 +++----------------------
> 1 file changed, 3 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c
> index feebb65ba641..79e112288065 100644
> --- a/drivers/gpu/drm/i915/gvt/render.c
> +++ b/drivers/gpu/drm/i915/gvt/render.c
> @@ -147,29 +147,20 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id)
> {
> struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
> i915_reg_t offset, l3_offset;
> - u32 regs[] = {
> - [RCS] = 0xc800,
> - [VCS] = 0xc900,
> - [VCS2] = 0xca00,
> - [BCS] = 0xcc00,
> - [VECS] = 0xcb00,
> - };
> int i;
>
> - if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
> - return;
> -
> if (!IS_SKYLAKE(dev_priv))
> return;
>
> for (i = 0; i < 64; i++) {
> + offset.reg = i * 4;
> gen9_render_mocs[ring_id][i] = I915_READ(offset);
> I915_WRITE(offset, vgpu_vreg(vgpu, offset));
> POSTING_READ(offset);
> - offset.reg += 4;
> }
>
> if (ring_id == RCS) {
> + offset.reg = 64 * 4;
> l3_offset.reg = 0xb020;
> for (i = 0; i < 32; i++) {
> gen9_render_mocs_L3[i] = I915_READ(l3_offset);
> @@ -184,26 +175,16 @@ static void restore_mocs(struct intel_vgpu *vgpu, int ring_id)
> {
> struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
> i915_reg_t offset, l3_offset;
> - u32 regs[] = {
> - [RCS] = 0xc800,
> - [VCS] = 0xc900,
> - [VCS2] = 0xca00,
> - [BCS] = 0xcc00,
> - [VECS] = 0xcb00,
> - };
> int i;
>
> - if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
> - return;
> -
> if (!IS_SKYLAKE(dev_priv))
> return;
>
> for (i = 0; i < 64; i++) {
> + offset.reg = i * 4;
> vgpu_vreg(vgpu, offset) = I915_READ(offset);
> I915_WRITE(offset, gen9_render_mocs[ring_id][i]);
> POSTING_READ(offset);
> - offset.reg += 4;
> }
>
> if (ring_id == RCS) {
> --
> 2.9.0
>
--
Open Source Technology Center, Intel ltd.
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] drm/i915/gvt: fix compilation
@ 2016-10-22 5:09 ` Zhenyu Wang
0 siblings, 0 replies; 8+ messages in thread
From: Zhenyu Wang @ 2016-10-22 5:09 UTC (permalink / raw)
To: Arnd Bergmann
Cc: dri-devel, intel-gfx, linux-kernel, Daniel Vetter, Zhi Wang, igvt-g-dev
[-- Attachment #1.1: Type: text/plain, Size: 3980 bytes --]
On 2016.10.21 17:25:50 +0200, Arnd Bergmann wrote:
> Two functions in the newly added gvt render code are obviously
> broken, as they reference a variable without initialization and
> don't reference another variable at all:
>
> drivers/gpu/drm/i915/gvt/render.c: In function ???intel_gvt_load_render_mmio???:
> drivers/gpu/drm/i915/gvt/render.c:148:13: error: ???offset.reg??? may be used uninitialized in this function [-Werror=maybe-uninitialized]
> drivers/gpu/drm/i915/gvt/render.c: In function ???intel_gvt_restore_render_mmio???:
> drivers/gpu/drm/i915/gvt/render.c:185:13: error: ???offset.reg??? may be used uninitialized in this function [-Werror=maybe-uninitialized]
>
> This is probably not a correct fix, but it gets us a clean build
> by removing the unused arrays and initializing the offset variable
> to something that potentially might be correct.
>
> Fixes: 178657139307 ("drm/i915/gvt: vGPU context switch")
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
I think the correct fix is like
diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c
index feebb65..cc23c3f 100644
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -162,6 +162,7 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id)
if (!IS_SKYLAKE(dev_priv))
return;
+ offset.reg = regs[ring_id];
for (i = 0; i < 64; i++) {
gen9_render_mocs[ring_id][i] = I915_READ(offset);
I915_WRITE(offset, vgpu_vreg(vgpu, offset));
@@ -199,6 +200,7 @@ static void restore_mocs(struct intel_vgpu *vgpu, int ring_id)
if (!IS_SKYLAKE(dev_priv))
return;
+ offset.reg = regs[ring_id];
for (i = 0; i < 64; i++) {
vgpu_vreg(vgpu, offset) = I915_READ(offset);
I915_WRITE(offset, gen9_render_mocs[ring_id][i]);
Thanks for pointing this out, it's a mistake during our code preparation for upstream.
I'll queue this up.
> drivers/gpu/drm/i915/gvt/render.c | 25 +++----------------------
> 1 file changed, 3 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c
> index feebb65ba641..79e112288065 100644
> --- a/drivers/gpu/drm/i915/gvt/render.c
> +++ b/drivers/gpu/drm/i915/gvt/render.c
> @@ -147,29 +147,20 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id)
> {
> struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
> i915_reg_t offset, l3_offset;
> - u32 regs[] = {
> - [RCS] = 0xc800,
> - [VCS] = 0xc900,
> - [VCS2] = 0xca00,
> - [BCS] = 0xcc00,
> - [VECS] = 0xcb00,
> - };
> int i;
>
> - if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
> - return;
> -
> if (!IS_SKYLAKE(dev_priv))
> return;
>
> for (i = 0; i < 64; i++) {
> + offset.reg = i * 4;
> gen9_render_mocs[ring_id][i] = I915_READ(offset);
> I915_WRITE(offset, vgpu_vreg(vgpu, offset));
> POSTING_READ(offset);
> - offset.reg += 4;
> }
>
> if (ring_id == RCS) {
> + offset.reg = 64 * 4;
> l3_offset.reg = 0xb020;
> for (i = 0; i < 32; i++) {
> gen9_render_mocs_L3[i] = I915_READ(l3_offset);
> @@ -184,26 +175,16 @@ static void restore_mocs(struct intel_vgpu *vgpu, int ring_id)
> {
> struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
> i915_reg_t offset, l3_offset;
> - u32 regs[] = {
> - [RCS] = 0xc800,
> - [VCS] = 0xc900,
> - [VCS2] = 0xca00,
> - [BCS] = 0xcc00,
> - [VECS] = 0xcb00,
> - };
> int i;
>
> - if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
> - return;
> -
> if (!IS_SKYLAKE(dev_priv))
> return;
>
> for (i = 0; i < 64; i++) {
> + offset.reg = i * 4;
> vgpu_vreg(vgpu, offset) = I915_READ(offset);
> I915_WRITE(offset, gen9_render_mocs[ring_id][i]);
> POSTING_READ(offset);
> - offset.reg += 4;
> }
>
> if (ring_id == RCS) {
> --
> 2.9.0
>
--
Open Source Technology Center, Intel ltd.
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^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2016-10-22 5:14 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-10-21 15:25 [PATCH 1/2] drm/i915/gvt: add ACPI and 64BIT dependencies Arnd Bergmann
2016-10-21 15:25 ` [PATCH 2/2] drm/i915/gvt: fix compilation Arnd Bergmann
2016-10-21 15:25 ` Arnd Bergmann
2016-10-22 5:09 ` Zhenyu Wang
2016-10-22 5:09 ` Zhenyu Wang
2016-10-21 16:47 ` ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915/gvt: add ACPI and 64BIT dependencies Patchwork
2016-10-22 5:06 ` [PATCH 1/2] " Zhenyu Wang
2016-10-22 5:06 ` Zhenyu Wang
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