* [PATCH 0/2] pinctrl: sh-pfc: Fixups for bias handeling
@ 2016-11-03 15:34 Niklas Söderlund
2016-11-03 15:34 ` [PATCH 1/2] pinctrl: sh-pfc: Do not unconditionally support PIN_CONFIG_BIAS_DISABLE Niklas Söderlund
2016-11-03 15:34 ` [PATCH 2/2] pinctrl: sh-pfc: r8a7795: Use lookup function for bias data Niklas Söderlund
0 siblings, 2 replies; 13+ messages in thread
From: Niklas Söderlund @ 2016-11-03 15:34 UTC (permalink / raw)
To: Geert Uytterhoeven, Laurent Pinchart
Cc: Linus Walleij, linux-renesas-soc, linux-gpio, Niklas Söderlund
Hi Geert and Laurent,
This series fixes two issues I encounter for bias handling in the PFC
while preparing my drive strength patch set.
I do believe we should try to get the r8a7795 specific fix in to v4.9,
do you agree (if the fix itself is acceptable ofc)?
Niklas Söderlund (2):
pinctrl: sh-pfc: Do not unconditionally support
PIN_CONFIG_BIAS_DISABLE
pinctrl: sh-pfc: r8a7795: Use lookup function for bias data
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 350 ++++++++++++++++++-----------------
drivers/pinctrl/sh-pfc/pinctrl.c | 3 +-
2 files changed, 182 insertions(+), 171 deletions(-)
--
2.10.2
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 1/2] pinctrl: sh-pfc: Do not unconditionally support PIN_CONFIG_BIAS_DISABLE
2016-11-03 15:34 [PATCH 0/2] pinctrl: sh-pfc: Fixups for bias handeling Niklas Söderlund
@ 2016-11-03 15:34 ` Niklas Söderlund
2016-11-03 16:55 ` Laurent Pinchart
2016-11-07 10:33 ` Geert Uytterhoeven
2016-11-03 15:34 ` [PATCH 2/2] pinctrl: sh-pfc: r8a7795: Use lookup function for bias data Niklas Söderlund
1 sibling, 2 replies; 13+ messages in thread
From: Niklas Söderlund @ 2016-11-03 15:34 UTC (permalink / raw)
To: Geert Uytterhoeven, Laurent Pinchart
Cc: Linus Walleij, linux-renesas-soc, linux-gpio, Niklas Söderlund
Always stating PIN_CONFIG_BIAS_DISABLE is supported gives untrue output
when examining /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins if
the operation get_bias() are implemented but the pin are not handled by
the get_bias() implementation. In that case the output will state that
"input bias disabled" indicating that this pin have bias control
support.
Make support for PIN_CONFIG_BIAS_DISABLE depend on that the pin either
support SH_PFC_PIN_CFG_PULL_UP or SH_PFC_PIN_CFG_PULL_DOWN. This also
solves the issue where SoC specific implementations print error messages
if there particular implementation of {set,get}_bias() is called with a
pin it do not know about.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
---
drivers/pinctrl/sh-pfc/pinctrl.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index c577258..fcacfa7 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -570,7 +570,8 @@ static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
- return true;
+ return pin->configs &
+ (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
case PIN_CONFIG_BIAS_PULL_UP:
return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
--
2.10.2
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/2] pinctrl: sh-pfc: r8a7795: Use lookup function for bias data
2016-11-03 15:34 [PATCH 0/2] pinctrl: sh-pfc: Fixups for bias handeling Niklas Söderlund
2016-11-03 15:34 ` [PATCH 1/2] pinctrl: sh-pfc: Do not unconditionally support PIN_CONFIG_BIAS_DISABLE Niklas Söderlund
@ 2016-11-03 15:34 ` Niklas Söderlund
2016-11-03 17:10 ` Laurent Pinchart
1 sibling, 1 reply; 13+ messages in thread
From: Niklas Söderlund @ 2016-11-03 15:34 UTC (permalink / raw)
To: Geert Uytterhoeven, Laurent Pinchart
Cc: Linus Walleij, linux-renesas-soc, linux-gpio, Niklas Söderlund
There is a bug in the r8a7795 bias code where a WARN() is trigged
anytime a pin from PUEN0/PUD0is accessed.
# cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins
WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364 r8a7795_pinmux_get_bias+0xbc/0xc8
[..]
Call trace:
[<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8
[<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270
[<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30
[<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188
[<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98
[<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128
[<ffff0000081fe3bc>] seq_read+0x16c/0x420
[<ffff00000831a110>] full_proxy_read+0x58/0x88
[<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8
[<ffff0000081d8874>] vfs_read+0x84/0x148
[<ffff0000081d9d64>] SyS_read+0x44/0xa0
[<ffff000008082f4c>] __sys_trace_return+0x0/0x4
This is due to the WARN() check if the reg field of the pullups struct
is zero, and this should be 0 for pins controlled by the PUEN0/PUD0
registers. Change the layout of the pullups struct to embed the pin
number inside the struct and loop over it to fetch the correct
information or WARN() if no pin is found.
Fixes: 560655247b627ac7 ("pinctrl: sh-pfc: r8a7795: Add bias pinconf support")
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
---
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 350 ++++++++++++++++++-----------------
1 file changed, 180 insertions(+), 170 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 2e8cc2a..69e1f31 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -5189,171 +5189,187 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
#define PU6 0x18
static const struct {
+ u16 pin;
u16 reg : 11;
u16 bit : 5;
} pullups[] = {
- [RCAR_GP_PIN(2, 11)] = { PU0, 31 }, /* AVB_PHY_INT */
- [RCAR_GP_PIN(2, 10)] = { PU0, 30 }, /* AVB_MAGIC */
- [RCAR_GP_PIN(2, 9)] = { PU0, 29 }, /* AVB_MDC */
-
- [RCAR_GP_PIN(1, 19)] = { PU1, 31 }, /* A19 */
- [RCAR_GP_PIN(1, 18)] = { PU1, 30 }, /* A18 */
- [RCAR_GP_PIN(1, 17)] = { PU1, 29 }, /* A17 */
- [RCAR_GP_PIN(1, 16)] = { PU1, 28 }, /* A16 */
- [RCAR_GP_PIN(1, 15)] = { PU1, 27 }, /* A15 */
- [RCAR_GP_PIN(1, 14)] = { PU1, 26 }, /* A14 */
- [RCAR_GP_PIN(1, 13)] = { PU1, 25 }, /* A13 */
- [RCAR_GP_PIN(1, 12)] = { PU1, 24 }, /* A12 */
- [RCAR_GP_PIN(1, 11)] = { PU1, 23 }, /* A11 */
- [RCAR_GP_PIN(1, 10)] = { PU1, 22 }, /* A10 */
- [RCAR_GP_PIN(1, 9)] = { PU1, 21 }, /* A9 */
- [RCAR_GP_PIN(1, 8)] = { PU1, 20 }, /* A8 */
- [RCAR_GP_PIN(1, 7)] = { PU1, 19 }, /* A7 */
- [RCAR_GP_PIN(1, 6)] = { PU1, 18 }, /* A6 */
- [RCAR_GP_PIN(1, 5)] = { PU1, 17 }, /* A5 */
- [RCAR_GP_PIN(1, 4)] = { PU1, 16 }, /* A4 */
- [RCAR_GP_PIN(1, 3)] = { PU1, 15 }, /* A3 */
- [RCAR_GP_PIN(1, 2)] = { PU1, 14 }, /* A2 */
- [RCAR_GP_PIN(1, 1)] = { PU1, 13 }, /* A1 */
- [RCAR_GP_PIN(1, 0)] = { PU1, 12 }, /* A0 */
- [RCAR_GP_PIN(2, 8)] = { PU1, 11 }, /* PWM2_A */
- [RCAR_GP_PIN(2, 7)] = { PU1, 10 }, /* PWM1_A */
- [RCAR_GP_PIN(2, 6)] = { PU1, 9 }, /* PWM0 */
- [RCAR_GP_PIN(2, 5)] = { PU1, 8 }, /* IRQ5 */
- [RCAR_GP_PIN(2, 4)] = { PU1, 7 }, /* IRQ4 */
- [RCAR_GP_PIN(2, 3)] = { PU1, 6 }, /* IRQ3 */
- [RCAR_GP_PIN(2, 2)] = { PU1, 5 }, /* IRQ2 */
- [RCAR_GP_PIN(2, 1)] = { PU1, 4 }, /* IRQ1 */
- [RCAR_GP_PIN(2, 0)] = { PU1, 3 }, /* IRQ0 */
- [RCAR_GP_PIN(2, 14)] = { PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
- [RCAR_GP_PIN(2, 13)] = { PU1, 1 }, /* AVB_AVTP_MATCH_A */
- [RCAR_GP_PIN(2, 12)] = { PU1, 0 }, /* AVB_LINK */
-
- [RCAR_GP_PIN(7, 3)] = { PU2, 29 }, /* HDMI1_CEC */
- [RCAR_GP_PIN(7, 2)] = { PU2, 28 }, /* HDMI0_CEC */
- [RCAR_GP_PIN(7, 1)] = { PU2, 27 }, /* AVS2 */
- [RCAR_GP_PIN(7, 0)] = { PU2, 26 }, /* AVS1 */
- [RCAR_GP_PIN(0, 15)] = { PU2, 25 }, /* D15 */
- [RCAR_GP_PIN(0, 14)] = { PU2, 24 }, /* D14 */
- [RCAR_GP_PIN(0, 13)] = { PU2, 23 }, /* D13 */
- [RCAR_GP_PIN(0, 12)] = { PU2, 22 }, /* D12 */
- [RCAR_GP_PIN(0, 11)] = { PU2, 21 }, /* D11 */
- [RCAR_GP_PIN(0, 10)] = { PU2, 20 }, /* D10 */
- [RCAR_GP_PIN(0, 9)] = { PU2, 19 }, /* D9 */
- [RCAR_GP_PIN(0, 8)] = { PU2, 18 }, /* D8 */
- [RCAR_GP_PIN(0, 7)] = { PU2, 17 }, /* D7 */
- [RCAR_GP_PIN(0, 6)] = { PU2, 16 }, /* D6 */
- [RCAR_GP_PIN(0, 5)] = { PU2, 15 }, /* D5 */
- [RCAR_GP_PIN(0, 4)] = { PU2, 14 }, /* D4 */
- [RCAR_GP_PIN(0, 3)] = { PU2, 13 }, /* D3 */
- [RCAR_GP_PIN(0, 2)] = { PU2, 12 }, /* D2 */
- [RCAR_GP_PIN(0, 1)] = { PU2, 11 }, /* D1 */
- [RCAR_GP_PIN(0, 0)] = { PU2, 10 }, /* D0 */
- [RCAR_GP_PIN(1, 27)] = { PU2, 8 }, /* EX_WAIT0_A */
- [RCAR_GP_PIN(1, 26)] = { PU2, 7 }, /* WE1_N */
- [RCAR_GP_PIN(1, 25)] = { PU2, 6 }, /* WE0_N */
- [RCAR_GP_PIN(1, 24)] = { PU2, 5 }, /* RD_WR_N */
- [RCAR_GP_PIN(1, 23)] = { PU2, 4 }, /* RD_N */
- [RCAR_GP_PIN(1, 22)] = { PU2, 3 }, /* BS_N */
- [RCAR_GP_PIN(1, 21)] = { PU2, 2 }, /* CS1_N_A26 */
- [RCAR_GP_PIN(1, 20)] = { PU2, 1 }, /* CS0_N */
-
- [RCAR_GP_PIN(4, 9)] = { PU3, 31 }, /* SD3_DAT0 */
- [RCAR_GP_PIN(4, 8)] = { PU3, 30 }, /* SD3_CMD */
- [RCAR_GP_PIN(4, 7)] = { PU3, 29 }, /* SD3_CLK */
- [RCAR_GP_PIN(4, 6)] = { PU3, 28 }, /* SD2_DS */
- [RCAR_GP_PIN(4, 5)] = { PU3, 27 }, /* SD2_DAT3 */
- [RCAR_GP_PIN(4, 4)] = { PU3, 26 }, /* SD2_DAT2 */
- [RCAR_GP_PIN(4, 3)] = { PU3, 25 }, /* SD2_DAT1 */
- [RCAR_GP_PIN(4, 2)] = { PU3, 24 }, /* SD2_DAT0 */
- [RCAR_GP_PIN(4, 1)] = { PU3, 23 }, /* SD2_CMD */
- [RCAR_GP_PIN(4, 0)] = { PU3, 22 }, /* SD2_CLK */
- [RCAR_GP_PIN(3, 11)] = { PU3, 21 }, /* SD1_DAT3 */
- [RCAR_GP_PIN(3, 10)] = { PU3, 20 }, /* SD1_DAT2 */
- [RCAR_GP_PIN(3, 9)] = { PU3, 19 }, /* SD1_DAT1 */
- [RCAR_GP_PIN(3, 8)] = { PU3, 18 }, /* SD1_DAT0 */
- [RCAR_GP_PIN(3, 7)] = { PU3, 17 }, /* SD1_CMD */
- [RCAR_GP_PIN(3, 6)] = { PU3, 16 }, /* SD1_CLK */
- [RCAR_GP_PIN(3, 5)] = { PU3, 15 }, /* SD0_DAT3 */
- [RCAR_GP_PIN(3, 4)] = { PU3, 14 }, /* SD0_DAT2 */
- [RCAR_GP_PIN(3, 3)] = { PU3, 13 }, /* SD0_DAT1 */
- [RCAR_GP_PIN(3, 2)] = { PU3, 12 }, /* SD0_DAT0 */
- [RCAR_GP_PIN(3, 1)] = { PU3, 11 }, /* SD0_CMD */
- [RCAR_GP_PIN(3, 0)] = { PU3, 10 }, /* SD0_CLK */
-
- [RCAR_GP_PIN(5, 19)] = { PU4, 31 }, /* MSIOF0_SS1 */
- [RCAR_GP_PIN(5, 18)] = { PU4, 30 }, /* MSIOF0_SYNC */
- [RCAR_GP_PIN(5, 17)] = { PU4, 29 }, /* MSIOF0_SCK */
- [RCAR_GP_PIN(5, 16)] = { PU4, 28 }, /* HRTS0_N */
- [RCAR_GP_PIN(5, 15)] = { PU4, 27 }, /* HCTS0_N */
- [RCAR_GP_PIN(5, 14)] = { PU4, 26 }, /* HTX0 */
- [RCAR_GP_PIN(5, 13)] = { PU4, 25 }, /* HRX0 */
- [RCAR_GP_PIN(5, 12)] = { PU4, 24 }, /* HSCK0 */
- [RCAR_GP_PIN(5, 11)] = { PU4, 23 }, /* RX2_A */
- [RCAR_GP_PIN(5, 10)] = { PU4, 22 }, /* TX2_A */
- [RCAR_GP_PIN(5, 9)] = { PU4, 21 }, /* SCK2 */
- [RCAR_GP_PIN(5, 8)] = { PU4, 20 }, /* RTS1_N_TANS */
- [RCAR_GP_PIN(5, 7)] = { PU4, 19 }, /* CTS1_N */
- [RCAR_GP_PIN(5, 6)] = { PU4, 18 }, /* TX1_A */
- [RCAR_GP_PIN(5, 5)] = { PU4, 17 }, /* RX1_A */
- [RCAR_GP_PIN(5, 4)] = { PU4, 16 }, /* RTS0_N_TANS */
- [RCAR_GP_PIN(5, 3)] = { PU4, 15 }, /* CTS0_N */
- [RCAR_GP_PIN(5, 2)] = { PU4, 14 }, /* TX0 */
- [RCAR_GP_PIN(5, 1)] = { PU4, 13 }, /* RX0 */
- [RCAR_GP_PIN(5, 0)] = { PU4, 12 }, /* SCK0 */
- [RCAR_GP_PIN(3, 15)] = { PU4, 11 }, /* SD1_WP */
- [RCAR_GP_PIN(3, 14)] = { PU4, 10 }, /* SD1_CD */
- [RCAR_GP_PIN(3, 13)] = { PU4, 9 }, /* SD0_WP */
- [RCAR_GP_PIN(3, 12)] = { PU4, 8 }, /* SD0_CD */
- [RCAR_GP_PIN(4, 17)] = { PU4, 7 }, /* SD3_DS */
- [RCAR_GP_PIN(4, 16)] = { PU4, 6 }, /* SD3_DAT7 */
- [RCAR_GP_PIN(4, 15)] = { PU4, 5 }, /* SD3_DAT6 */
- [RCAR_GP_PIN(4, 14)] = { PU4, 4 }, /* SD3_DAT5 */
- [RCAR_GP_PIN(4, 13)] = { PU4, 3 }, /* SD3_DAT4 */
- [RCAR_GP_PIN(4, 12)] = { PU4, 2 }, /* SD3_DAT3 */
- [RCAR_GP_PIN(4, 11)] = { PU4, 1 }, /* SD3_DAT2 */
- [RCAR_GP_PIN(4, 10)] = { PU4, 0 }, /* SD3_DAT1 */
-
- [RCAR_GP_PIN(6, 24)] = { PU5, 31 }, /* USB0_PWEN */
- [RCAR_GP_PIN(6, 23)] = { PU5, 30 }, /* AUDIO_CLKB_B */
- [RCAR_GP_PIN(6, 22)] = { PU5, 29 }, /* AUDIO_CLKA_A */
- [RCAR_GP_PIN(6, 21)] = { PU5, 28 }, /* SSI_SDATA9_A */
- [RCAR_GP_PIN(6, 20)] = { PU5, 27 }, /* SSI_SDATA8 */
- [RCAR_GP_PIN(6, 19)] = { PU5, 26 }, /* SSI_SDATA7 */
- [RCAR_GP_PIN(6, 18)] = { PU5, 25 }, /* SSI_WS78 */
- [RCAR_GP_PIN(6, 17)] = { PU5, 24 }, /* SSI_SCK78 */
- [RCAR_GP_PIN(6, 16)] = { PU5, 23 }, /* SSI_SDATA6 */
- [RCAR_GP_PIN(6, 15)] = { PU5, 22 }, /* SSI_WS6 */
- [RCAR_GP_PIN(6, 14)] = { PU5, 21 }, /* SSI_SCK6 */
- [RCAR_GP_PIN(6, 13)] = { PU5, 20 }, /* SSI_SDATA5 */
- [RCAR_GP_PIN(6, 12)] = { PU5, 19 }, /* SSI_WS5 */
- [RCAR_GP_PIN(6, 11)] = { PU5, 18 }, /* SSI_SCK5 */
- [RCAR_GP_PIN(6, 10)] = { PU5, 17 }, /* SSI_SDATA4 */
- [RCAR_GP_PIN(6, 9)] = { PU5, 16 }, /* SSI_WS4 */
- [RCAR_GP_PIN(6, 8)] = { PU5, 15 }, /* SSI_SCK4 */
- [RCAR_GP_PIN(6, 7)] = { PU5, 14 }, /* SSI_SDATA3 */
- [RCAR_GP_PIN(6, 6)] = { PU5, 13 }, /* SSI_WS34 */
- [RCAR_GP_PIN(6, 5)] = { PU5, 12 }, /* SSI_SCK34 */
- [RCAR_GP_PIN(6, 4)] = { PU5, 11 }, /* SSI_SDATA2_A */
- [RCAR_GP_PIN(6, 3)] = { PU5, 10 }, /* SSI_SDATA1_A */
- [RCAR_GP_PIN(6, 2)] = { PU5, 9 }, /* SSI_SDATA0 */
- [RCAR_GP_PIN(6, 1)] = { PU5, 8 }, /* SSI_WS01239 */
- [RCAR_GP_PIN(6, 0)] = { PU5, 7 }, /* SSI_SCK01239 */
- [RCAR_GP_PIN(5, 25)] = { PU5, 5 }, /* MLB_DAT */
- [RCAR_GP_PIN(5, 24)] = { PU5, 4 }, /* MLB_SIG */
- [RCAR_GP_PIN(5, 23)] = { PU5, 3 }, /* MLB_CLK */
- [RCAR_GP_PIN(5, 22)] = { PU5, 2 }, /* MSIOF0_RXD */
- [RCAR_GP_PIN(5, 21)] = { PU5, 1 }, /* MSIOF0_SS2 */
- [RCAR_GP_PIN(5, 20)] = { PU5, 0 }, /* MSIOF0_TXD */
-
- [RCAR_GP_PIN(6, 31)] = { PU6, 6 }, /* USB31_OVC */
- [RCAR_GP_PIN(6, 30)] = { PU6, 5 }, /* USB31_PWEN */
- [RCAR_GP_PIN(6, 29)] = { PU6, 4 }, /* USB30_OVC */
- [RCAR_GP_PIN(6, 28)] = { PU6, 3 }, /* USB30_PWEN */
- [RCAR_GP_PIN(6, 27)] = { PU6, 2 }, /* USB1_OVC */
- [RCAR_GP_PIN(6, 26)] = { PU6, 1 }, /* USB1_PWEN */
- [RCAR_GP_PIN(6, 25)] = { PU6, 0 }, /* USB0_OVC */
-};
+ { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
+ { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
+ { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
+
+ { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
+ { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
+ { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
+ { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
+ { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
+ { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
+ { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
+ { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
+ { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
+ { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
+ { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
+ { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
+ { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
+ { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
+ { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
+ { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
+ { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
+ { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
+ { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
+ { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
+ { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
+ { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
+ { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
+ { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
+ { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
+ { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
+ { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
+ { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
+ { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
+ { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
+ { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
+ { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
+
+ { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */
+ { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
+ { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
+ { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
+ { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
+ { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
+ { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
+ { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
+ { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
+ { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
+ { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
+ { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
+ { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
+ { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
+ { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
+ { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
+ { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
+ { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
+ { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
+ { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
+ { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
+ { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
+ { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
+ { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
+ { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
+ { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
+ { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */
+ { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
+
+ { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
+ { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
+ { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
+ { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
+ { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
+ { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
+ { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
+ { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
+ { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
+ { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
+ { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
+ { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
+ { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
+ { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
+ { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
+ { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
+ { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
+ { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
+ { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
+ { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
+ { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
+ { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
+
+ { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
+ { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
+ { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
+ { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
+ { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
+ { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
+ { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
+ { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
+ { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
+ { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
+ { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
+ { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
+ { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
+ { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
+ { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
+ { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
+ { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
+ { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
+ { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
+ { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
+ { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
+ { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
+ { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
+ { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
+ { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
+ { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
+ { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
+ { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
+ { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
+ { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
+ { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
+ { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
+
+ { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
+ { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
+ { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
+ { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
+ { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
+ { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
+ { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
+ { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
+ { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
+ { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
+ { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
+ { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
+ { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
+ { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
+ { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
+ { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
+ { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
+ { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
+ { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */
+ { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */
+ { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
+ { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
+ { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
+ { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
+ { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
+ { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
+ { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
+ { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
+ { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
+ { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
+ { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
+
+ { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB31_OVC */
+ { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB31_PWEN */
+ { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
+ { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
+ { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
+ { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
+ { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
+};
+
+static int r8a7795_pin_to_bias_data(unsigned int pin, u32 *reg, u32 *bit)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(pullups); i++) {
+ if (pullups[i].pin == pin) {
+ *reg = pullups[i].reg;
+ *bit = BIT(pullups[i].bit);
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
unsigned int pin)
@@ -5361,12 +5377,9 @@ static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
u32 reg;
u32 bit;
- if (WARN_ON_ONCE(!pullups[pin].reg))
+ if (WARN_ON_ONCE(r8a7795_pin_to_bias_data(pin, ®, &bit)))
return PIN_CONFIG_BIAS_DISABLE;
- reg = pullups[pin].reg;
- bit = BIT(pullups[pin].bit);
-
if (sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit) {
if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
return PIN_CONFIG_BIAS_PULL_UP;
@@ -5383,12 +5396,9 @@ static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
u32 reg;
u32 bit;
- if (WARN_ON_ONCE(!pullups[pin].reg))
+ if (WARN_ON_ONCE(r8a7795_pin_to_bias_data(pin, ®, &bit)))
return;
- reg = pullups[pin].reg;
- bit = BIT(pullups[pin].bit);
-
enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
if (bias != PIN_CONFIG_BIAS_DISABLE)
enable |= bit;
--
2.10.2
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] pinctrl: sh-pfc: Do not unconditionally support PIN_CONFIG_BIAS_DISABLE
2016-11-03 15:34 ` [PATCH 1/2] pinctrl: sh-pfc: Do not unconditionally support PIN_CONFIG_BIAS_DISABLE Niklas Söderlund
@ 2016-11-03 16:55 ` Laurent Pinchart
2016-11-07 10:33 ` Geert Uytterhoeven
1 sibling, 0 replies; 13+ messages in thread
From: Laurent Pinchart @ 2016-11-03 16:55 UTC (permalink / raw)
To: Niklas Söderlund
Cc: Geert Uytterhoeven, Linus Walleij, linux-renesas-soc, linux-gpio
Hi Niklas,
Thank you for the patch.
On Thursday 03 Nov 2016 16:34:20 Niklas Söderlund wrote:
> Always stating PIN_CONFIG_BIAS_DISABLE is supported gives untrue output
> when examining /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins if
> the operation get_bias() are implemented but the pin are not handled by
> the get_bias() implementation. In that case the output will state that
> "input bias disabled" indicating that this pin have bias control
> support.
>
> Make support for PIN_CONFIG_BIAS_DISABLE depend on that the pin either
> support SH_PFC_PIN_CFG_PULL_UP or SH_PFC_PIN_CFG_PULL_DOWN. This also
> solves the issue where SoC specific implementations print error messages
> if there particular implementation of {set,get}_bias() is called with a
> pin it do not know about.
>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> drivers/pinctrl/sh-pfc/pinctrl.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c
> b/drivers/pinctrl/sh-pfc/pinctrl.c index c577258..fcacfa7 100644
> --- a/drivers/pinctrl/sh-pfc/pinctrl.c
> +++ b/drivers/pinctrl/sh-pfc/pinctrl.c
> @@ -570,7 +570,8 @@ static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc,
> unsigned int _pin,
>
> switch (param) {
> case PIN_CONFIG_BIAS_DISABLE:
> - return true;
> + return pin->configs &
> + (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
>
> case PIN_CONFIG_BIAS_PULL_UP:
> return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] pinctrl: sh-pfc: r8a7795: Use lookup function for bias data
2016-11-03 15:34 ` [PATCH 2/2] pinctrl: sh-pfc: r8a7795: Use lookup function for bias data Niklas Söderlund
@ 2016-11-03 17:10 ` Laurent Pinchart
2016-11-03 19:26 ` Niklas Söderlund
2016-11-07 10:57 ` Geert Uytterhoeven
0 siblings, 2 replies; 13+ messages in thread
From: Laurent Pinchart @ 2016-11-03 17:10 UTC (permalink / raw)
To: Niklas Söderlund
Cc: Geert Uytterhoeven, Linus Walleij, linux-renesas-soc, linux-gpio
Hi Niklas,
Thank you for thr patch.
On Thursday 03 Nov 2016 16:34:21 Niklas Söderlund wrote:
> There is a bug in the r8a7795 bias code where a WARN() is trigged
> anytime a pin from PUEN0/PUD0is accessed.
>
> # cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins
>
> WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364
> r8a7795_pinmux_get_bias+0xbc/0xc8 [..]
> Call trace:
> [<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8
> [<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270
> [<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30
> [<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188
> [<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98
> [<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128
> [<ffff0000081fe3bc>] seq_read+0x16c/0x420
> [<ffff00000831a110>] full_proxy_read+0x58/0x88
> [<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8
> [<ffff0000081d8874>] vfs_read+0x84/0x148
> [<ffff0000081d9d64>] SyS_read+0x44/0xa0
> [<ffff000008082f4c>] __sys_trace_return+0x0/0x4
>
> This is due to the WARN() check if the reg field of the pullups struct
> is zero, and this should be 0 for pins controlled by the PUEN0/PUD0
> registers. Change the layout of the pullups struct to embed the pin
> number inside the struct and loop over it to fetch the correct
> information or WARN() if no pin is found.
This lowers the memory consumption at the cost of increased CPU usage. Given
that the get/set bias functions are not part of a critical path I'm fine with
that. We could possibly optimize the implementation by using a dichotomic
search, but I don't think that's needed at the moment.
I can foresee the r8a7795_pin_to_bias_data() function being used for other
Gen3 SoCs. Could you move it to the core, and move the WARN_ON_ONCE() from the
caller to the function ? It would be great if you could also convert r8a7778
to use this new method.
> Fixes: 560655247b627ac7 ("pinctrl: sh-pfc: r8a7795: Add bias pinconf
> support") Signed-off-by: Niklas Söderlund
> <niklas.soderlund+renesas@ragnatech.se>
> ---
> drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 350 ++++++++++++++++---------------
> 1 file changed, 180 insertions(+), 170 deletions(-)
>
> diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 2e8cc2a..69e1f31 100644
> --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> @@ -5189,171 +5189,187 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc
> *pfc, unsigned int pin, u32 *poc #define PU6 0x18
>
> static const struct {
> + u16 pin;
> u16 reg : 11;
> u16 bit : 5;
> } pullups[] = {
> - [RCAR_GP_PIN(2, 11)] = { PU0, 31 }, /* AVB_PHY_INT */
> - [RCAR_GP_PIN(2, 10)] = { PU0, 30 }, /* AVB_MAGIC */
> - [RCAR_GP_PIN(2, 9)] = { PU0, 29 }, /* AVB_MDC */
> -
> - [RCAR_GP_PIN(1, 19)] = { PU1, 31 }, /* A19 */
> - [RCAR_GP_PIN(1, 18)] = { PU1, 30 }, /* A18 */
> - [RCAR_GP_PIN(1, 17)] = { PU1, 29 }, /* A17 */
> - [RCAR_GP_PIN(1, 16)] = { PU1, 28 }, /* A16 */
> - [RCAR_GP_PIN(1, 15)] = { PU1, 27 }, /* A15 */
> - [RCAR_GP_PIN(1, 14)] = { PU1, 26 }, /* A14 */
> - [RCAR_GP_PIN(1, 13)] = { PU1, 25 }, /* A13 */
> - [RCAR_GP_PIN(1, 12)] = { PU1, 24 }, /* A12 */
> - [RCAR_GP_PIN(1, 11)] = { PU1, 23 }, /* A11 */
> - [RCAR_GP_PIN(1, 10)] = { PU1, 22 }, /* A10 */
> - [RCAR_GP_PIN(1, 9)] = { PU1, 21 }, /* A9 */
> - [RCAR_GP_PIN(1, 8)] = { PU1, 20 }, /* A8 */
> - [RCAR_GP_PIN(1, 7)] = { PU1, 19 }, /* A7 */
> - [RCAR_GP_PIN(1, 6)] = { PU1, 18 }, /* A6 */
> - [RCAR_GP_PIN(1, 5)] = { PU1, 17 }, /* A5 */
> - [RCAR_GP_PIN(1, 4)] = { PU1, 16 }, /* A4 */
> - [RCAR_GP_PIN(1, 3)] = { PU1, 15 }, /* A3 */
> - [RCAR_GP_PIN(1, 2)] = { PU1, 14 }, /* A2 */
> - [RCAR_GP_PIN(1, 1)] = { PU1, 13 }, /* A1 */
> - [RCAR_GP_PIN(1, 0)] = { PU1, 12 }, /* A0 */
> - [RCAR_GP_PIN(2, 8)] = { PU1, 11 }, /* PWM2_A */
> - [RCAR_GP_PIN(2, 7)] = { PU1, 10 }, /* PWM1_A */
> - [RCAR_GP_PIN(2, 6)] = { PU1, 9 }, /* PWM0 */
> - [RCAR_GP_PIN(2, 5)] = { PU1, 8 }, /* IRQ5 */
> - [RCAR_GP_PIN(2, 4)] = { PU1, 7 }, /* IRQ4 */
> - [RCAR_GP_PIN(2, 3)] = { PU1, 6 }, /* IRQ3 */
> - [RCAR_GP_PIN(2, 2)] = { PU1, 5 }, /* IRQ2 */
> - [RCAR_GP_PIN(2, 1)] = { PU1, 4 }, /* IRQ1 */
> - [RCAR_GP_PIN(2, 0)] = { PU1, 3 }, /* IRQ0 */
> - [RCAR_GP_PIN(2, 14)] = { PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
> - [RCAR_GP_PIN(2, 13)] = { PU1, 1 }, /* AVB_AVTP_MATCH_A */
> - [RCAR_GP_PIN(2, 12)] = { PU1, 0 }, /* AVB_LINK */
> -
> - [RCAR_GP_PIN(7, 3)] = { PU2, 29 }, /* HDMI1_CEC */
> - [RCAR_GP_PIN(7, 2)] = { PU2, 28 }, /* HDMI0_CEC */
> - [RCAR_GP_PIN(7, 1)] = { PU2, 27 }, /* AVS2 */
> - [RCAR_GP_PIN(7, 0)] = { PU2, 26 }, /* AVS1 */
> - [RCAR_GP_PIN(0, 15)] = { PU2, 25 }, /* D15 */
> - [RCAR_GP_PIN(0, 14)] = { PU2, 24 }, /* D14 */
> - [RCAR_GP_PIN(0, 13)] = { PU2, 23 }, /* D13 */
> - [RCAR_GP_PIN(0, 12)] = { PU2, 22 }, /* D12 */
> - [RCAR_GP_PIN(0, 11)] = { PU2, 21 }, /* D11 */
> - [RCAR_GP_PIN(0, 10)] = { PU2, 20 }, /* D10 */
> - [RCAR_GP_PIN(0, 9)] = { PU2, 19 }, /* D9 */
> - [RCAR_GP_PIN(0, 8)] = { PU2, 18 }, /* D8 */
> - [RCAR_GP_PIN(0, 7)] = { PU2, 17 }, /* D7 */
> - [RCAR_GP_PIN(0, 6)] = { PU2, 16 }, /* D6 */
> - [RCAR_GP_PIN(0, 5)] = { PU2, 15 }, /* D5 */
> - [RCAR_GP_PIN(0, 4)] = { PU2, 14 }, /* D4 */
> - [RCAR_GP_PIN(0, 3)] = { PU2, 13 }, /* D3 */
> - [RCAR_GP_PIN(0, 2)] = { PU2, 12 }, /* D2 */
> - [RCAR_GP_PIN(0, 1)] = { PU2, 11 }, /* D1 */
> - [RCAR_GP_PIN(0, 0)] = { PU2, 10 }, /* D0 */
> - [RCAR_GP_PIN(1, 27)] = { PU2, 8 }, /* EX_WAIT0_A */
> - [RCAR_GP_PIN(1, 26)] = { PU2, 7 }, /* WE1_N */
> - [RCAR_GP_PIN(1, 25)] = { PU2, 6 }, /* WE0_N */
> - [RCAR_GP_PIN(1, 24)] = { PU2, 5 }, /* RD_WR_N */
> - [RCAR_GP_PIN(1, 23)] = { PU2, 4 }, /* RD_N */
> - [RCAR_GP_PIN(1, 22)] = { PU2, 3 }, /* BS_N */
> - [RCAR_GP_PIN(1, 21)] = { PU2, 2 }, /* CS1_N_A26 */
> - [RCAR_GP_PIN(1, 20)] = { PU2, 1 }, /* CS0_N */
> -
> - [RCAR_GP_PIN(4, 9)] = { PU3, 31 }, /* SD3_DAT0 */
> - [RCAR_GP_PIN(4, 8)] = { PU3, 30 }, /* SD3_CMD */
> - [RCAR_GP_PIN(4, 7)] = { PU3, 29 }, /* SD3_CLK */
> - [RCAR_GP_PIN(4, 6)] = { PU3, 28 }, /* SD2_DS */
> - [RCAR_GP_PIN(4, 5)] = { PU3, 27 }, /* SD2_DAT3 */
> - [RCAR_GP_PIN(4, 4)] = { PU3, 26 }, /* SD2_DAT2 */
> - [RCAR_GP_PIN(4, 3)] = { PU3, 25 }, /* SD2_DAT1 */
> - [RCAR_GP_PIN(4, 2)] = { PU3, 24 }, /* SD2_DAT0 */
> - [RCAR_GP_PIN(4, 1)] = { PU3, 23 }, /* SD2_CMD */
> - [RCAR_GP_PIN(4, 0)] = { PU3, 22 }, /* SD2_CLK */
> - [RCAR_GP_PIN(3, 11)] = { PU3, 21 }, /* SD1_DAT3 */
> - [RCAR_GP_PIN(3, 10)] = { PU3, 20 }, /* SD1_DAT2 */
> - [RCAR_GP_PIN(3, 9)] = { PU3, 19 }, /* SD1_DAT1 */
> - [RCAR_GP_PIN(3, 8)] = { PU3, 18 }, /* SD1_DAT0 */
> - [RCAR_GP_PIN(3, 7)] = { PU3, 17 }, /* SD1_CMD */
> - [RCAR_GP_PIN(3, 6)] = { PU3, 16 }, /* SD1_CLK */
> - [RCAR_GP_PIN(3, 5)] = { PU3, 15 }, /* SD0_DAT3 */
> - [RCAR_GP_PIN(3, 4)] = { PU3, 14 }, /* SD0_DAT2 */
> - [RCAR_GP_PIN(3, 3)] = { PU3, 13 }, /* SD0_DAT1 */
> - [RCAR_GP_PIN(3, 2)] = { PU3, 12 }, /* SD0_DAT0 */
> - [RCAR_GP_PIN(3, 1)] = { PU3, 11 }, /* SD0_CMD */
> - [RCAR_GP_PIN(3, 0)] = { PU3, 10 }, /* SD0_CLK */
> -
> - [RCAR_GP_PIN(5, 19)] = { PU4, 31 }, /* MSIOF0_SS1 */
> - [RCAR_GP_PIN(5, 18)] = { PU4, 30 }, /* MSIOF0_SYNC */
> - [RCAR_GP_PIN(5, 17)] = { PU4, 29 }, /* MSIOF0_SCK */
> - [RCAR_GP_PIN(5, 16)] = { PU4, 28 }, /* HRTS0_N */
> - [RCAR_GP_PIN(5, 15)] = { PU4, 27 }, /* HCTS0_N */
> - [RCAR_GP_PIN(5, 14)] = { PU4, 26 }, /* HTX0 */
> - [RCAR_GP_PIN(5, 13)] = { PU4, 25 }, /* HRX0 */
> - [RCAR_GP_PIN(5, 12)] = { PU4, 24 }, /* HSCK0 */
> - [RCAR_GP_PIN(5, 11)] = { PU4, 23 }, /* RX2_A */
> - [RCAR_GP_PIN(5, 10)] = { PU4, 22 }, /* TX2_A */
> - [RCAR_GP_PIN(5, 9)] = { PU4, 21 }, /* SCK2 */
> - [RCAR_GP_PIN(5, 8)] = { PU4, 20 }, /* RTS1_N_TANS */
> - [RCAR_GP_PIN(5, 7)] = { PU4, 19 }, /* CTS1_N */
> - [RCAR_GP_PIN(5, 6)] = { PU4, 18 }, /* TX1_A */
> - [RCAR_GP_PIN(5, 5)] = { PU4, 17 }, /* RX1_A */
> - [RCAR_GP_PIN(5, 4)] = { PU4, 16 }, /* RTS0_N_TANS */
> - [RCAR_GP_PIN(5, 3)] = { PU4, 15 }, /* CTS0_N */
> - [RCAR_GP_PIN(5, 2)] = { PU4, 14 }, /* TX0 */
> - [RCAR_GP_PIN(5, 1)] = { PU4, 13 }, /* RX0 */
> - [RCAR_GP_PIN(5, 0)] = { PU4, 12 }, /* SCK0 */
> - [RCAR_GP_PIN(3, 15)] = { PU4, 11 }, /* SD1_WP */
> - [RCAR_GP_PIN(3, 14)] = { PU4, 10 }, /* SD1_CD */
> - [RCAR_GP_PIN(3, 13)] = { PU4, 9 }, /* SD0_WP */
> - [RCAR_GP_PIN(3, 12)] = { PU4, 8 }, /* SD0_CD */
> - [RCAR_GP_PIN(4, 17)] = { PU4, 7 }, /* SD3_DS */
> - [RCAR_GP_PIN(4, 16)] = { PU4, 6 }, /* SD3_DAT7 */
> - [RCAR_GP_PIN(4, 15)] = { PU4, 5 }, /* SD3_DAT6 */
> - [RCAR_GP_PIN(4, 14)] = { PU4, 4 }, /* SD3_DAT5 */
> - [RCAR_GP_PIN(4, 13)] = { PU4, 3 }, /* SD3_DAT4 */
> - [RCAR_GP_PIN(4, 12)] = { PU4, 2 }, /* SD3_DAT3 */
> - [RCAR_GP_PIN(4, 11)] = { PU4, 1 }, /* SD3_DAT2 */
> - [RCAR_GP_PIN(4, 10)] = { PU4, 0 }, /* SD3_DAT1 */
> -
> - [RCAR_GP_PIN(6, 24)] = { PU5, 31 }, /* USB0_PWEN */
> - [RCAR_GP_PIN(6, 23)] = { PU5, 30 }, /* AUDIO_CLKB_B */
> - [RCAR_GP_PIN(6, 22)] = { PU5, 29 }, /* AUDIO_CLKA_A */
> - [RCAR_GP_PIN(6, 21)] = { PU5, 28 }, /* SSI_SDATA9_A */
> - [RCAR_GP_PIN(6, 20)] = { PU5, 27 }, /* SSI_SDATA8 */
> - [RCAR_GP_PIN(6, 19)] = { PU5, 26 }, /* SSI_SDATA7 */
> - [RCAR_GP_PIN(6, 18)] = { PU5, 25 }, /* SSI_WS78 */
> - [RCAR_GP_PIN(6, 17)] = { PU5, 24 }, /* SSI_SCK78 */
> - [RCAR_GP_PIN(6, 16)] = { PU5, 23 }, /* SSI_SDATA6 */
> - [RCAR_GP_PIN(6, 15)] = { PU5, 22 }, /* SSI_WS6 */
> - [RCAR_GP_PIN(6, 14)] = { PU5, 21 }, /* SSI_SCK6 */
> - [RCAR_GP_PIN(6, 13)] = { PU5, 20 }, /* SSI_SDATA5 */
> - [RCAR_GP_PIN(6, 12)] = { PU5, 19 }, /* SSI_WS5 */
> - [RCAR_GP_PIN(6, 11)] = { PU5, 18 }, /* SSI_SCK5 */
> - [RCAR_GP_PIN(6, 10)] = { PU5, 17 }, /* SSI_SDATA4 */
> - [RCAR_GP_PIN(6, 9)] = { PU5, 16 }, /* SSI_WS4 */
> - [RCAR_GP_PIN(6, 8)] = { PU5, 15 }, /* SSI_SCK4 */
> - [RCAR_GP_PIN(6, 7)] = { PU5, 14 }, /* SSI_SDATA3 */
> - [RCAR_GP_PIN(6, 6)] = { PU5, 13 }, /* SSI_WS34 */
> - [RCAR_GP_PIN(6, 5)] = { PU5, 12 }, /* SSI_SCK34 */
> - [RCAR_GP_PIN(6, 4)] = { PU5, 11 }, /* SSI_SDATA2_A */
> - [RCAR_GP_PIN(6, 3)] = { PU5, 10 }, /* SSI_SDATA1_A */
> - [RCAR_GP_PIN(6, 2)] = { PU5, 9 }, /* SSI_SDATA0 */
> - [RCAR_GP_PIN(6, 1)] = { PU5, 8 }, /* SSI_WS01239 */
> - [RCAR_GP_PIN(6, 0)] = { PU5, 7 }, /* SSI_SCK01239 */
> - [RCAR_GP_PIN(5, 25)] = { PU5, 5 }, /* MLB_DAT */
> - [RCAR_GP_PIN(5, 24)] = { PU5, 4 }, /* MLB_SIG */
> - [RCAR_GP_PIN(5, 23)] = { PU5, 3 }, /* MLB_CLK */
> - [RCAR_GP_PIN(5, 22)] = { PU5, 2 }, /* MSIOF0_RXD */
> - [RCAR_GP_PIN(5, 21)] = { PU5, 1 }, /* MSIOF0_SS2 */
> - [RCAR_GP_PIN(5, 20)] = { PU5, 0 }, /* MSIOF0_TXD */
> -
> - [RCAR_GP_PIN(6, 31)] = { PU6, 6 }, /* USB31_OVC */
> - [RCAR_GP_PIN(6, 30)] = { PU6, 5 }, /* USB31_PWEN */
> - [RCAR_GP_PIN(6, 29)] = { PU6, 4 }, /* USB30_OVC */
> - [RCAR_GP_PIN(6, 28)] = { PU6, 3 }, /* USB30_PWEN */
> - [RCAR_GP_PIN(6, 27)] = { PU6, 2 }, /* USB1_OVC */
> - [RCAR_GP_PIN(6, 26)] = { PU6, 1 }, /* USB1_PWEN */
> - [RCAR_GP_PIN(6, 25)] = { PU6, 0 }, /* USB0_OVC */
> -};
> + { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
> + { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
> + { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
> +
> + { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
> + { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
> + { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
> + { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
> + { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
> + { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
> + { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
> + { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
> + { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
> + { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
> + { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
> + { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
> + { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
> + { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
> + { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
> + { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
> + { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
> + { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
> + { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
> + { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
> + { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
> + { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
> + { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
> + { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
> + { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
> + { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
> + { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
> + { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
> + { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
> + { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
> + { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
> + { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
> +
> + { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */
> + { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
> + { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
> + { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
> + { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
> + { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
> + { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
> + { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
> + { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
> + { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
> + { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
> + { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
> + { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
> + { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
> + { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
> + { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
> + { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
> + { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
> + { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
> + { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
> + { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
> + { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
> + { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
> + { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
> + { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
> + { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
> + { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */
> + { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
> +
> + { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
> + { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
> + { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
> + { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
> + { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
> + { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
> + { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
> + { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
> + { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
> + { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
> + { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
> + { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
> + { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
> + { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
> + { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
> + { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
> + { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
> + { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
> + { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
> + { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
> + { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
> + { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
> +
> + { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
> + { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
> + { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
> + { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
> + { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
> + { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
> + { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
> + { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
> + { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
> + { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
> + { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
> + { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
> + { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
> + { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
> + { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
> + { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
> + { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
> + { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
> + { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
> + { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
> + { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
> + { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
> + { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
> + { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
> + { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
> + { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
> + { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
> + { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
> + { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
> + { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
> + { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
> + { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
> +
> + { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
> + { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
> + { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
> + { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
> + { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
> + { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
> + { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
> + { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
> + { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
> + { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
> + { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
> + { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
> + { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
> + { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
> + { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
> + { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
> + { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
> + { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
> + { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */
> + { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */
> + { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
> + { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
> + { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
> + { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
> + { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
> + { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
> + { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
> + { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
> + { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
> + { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
> + { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
> +
> + { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB31_OVC */
> + { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB31_PWEN */
> + { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
> + { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
> + { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
> + { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
> + { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
> +};
> +
> +static int r8a7795_pin_to_bias_data(unsigned int pin, u32 *reg, u32 *bit)
> +{
> + unsigned int i;
> +
> + for (i = 0; i < ARRAY_SIZE(pullups); i++) {
> + if (pullups[i].pin == pin) {
> + *reg = pullups[i].reg;
> + *bit = BIT(pullups[i].bit);
> + return 0;
> + }
> + }
> +
> + return -EINVAL;
> +}
>
> static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
> unsigned int pin)
> @@ -5361,12 +5377,9 @@ static unsigned int r8a7795_pinmux_get_bias(struct
> sh_pfc *pfc, u32 reg;
> u32 bit;
>
> - if (WARN_ON_ONCE(!pullups[pin].reg))
> + if (WARN_ON_ONCE(r8a7795_pin_to_bias_data(pin, ®, &bit)))
> return PIN_CONFIG_BIAS_DISABLE;
>
> - reg = pullups[pin].reg;
> - bit = BIT(pullups[pin].bit);
> -
> if (sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit) {
> if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
> return PIN_CONFIG_BIAS_PULL_UP;
Slightly out of scope, but the following code
if (sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit) {
if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
return PIN_CONFIG_BIAS_PULL_UP;
else
return PIN_CONFIG_BIAS_PULL_DOWN;
} else
return PIN_CONFIG_BIAS_DISABLE;
misses braces around the else. It could be written
if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
return PIN_CONFIG_BIAS_DISABLE;
else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
return PIN_CONFIG_BIAS_PULL_UP;
else
return PIN_CONFIG_BIAS_PULL_DOWN;
> @@ -5383,12 +5396,9 @@ static void r8a7795_pinmux_set_bias(struct sh_pfc
> *pfc, unsigned int pin, u32 reg;
> u32 bit;
>
> - if (WARN_ON_ONCE(!pullups[pin].reg))
> + if (WARN_ON_ONCE(r8a7795_pin_to_bias_data(pin, ®, &bit)))
> return;
>
> - reg = pullups[pin].reg;
> - bit = BIT(pullups[pin].bit);
> -
> enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
> if (bias != PIN_CONFIG_BIAS_DISABLE)
> enable |= bit;
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] pinctrl: sh-pfc: r8a7795: Use lookup function for bias data
2016-11-03 17:10 ` Laurent Pinchart
@ 2016-11-03 19:26 ` Niklas Söderlund
2016-11-07 10:57 ` Geert Uytterhoeven
1 sibling, 0 replies; 13+ messages in thread
From: Niklas Söderlund @ 2016-11-03 19:26 UTC (permalink / raw)
To: Laurent Pinchart
Cc: Geert Uytterhoeven, Linus Walleij, linux-renesas-soc, linux-gpio
Hi Laurent,
On 2016-11-03 19:10:06 +0200, Laurent Pinchart wrote:
> Hi Niklas,
>
> Thank you for thr patch.
Thanks for your feedback.
>
> On Thursday 03 Nov 2016 16:34:21 Niklas Söderlund wrote:
> > There is a bug in the r8a7795 bias code where a WARN() is trigged
> > anytime a pin from PUEN0/PUD0is accessed.
> >
> > # cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins
> >
> > WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364
> > r8a7795_pinmux_get_bias+0xbc/0xc8 [..]
> > Call trace:
> > [<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8
> > [<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270
> > [<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30
> > [<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188
> > [<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98
> > [<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128
> > [<ffff0000081fe3bc>] seq_read+0x16c/0x420
> > [<ffff00000831a110>] full_proxy_read+0x58/0x88
> > [<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8
> > [<ffff0000081d8874>] vfs_read+0x84/0x148
> > [<ffff0000081d9d64>] SyS_read+0x44/0xa0
> > [<ffff000008082f4c>] __sys_trace_return+0x0/0x4
> >
> > This is due to the WARN() check if the reg field of the pullups struct
> > is zero, and this should be 0 for pins controlled by the PUEN0/PUD0
> > registers. Change the layout of the pullups struct to embed the pin
> > number inside the struct and loop over it to fetch the correct
> > information or WARN() if no pin is found.
>
> This lowers the memory consumption at the cost of increased CPU usage. Given
> that the get/set bias functions are not part of a critical path I'm fine with
> that. We could possibly optimize the implementation by using a dichotomic
> search, but I don't think that's needed at the moment.
>
> I can foresee the r8a7795_pin_to_bias_data() function being used for other
> Gen3 SoCs. Could you move it to the core, and move the WARN_ON_ONCE() from the
> caller to the function ? It would be great if you could also convert r8a7778
> to use this new method.
Yes, I will move the function and convert r8a7778 and include those
patches in my v3.
>
> > Fixes: 560655247b627ac7 ("pinctrl: sh-pfc: r8a7795: Add bias pinconf
> > support") Signed-off-by: Niklas Söderlund
> > <niklas.soderlund+renesas@ragnatech.se>
> > ---
> > drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 350 ++++++++++++++++---------------
> > 1 file changed, 180 insertions(+), 170 deletions(-)
> >
> > diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> > b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 2e8cc2a..69e1f31 100644
> > --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> > +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> > @@ -5189,171 +5189,187 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc
> > *pfc, unsigned int pin, u32 *poc #define PU6 0x18
> >
> > static const struct {
> > + u16 pin;
> > u16 reg : 11;
> > u16 bit : 5;
> > } pullups[] = {
> > - [RCAR_GP_PIN(2, 11)] = { PU0, 31 }, /* AVB_PHY_INT */
> > - [RCAR_GP_PIN(2, 10)] = { PU0, 30 }, /* AVB_MAGIC */
> > - [RCAR_GP_PIN(2, 9)] = { PU0, 29 }, /* AVB_MDC */
> > -
> > - [RCAR_GP_PIN(1, 19)] = { PU1, 31 }, /* A19 */
> > - [RCAR_GP_PIN(1, 18)] = { PU1, 30 }, /* A18 */
> > - [RCAR_GP_PIN(1, 17)] = { PU1, 29 }, /* A17 */
> > - [RCAR_GP_PIN(1, 16)] = { PU1, 28 }, /* A16 */
> > - [RCAR_GP_PIN(1, 15)] = { PU1, 27 }, /* A15 */
> > - [RCAR_GP_PIN(1, 14)] = { PU1, 26 }, /* A14 */
> > - [RCAR_GP_PIN(1, 13)] = { PU1, 25 }, /* A13 */
> > - [RCAR_GP_PIN(1, 12)] = { PU1, 24 }, /* A12 */
> > - [RCAR_GP_PIN(1, 11)] = { PU1, 23 }, /* A11 */
> > - [RCAR_GP_PIN(1, 10)] = { PU1, 22 }, /* A10 */
> > - [RCAR_GP_PIN(1, 9)] = { PU1, 21 }, /* A9 */
> > - [RCAR_GP_PIN(1, 8)] = { PU1, 20 }, /* A8 */
> > - [RCAR_GP_PIN(1, 7)] = { PU1, 19 }, /* A7 */
> > - [RCAR_GP_PIN(1, 6)] = { PU1, 18 }, /* A6 */
> > - [RCAR_GP_PIN(1, 5)] = { PU1, 17 }, /* A5 */
> > - [RCAR_GP_PIN(1, 4)] = { PU1, 16 }, /* A4 */
> > - [RCAR_GP_PIN(1, 3)] = { PU1, 15 }, /* A3 */
> > - [RCAR_GP_PIN(1, 2)] = { PU1, 14 }, /* A2 */
> > - [RCAR_GP_PIN(1, 1)] = { PU1, 13 }, /* A1 */
> > - [RCAR_GP_PIN(1, 0)] = { PU1, 12 }, /* A0 */
> > - [RCAR_GP_PIN(2, 8)] = { PU1, 11 }, /* PWM2_A */
> > - [RCAR_GP_PIN(2, 7)] = { PU1, 10 }, /* PWM1_A */
> > - [RCAR_GP_PIN(2, 6)] = { PU1, 9 }, /* PWM0 */
> > - [RCAR_GP_PIN(2, 5)] = { PU1, 8 }, /* IRQ5 */
> > - [RCAR_GP_PIN(2, 4)] = { PU1, 7 }, /* IRQ4 */
> > - [RCAR_GP_PIN(2, 3)] = { PU1, 6 }, /* IRQ3 */
> > - [RCAR_GP_PIN(2, 2)] = { PU1, 5 }, /* IRQ2 */
> > - [RCAR_GP_PIN(2, 1)] = { PU1, 4 }, /* IRQ1 */
> > - [RCAR_GP_PIN(2, 0)] = { PU1, 3 }, /* IRQ0 */
> > - [RCAR_GP_PIN(2, 14)] = { PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
> > - [RCAR_GP_PIN(2, 13)] = { PU1, 1 }, /* AVB_AVTP_MATCH_A */
> > - [RCAR_GP_PIN(2, 12)] = { PU1, 0 }, /* AVB_LINK */
> > -
> > - [RCAR_GP_PIN(7, 3)] = { PU2, 29 }, /* HDMI1_CEC */
> > - [RCAR_GP_PIN(7, 2)] = { PU2, 28 }, /* HDMI0_CEC */
> > - [RCAR_GP_PIN(7, 1)] = { PU2, 27 }, /* AVS2 */
> > - [RCAR_GP_PIN(7, 0)] = { PU2, 26 }, /* AVS1 */
> > - [RCAR_GP_PIN(0, 15)] = { PU2, 25 }, /* D15 */
> > - [RCAR_GP_PIN(0, 14)] = { PU2, 24 }, /* D14 */
> > - [RCAR_GP_PIN(0, 13)] = { PU2, 23 }, /* D13 */
> > - [RCAR_GP_PIN(0, 12)] = { PU2, 22 }, /* D12 */
> > - [RCAR_GP_PIN(0, 11)] = { PU2, 21 }, /* D11 */
> > - [RCAR_GP_PIN(0, 10)] = { PU2, 20 }, /* D10 */
> > - [RCAR_GP_PIN(0, 9)] = { PU2, 19 }, /* D9 */
> > - [RCAR_GP_PIN(0, 8)] = { PU2, 18 }, /* D8 */
> > - [RCAR_GP_PIN(0, 7)] = { PU2, 17 }, /* D7 */
> > - [RCAR_GP_PIN(0, 6)] = { PU2, 16 }, /* D6 */
> > - [RCAR_GP_PIN(0, 5)] = { PU2, 15 }, /* D5 */
> > - [RCAR_GP_PIN(0, 4)] = { PU2, 14 }, /* D4 */
> > - [RCAR_GP_PIN(0, 3)] = { PU2, 13 }, /* D3 */
> > - [RCAR_GP_PIN(0, 2)] = { PU2, 12 }, /* D2 */
> > - [RCAR_GP_PIN(0, 1)] = { PU2, 11 }, /* D1 */
> > - [RCAR_GP_PIN(0, 0)] = { PU2, 10 }, /* D0 */
> > - [RCAR_GP_PIN(1, 27)] = { PU2, 8 }, /* EX_WAIT0_A */
> > - [RCAR_GP_PIN(1, 26)] = { PU2, 7 }, /* WE1_N */
> > - [RCAR_GP_PIN(1, 25)] = { PU2, 6 }, /* WE0_N */
> > - [RCAR_GP_PIN(1, 24)] = { PU2, 5 }, /* RD_WR_N */
> > - [RCAR_GP_PIN(1, 23)] = { PU2, 4 }, /* RD_N */
> > - [RCAR_GP_PIN(1, 22)] = { PU2, 3 }, /* BS_N */
> > - [RCAR_GP_PIN(1, 21)] = { PU2, 2 }, /* CS1_N_A26 */
> > - [RCAR_GP_PIN(1, 20)] = { PU2, 1 }, /* CS0_N */
> > -
> > - [RCAR_GP_PIN(4, 9)] = { PU3, 31 }, /* SD3_DAT0 */
> > - [RCAR_GP_PIN(4, 8)] = { PU3, 30 }, /* SD3_CMD */
> > - [RCAR_GP_PIN(4, 7)] = { PU3, 29 }, /* SD3_CLK */
> > - [RCAR_GP_PIN(4, 6)] = { PU3, 28 }, /* SD2_DS */
> > - [RCAR_GP_PIN(4, 5)] = { PU3, 27 }, /* SD2_DAT3 */
> > - [RCAR_GP_PIN(4, 4)] = { PU3, 26 }, /* SD2_DAT2 */
> > - [RCAR_GP_PIN(4, 3)] = { PU3, 25 }, /* SD2_DAT1 */
> > - [RCAR_GP_PIN(4, 2)] = { PU3, 24 }, /* SD2_DAT0 */
> > - [RCAR_GP_PIN(4, 1)] = { PU3, 23 }, /* SD2_CMD */
> > - [RCAR_GP_PIN(4, 0)] = { PU3, 22 }, /* SD2_CLK */
> > - [RCAR_GP_PIN(3, 11)] = { PU3, 21 }, /* SD1_DAT3 */
> > - [RCAR_GP_PIN(3, 10)] = { PU3, 20 }, /* SD1_DAT2 */
> > - [RCAR_GP_PIN(3, 9)] = { PU3, 19 }, /* SD1_DAT1 */
> > - [RCAR_GP_PIN(3, 8)] = { PU3, 18 }, /* SD1_DAT0 */
> > - [RCAR_GP_PIN(3, 7)] = { PU3, 17 }, /* SD1_CMD */
> > - [RCAR_GP_PIN(3, 6)] = { PU3, 16 }, /* SD1_CLK */
> > - [RCAR_GP_PIN(3, 5)] = { PU3, 15 }, /* SD0_DAT3 */
> > - [RCAR_GP_PIN(3, 4)] = { PU3, 14 }, /* SD0_DAT2 */
> > - [RCAR_GP_PIN(3, 3)] = { PU3, 13 }, /* SD0_DAT1 */
> > - [RCAR_GP_PIN(3, 2)] = { PU3, 12 }, /* SD0_DAT0 */
> > - [RCAR_GP_PIN(3, 1)] = { PU3, 11 }, /* SD0_CMD */
> > - [RCAR_GP_PIN(3, 0)] = { PU3, 10 }, /* SD0_CLK */
> > -
> > - [RCAR_GP_PIN(5, 19)] = { PU4, 31 }, /* MSIOF0_SS1 */
> > - [RCAR_GP_PIN(5, 18)] = { PU4, 30 }, /* MSIOF0_SYNC */
> > - [RCAR_GP_PIN(5, 17)] = { PU4, 29 }, /* MSIOF0_SCK */
> > - [RCAR_GP_PIN(5, 16)] = { PU4, 28 }, /* HRTS0_N */
> > - [RCAR_GP_PIN(5, 15)] = { PU4, 27 }, /* HCTS0_N */
> > - [RCAR_GP_PIN(5, 14)] = { PU4, 26 }, /* HTX0 */
> > - [RCAR_GP_PIN(5, 13)] = { PU4, 25 }, /* HRX0 */
> > - [RCAR_GP_PIN(5, 12)] = { PU4, 24 }, /* HSCK0 */
> > - [RCAR_GP_PIN(5, 11)] = { PU4, 23 }, /* RX2_A */
> > - [RCAR_GP_PIN(5, 10)] = { PU4, 22 }, /* TX2_A */
> > - [RCAR_GP_PIN(5, 9)] = { PU4, 21 }, /* SCK2 */
> > - [RCAR_GP_PIN(5, 8)] = { PU4, 20 }, /* RTS1_N_TANS */
> > - [RCAR_GP_PIN(5, 7)] = { PU4, 19 }, /* CTS1_N */
> > - [RCAR_GP_PIN(5, 6)] = { PU4, 18 }, /* TX1_A */
> > - [RCAR_GP_PIN(5, 5)] = { PU4, 17 }, /* RX1_A */
> > - [RCAR_GP_PIN(5, 4)] = { PU4, 16 }, /* RTS0_N_TANS */
> > - [RCAR_GP_PIN(5, 3)] = { PU4, 15 }, /* CTS0_N */
> > - [RCAR_GP_PIN(5, 2)] = { PU4, 14 }, /* TX0 */
> > - [RCAR_GP_PIN(5, 1)] = { PU4, 13 }, /* RX0 */
> > - [RCAR_GP_PIN(5, 0)] = { PU4, 12 }, /* SCK0 */
> > - [RCAR_GP_PIN(3, 15)] = { PU4, 11 }, /* SD1_WP */
> > - [RCAR_GP_PIN(3, 14)] = { PU4, 10 }, /* SD1_CD */
> > - [RCAR_GP_PIN(3, 13)] = { PU4, 9 }, /* SD0_WP */
> > - [RCAR_GP_PIN(3, 12)] = { PU4, 8 }, /* SD0_CD */
> > - [RCAR_GP_PIN(4, 17)] = { PU4, 7 }, /* SD3_DS */
> > - [RCAR_GP_PIN(4, 16)] = { PU4, 6 }, /* SD3_DAT7 */
> > - [RCAR_GP_PIN(4, 15)] = { PU4, 5 }, /* SD3_DAT6 */
> > - [RCAR_GP_PIN(4, 14)] = { PU4, 4 }, /* SD3_DAT5 */
> > - [RCAR_GP_PIN(4, 13)] = { PU4, 3 }, /* SD3_DAT4 */
> > - [RCAR_GP_PIN(4, 12)] = { PU4, 2 }, /* SD3_DAT3 */
> > - [RCAR_GP_PIN(4, 11)] = { PU4, 1 }, /* SD3_DAT2 */
> > - [RCAR_GP_PIN(4, 10)] = { PU4, 0 }, /* SD3_DAT1 */
> > -
> > - [RCAR_GP_PIN(6, 24)] = { PU5, 31 }, /* USB0_PWEN */
> > - [RCAR_GP_PIN(6, 23)] = { PU5, 30 }, /* AUDIO_CLKB_B */
> > - [RCAR_GP_PIN(6, 22)] = { PU5, 29 }, /* AUDIO_CLKA_A */
> > - [RCAR_GP_PIN(6, 21)] = { PU5, 28 }, /* SSI_SDATA9_A */
> > - [RCAR_GP_PIN(6, 20)] = { PU5, 27 }, /* SSI_SDATA8 */
> > - [RCAR_GP_PIN(6, 19)] = { PU5, 26 }, /* SSI_SDATA7 */
> > - [RCAR_GP_PIN(6, 18)] = { PU5, 25 }, /* SSI_WS78 */
> > - [RCAR_GP_PIN(6, 17)] = { PU5, 24 }, /* SSI_SCK78 */
> > - [RCAR_GP_PIN(6, 16)] = { PU5, 23 }, /* SSI_SDATA6 */
> > - [RCAR_GP_PIN(6, 15)] = { PU5, 22 }, /* SSI_WS6 */
> > - [RCAR_GP_PIN(6, 14)] = { PU5, 21 }, /* SSI_SCK6 */
> > - [RCAR_GP_PIN(6, 13)] = { PU5, 20 }, /* SSI_SDATA5 */
> > - [RCAR_GP_PIN(6, 12)] = { PU5, 19 }, /* SSI_WS5 */
> > - [RCAR_GP_PIN(6, 11)] = { PU5, 18 }, /* SSI_SCK5 */
> > - [RCAR_GP_PIN(6, 10)] = { PU5, 17 }, /* SSI_SDATA4 */
> > - [RCAR_GP_PIN(6, 9)] = { PU5, 16 }, /* SSI_WS4 */
> > - [RCAR_GP_PIN(6, 8)] = { PU5, 15 }, /* SSI_SCK4 */
> > - [RCAR_GP_PIN(6, 7)] = { PU5, 14 }, /* SSI_SDATA3 */
> > - [RCAR_GP_PIN(6, 6)] = { PU5, 13 }, /* SSI_WS34 */
> > - [RCAR_GP_PIN(6, 5)] = { PU5, 12 }, /* SSI_SCK34 */
> > - [RCAR_GP_PIN(6, 4)] = { PU5, 11 }, /* SSI_SDATA2_A */
> > - [RCAR_GP_PIN(6, 3)] = { PU5, 10 }, /* SSI_SDATA1_A */
> > - [RCAR_GP_PIN(6, 2)] = { PU5, 9 }, /* SSI_SDATA0 */
> > - [RCAR_GP_PIN(6, 1)] = { PU5, 8 }, /* SSI_WS01239 */
> > - [RCAR_GP_PIN(6, 0)] = { PU5, 7 }, /* SSI_SCK01239 */
> > - [RCAR_GP_PIN(5, 25)] = { PU5, 5 }, /* MLB_DAT */
> > - [RCAR_GP_PIN(5, 24)] = { PU5, 4 }, /* MLB_SIG */
> > - [RCAR_GP_PIN(5, 23)] = { PU5, 3 }, /* MLB_CLK */
> > - [RCAR_GP_PIN(5, 22)] = { PU5, 2 }, /* MSIOF0_RXD */
> > - [RCAR_GP_PIN(5, 21)] = { PU5, 1 }, /* MSIOF0_SS2 */
> > - [RCAR_GP_PIN(5, 20)] = { PU5, 0 }, /* MSIOF0_TXD */
> > -
> > - [RCAR_GP_PIN(6, 31)] = { PU6, 6 }, /* USB31_OVC */
> > - [RCAR_GP_PIN(6, 30)] = { PU6, 5 }, /* USB31_PWEN */
> > - [RCAR_GP_PIN(6, 29)] = { PU6, 4 }, /* USB30_OVC */
> > - [RCAR_GP_PIN(6, 28)] = { PU6, 3 }, /* USB30_PWEN */
> > - [RCAR_GP_PIN(6, 27)] = { PU6, 2 }, /* USB1_OVC */
> > - [RCAR_GP_PIN(6, 26)] = { PU6, 1 }, /* USB1_PWEN */
> > - [RCAR_GP_PIN(6, 25)] = { PU6, 0 }, /* USB0_OVC */
> > -};
> > + { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
> > + { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
> > + { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
> > +
> > + { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
> > + { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
> > + { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
> > + { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
> > + { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
> > + { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
> > + { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
> > + { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
> > + { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
> > + { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
> > + { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
> > + { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
> > + { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
> > + { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
> > + { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
> > + { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
> > + { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
> > + { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
> > + { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
> > + { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
> > + { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
> > + { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
> > + { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
> > + { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
> > + { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
> > + { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
> > + { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
> > + { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
> > + { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
> > + { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
> > + { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
> > + { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
> > +
> > + { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */
> > + { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
> > + { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
> > + { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
> > + { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
> > + { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
> > + { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
> > + { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
> > + { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
> > + { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
> > + { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
> > + { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
> > + { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
> > + { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
> > + { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
> > + { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
> > + { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
> > + { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
> > + { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
> > + { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
> > + { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
> > + { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
> > + { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
> > + { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
> > + { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
> > + { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
> > + { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */
> > + { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
> > +
> > + { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
> > + { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
> > + { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
> > + { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
> > + { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
> > + { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
> > + { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
> > + { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
> > + { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
> > + { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
> > + { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
> > + { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
> > + { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
> > + { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
> > + { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
> > + { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
> > + { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
> > + { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
> > + { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
> > + { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
> > + { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
> > + { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
> > +
> > + { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
> > + { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
> > + { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
> > + { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
> > + { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
> > + { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
> > + { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
> > + { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
> > + { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
> > + { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
> > + { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
> > + { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
> > + { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
> > + { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
> > + { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
> > + { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
> > + { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
> > + { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
> > + { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
> > + { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
> > + { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
> > + { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
> > + { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
> > + { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
> > + { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
> > + { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
> > + { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
> > + { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
> > + { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
> > + { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
> > + { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
> > + { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
> > +
> > + { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
> > + { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
> > + { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
> > + { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
> > + { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
> > + { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
> > + { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
> > + { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
> > + { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
> > + { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
> > + { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
> > + { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
> > + { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
> > + { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
> > + { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
> > + { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
> > + { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
> > + { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
> > + { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */
> > + { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */
> > + { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
> > + { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
> > + { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
> > + { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
> > + { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
> > + { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
> > + { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
> > + { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
> > + { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
> > + { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
> > + { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
> > +
> > + { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB31_OVC */
> > + { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB31_PWEN */
> > + { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
> > + { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
> > + { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
> > + { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
> > + { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
> > +};
> > +
> > +static int r8a7795_pin_to_bias_data(unsigned int pin, u32 *reg, u32 *bit)
> > +{
> > + unsigned int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(pullups); i++) {
> > + if (pullups[i].pin == pin) {
> > + *reg = pullups[i].reg;
> > + *bit = BIT(pullups[i].bit);
> > + return 0;
> > + }
> > + }
> > +
> > + return -EINVAL;
> > +}
> >
> > static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
> > unsigned int pin)
> > @@ -5361,12 +5377,9 @@ static unsigned int r8a7795_pinmux_get_bias(struct
> > sh_pfc *pfc, u32 reg;
> > u32 bit;
> >
> > - if (WARN_ON_ONCE(!pullups[pin].reg))
> > + if (WARN_ON_ONCE(r8a7795_pin_to_bias_data(pin, ®, &bit)))
> > return PIN_CONFIG_BIAS_DISABLE;
> >
> > - reg = pullups[pin].reg;
> > - bit = BIT(pullups[pin].bit);
> > -
> > if (sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit) {
> > if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
> > return PIN_CONFIG_BIAS_PULL_UP;
>
> Slightly out of scope, but the following code
>
> if (sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit) {
> if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
> return PIN_CONFIG_BIAS_PULL_UP;
> else
> return PIN_CONFIG_BIAS_PULL_DOWN;
> } else
> return PIN_CONFIG_BIAS_DISABLE;
>
> misses braces around the else. It could be written
>
> if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
> return PIN_CONFIG_BIAS_DISABLE;
> else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
> return PIN_CONFIG_BIAS_PULL_UP;
> else
> return PIN_CONFIG_BIAS_PULL_DOWN;
I can include a patch fixing this up in my v3.
>
> > @@ -5383,12 +5396,9 @@ static void r8a7795_pinmux_set_bias(struct sh_pfc
> > *pfc, unsigned int pin, u32 reg;
> > u32 bit;
> >
> > - if (WARN_ON_ONCE(!pullups[pin].reg))
> > + if (WARN_ON_ONCE(r8a7795_pin_to_bias_data(pin, ®, &bit)))
> > return;
> >
> > - reg = pullups[pin].reg;
> > - bit = BIT(pullups[pin].bit);
> > -
> > enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
> > if (bias != PIN_CONFIG_BIAS_DISABLE)
> > enable |= bit;
>
--
Regards,
Niklas Söderlund
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] pinctrl: sh-pfc: r8a7795: Use lookup function for bias data
@ 2016-11-03 19:26 ` Niklas Söderlund
0 siblings, 0 replies; 13+ messages in thread
From: Niklas Söderlund @ 2016-11-03 19:26 UTC (permalink / raw)
To: Laurent Pinchart
Cc: Geert Uytterhoeven, Linus Walleij, linux-renesas-soc, linux-gpio
Hi Laurent,
On 2016-11-03 19:10:06 +0200, Laurent Pinchart wrote:
> Hi Niklas,
>
> Thank you for thr patch.
Thanks for your feedback.
>
> On Thursday 03 Nov 2016 16:34:21 Niklas S�derlund wrote:
> > There is a bug in the r8a7795 bias code where a WARN() is trigged
> > anytime a pin from PUEN0/PUD0is accessed.
> >
> > # cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins
> >
> > WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364
> > r8a7795_pinmux_get_bias+0xbc/0xc8 [..]
> > Call trace:
> > [<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8
> > [<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270
> > [<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30
> > [<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188
> > [<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98
> > [<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128
> > [<ffff0000081fe3bc>] seq_read+0x16c/0x420
> > [<ffff00000831a110>] full_proxy_read+0x58/0x88
> > [<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8
> > [<ffff0000081d8874>] vfs_read+0x84/0x148
> > [<ffff0000081d9d64>] SyS_read+0x44/0xa0
> > [<ffff000008082f4c>] __sys_trace_return+0x0/0x4
> >
> > This is due to the WARN() check if the reg field of the pullups struct
> > is zero, and this should be 0 for pins controlled by the PUEN0/PUD0
> > registers. Change the layout of the pullups struct to embed the pin
> > number inside the struct and loop over it to fetch the correct
> > information or WARN() if no pin is found.
>
> This lowers the memory consumption at the cost of increased CPU usage. Given
> that the get/set bias functions are not part of a critical path I'm fine with
> that. We could possibly optimize the implementation by using a dichotomic
> search, but I don't think that's needed at the moment.
>
> I can foresee the r8a7795_pin_to_bias_data() function being used for other
> Gen3 SoCs. Could you move it to the core, and move the WARN_ON_ONCE() from the
> caller to the function ? It would be great if you could also convert r8a7778
> to use this new method.
Yes, I will move the function and convert r8a7778 and include those
patches in my v3.
>
> > Fixes: 560655247b627ac7 ("pinctrl: sh-pfc: r8a7795: Add bias pinconf
> > support") Signed-off-by: Niklas S�derlund
> > <niklas.soderlund+renesas@ragnatech.se>
> > ---
> > drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 350 ++++++++++++++++---------------
> > 1 file changed, 180 insertions(+), 170 deletions(-)
> >
> > diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> > b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 2e8cc2a..69e1f31 100644
> > --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> > +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
> > @@ -5189,171 +5189,187 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc
> > *pfc, unsigned int pin, u32 *poc #define PU6 0x18
> >
> > static const struct {
> > + u16 pin;
> > u16 reg : 11;
> > u16 bit : 5;
> > } pullups[] = {
> > - [RCAR_GP_PIN(2, 11)] = { PU0, 31 }, /* AVB_PHY_INT */
> > - [RCAR_GP_PIN(2, 10)] = { PU0, 30 }, /* AVB_MAGIC */
> > - [RCAR_GP_PIN(2, 9)] = { PU0, 29 }, /* AVB_MDC */
> > -
> > - [RCAR_GP_PIN(1, 19)] = { PU1, 31 }, /* A19 */
> > - [RCAR_GP_PIN(1, 18)] = { PU1, 30 }, /* A18 */
> > - [RCAR_GP_PIN(1, 17)] = { PU1, 29 }, /* A17 */
> > - [RCAR_GP_PIN(1, 16)] = { PU1, 28 }, /* A16 */
> > - [RCAR_GP_PIN(1, 15)] = { PU1, 27 }, /* A15 */
> > - [RCAR_GP_PIN(1, 14)] = { PU1, 26 }, /* A14 */
> > - [RCAR_GP_PIN(1, 13)] = { PU1, 25 }, /* A13 */
> > - [RCAR_GP_PIN(1, 12)] = { PU1, 24 }, /* A12 */
> > - [RCAR_GP_PIN(1, 11)] = { PU1, 23 }, /* A11 */
> > - [RCAR_GP_PIN(1, 10)] = { PU1, 22 }, /* A10 */
> > - [RCAR_GP_PIN(1, 9)] = { PU1, 21 }, /* A9 */
> > - [RCAR_GP_PIN(1, 8)] = { PU1, 20 }, /* A8 */
> > - [RCAR_GP_PIN(1, 7)] = { PU1, 19 }, /* A7 */
> > - [RCAR_GP_PIN(1, 6)] = { PU1, 18 }, /* A6 */
> > - [RCAR_GP_PIN(1, 5)] = { PU1, 17 }, /* A5 */
> > - [RCAR_GP_PIN(1, 4)] = { PU1, 16 }, /* A4 */
> > - [RCAR_GP_PIN(1, 3)] = { PU1, 15 }, /* A3 */
> > - [RCAR_GP_PIN(1, 2)] = { PU1, 14 }, /* A2 */
> > - [RCAR_GP_PIN(1, 1)] = { PU1, 13 }, /* A1 */
> > - [RCAR_GP_PIN(1, 0)] = { PU1, 12 }, /* A0 */
> > - [RCAR_GP_PIN(2, 8)] = { PU1, 11 }, /* PWM2_A */
> > - [RCAR_GP_PIN(2, 7)] = { PU1, 10 }, /* PWM1_A */
> > - [RCAR_GP_PIN(2, 6)] = { PU1, 9 }, /* PWM0 */
> > - [RCAR_GP_PIN(2, 5)] = { PU1, 8 }, /* IRQ5 */
> > - [RCAR_GP_PIN(2, 4)] = { PU1, 7 }, /* IRQ4 */
> > - [RCAR_GP_PIN(2, 3)] = { PU1, 6 }, /* IRQ3 */
> > - [RCAR_GP_PIN(2, 2)] = { PU1, 5 }, /* IRQ2 */
> > - [RCAR_GP_PIN(2, 1)] = { PU1, 4 }, /* IRQ1 */
> > - [RCAR_GP_PIN(2, 0)] = { PU1, 3 }, /* IRQ0 */
> > - [RCAR_GP_PIN(2, 14)] = { PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
> > - [RCAR_GP_PIN(2, 13)] = { PU1, 1 }, /* AVB_AVTP_MATCH_A */
> > - [RCAR_GP_PIN(2, 12)] = { PU1, 0 }, /* AVB_LINK */
> > -
> > - [RCAR_GP_PIN(7, 3)] = { PU2, 29 }, /* HDMI1_CEC */
> > - [RCAR_GP_PIN(7, 2)] = { PU2, 28 }, /* HDMI0_CEC */
> > - [RCAR_GP_PIN(7, 1)] = { PU2, 27 }, /* AVS2 */
> > - [RCAR_GP_PIN(7, 0)] = { PU2, 26 }, /* AVS1 */
> > - [RCAR_GP_PIN(0, 15)] = { PU2, 25 }, /* D15 */
> > - [RCAR_GP_PIN(0, 14)] = { PU2, 24 }, /* D14 */
> > - [RCAR_GP_PIN(0, 13)] = { PU2, 23 }, /* D13 */
> > - [RCAR_GP_PIN(0, 12)] = { PU2, 22 }, /* D12 */
> > - [RCAR_GP_PIN(0, 11)] = { PU2, 21 }, /* D11 */
> > - [RCAR_GP_PIN(0, 10)] = { PU2, 20 }, /* D10 */
> > - [RCAR_GP_PIN(0, 9)] = { PU2, 19 }, /* D9 */
> > - [RCAR_GP_PIN(0, 8)] = { PU2, 18 }, /* D8 */
> > - [RCAR_GP_PIN(0, 7)] = { PU2, 17 }, /* D7 */
> > - [RCAR_GP_PIN(0, 6)] = { PU2, 16 }, /* D6 */
> > - [RCAR_GP_PIN(0, 5)] = { PU2, 15 }, /* D5 */
> > - [RCAR_GP_PIN(0, 4)] = { PU2, 14 }, /* D4 */
> > - [RCAR_GP_PIN(0, 3)] = { PU2, 13 }, /* D3 */
> > - [RCAR_GP_PIN(0, 2)] = { PU2, 12 }, /* D2 */
> > - [RCAR_GP_PIN(0, 1)] = { PU2, 11 }, /* D1 */
> > - [RCAR_GP_PIN(0, 0)] = { PU2, 10 }, /* D0 */
> > - [RCAR_GP_PIN(1, 27)] = { PU2, 8 }, /* EX_WAIT0_A */
> > - [RCAR_GP_PIN(1, 26)] = { PU2, 7 }, /* WE1_N */
> > - [RCAR_GP_PIN(1, 25)] = { PU2, 6 }, /* WE0_N */
> > - [RCAR_GP_PIN(1, 24)] = { PU2, 5 }, /* RD_WR_N */
> > - [RCAR_GP_PIN(1, 23)] = { PU2, 4 }, /* RD_N */
> > - [RCAR_GP_PIN(1, 22)] = { PU2, 3 }, /* BS_N */
> > - [RCAR_GP_PIN(1, 21)] = { PU2, 2 }, /* CS1_N_A26 */
> > - [RCAR_GP_PIN(1, 20)] = { PU2, 1 }, /* CS0_N */
> > -
> > - [RCAR_GP_PIN(4, 9)] = { PU3, 31 }, /* SD3_DAT0 */
> > - [RCAR_GP_PIN(4, 8)] = { PU3, 30 }, /* SD3_CMD */
> > - [RCAR_GP_PIN(4, 7)] = { PU3, 29 }, /* SD3_CLK */
> > - [RCAR_GP_PIN(4, 6)] = { PU3, 28 }, /* SD2_DS */
> > - [RCAR_GP_PIN(4, 5)] = { PU3, 27 }, /* SD2_DAT3 */
> > - [RCAR_GP_PIN(4, 4)] = { PU3, 26 }, /* SD2_DAT2 */
> > - [RCAR_GP_PIN(4, 3)] = { PU3, 25 }, /* SD2_DAT1 */
> > - [RCAR_GP_PIN(4, 2)] = { PU3, 24 }, /* SD2_DAT0 */
> > - [RCAR_GP_PIN(4, 1)] = { PU3, 23 }, /* SD2_CMD */
> > - [RCAR_GP_PIN(4, 0)] = { PU3, 22 }, /* SD2_CLK */
> > - [RCAR_GP_PIN(3, 11)] = { PU3, 21 }, /* SD1_DAT3 */
> > - [RCAR_GP_PIN(3, 10)] = { PU3, 20 }, /* SD1_DAT2 */
> > - [RCAR_GP_PIN(3, 9)] = { PU3, 19 }, /* SD1_DAT1 */
> > - [RCAR_GP_PIN(3, 8)] = { PU3, 18 }, /* SD1_DAT0 */
> > - [RCAR_GP_PIN(3, 7)] = { PU3, 17 }, /* SD1_CMD */
> > - [RCAR_GP_PIN(3, 6)] = { PU3, 16 }, /* SD1_CLK */
> > - [RCAR_GP_PIN(3, 5)] = { PU3, 15 }, /* SD0_DAT3 */
> > - [RCAR_GP_PIN(3, 4)] = { PU3, 14 }, /* SD0_DAT2 */
> > - [RCAR_GP_PIN(3, 3)] = { PU3, 13 }, /* SD0_DAT1 */
> > - [RCAR_GP_PIN(3, 2)] = { PU3, 12 }, /* SD0_DAT0 */
> > - [RCAR_GP_PIN(3, 1)] = { PU3, 11 }, /* SD0_CMD */
> > - [RCAR_GP_PIN(3, 0)] = { PU3, 10 }, /* SD0_CLK */
> > -
> > - [RCAR_GP_PIN(5, 19)] = { PU4, 31 }, /* MSIOF0_SS1 */
> > - [RCAR_GP_PIN(5, 18)] = { PU4, 30 }, /* MSIOF0_SYNC */
> > - [RCAR_GP_PIN(5, 17)] = { PU4, 29 }, /* MSIOF0_SCK */
> > - [RCAR_GP_PIN(5, 16)] = { PU4, 28 }, /* HRTS0_N */
> > - [RCAR_GP_PIN(5, 15)] = { PU4, 27 }, /* HCTS0_N */
> > - [RCAR_GP_PIN(5, 14)] = { PU4, 26 }, /* HTX0 */
> > - [RCAR_GP_PIN(5, 13)] = { PU4, 25 }, /* HRX0 */
> > - [RCAR_GP_PIN(5, 12)] = { PU4, 24 }, /* HSCK0 */
> > - [RCAR_GP_PIN(5, 11)] = { PU4, 23 }, /* RX2_A */
> > - [RCAR_GP_PIN(5, 10)] = { PU4, 22 }, /* TX2_A */
> > - [RCAR_GP_PIN(5, 9)] = { PU4, 21 }, /* SCK2 */
> > - [RCAR_GP_PIN(5, 8)] = { PU4, 20 }, /* RTS1_N_TANS */
> > - [RCAR_GP_PIN(5, 7)] = { PU4, 19 }, /* CTS1_N */
> > - [RCAR_GP_PIN(5, 6)] = { PU4, 18 }, /* TX1_A */
> > - [RCAR_GP_PIN(5, 5)] = { PU4, 17 }, /* RX1_A */
> > - [RCAR_GP_PIN(5, 4)] = { PU4, 16 }, /* RTS0_N_TANS */
> > - [RCAR_GP_PIN(5, 3)] = { PU4, 15 }, /* CTS0_N */
> > - [RCAR_GP_PIN(5, 2)] = { PU4, 14 }, /* TX0 */
> > - [RCAR_GP_PIN(5, 1)] = { PU4, 13 }, /* RX0 */
> > - [RCAR_GP_PIN(5, 0)] = { PU4, 12 }, /* SCK0 */
> > - [RCAR_GP_PIN(3, 15)] = { PU4, 11 }, /* SD1_WP */
> > - [RCAR_GP_PIN(3, 14)] = { PU4, 10 }, /* SD1_CD */
> > - [RCAR_GP_PIN(3, 13)] = { PU4, 9 }, /* SD0_WP */
> > - [RCAR_GP_PIN(3, 12)] = { PU4, 8 }, /* SD0_CD */
> > - [RCAR_GP_PIN(4, 17)] = { PU4, 7 }, /* SD3_DS */
> > - [RCAR_GP_PIN(4, 16)] = { PU4, 6 }, /* SD3_DAT7 */
> > - [RCAR_GP_PIN(4, 15)] = { PU4, 5 }, /* SD3_DAT6 */
> > - [RCAR_GP_PIN(4, 14)] = { PU4, 4 }, /* SD3_DAT5 */
> > - [RCAR_GP_PIN(4, 13)] = { PU4, 3 }, /* SD3_DAT4 */
> > - [RCAR_GP_PIN(4, 12)] = { PU4, 2 }, /* SD3_DAT3 */
> > - [RCAR_GP_PIN(4, 11)] = { PU4, 1 }, /* SD3_DAT2 */
> > - [RCAR_GP_PIN(4, 10)] = { PU4, 0 }, /* SD3_DAT1 */
> > -
> > - [RCAR_GP_PIN(6, 24)] = { PU5, 31 }, /* USB0_PWEN */
> > - [RCAR_GP_PIN(6, 23)] = { PU5, 30 }, /* AUDIO_CLKB_B */
> > - [RCAR_GP_PIN(6, 22)] = { PU5, 29 }, /* AUDIO_CLKA_A */
> > - [RCAR_GP_PIN(6, 21)] = { PU5, 28 }, /* SSI_SDATA9_A */
> > - [RCAR_GP_PIN(6, 20)] = { PU5, 27 }, /* SSI_SDATA8 */
> > - [RCAR_GP_PIN(6, 19)] = { PU5, 26 }, /* SSI_SDATA7 */
> > - [RCAR_GP_PIN(6, 18)] = { PU5, 25 }, /* SSI_WS78 */
> > - [RCAR_GP_PIN(6, 17)] = { PU5, 24 }, /* SSI_SCK78 */
> > - [RCAR_GP_PIN(6, 16)] = { PU5, 23 }, /* SSI_SDATA6 */
> > - [RCAR_GP_PIN(6, 15)] = { PU5, 22 }, /* SSI_WS6 */
> > - [RCAR_GP_PIN(6, 14)] = { PU5, 21 }, /* SSI_SCK6 */
> > - [RCAR_GP_PIN(6, 13)] = { PU5, 20 }, /* SSI_SDATA5 */
> > - [RCAR_GP_PIN(6, 12)] = { PU5, 19 }, /* SSI_WS5 */
> > - [RCAR_GP_PIN(6, 11)] = { PU5, 18 }, /* SSI_SCK5 */
> > - [RCAR_GP_PIN(6, 10)] = { PU5, 17 }, /* SSI_SDATA4 */
> > - [RCAR_GP_PIN(6, 9)] = { PU5, 16 }, /* SSI_WS4 */
> > - [RCAR_GP_PIN(6, 8)] = { PU5, 15 }, /* SSI_SCK4 */
> > - [RCAR_GP_PIN(6, 7)] = { PU5, 14 }, /* SSI_SDATA3 */
> > - [RCAR_GP_PIN(6, 6)] = { PU5, 13 }, /* SSI_WS34 */
> > - [RCAR_GP_PIN(6, 5)] = { PU5, 12 }, /* SSI_SCK34 */
> > - [RCAR_GP_PIN(6, 4)] = { PU5, 11 }, /* SSI_SDATA2_A */
> > - [RCAR_GP_PIN(6, 3)] = { PU5, 10 }, /* SSI_SDATA1_A */
> > - [RCAR_GP_PIN(6, 2)] = { PU5, 9 }, /* SSI_SDATA0 */
> > - [RCAR_GP_PIN(6, 1)] = { PU5, 8 }, /* SSI_WS01239 */
> > - [RCAR_GP_PIN(6, 0)] = { PU5, 7 }, /* SSI_SCK01239 */
> > - [RCAR_GP_PIN(5, 25)] = { PU5, 5 }, /* MLB_DAT */
> > - [RCAR_GP_PIN(5, 24)] = { PU5, 4 }, /* MLB_SIG */
> > - [RCAR_GP_PIN(5, 23)] = { PU5, 3 }, /* MLB_CLK */
> > - [RCAR_GP_PIN(5, 22)] = { PU5, 2 }, /* MSIOF0_RXD */
> > - [RCAR_GP_PIN(5, 21)] = { PU5, 1 }, /* MSIOF0_SS2 */
> > - [RCAR_GP_PIN(5, 20)] = { PU5, 0 }, /* MSIOF0_TXD */
> > -
> > - [RCAR_GP_PIN(6, 31)] = { PU6, 6 }, /* USB31_OVC */
> > - [RCAR_GP_PIN(6, 30)] = { PU6, 5 }, /* USB31_PWEN */
> > - [RCAR_GP_PIN(6, 29)] = { PU6, 4 }, /* USB30_OVC */
> > - [RCAR_GP_PIN(6, 28)] = { PU6, 3 }, /* USB30_PWEN */
> > - [RCAR_GP_PIN(6, 27)] = { PU6, 2 }, /* USB1_OVC */
> > - [RCAR_GP_PIN(6, 26)] = { PU6, 1 }, /* USB1_PWEN */
> > - [RCAR_GP_PIN(6, 25)] = { PU6, 0 }, /* USB0_OVC */
> > -};
> > + { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
> > + { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
> > + { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
> > +
> > + { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
> > + { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
> > + { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
> > + { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
> > + { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
> > + { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
> > + { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
> > + { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
> > + { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
> > + { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
> > + { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
> > + { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
> > + { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
> > + { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
> > + { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
> > + { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
> > + { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
> > + { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
> > + { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
> > + { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
> > + { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
> > + { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
> > + { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
> > + { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
> > + { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
> > + { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
> > + { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
> > + { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
> > + { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
> > + { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
> > + { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
> > + { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
> > +
> > + { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */
> > + { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
> > + { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
> > + { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
> > + { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
> > + { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
> > + { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
> > + { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
> > + { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
> > + { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
> > + { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
> > + { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
> > + { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
> > + { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
> > + { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
> > + { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
> > + { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
> > + { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
> > + { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
> > + { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
> > + { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
> > + { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
> > + { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
> > + { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
> > + { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
> > + { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
> > + { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */
> > + { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
> > +
> > + { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
> > + { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
> > + { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
> > + { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
> > + { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
> > + { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
> > + { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
> > + { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
> > + { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
> > + { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
> > + { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
> > + { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
> > + { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
> > + { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
> > + { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
> > + { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
> > + { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
> > + { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
> > + { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
> > + { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
> > + { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
> > + { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
> > +
> > + { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
> > + { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
> > + { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
> > + { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
> > + { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
> > + { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
> > + { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
> > + { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
> > + { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
> > + { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
> > + { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
> > + { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
> > + { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
> > + { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
> > + { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
> > + { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
> > + { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
> > + { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
> > + { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
> > + { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
> > + { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
> > + { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
> > + { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
> > + { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
> > + { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
> > + { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
> > + { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
> > + { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
> > + { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
> > + { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
> > + { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
> > + { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
> > +
> > + { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
> > + { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
> > + { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
> > + { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
> > + { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
> > + { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
> > + { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
> > + { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
> > + { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
> > + { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
> > + { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
> > + { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
> > + { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
> > + { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
> > + { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
> > + { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
> > + { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
> > + { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
> > + { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */
> > + { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */
> > + { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
> > + { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
> > + { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
> > + { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
> > + { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
> > + { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
> > + { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
> > + { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
> > + { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
> > + { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
> > + { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
> > +
> > + { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB31_OVC */
> > + { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB31_PWEN */
> > + { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
> > + { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
> > + { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
> > + { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
> > + { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
> > +};
> > +
> > +static int r8a7795_pin_to_bias_data(unsigned int pin, u32 *reg, u32 *bit)
> > +{
> > + unsigned int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(pullups); i++) {
> > + if (pullups[i].pin == pin) {
> > + *reg = pullups[i].reg;
> > + *bit = BIT(pullups[i].bit);
> > + return 0;
> > + }
> > + }
> > +
> > + return -EINVAL;
> > +}
> >
> > static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
> > unsigned int pin)
> > @@ -5361,12 +5377,9 @@ static unsigned int r8a7795_pinmux_get_bias(struct
> > sh_pfc *pfc, u32 reg;
> > u32 bit;
> >
> > - if (WARN_ON_ONCE(!pullups[pin].reg))
> > + if (WARN_ON_ONCE(r8a7795_pin_to_bias_data(pin, ®, &bit)))
> > return PIN_CONFIG_BIAS_DISABLE;
> >
> > - reg = pullups[pin].reg;
> > - bit = BIT(pullups[pin].bit);
> > -
> > if (sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit) {
> > if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
> > return PIN_CONFIG_BIAS_PULL_UP;
>
> Slightly out of scope, but the following code
>
> if (sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit) {
> if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
> return PIN_CONFIG_BIAS_PULL_UP;
> else
> return PIN_CONFIG_BIAS_PULL_DOWN;
> } else
> return PIN_CONFIG_BIAS_DISABLE;
>
> misses braces around the else. It could be written
>
> if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
> return PIN_CONFIG_BIAS_DISABLE;
> else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
> return PIN_CONFIG_BIAS_PULL_UP;
> else
> return PIN_CONFIG_BIAS_PULL_DOWN;
I can include a patch fixing this up in my v3.
>
> > @@ -5383,12 +5396,9 @@ static void r8a7795_pinmux_set_bias(struct sh_pfc
> > *pfc, unsigned int pin, u32 reg;
> > u32 bit;
> >
> > - if (WARN_ON_ONCE(!pullups[pin].reg))
> > + if (WARN_ON_ONCE(r8a7795_pin_to_bias_data(pin, ®, &bit)))
> > return;
> >
> > - reg = pullups[pin].reg;
> > - bit = BIT(pullups[pin].bit);
> > -
> > enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
> > if (bias != PIN_CONFIG_BIAS_DISABLE)
> > enable |= bit;
>
--
Regards,
Niklas S�derlund
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] pinctrl: sh-pfc: Do not unconditionally support PIN_CONFIG_BIAS_DISABLE
2016-11-03 15:34 ` [PATCH 1/2] pinctrl: sh-pfc: Do not unconditionally support PIN_CONFIG_BIAS_DISABLE Niklas Söderlund
2016-11-03 16:55 ` Laurent Pinchart
@ 2016-11-07 10:33 ` Geert Uytterhoeven
1 sibling, 0 replies; 13+ messages in thread
From: Geert Uytterhoeven @ 2016-11-07 10:33 UTC (permalink / raw)
To: Niklas Söderlund
Cc: Geert Uytterhoeven, Laurent Pinchart, Linus Walleij,
Linux-Renesas, linux-gpio
On Thu, Nov 3, 2016 at 4:34 PM, Niklas Söderlund
<niklas.soderlund+renesas@ragnatech.se> wrote:
> Always stating PIN_CONFIG_BIAS_DISABLE is supported gives untrue output
> when examining /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins if
> the operation get_bias() are implemented but the pin are not handled by
is implemented
is not handled
> the get_bias() implementation. In that case the output will state that
> "input bias disabled" indicating that this pin have bias control
has
> support.
>
> Make support for PIN_CONFIG_BIAS_DISABLE depend on that the pin either
> support SH_PFC_PIN_CFG_PULL_UP or SH_PFC_PIN_CFG_PULL_DOWN. This also
supports
> solves the issue where SoC specific implementations print error messages
> if there particular implementation of {set,get}_bias() is called with a
their
> pin it do not know about.
does
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] pinctrl: sh-pfc: r8a7795: Use lookup function for bias data
2016-11-03 17:10 ` Laurent Pinchart
2016-11-03 19:26 ` Niklas Söderlund
@ 2016-11-07 10:57 ` Geert Uytterhoeven
2016-11-07 12:23 ` Niklas Söderlund
2016-11-09 10:43 ` Laurent Pinchart
1 sibling, 2 replies; 13+ messages in thread
From: Geert Uytterhoeven @ 2016-11-07 10:57 UTC (permalink / raw)
To: Laurent Pinchart
Cc: Niklas Söderlund, Geert Uytterhoeven, Linus Walleij,
Linux-Renesas, linux-gpio
On Thu, Nov 3, 2016 at 6:10 PM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
> On Thursday 03 Nov 2016 16:34:21 Niklas Söderlund wrote:
>> There is a bug in the r8a7795 bias code where a WARN() is trigged
>> anytime a pin from PUEN0/PUD0is accessed.
>>
>> # cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins
>>
>> WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364
>> r8a7795_pinmux_get_bias+0xbc/0xc8 [..]
>> Call trace:
>> [<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8
>> [<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270
>> [<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30
>> [<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188
>> [<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98
>> [<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128
>> [<ffff0000081fe3bc>] seq_read+0x16c/0x420
>> [<ffff00000831a110>] full_proxy_read+0x58/0x88
>> [<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8
>> [<ffff0000081d8874>] vfs_read+0x84/0x148
>> [<ffff0000081d9d64>] SyS_read+0x44/0xa0
>> [<ffff000008082f4c>] __sys_trace_return+0x0/0x4
>>
>> This is due to the WARN() check if the reg field of the pullups struct
>> is zero, and this should be 0 for pins controlled by the PUEN0/PUD0
>> registers. Change the layout of the pullups struct to embed the pin
>> number inside the struct and loop over it to fetch the correct
>> information or WARN() if no pin is found.
>
> This lowers the memory consumption at the cost of increased CPU usage. Given
> that the get/set bias functions are not part of a critical path I'm fine with
> that. We could possibly optimize the implementation by using a dichotomic
> search, but I don't think that's needed at the moment.
Alternatively, we could steal one bit from the "reg" bitifield to
add a "present" bit, without increasing the table size:
static const struct {
u16 present : 1;
u16 reg : 10;
u16 bit : 5;
} pullups[] = {
While 10 bits is not sufficient in general (the PFC register block size
is 0x50c), it's good enough to address the PUx registers. And if needed,
we can switch from register byte offsets to register indices, indexing the
32-bit register file.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] pinctrl: sh-pfc: r8a7795: Use lookup function for bias data
2016-11-07 10:57 ` Geert Uytterhoeven
@ 2016-11-07 12:23 ` Niklas Söderlund
2016-11-09 10:43 ` Laurent Pinchart
1 sibling, 0 replies; 13+ messages in thread
From: Niklas Söderlund @ 2016-11-07 12:23 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Laurent Pinchart, Geert Uytterhoeven, Linus Walleij,
Linux-Renesas, linux-gpio
On 2016-11-07 11:57:36 +0100, Geert Uytterhoeven wrote:
> On Thu, Nov 3, 2016 at 6:10 PM, Laurent Pinchart
> <laurent.pinchart@ideasonboard.com> wrote:
> > On Thursday 03 Nov 2016 16:34:21 Niklas Söderlund wrote:
> >> There is a bug in the r8a7795 bias code where a WARN() is trigged
> >> anytime a pin from PUEN0/PUD0is accessed.
> >>
> >> # cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins
> >>
> >> WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364
> >> r8a7795_pinmux_get_bias+0xbc/0xc8 [..]
> >> Call trace:
> >> [<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8
> >> [<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270
> >> [<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30
> >> [<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188
> >> [<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98
> >> [<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128
> >> [<ffff0000081fe3bc>] seq_read+0x16c/0x420
> >> [<ffff00000831a110>] full_proxy_read+0x58/0x88
> >> [<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8
> >> [<ffff0000081d8874>] vfs_read+0x84/0x148
> >> [<ffff0000081d9d64>] SyS_read+0x44/0xa0
> >> [<ffff000008082f4c>] __sys_trace_return+0x0/0x4
> >>
> >> This is due to the WARN() check if the reg field of the pullups struct
> >> is zero, and this should be 0 for pins controlled by the PUEN0/PUD0
> >> registers. Change the layout of the pullups struct to embed the pin
> >> number inside the struct and loop over it to fetch the correct
> >> information or WARN() if no pin is found.
> >
> > This lowers the memory consumption at the cost of increased CPU usage. Given
> > that the get/set bias functions are not part of a critical path I'm fine with
> > that. We could possibly optimize the implementation by using a dichotomic
> > search, but I don't think that's needed at the moment.
>
> Alternatively, we could steal one bit from the "reg" bitifield to
> add a "present" bit, without increasing the table size:
>
> static const struct {
> u16 present : 1;
> u16 reg : 10;
> u16 bit : 5;
> } pullups[] = {
>
> While 10 bits is not sufficient in general (the PFC register block size
> is 0x50c), it's good enough to address the PUx registers. And if needed,
> we can switch from register byte offsets to register indices, indexing the
> 32-bit register file.
I think this is a solution to consider. Before we decide on how to move
forward I would like to also consider what you and I talked about on IRC
about how this table will look if bias support are added for non GPIO
pins.
If we keep using the H3SiP physical pin layout as the method to generate
unique pin numbers for pins without GPIO, this is done on the series
which adds drive-strength support to the r8a7795 SoC. Then the largest
pin number which will be used as an index in this array would be 2085
instead of 227 as it is today.
Snippet from /sys/kernel/debug/pinctrl/e6060000.pfc/pins with the
drive-strength patch applied:
<snip>
pin 223 (GP_6_31) sh-pfc
pin 224 (GP_7_0) sh-pfc
pin 225 (GP_7_1) sh-pfc
pin 226 (GP_7_2) sh-pfc
pin 227 (GP_7_3) sh-pfc
pin 308 (PIN_AVB_TX_CTL) sh-pfc
pin 309 (PIN_AVB_MDIO) sh-pfc
pin 312 (PIN_AVB_TXCREFCLK) sh-pfc
pin 313 (PIN_AVB_RD0) sh-pfc
pin 314 (PIN_AVB_RD2) sh-pfc
pin 316 (PIN_AVB_RX_CTL) sh-pfc
pin 317 (PIN_AVB_TD2) sh-pfc
pin 318 (PIN_AVB_TD0) sh-pfc
pin 319 (PIN_AVB_TXC) sh-pfc
pin 352 (PIN_AVB_RD1) sh-pfc
pin 353 (PIN_AVB_RD3) sh-pfc
pin 356 (PIN_AVB_TD3) sh-pfc
pin 357 (PIN_AVB_TD1) sh-pfc
pin 358 (PIN_AVB_RXC) sh-pfc
pin 379 (PIN_PRESETOUT#) sh-pfc
pin 496 (PIN_CLKOUT) sh-pfc
pin 610 (PIN_MLB_REF) sh-pfc
pin 1122 (PIN_QSPI1_SPCLK) sh-pfc
pin 1124 (PIN_QSPI1_SSL) sh-pfc
pin 1125 (PIN_RPC_WP#) sh-pfc
pin 1126 (PIN_RPC_RESET#) sh-pfc
pin 1161 (PIN_QSPI0_SPCLK) sh-pfc
pin 1239 (PIN_QSPI0_SSL) sh-pfc
pin 1242 (PIN_QSPI0_IO2) sh-pfc
pin 1243 (PIN_RPC_INT#) sh-pfc
pin 1357 (PIN_QSPI0_MISO_IO1) sh-pfc
pin 1359 (PIN_QSPI0_IO3) sh-pfc
pin 1395 (PIN_QSPI1_IO3) sh-pfc
pin 1397 (PIN_QSPI0_MOSI_IO0) sh-pfc
pin 1399 (PIN_QSPI1_MOSI_IO0) sh-pfc
pin 1469 (PIN_FSCLKST#) sh-pfc
pin 1474 (PIN_QSPI1_IO2) sh-pfc
pin 1475 (PIN_QSPI1_MISO_IO1) sh-pfc
pin 1906 (PIN_DU_DOTCLKIN0) sh-pfc
pin 1907 (PIN_DU_DOTCLKIN1) sh-pfc
pin 1984 (PIN_DU_DOTCLKIN2) sh-pfc
pin 1985 (PIN_DU_DOTCLKIN3) sh-pfc
pin 2007 (PIN_TMS) sh-pfc
pin 2083 (PIN_TDO) sh-pfc
pin 2085 (PIN_ASEBRK) sh-pfc
Pins with a number lower then 300 are GPIO pins and above are pins which
do not have a GPIO function. So if we where to go with the solution to
use a 'present' bit that would grow the lookup table quiet a lot when
bias for non GPIO pins are added, also the array would mostly be entries
where the 'present' bit is not set.
I'm fine with either solution, Laurent what do you think? I will hold
off a few days with posting a v2 so we can agree on the best solution
for this.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
--
Regards,
Niklas Söderlund
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] pinctrl: sh-pfc: r8a7795: Use lookup function for bias data
@ 2016-11-07 12:23 ` Niklas Söderlund
0 siblings, 0 replies; 13+ messages in thread
From: Niklas Söderlund @ 2016-11-07 12:23 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Laurent Pinchart, Geert Uytterhoeven, Linus Walleij,
Linux-Renesas, linux-gpio
On 2016-11-07 11:57:36 +0100, Geert Uytterhoeven wrote:
> On Thu, Nov 3, 2016 at 6:10 PM, Laurent Pinchart
> <laurent.pinchart@ideasonboard.com> wrote:
> > On Thursday 03 Nov 2016 16:34:21 Niklas S�derlund wrote:
> >> There is a bug in the r8a7795 bias code where a WARN() is trigged
> >> anytime a pin from PUEN0/PUD0is accessed.
> >>
> >> # cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins
> >>
> >> WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364
> >> r8a7795_pinmux_get_bias+0xbc/0xc8 [..]
> >> Call trace:
> >> [<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8
> >> [<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270
> >> [<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30
> >> [<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188
> >> [<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98
> >> [<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128
> >> [<ffff0000081fe3bc>] seq_read+0x16c/0x420
> >> [<ffff00000831a110>] full_proxy_read+0x58/0x88
> >> [<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8
> >> [<ffff0000081d8874>] vfs_read+0x84/0x148
> >> [<ffff0000081d9d64>] SyS_read+0x44/0xa0
> >> [<ffff000008082f4c>] __sys_trace_return+0x0/0x4
> >>
> >> This is due to the WARN() check if the reg field of the pullups struct
> >> is zero, and this should be 0 for pins controlled by the PUEN0/PUD0
> >> registers. Change the layout of the pullups struct to embed the pin
> >> number inside the struct and loop over it to fetch the correct
> >> information or WARN() if no pin is found.
> >
> > This lowers the memory consumption at the cost of increased CPU usage. Given
> > that the get/set bias functions are not part of a critical path I'm fine with
> > that. We could possibly optimize the implementation by using a dichotomic
> > search, but I don't think that's needed at the moment.
>
> Alternatively, we could steal one bit from the "reg" bitifield to
> add a "present" bit, without increasing the table size:
>
> static const struct {
> u16 present : 1;
> u16 reg : 10;
> u16 bit : 5;
> } pullups[] = {
>
> While 10 bits is not sufficient in general (the PFC register block size
> is 0x50c), it's good enough to address the PUx registers. And if needed,
> we can switch from register byte offsets to register indices, indexing the
> 32-bit register file.
I think this is a solution to consider. Before we decide on how to move
forward I would like to also consider what you and I talked about on IRC
about how this table will look if bias support are added for non GPIO
pins.
If we keep using the H3SiP physical pin layout as the method to generate
unique pin numbers for pins without GPIO, this is done on the series
which adds drive-strength support to the r8a7795 SoC. Then the largest
pin number which will be used as an index in this array would be 2085
instead of 227 as it is today.
Snippet from /sys/kernel/debug/pinctrl/e6060000.pfc/pins with the
drive-strength patch applied:
<snip>
pin 223 (GP_6_31) sh-pfc
pin 224 (GP_7_0) sh-pfc
pin 225 (GP_7_1) sh-pfc
pin 226 (GP_7_2) sh-pfc
pin 227 (GP_7_3) sh-pfc
pin 308 (PIN_AVB_TX_CTL) sh-pfc
pin 309 (PIN_AVB_MDIO) sh-pfc
pin 312 (PIN_AVB_TXCREFCLK) sh-pfc
pin 313 (PIN_AVB_RD0) sh-pfc
pin 314 (PIN_AVB_RD2) sh-pfc
pin 316 (PIN_AVB_RX_CTL) sh-pfc
pin 317 (PIN_AVB_TD2) sh-pfc
pin 318 (PIN_AVB_TD0) sh-pfc
pin 319 (PIN_AVB_TXC) sh-pfc
pin 352 (PIN_AVB_RD1) sh-pfc
pin 353 (PIN_AVB_RD3) sh-pfc
pin 356 (PIN_AVB_TD3) sh-pfc
pin 357 (PIN_AVB_TD1) sh-pfc
pin 358 (PIN_AVB_RXC) sh-pfc
pin 379 (PIN_PRESETOUT#) sh-pfc
pin 496 (PIN_CLKOUT) sh-pfc
pin 610 (PIN_MLB_REF) sh-pfc
pin 1122 (PIN_QSPI1_SPCLK) sh-pfc
pin 1124 (PIN_QSPI1_SSL) sh-pfc
pin 1125 (PIN_RPC_WP#) sh-pfc
pin 1126 (PIN_RPC_RESET#) sh-pfc
pin 1161 (PIN_QSPI0_SPCLK) sh-pfc
pin 1239 (PIN_QSPI0_SSL) sh-pfc
pin 1242 (PIN_QSPI0_IO2) sh-pfc
pin 1243 (PIN_RPC_INT#) sh-pfc
pin 1357 (PIN_QSPI0_MISO_IO1) sh-pfc
pin 1359 (PIN_QSPI0_IO3) sh-pfc
pin 1395 (PIN_QSPI1_IO3) sh-pfc
pin 1397 (PIN_QSPI0_MOSI_IO0) sh-pfc
pin 1399 (PIN_QSPI1_MOSI_IO0) sh-pfc
pin 1469 (PIN_FSCLKST#) sh-pfc
pin 1474 (PIN_QSPI1_IO2) sh-pfc
pin 1475 (PIN_QSPI1_MISO_IO1) sh-pfc
pin 1906 (PIN_DU_DOTCLKIN0) sh-pfc
pin 1907 (PIN_DU_DOTCLKIN1) sh-pfc
pin 1984 (PIN_DU_DOTCLKIN2) sh-pfc
pin 1985 (PIN_DU_DOTCLKIN3) sh-pfc
pin 2007 (PIN_TMS) sh-pfc
pin 2083 (PIN_TDO) sh-pfc
pin 2085 (PIN_ASEBRK) sh-pfc
Pins with a number lower then 300 are GPIO pins and above are pins which
do not have a GPIO function. So if we where to go with the solution to
use a 'present' bit that would grow the lookup table quiet a lot when
bias for non GPIO pins are added, also the array would mostly be entries
where the 'present' bit is not set.
I'm fine with either solution, Laurent what do you think? I will hold
off a few days with posting a v2 so we can agree on the best solution
for this.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
--
Regards,
Niklas S�derlund
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] pinctrl: sh-pfc: r8a7795: Use lookup function for bias data
2016-11-07 10:57 ` Geert Uytterhoeven
2016-11-07 12:23 ` Niklas Söderlund
@ 2016-11-09 10:43 ` Laurent Pinchart
2016-11-09 12:30 ` Geert Uytterhoeven
1 sibling, 1 reply; 13+ messages in thread
From: Laurent Pinchart @ 2016-11-09 10:43 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Niklas Söderlund, Geert Uytterhoeven, Linus Walleij,
Linux-Renesas, linux-gpio
Hi Geert,
On Monday 07 Nov 2016 11:57:36 Geert Uytterhoeven wrote:
> On Thu, Nov 3, 2016 at 6:10 PM, Laurent Pinchart wrote:
> > On Thursday 03 Nov 2016 16:34:21 Niklas Söderlund wrote:
> >> There is a bug in the r8a7795 bias code where a WARN() is trigged
> >> anytime a pin from PUEN0/PUD0is accessed.
> >>
> >> # cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins
> >>
> >> WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364
> >>
> >> r8a7795_pinmux_get_bias+0xbc/0xc8 [..]
> >>
> >> Call trace:
> >> [<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8
> >> [<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270
> >> [<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30
> >> [<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188
> >> [<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98
> >> [<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128
> >> [<ffff0000081fe3bc>] seq_read+0x16c/0x420
> >> [<ffff00000831a110>] full_proxy_read+0x58/0x88
> >> [<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8
> >> [<ffff0000081d8874>] vfs_read+0x84/0x148
> >> [<ffff0000081d9d64>] SyS_read+0x44/0xa0
> >> [<ffff000008082f4c>] __sys_trace_return+0x0/0x4
> >>
> >> This is due to the WARN() check if the reg field of the pullups struct
> >> is zero, and this should be 0 for pins controlled by the PUEN0/PUD0
> >> registers. Change the layout of the pullups struct to embed the pin
> >> number inside the struct and loop over it to fetch the correct
> >> information or WARN() if no pin is found.
> >
> > This lowers the memory consumption at the cost of increased CPU usage.
> > Given that the get/set bias functions are not part of a critical path I'm
> > fine with that. We could possibly optimize the implementation by using a
> > dichotomic search, but I don't think that's needed at the moment.
>
> Alternatively, we could steal one bit from the "reg" bitifield to
> add a "present" bit, without increasing the table size:
That's an option too, but given how sparsely populated the table is at the
moment, I'd prefer lowering the memory consumption by moving the pin number in
the table and removing unused entries. The increase in CPU time could be
further limited by using a dichotomic search if needed.
> static const struct {
> u16 present : 1;
> u16 reg : 10;
> u16 bit : 5;
> } pullups[] = {
>
> While 10 bits is not sufficient in general (the PFC register block size
> is 0x50c), it's good enough to address the PUx registers. And if needed,
> we can switch from register byte offsets to register indices, indexing the
> 32-bit register file.
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] pinctrl: sh-pfc: r8a7795: Use lookup function for bias data
2016-11-09 10:43 ` Laurent Pinchart
@ 2016-11-09 12:30 ` Geert Uytterhoeven
0 siblings, 0 replies; 13+ messages in thread
From: Geert Uytterhoeven @ 2016-11-09 12:30 UTC (permalink / raw)
To: Laurent Pinchart
Cc: Niklas Söderlund, Geert Uytterhoeven, Linus Walleij,
Linux-Renesas, linux-gpio
Hi Laurent,
On Wed, Nov 9, 2016 at 11:43 AM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
> On Monday 07 Nov 2016 11:57:36 Geert Uytterhoeven wrote:
>> On Thu, Nov 3, 2016 at 6:10 PM, Laurent Pinchart wrote:
>> > On Thursday 03 Nov 2016 16:34:21 Niklas Söderlund wrote:
>> >> There is a bug in the r8a7795 bias code where a WARN() is trigged
>> >> anytime a pin from PUEN0/PUD0is accessed.
>> >> # cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins
>> >>
>> >> WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364
>> >>
>> >> r8a7795_pinmux_get_bias+0xbc/0xc8 [..]
>> >>
>> >> Call trace:
>> >> [<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8
>> >> [<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270
>> >> [<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30
>> >> [<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188
>> >> [<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98
>> >> [<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128
>> >> [<ffff0000081fe3bc>] seq_read+0x16c/0x420
>> >> [<ffff00000831a110>] full_proxy_read+0x58/0x88
>> >> [<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8
>> >> [<ffff0000081d8874>] vfs_read+0x84/0x148
>> >> [<ffff0000081d9d64>] SyS_read+0x44/0xa0
>> >> [<ffff000008082f4c>] __sys_trace_return+0x0/0x4
>> >>
>> >> This is due to the WARN() check if the reg field of the pullups struct
>> >> is zero, and this should be 0 for pins controlled by the PUEN0/PUD0
>> >> registers. Change the layout of the pullups struct to embed the pin
>> >> number inside the struct and loop over it to fetch the correct
>> >> information or WARN() if no pin is found.
>> >
>> > This lowers the memory consumption at the cost of increased CPU usage.
>> > Given that the get/set bias functions are not part of a critical path I'm
>> > fine with that. We could possibly optimize the implementation by using a
>> > dichotomic search, but I don't think that's needed at the moment.
>>
>> Alternatively, we could steal one bit from the "reg" bitifield to
>> add a "present" bit, without increasing the table size:
>
> That's an option too, but given how sparsely populated the table is at the
> moment, I'd prefer lowering the memory consumption by moving the pin number in
> the table and removing unused entries. The increase in CPU time could be
> further limited by using a dichotomic search if needed.
After discussing with Niklas, I agree.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2016-11-09 12:30 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-11-03 15:34 [PATCH 0/2] pinctrl: sh-pfc: Fixups for bias handeling Niklas Söderlund
2016-11-03 15:34 ` [PATCH 1/2] pinctrl: sh-pfc: Do not unconditionally support PIN_CONFIG_BIAS_DISABLE Niklas Söderlund
2016-11-03 16:55 ` Laurent Pinchart
2016-11-07 10:33 ` Geert Uytterhoeven
2016-11-03 15:34 ` [PATCH 2/2] pinctrl: sh-pfc: r8a7795: Use lookup function for bias data Niklas Söderlund
2016-11-03 17:10 ` Laurent Pinchart
2016-11-03 19:26 ` Niklas Söderlund
2016-11-03 19:26 ` Niklas Söderlund
2016-11-07 10:57 ` Geert Uytterhoeven
2016-11-07 12:23 ` Niklas Söderlund
2016-11-07 12:23 ` Niklas Söderlund
2016-11-09 10:43 ` Laurent Pinchart
2016-11-09 12:30 ` Geert Uytterhoeven
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