* [PATCH] drm/i915: Mark CPU cache as dirty when used for rendering
@ 2016-11-07 15:46 ` Chris Wilson
0 siblings, 0 replies; 9+ messages in thread
From: Chris Wilson @ 2016-11-07 15:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson, Jani Nikula, Ville Syrjälä, # v4 . 0+
On LLC, or even snooped, machines rendering via the GPU ends up in the CPU
cache. This cacheline dirt also needs to be flushed to main memory when
moving to an incoherent domain, such as the display's scanout engine.
Mostly, this happens because either the object is marked as dirty from
its first use or is avoided by setting the object into the display
domain from the start.
Fixes: 0f71979ab7fb ("drm/i915: Performed deferred clflush inside set-cache-level")
References: https://bugs.freedesktop.org/show_bug.cgi?id=95414
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: <stable@vger.kernel.org> # v4.0+
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 30f6eb516ca3..30b684fecf09 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1282,6 +1282,7 @@ void i915_vma_move_to_active(struct i915_vma *vma,
/* update for the implicit flush after a batch */
obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
+ obj->cache_dirty |= obj->cache_level != I915_CACHE_NONE;
}
if (flags & EXEC_OBJECT_NEEDS_FENCE)
--
2.10.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH] drm/i915: Mark CPU cache as dirty when used for rendering
@ 2016-11-07 15:46 ` Chris Wilson
0 siblings, 0 replies; 9+ messages in thread
From: Chris Wilson @ 2016-11-07 15:46 UTC (permalink / raw)
To: intel-gfx; +Cc: # v4 . 0+
On LLC, or even snooped, machines rendering via the GPU ends up in the CPU
cache. This cacheline dirt also needs to be flushed to main memory when
moving to an incoherent domain, such as the display's scanout engine.
Mostly, this happens because either the object is marked as dirty from
its first use or is avoided by setting the object into the display
domain from the start.
Fixes: 0f71979ab7fb ("drm/i915: Performed deferred clflush inside set-cache-level")
References: https://bugs.freedesktop.org/show_bug.cgi?id=95414
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: <stable@vger.kernel.org> # v4.0+
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 30f6eb516ca3..30b684fecf09 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1282,6 +1282,7 @@ void i915_vma_move_to_active(struct i915_vma *vma,
/* update for the implicit flush after a batch */
obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
+ obj->cache_dirty |= obj->cache_level != I915_CACHE_NONE;
}
if (flags & EXEC_OBJECT_NEEDS_FENCE)
--
2.10.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Mark CPU cache as dirty when used for rendering
2016-11-07 15:46 ` Chris Wilson
(?)
@ 2016-11-07 16:16 ` Patchwork
-1 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2016-11-07 16:16 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Mark CPU cache as dirty when used for rendering
URL : https://patchwork.freedesktop.org/series/14930/
State : success
== Summary ==
Series 14930v1 drm/i915: Mark CPU cache as dirty when used for rendering
https://patchwork.freedesktop.org/api/1.0/series/14930/revisions/1/mbox/
fi-bdw-5557u total:241 pass:226 dwarn:0 dfail:0 fail:0 skip:15
fi-bsw-n3050 total:241 pass:201 dwarn:0 dfail:0 fail:0 skip:40
fi-bxt-t5700 total:241 pass:213 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-j1900 total:241 pass:213 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-n2820 total:241 pass:209 dwarn:0 dfail:0 fail:0 skip:32
fi-hsw-4770 total:241 pass:221 dwarn:0 dfail:0 fail:0 skip:20
fi-hsw-4770r total:241 pass:221 dwarn:0 dfail:0 fail:0 skip:20
fi-ilk-650 total:241 pass:188 dwarn:0 dfail:0 fail:0 skip:53
fi-ivb-3520m total:241 pass:219 dwarn:0 dfail:0 fail:0 skip:22
fi-ivb-3770 total:241 pass:219 dwarn:0 dfail:0 fail:0 skip:22
fi-kbl-7200u total:241 pass:219 dwarn:0 dfail:0 fail:0 skip:22
fi-skl-6260u total:241 pass:227 dwarn:0 dfail:0 fail:0 skip:14
fi-skl-6700hq total:241 pass:220 dwarn:0 dfail:0 fail:0 skip:21
fi-skl-6700k total:241 pass:219 dwarn:1 dfail:0 fail:0 skip:21
fi-skl-6770hq total:241 pass:227 dwarn:0 dfail:0 fail:0 skip:14
fi-snb-2520m total:241 pass:209 dwarn:0 dfail:0 fail:0 skip:32
fi-snb-2600 total:241 pass:208 dwarn:0 dfail:0 fail:0 skip:33
44f80301cde325b9a33e594f8bec88f84e02fffa drm-intel-nightly: 2016y-11m-07d-12h-48m-36s UTC integration manifest
6eeb625 drm/i915: Mark CPU cache as dirty when used for rendering
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2922/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: Mark CPU cache as dirty when used for rendering
2016-11-07 15:46 ` Chris Wilson
@ 2016-11-07 16:35 ` Ville Syrjälä
-1 siblings, 0 replies; 9+ messages in thread
From: Ville Syrjälä @ 2016-11-07 16:35 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx, Jani Nikula, # v4 . 0+
On Mon, Nov 07, 2016 at 03:46:28PM +0000, Chris Wilson wrote:
> On LLC, or even snooped, machines rendering via the GPU ends up in the CPU
> cache. This cacheline dirt also needs to be flushed to main memory when
> moving to an incoherent domain, such as the display's scanout engine.
> Mostly, this happens because either the object is marked as dirty from
> its first use or is avoided by setting the object into the display
> domain from the start.
>
> Fixes: 0f71979ab7fb ("drm/i915: Performed deferred clflush inside set-cache-level")
> References: https://bugs.freedesktop.org/show_bug.cgi?id=95414
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrj�l� <ville.syrjala@linux.intel.com>
> Cc: <stable@vger.kernel.org> # v4.0+
> ---
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index 30f6eb516ca3..30b684fecf09 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -1282,6 +1282,7 @@ void i915_vma_move_to_active(struct i915_vma *vma,
>
> /* update for the implicit flush after a batch */
> obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
> + obj->cache_dirty |= obj->cache_level != I915_CACHE_NONE;
I915_CACHE_WT shouldn't dirty the cache either, so could be excluded
as well.
Everything else makes sense
Reviewed-by: Ville Syrj�l� <ville.syrjala@linux.intel.com>
> }
>
> if (flags & EXEC_OBJECT_NEEDS_FENCE)
> --
> 2.10.2
--
Ville Syrj�l�
Intel OTC
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: Mark CPU cache as dirty when used for rendering
@ 2016-11-07 16:35 ` Ville Syrjälä
0 siblings, 0 replies; 9+ messages in thread
From: Ville Syrjälä @ 2016-11-07 16:35 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx, Jani Nikula, # v4 . 0+
On Mon, Nov 07, 2016 at 03:46:28PM +0000, Chris Wilson wrote:
> On LLC, or even snooped, machines rendering via the GPU ends up in the CPU
> cache. This cacheline dirt also needs to be flushed to main memory when
> moving to an incoherent domain, such as the display's scanout engine.
> Mostly, this happens because either the object is marked as dirty from
> its first use or is avoided by setting the object into the display
> domain from the start.
>
> Fixes: 0f71979ab7fb ("drm/i915: Performed deferred clflush inside set-cache-level")
> References: https://bugs.freedesktop.org/show_bug.cgi?id=95414
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: <stable@vger.kernel.org> # v4.0+
> ---
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index 30f6eb516ca3..30b684fecf09 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -1282,6 +1282,7 @@ void i915_vma_move_to_active(struct i915_vma *vma,
>
> /* update for the implicit flush after a batch */
> obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
> + obj->cache_dirty |= obj->cache_level != I915_CACHE_NONE;
I915_CACHE_WT shouldn't dirty the cache either, so could be excluded
as well.
Everything else makes sense
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> }
>
> if (flags & EXEC_OBJECT_NEEDS_FENCE)
> --
> 2.10.2
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2] drm/i915: Mark CPU cache as dirty when used for rendering
2016-11-07 15:46 ` Chris Wilson
@ 2016-11-07 16:52 ` Chris Wilson
-1 siblings, 0 replies; 9+ messages in thread
From: Chris Wilson @ 2016-11-07 16:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson, Jani Nikula, Ville Syrjälä, # v4 . 0+
On LLC, or even snooped, machines rendering via the GPU ends up in the CPU
cache. This cacheline dirt also needs to be flushed to main memory when
moving to an incoherent domain, such as the display's scanout engine.
Mostly, this happens because either the object is marked as dirty from
its first use or is avoided by setting the object into the display
domain from the start.
v2: Treat WT as not requiring a clflush prior to use on the display
engine as well.
Fixes: 0f71979ab7fb ("drm/i915: Performed deferred clflush inside set-cache-level")
References: https://bugs.freedesktop.org/show_bug.cgi?id=95414
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: <stable@vger.kernel.org> # v4.0+
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 30f6eb516ca3..f1ffbdcbcfaf 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1253,6 +1253,12 @@ i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
return ctx;
}
+static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
+{
+ return !(obj->cache_level == I915_CACHE_NONE ||
+ obj->cache_level == I915_CACHE_WT);
+}
+
void i915_vma_move_to_active(struct i915_vma *vma,
struct drm_i915_gem_request *req,
unsigned int flags)
@@ -1282,6 +1288,8 @@ void i915_vma_move_to_active(struct i915_vma *vma,
/* update for the implicit flush after a batch */
obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
+ if (!obj->cache_dirty)
+ obj->cache_dirty = gpu_write_needs_clflush(obj);
}
if (flags & EXEC_OBJECT_NEEDS_FENCE)
--
2.10.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2] drm/i915: Mark CPU cache as dirty when used for rendering
@ 2016-11-07 16:52 ` Chris Wilson
0 siblings, 0 replies; 9+ messages in thread
From: Chris Wilson @ 2016-11-07 16:52 UTC (permalink / raw)
To: intel-gfx; +Cc: # v4 . 0+
On LLC, or even snooped, machines rendering via the GPU ends up in the CPU
cache. This cacheline dirt also needs to be flushed to main memory when
moving to an incoherent domain, such as the display's scanout engine.
Mostly, this happens because either the object is marked as dirty from
its first use or is avoided by setting the object into the display
domain from the start.
v2: Treat WT as not requiring a clflush prior to use on the display
engine as well.
Fixes: 0f71979ab7fb ("drm/i915: Performed deferred clflush inside set-cache-level")
References: https://bugs.freedesktop.org/show_bug.cgi?id=95414
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: <stable@vger.kernel.org> # v4.0+
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 30f6eb516ca3..f1ffbdcbcfaf 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1253,6 +1253,12 @@ i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
return ctx;
}
+static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
+{
+ return !(obj->cache_level == I915_CACHE_NONE ||
+ obj->cache_level == I915_CACHE_WT);
+}
+
void i915_vma_move_to_active(struct i915_vma *vma,
struct drm_i915_gem_request *req,
unsigned int flags)
@@ -1282,6 +1288,8 @@ void i915_vma_move_to_active(struct i915_vma *vma,
/* update for the implicit flush after a batch */
obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
+ if (!obj->cache_dirty)
+ obj->cache_dirty = gpu_write_needs_clflush(obj);
}
if (flags & EXEC_OBJECT_NEEDS_FENCE)
--
2.10.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Mark CPU cache as dirty when used for rendering (rev2)
2016-11-07 15:46 ` Chris Wilson
` (3 preceding siblings ...)
(?)
@ 2016-11-07 17:15 ` Patchwork
2016-11-07 20:59 ` Chris Wilson
-1 siblings, 1 reply; 9+ messages in thread
From: Patchwork @ 2016-11-07 17:15 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Mark CPU cache as dirty when used for rendering (rev2)
URL : https://patchwork.freedesktop.org/series/14930/
State : success
== Summary ==
Series 14930v2 drm/i915: Mark CPU cache as dirty when used for rendering
https://patchwork.freedesktop.org/api/1.0/series/14930/revisions/2/mbox/
fi-bdw-5557u total:241 pass:226 dwarn:0 dfail:0 fail:0 skip:15
fi-bsw-n3050 total:241 pass:201 dwarn:0 dfail:0 fail:0 skip:40
fi-bxt-t5700 total:241 pass:213 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-j1900 total:241 pass:213 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-n2820 total:241 pass:209 dwarn:0 dfail:0 fail:0 skip:32
fi-hsw-4770 total:241 pass:221 dwarn:0 dfail:0 fail:0 skip:20
fi-hsw-4770r total:241 pass:221 dwarn:0 dfail:0 fail:0 skip:20
fi-ilk-650 total:241 pass:188 dwarn:0 dfail:0 fail:0 skip:53
fi-ivb-3520m total:241 pass:219 dwarn:0 dfail:0 fail:0 skip:22
fi-ivb-3770 total:241 pass:219 dwarn:0 dfail:0 fail:0 skip:22
fi-kbl-7200u total:241 pass:219 dwarn:0 dfail:0 fail:0 skip:22
fi-skl-6260u total:241 pass:227 dwarn:0 dfail:0 fail:0 skip:14
fi-skl-6700hq total:241 pass:220 dwarn:0 dfail:0 fail:0 skip:21
fi-skl-6700k total:241 pass:219 dwarn:1 dfail:0 fail:0 skip:21
fi-skl-6770hq total:241 pass:227 dwarn:0 dfail:0 fail:0 skip:14
fi-snb-2520m total:241 pass:209 dwarn:0 dfail:0 fail:0 skip:32
fi-snb-2600 total:241 pass:208 dwarn:0 dfail:0 fail:0 skip:33
44f80301cde325b9a33e594f8bec88f84e02fffa drm-intel-nightly: 2016y-11m-07d-12h-48m-36s UTC integration manifest
4a0f76d drm/i915: Mark CPU cache as dirty when used for rendering
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2924/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: ✓ Fi.CI.BAT: success for drm/i915: Mark CPU cache as dirty when used for rendering (rev2)
2016-11-07 17:15 ` ✓ Fi.CI.BAT: success for drm/i915: Mark CPU cache as dirty when used for rendering (rev2) Patchwork
@ 2016-11-07 20:59 ` Chris Wilson
0 siblings, 0 replies; 9+ messages in thread
From: Chris Wilson @ 2016-11-07 20:59 UTC (permalink / raw)
To: intel-gfx
On Mon, Nov 07, 2016 at 05:15:49PM -0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Mark CPU cache as dirty when used for rendering (rev2)
> URL : https://patchwork.freedesktop.org/series/14930/
> State : success
An indication that we are missing some coverage. Pushed.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2016-11-07 20:59 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-11-07 15:46 [PATCH] drm/i915: Mark CPU cache as dirty when used for rendering Chris Wilson
2016-11-07 15:46 ` Chris Wilson
2016-11-07 16:16 ` ✓ Fi.CI.BAT: success for " Patchwork
2016-11-07 16:35 ` [PATCH] " Ville Syrjälä
2016-11-07 16:35 ` Ville Syrjälä
2016-11-07 16:52 ` [PATCH v2] " Chris Wilson
2016-11-07 16:52 ` Chris Wilson
2016-11-07 17:15 ` ✓ Fi.CI.BAT: success for drm/i915: Mark CPU cache as dirty when used for rendering (rev2) Patchwork
2016-11-07 20:59 ` Chris Wilson
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