* [PATCH] drm/i915: Only poll DW3_A when init DDI PHY for ports B and C.
@ 2016-11-11 1:03 Rodrigo Vivi
2016-11-11 1:54 ` ✗ Fi.CI.BAT: failure for " Patchwork
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Rodrigo Vivi @ 2016-11-11 1:03 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira, Rodrigo Vivi
According to Bspec we need to
"Poll for PORT_REF_DW3_A grc_done == 1b"
only on ports B and C initialization sequence when
copying rcomp from port A.
So let's follow the spec and only poll for that case
and not on every port A initialization.
Cc: Imre Deak <imre.deak@intel.com>
Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_dpio_phy.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 7a8e82d..277b1aa 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -367,6 +367,9 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
if (phy_info->rcomp_phy != -1) {
uint32_t grc_code;
+
+ bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy);
+
/*
* PHY0 isn't connected to an RCOMP resistor so copy over
* the corresponding calibrated value from PHY1, and disable
@@ -387,10 +390,6 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
val |= COMMON_RESET_DIS;
I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
-
- if (phy_info->rcomp_phy == -1)
- bxt_phy_wait_grc_done(dev_priv, phy);
-
}
void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
--
1.9.1
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Only poll DW3_A when init DDI PHY for ports B and C.
2016-11-11 1:03 [PATCH] drm/i915: Only poll DW3_A when init DDI PHY for ports B and C Rodrigo Vivi
@ 2016-11-11 1:54 ` Patchwork
2016-11-11 8:40 ` [PATCH] " Jani Nikula
` (2 subsequent siblings)
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2016-11-11 1:54 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Only poll DW3_A when init DDI PHY for ports B and C.
URL : https://patchwork.freedesktop.org/series/15139/
State : failure
== Summary ==
Series 15139v1 drm/i915: Only poll DW3_A when init DDI PHY for ports B and C.
https://patchwork.freedesktop.org/api/1.0/series/15139/revisions/1/mbox/
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> INCOMPLETE (fi-snb-2600)
fi-bdw-5557u total:244 pass:229 dwarn:0 dfail:0 fail:0 skip:15
fi-bsw-n3050 total:244 pass:204 dwarn:0 dfail:0 fail:0 skip:40
fi-bxt-t5700 total:244 pass:216 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-j1900 total:244 pass:216 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-n2820 total:244 pass:212 dwarn:0 dfail:0 fail:0 skip:32
fi-hsw-4770 total:244 pass:224 dwarn:0 dfail:0 fail:0 skip:20
fi-hsw-4770r total:244 pass:224 dwarn:0 dfail:0 fail:0 skip:20
fi-ilk-650 total:244 pass:191 dwarn:0 dfail:0 fail:0 skip:53
fi-ivb-3520m total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-ivb-3770 total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-kbl-7200u total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-skl-6260u total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14
fi-skl-6700hq total:244 pass:223 dwarn:0 dfail:0 fail:0 skip:21
fi-skl-6700k total:244 pass:222 dwarn:1 dfail:0 fail:0 skip:21
fi-skl-6770hq total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14
fi-snb-2520m total:244 pass:212 dwarn:0 dfail:0 fail:0 skip:32
fi-snb-2600 total:207 pass:178 dwarn:0 dfail:0 fail:0 skip:28
eb88955cdc6a1f4dabff6bc27747c1c9e9a3aaef drm-intel-nightly: 2016y-11m-10d-09h-29m-41s UTC integration manifest
6c16646 drm/i915: Only poll DW3_A when init DDI PHY for ports B and C.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2960/
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: Only poll DW3_A when init DDI PHY for ports B and C.
2016-11-11 1:03 [PATCH] drm/i915: Only poll DW3_A when init DDI PHY for ports B and C Rodrigo Vivi
2016-11-11 1:54 ` ✗ Fi.CI.BAT: failure for " Patchwork
@ 2016-11-11 8:40 ` Jani Nikula
2016-11-11 13:09 ` Imre Deak
2016-11-17 19:45 ` ✓ Fi.CI.BAT: success for drm/i915: Only poll DW3_A when init DDI PHY for ports B and C. (rev2) Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Jani Nikula @ 2016-11-11 8:40 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira, Rodrigo Vivi
On Fri, 11 Nov 2016, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> According to Bspec we need to
> "Poll for PORT_REF_DW3_A grc_done == 1b"
> only on ports B and C initialization sequence when
> copying rcomp from port A.
>
> So let's follow the spec and only poll for that case
> and not on every port A initialization.
>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Fixes: ?
Cc: stable?
> ---
> drivers/gpu/drm/i915/intel_dpio_phy.c | 7 +++----
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index 7a8e82d..277b1aa 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -367,6 +367,9 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
>
> if (phy_info->rcomp_phy != -1) {
> uint32_t grc_code;
> +
> + bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy);
> +
> /*
> * PHY0 isn't connected to an RCOMP resistor so copy over
> * the corresponding calibrated value from PHY1, and disable
> @@ -387,10 +390,6 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
> val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
> val |= COMMON_RESET_DIS;
> I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
> -
> - if (phy_info->rcomp_phy == -1)
> - bxt_phy_wait_grc_done(dev_priv, phy);
> -
> }
>
> void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: Only poll DW3_A when init DDI PHY for ports B and C.
2016-11-11 1:03 [PATCH] drm/i915: Only poll DW3_A when init DDI PHY for ports B and C Rodrigo Vivi
2016-11-11 1:54 ` ✗ Fi.CI.BAT: failure for " Patchwork
2016-11-11 8:40 ` [PATCH] " Jani Nikula
@ 2016-11-11 13:09 ` Imre Deak
2016-11-14 19:51 ` Vivi, Rodrigo
2016-11-17 19:45 ` ✓ Fi.CI.BAT: success for drm/i915: Only poll DW3_A when init DDI PHY for ports B and C. (rev2) Patchwork
3 siblings, 1 reply; 9+ messages in thread
From: Imre Deak @ 2016-11-11 13:09 UTC (permalink / raw)
To: Rodrigo Vivi, intel-gfx; +Cc: Ander Conselvan de Oliveira
On to, 2016-11-10 at 17:03 -0800, Rodrigo Vivi wrote:
> According to Bspec we need to
> "Poll for PORT_REF_DW3_A grc_done == 1b"
> only on ports B and C initialization sequence when
> copying rcomp from port A.
>
> So let's follow the spec and only poll for that case
> and not on every port A initialization.
>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Ander Conselvan de Oliveira
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
The current code isn't against the spec, we just wait for the
calibration to complete earlier. This way we also wait in case only
port A is enabled which is imo safer to do before a subsequent modeset
on port A. But yes, the spec suggests the HW will handle the wait for
this - only port A - case internally, so we can move the wait later to
reduce somewhat the init time:
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dpio_phy.c | 7 +++----
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index 7a8e82d..277b1aa 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -367,6 +367,9 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
>
> if (phy_info->rcomp_phy != -1) {
> uint32_t grc_code;
> +
> + bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy);
> +
> /*
> * PHY0 isn't connected to an RCOMP resistor so copy over
> * the corresponding calibrated value from PHY1, and disable
> @@ -387,10 +390,6 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
> val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
> val |= COMMON_RESET_DIS;
> I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
> -
> - if (phy_info->rcomp_phy == -1)
> - bxt_phy_wait_grc_done(dev_priv, phy);
> -
> }
>
> void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: Only poll DW3_A when init DDI PHY for ports B and C.
2016-11-11 13:09 ` Imre Deak
@ 2016-11-14 19:51 ` Vivi, Rodrigo
2016-11-17 15:18 ` Imre Deak
0 siblings, 1 reply; 9+ messages in thread
From: Vivi, Rodrigo @ 2016-11-14 19:51 UTC (permalink / raw)
To: Deak, Imre; +Cc: Conselvan De Oliveira, Ander, intel-gfx
On Fri, 2016-11-11 at 15:09 +0200, Imre Deak wrote:
> On to, 2016-11-10 at 17:03 -0800, Rodrigo Vivi wrote:
> > According to Bspec we need to
> > "Poll for PORT_REF_DW3_A grc_done == 1b"
> > only on ports B and C initialization sequence when
> > copying rcomp from port A.
> >
> > So let's follow the spec and only poll for that case
> > and not on every port A initialization.
> >
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Ander Conselvan de Oliveira
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> The current code isn't against the spec, we just wait for the
> calibration to complete earlier. This way we also wait in case only
> port A is enabled which is imo safer to do before a subsequent modeset
> on port A. But yes, the spec suggests the HW will handle the wait for
> this - only port A - case internally, so we can move the wait later to
> reduce somewhat the init time:
>
> Reviewed-by: Imre Deak <imre.deak@intel.com>
Ops, actually I noticed later that I need to remove the warning block
with return false from is_phy_enabled if grc isn't done. otherwise it
will force a reprograming without this line there.
So, do you believe it is worth to do a v2 removing that block or better
to just ignore this patch?
>
> > ---
> > drivers/gpu/drm/i915/intel_dpio_phy.c | 7 +++----
> > 1 file changed, 3 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> > index 7a8e82d..277b1aa 100644
> > --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> > +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> > @@ -367,6 +367,9 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
> >
> > if (phy_info->rcomp_phy != -1) {
> > uint32_t grc_code;
> > +
> > + bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy);
> > +
> > /*
> > * PHY0 isn't connected to an RCOMP resistor so copy over
> > * the corresponding calibrated value from PHY1, and disable
> > @@ -387,10 +390,6 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
> > val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
> > val |= COMMON_RESET_DIS;
> > I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
> > -
> > - if (phy_info->rcomp_phy == -1)
> > - bxt_phy_wait_grc_done(dev_priv, phy);
> > -
> > }
> >
> > void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: Only poll DW3_A when init DDI PHY for ports B and C.
2016-11-14 19:51 ` Vivi, Rodrigo
@ 2016-11-17 15:18 ` Imre Deak
2016-11-17 19:17 ` Rodrigo Vivi
0 siblings, 1 reply; 9+ messages in thread
From: Imre Deak @ 2016-11-17 15:18 UTC (permalink / raw)
To: Vivi, Rodrigo; +Cc: Conselvan De Oliveira, Ander, intel-gfx
On ma, 2016-11-14 at 21:51 +0200, Vivi, Rodrigo wrote:
> On Fri, 2016-11-11 at 15:09 +0200, Imre Deak wrote:
> > On to, 2016-11-10 at 17:03 -0800, Rodrigo Vivi wrote:
> > > According to Bspec we need to
> > > "Poll for PORT_REF_DW3_A grc_done == 1b"
> > > only on ports B and C initialization sequence when
> > > copying rcomp from port A.
> > >
> > > So let's follow the spec and only poll for that case
> > > and not on every port A initialization.
> > >
> > > Cc: Imre Deak <imre.deak@intel.com>
> > > Cc: Ander Conselvan de Oliveira
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >
> > The current code isn't against the spec, we just wait for the
> > calibration to complete earlier. This way we also wait in case only
> > port A is enabled which is imo safer to do before a subsequent
> > modeset
> > on port A. But yes, the spec suggests the HW will handle the wait
> > for
> > this - only port A - case internally, so we can move the wait later
> > to
> > reduce somewhat the init time:
> >
> > Reviewed-by: Imre Deak <imre.deak@intel.com>
>
> Ops, actually I noticed later that I need to remove the warning block
> with return false from is_phy_enabled if grc isn't done. otherwise it
> will force a reprograming without this line there.
Yea, missed that too.
>
> So, do you believe it is worth to do a v2 removing that block or
> better
> to just ignore this patch?
The calibration takes ~2ms on my APL, so I think it's worth reducing
that delay.
>
> >
> > > ---
> > > drivers/gpu/drm/i915/intel_dpio_phy.c | 7 +++----
> > > 1 file changed, 3 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c
> > > b/drivers/gpu/drm/i915/intel_dpio_phy.c
> > > index 7a8e82d..277b1aa 100644
> > > --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> > > +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> > > @@ -367,6 +367,9 @@ static void _bxt_ddi_phy_init(struct
> > > drm_i915_private *dev_priv,
> > >
> > > if (phy_info->rcomp_phy != -1) {
> > > uint32_t grc_code;
> > > +
> > > + bxt_phy_wait_grc_done(dev_priv, phy_info-
> > > >rcomp_phy);
> > > +
> > > /*
> > > * PHY0 isn't connected to an RCOMP resistor so
> > > copy over
> > > * the corresponding calibrated value from PHY1,
> > > and disable
> > > @@ -387,10 +390,6 @@ static void _bxt_ddi_phy_init(struct
> > > drm_i915_private *dev_priv,
> > > val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
> > > val |= COMMON_RESET_DIS;
> > > I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
> > > -
> > > - if (phy_info->rcomp_phy == -1)
> > > - bxt_phy_wait_grc_done(dev_priv, phy);
> > > -
> > > }
> > >
> > > void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum
> > > dpio_phy phy)
>
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH] drm/i915: Only poll DW3_A when init DDI PHY for ports B and C.
2016-11-17 15:18 ` Imre Deak
@ 2016-11-17 19:17 ` Rodrigo Vivi
2016-11-18 10:07 ` Imre Deak
0 siblings, 1 reply; 9+ messages in thread
From: Rodrigo Vivi @ 2016-11-17 19:17 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira, Rodrigo Vivi
According to Bspec we need to
"Poll for PORT_REF_DW3_A grc_done == 1b"
only on ports B and C initialization sequence when
copying rcomp from port A.
So let's follow the spec and only poll for that case
and not on every port A initialization.
v2: Also remove the grc_done check from bxt_ddi_phy_is_enabled()
otherwise it might believe it is disabled and force it to re program.
Cc: Imre Deak <imre.deak@intel.com>
Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_dpio_phy.c | 15 +++------------
1 file changed, 3 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 7a8e82d..321a2ee 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -255,14 +255,6 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
return false;
}
- if (phy_info->rcomp_phy == -1 &&
- !(I915_READ(BXT_PORT_REF_DW3(phy)) & GRC_DONE)) {
- DRM_DEBUG_DRIVER("DDI PHY %d powered, but GRC isn't done\n",
- phy);
-
- return false;
- }
-
if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
phy);
@@ -367,6 +359,9 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
if (phy_info->rcomp_phy != -1) {
uint32_t grc_code;
+
+ bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy);
+
/*
* PHY0 isn't connected to an RCOMP resistor so copy over
* the corresponding calibrated value from PHY1, and disable
@@ -387,10 +382,6 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
val |= COMMON_RESET_DIS;
I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
-
- if (phy_info->rcomp_phy == -1)
- bxt_phy_wait_grc_done(dev_priv, phy);
-
}
void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
--
1.9.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Only poll DW3_A when init DDI PHY for ports B and C. (rev2)
2016-11-11 1:03 [PATCH] drm/i915: Only poll DW3_A when init DDI PHY for ports B and C Rodrigo Vivi
` (2 preceding siblings ...)
2016-11-11 13:09 ` Imre Deak
@ 2016-11-17 19:45 ` Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2016-11-17 19:45 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Only poll DW3_A when init DDI PHY for ports B and C. (rev2)
URL : https://patchwork.freedesktop.org/series/15139/
State : success
== Summary ==
Series 15139v2 drm/i915: Only poll DW3_A when init DDI PHY for ports B and C.
https://patchwork.freedesktop.org/api/1.0/series/15139/revisions/2/mbox/
Test drv_module_reload_basic:
dmesg-warn -> PASS (fi-skl-6770hq)
fi-bdw-5557u total:244 pass:229 dwarn:0 dfail:0 fail:0 skip:15
fi-bsw-n3050 total:244 pass:204 dwarn:0 dfail:0 fail:0 skip:40
fi-byt-j1900 total:244 pass:216 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-n2820 total:244 pass:212 dwarn:0 dfail:0 fail:0 skip:32
fi-hsw-4770 total:244 pass:224 dwarn:0 dfail:0 fail:0 skip:20
fi-hsw-4770r total:244 pass:224 dwarn:0 dfail:0 fail:0 skip:20
fi-ilk-650 total:244 pass:191 dwarn:0 dfail:0 fail:0 skip:53
fi-ivb-3520m total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-ivb-3770 total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-kbl-7200u total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-skl-6260u total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14
fi-skl-6700hq total:244 pass:223 dwarn:0 dfail:0 fail:0 skip:21
fi-skl-6700k total:244 pass:222 dwarn:1 dfail:0 fail:0 skip:21
fi-skl-6770hq total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14
fi-snb-2520m total:244 pass:212 dwarn:0 dfail:0 fail:0 skip:32
fi-snb-2600 total:244 pass:211 dwarn:0 dfail:0 fail:0 skip:33
4f5493e90cc50f1c6391c4f389f7a79c8fe52355 drm-intel-nightly: 2016y-11m-17d-15h-37m-59s UTC integration manifest
f3e8782 drm/i915: Only poll DW3_A when init DDI PHY for ports B and C.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3041/
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: Only poll DW3_A when init DDI PHY for ports B and C.
2016-11-17 19:17 ` Rodrigo Vivi
@ 2016-11-18 10:07 ` Imre Deak
0 siblings, 0 replies; 9+ messages in thread
From: Imre Deak @ 2016-11-18 10:07 UTC (permalink / raw)
To: Rodrigo Vivi, intel-gfx; +Cc: Ander Conselvan de Oliveira
On to, 2016-11-17 at 11:17 -0800, Rodrigo Vivi wrote:
> According to Bspec we need to
> "Poll for PORT_REF_DW3_A grc_done == 1b"
> only on ports B and C initialization sequence when
> copying rcomp from port A.
>
> So let's follow the spec and only poll for that case
> and not on every port A initialization.
>
> v2: Also remove the grc_done check from bxt_ddi_phy_is_enabled()
> otherwise it might believe it is disabled and force it to re program.
>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Ander Conselvan de Oliveira
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dpio_phy.c | 15 +++------------
> 1 file changed, 3 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index 7a8e82d..321a2ee 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -255,14 +255,6 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
> return false;
> }
>
> - if (phy_info->rcomp_phy == -1 &&
> - !(I915_READ(BXT_PORT_REF_DW3(phy)) & GRC_DONE)) {
> - DRM_DEBUG_DRIVER("DDI PHY %d powered, but GRC isn't done\n",
> - phy);
> -
> - return false;
> - }
> -
> if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
> DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
> phy);
> @@ -367,6 +359,9 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
>
> if (phy_info->rcomp_phy != -1) {
> uint32_t grc_code;
> +
> + bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy);
> +
> /*
> * PHY0 isn't connected to an RCOMP resistor so copy over
> * the corresponding calibrated value from PHY1, and disable
> @@ -387,10 +382,6 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
> val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
> val |= COMMON_RESET_DIS;
> I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
> -
> - if (phy_info->rcomp_phy == -1)
> - bxt_phy_wait_grc_done(dev_priv, phy);
> -
> }
>
> void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
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^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2016-11-18 10:08 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-11-11 1:03 [PATCH] drm/i915: Only poll DW3_A when init DDI PHY for ports B and C Rodrigo Vivi
2016-11-11 1:54 ` ✗ Fi.CI.BAT: failure for " Patchwork
2016-11-11 8:40 ` [PATCH] " Jani Nikula
2016-11-11 13:09 ` Imre Deak
2016-11-14 19:51 ` Vivi, Rodrigo
2016-11-17 15:18 ` Imre Deak
2016-11-17 19:17 ` Rodrigo Vivi
2016-11-18 10:07 ` Imre Deak
2016-11-17 19:45 ` ✓ Fi.CI.BAT: success for drm/i915: Only poll DW3_A when init DDI PHY for ports B and C. (rev2) Patchwork
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