From: Mark Rutland <mark.rutland@arm.com>
To: Anurup M <anurupvasu@gmail.com>
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-doc@vger.kernel.org, will.deacon@arm.com, corbet@lwn.net,
catalin.marinas@arm.com, robh+dt@kernel.org, arnd@arndb.de,
f.fainelli@gmail.com, rmk+kernel@arm.linux.org.uk,
krzk@kernel.org, anurup.m@huawei.com, zhangshaokun@hisilicon.com,
tanxiaojun@huawei.com, xuwei5@hisilicon.com,
sanil.kumar@hisilicon.com, john.garry@huawei.com,
gabriele.paoloni@huawei.com, shiju.jose@huawei.com,
wangkefeng.wang@huawei.com, guohanjun@huawei.com,
shyju.pv@huawei.com, linuxarm@huawei.com
Subject: Re: [RESEND PATCH v1 02/11] dt-bindings: hisi: Add Hisilicon HiP05/06/07 Sysctrl and Djtag dts bindings
Date: Fri, 11 Nov 2016 11:53:47 +0000 [thread overview]
Message-ID: <20161111115346.GC11945@leverpostej> (raw)
In-Reply-To: <5825A927.2000202@gmail.com>
On Fri, Nov 11, 2016 at 04:49:03PM +0530, Anurup M wrote:
> On Thursday 10 November 2016 10:53 PM, Mark Rutland wrote:
> >On Thu, Nov 03, 2016 at 01:41:58AM -0400, Anurup M wrote:
> >>diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
> >>+Example:
> >>+ /* for Hisilicon HiP05 djtag for CPU sysctrl */
> >>+ djtag0: djtag@80010000 {
> >>+ compatible = "hisilicon,hip05-cpu-djtag-v1";
> >>+ reg = <0x0 0x80010000 0x0 0x10000>;
> >>+
> >>+ /* For L3 cache PMU */
> >>+ pmul3c0 {
> >>+ compatible = "hisilicon,hisi-pmu-l3c-v1";
> >>+ scl-id = <0x02>;
> >>+ num-events = <0x16>;
> >>+ num-counters = <0x08>;
> >>+ module-id = <0x04>;
> >>+ num-banks = <0x04>;
> >>+ cfgen-map = <0x02 0x04 0x01 0x08>;
> >>+ counter-reg = <0x170>;
> >>+ evctrl-reg = <0x04>;
> >>+ event-en = <0x1000000>;
> >>+ evtype-reg = <0x140>;
> >>+ };
> >This sub-node needs a binding document.
> >
> >These properties are completely opaque
> The L3 cache PMU bindings are defined @bindings/arm/hisilicon/pmu.txt.
> Is it OK that I document here(hisilicon/djtag.txt), a reference to
> the PMU bindings doc ?
At this point in the series, that file does not exist yet, and this is
an undocumented beinding.
Please introduce this sub-node long with the PMU bindings, later in the
series.
Thanks,
Mark.
WARNING: multiple messages have this Message-ID (diff)
From: mark.rutland@arm.com (Mark Rutland)
To: linux-arm-kernel@lists.infradead.org
Subject: [RESEND PATCH v1 02/11] dt-bindings: hisi: Add Hisilicon HiP05/06/07 Sysctrl and Djtag dts bindings
Date: Fri, 11 Nov 2016 11:53:47 +0000 [thread overview]
Message-ID: <20161111115346.GC11945@leverpostej> (raw)
In-Reply-To: <5825A927.2000202@gmail.com>
On Fri, Nov 11, 2016 at 04:49:03PM +0530, Anurup M wrote:
> On Thursday 10 November 2016 10:53 PM, Mark Rutland wrote:
> >On Thu, Nov 03, 2016 at 01:41:58AM -0400, Anurup M wrote:
> >>diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
> >>+Example:
> >>+ /* for Hisilicon HiP05 djtag for CPU sysctrl */
> >>+ djtag0: djtag at 80010000 {
> >>+ compatible = "hisilicon,hip05-cpu-djtag-v1";
> >>+ reg = <0x0 0x80010000 0x0 0x10000>;
> >>+
> >>+ /* For L3 cache PMU */
> >>+ pmul3c0 {
> >>+ compatible = "hisilicon,hisi-pmu-l3c-v1";
> >>+ scl-id = <0x02>;
> >>+ num-events = <0x16>;
> >>+ num-counters = <0x08>;
> >>+ module-id = <0x04>;
> >>+ num-banks = <0x04>;
> >>+ cfgen-map = <0x02 0x04 0x01 0x08>;
> >>+ counter-reg = <0x170>;
> >>+ evctrl-reg = <0x04>;
> >>+ event-en = <0x1000000>;
> >>+ evtype-reg = <0x140>;
> >>+ };
> >This sub-node needs a binding document.
> >
> >These properties are completely opaque
> The L3 cache PMU bindings are defined @bindings/arm/hisilicon/pmu.txt.
> Is it OK that I document here(hisilicon/djtag.txt), a reference to
> the PMU bindings doc ?
At this point in the series, that file does not exist yet, and this is
an undocumented beinding.
Please introduce this sub-node long with the PMU bindings, later in the
series.
Thanks,
Mark.
next prev parent reply other threads:[~2016-11-11 11:53 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-03 5:41 [RESEND PATCH v1 00/11] perf: arm64: Support for Hisilicon SoC Hardware event counters Anurup M
2016-11-03 5:41 ` Anurup M
2016-11-03 5:41 ` [RESEND PATCH v1 03/11] drivers: soc: hisi: Add support for Hisilicon Djtag driver Anurup M
2016-11-03 5:41 ` Anurup M
[not found] ` <1478151727-20250-4-git-send-email-anurup.m-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2016-11-10 17:55 ` Mark Rutland
2016-11-10 17:55 ` Mark Rutland
2016-11-15 10:15 ` Anurup M
2016-11-15 10:15 ` Anurup M
2016-11-03 5:42 ` [RESEND PATCH v1 04/11] Documentation: perf: hisi: Documentation for HIP05/06/07 PMU event counting Anurup M
2016-11-03 5:42 ` Anurup M
2016-11-03 5:42 ` [RESEND PATCH v1 05/11] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU Anurup M
2016-11-03 5:42 ` Anurup M
2016-11-03 18:26 ` Krzysztof Kozlowski
2016-11-03 18:26 ` Krzysztof Kozlowski
2016-11-04 5:06 ` Anurup M
2016-11-04 5:06 ` Anurup M
2016-11-10 18:30 ` Mark Rutland
2016-11-10 18:30 ` Mark Rutland
2016-11-14 0:06 ` Anurup M
2016-11-14 0:06 ` Anurup M
2016-11-15 9:51 ` Mark Rutland
2016-11-15 9:51 ` Mark Rutland
2016-11-16 5:54 ` Anurup M
2016-11-16 5:54 ` Anurup M
2016-11-03 5:42 ` [RESEND PATCH v1 06/11] perf: hisi: Update Kconfig for Hisilicon PMU support Anurup M
2016-11-03 5:42 ` Anurup M
2016-11-03 5:42 ` [RESEND PATCH v1 07/11] perf: hisi: Add support for Hisilicon SoC event counters Anurup M
2016-11-03 5:42 ` Anurup M
2016-11-10 19:10 ` Mark Rutland
2016-11-10 19:10 ` Mark Rutland
2016-11-14 8:11 ` Anurup M
2016-11-14 8:11 ` Anurup M
[not found] ` <1478151727-20250-1-git-send-email-anurup.m-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2016-11-03 5:41 ` [RESEND PATCH v1 01/11] arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support Anurup M
2016-11-03 5:41 ` Anurup M
2016-11-03 5:41 ` [RESEND PATCH v1 02/11] dt-bindings: hisi: Add Hisilicon HiP05/06/07 Sysctrl and Djtag dts bindings Anurup M
2016-11-03 5:41 ` Anurup M
2016-11-10 17:23 ` Mark Rutland
2016-11-10 17:23 ` Mark Rutland
2016-11-11 11:19 ` Anurup M
2016-11-11 11:19 ` Anurup M
2016-11-11 11:53 ` Mark Rutland [this message]
2016-11-11 11:53 ` Mark Rutland
2016-11-11 11:59 ` Anurup M
2016-11-11 11:59 ` Anurup M
2016-11-03 5:42 ` [RESEND PATCH v1 08/11] perf: hisi: Add sysfs attributes for L3 cache(L3C) PMU Anurup M
2016-11-03 5:42 ` Anurup M
2016-11-03 5:42 ` [RESEND PATCH v1 10/11] perf: hisi: Support for Hisilicon DDRC PMU Anurup M
2016-11-03 5:42 ` Anurup M
2016-11-03 5:42 ` [RESEND PATCH v1 09/11] perf: hisi: Miscellanous node(MN) event counting in perf Anurup M
2016-11-03 5:42 ` Anurup M
2016-11-03 5:42 ` [RESEND PATCH v1 11/11] dts: arm64: hip06: Add Hisilicon SoC PMU support Anurup M
2016-11-03 5:42 ` Anurup M
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