* [Qemu-devel] [PATCH] ppc: BOOK3E: nothing should be done when MSR:PR is set
@ 2016-11-17 13:49 Vladimir Svoboda
2016-11-17 14:53 ` Thomas Huth
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Vladimir Svoboda @ 2016-11-17 13:49 UTC (permalink / raw)
To: qemu-devel; +Cc: Vladimir Svoboda, Benjamin Herrenschmidt
The server architecture (BOOK3S) specifies that any instruction that
sets MSR:PR will also set MSR:EE, IR and DR.
However there is no such behavior specification for the embedded
architecture (BOOK3E).
Signed-off-by: Vladimir Svoboda <ze.vlad@gmail.com>
---
target-ppc/helper_regs.h | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h
index bb9ce60..6213816 100644
--- a/target-ppc/helper_regs.h
+++ b/target-ppc/helper_regs.h
@@ -131,11 +131,14 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
}
/* If PR=1 then EE, IR and DR must be 1
*
- * Note: We only enforce this on 64-bit processors. It appears that
- * 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS
- * exploits it.
+ * Note: We only enforce this on 64-bit server processors.
+ * It appears that:
+ * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS
+ * exploits it.
+ * - 64-bit embedded implementations do not need any operation to be
+ * performed when PR is set.
*/
- if ((env->insns_flags & PPC_64B) && ((value >> MSR_PR) & 1)) {
+ if ((env->insns_flags & PPC_SEGMENT_64B) && ((value >> MSR_PR) & 1)) {
value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR);
}
#endif
--
2.10.2
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [PATCH] ppc: BOOK3E: nothing should be done when MSR:PR is set
2016-11-17 13:49 [Qemu-devel] [PATCH] ppc: BOOK3E: nothing should be done when MSR:PR is set Vladimir Svoboda
@ 2016-11-17 14:53 ` Thomas Huth
2016-11-17 19:45 ` Benjamin Herrenschmidt
2016-11-18 6:09 ` David Gibson
2 siblings, 0 replies; 4+ messages in thread
From: Thomas Huth @ 2016-11-17 14:53 UTC (permalink / raw)
To: Vladimir Svoboda, qemu-devel, qemu-ppc
Cc: David Gibson, Benjamin Herrenschmidt, Alexander Graf
On 17.11.2016 14:49, Vladimir Svoboda wrote:
> The server architecture (BOOK3S) specifies that any instruction that
> sets MSR:PR will also set MSR:EE, IR and DR.
> However there is no such behavior specification for the embedded
> architecture (BOOK3E).
>
> Signed-off-by: Vladimir Svoboda <ze.vlad@gmail.com>
> ---
> target-ppc/helper_regs.h | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h
> index bb9ce60..6213816 100644
> --- a/target-ppc/helper_regs.h
> +++ b/target-ppc/helper_regs.h
> @@ -131,11 +131,14 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
> }
> /* If PR=1 then EE, IR and DR must be 1
> *
> - * Note: We only enforce this on 64-bit processors. It appears that
> - * 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS
> - * exploits it.
> + * Note: We only enforce this on 64-bit server processors.
> + * It appears that:
> + * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS
> + * exploits it.
> + * - 64-bit embedded implementations do not need any operation to be
> + * performed when PR is set.
> */
> - if ((env->insns_flags & PPC_64B) && ((value >> MSR_PR) & 1)) {
> + if ((env->insns_flags & PPC_SEGMENT_64B) && ((value >> MSR_PR) & 1)) {
> value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR);
> }
> #endif
>
Reviewed-by: Thomas Huth <thuth@redhat.com>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [PATCH] ppc: BOOK3E: nothing should be done when MSR:PR is set
2016-11-17 13:49 [Qemu-devel] [PATCH] ppc: BOOK3E: nothing should be done when MSR:PR is set Vladimir Svoboda
2016-11-17 14:53 ` Thomas Huth
@ 2016-11-17 19:45 ` Benjamin Herrenschmidt
2016-11-18 6:09 ` David Gibson
2 siblings, 0 replies; 4+ messages in thread
From: Benjamin Herrenschmidt @ 2016-11-17 19:45 UTC (permalink / raw)
To: Vladimir Svoboda, qemu-devel
On Thu, 2016-11-17 at 14:49 +0100, Vladimir Svoboda wrote:
> The server architecture (BOOK3S) specifies that any instruction that
> sets MSR:PR will also set MSR:EE, IR and DR.
> However there is no such behavior specification for the embedded
> architecture (BOOK3E).
>
> Signed-off-by: Vladimir Svoboda <ze.vlad@gmail.com>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
> target-ppc/helper_regs.h | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h
> index bb9ce60..6213816 100644
> --- a/target-ppc/helper_regs.h
> +++ b/target-ppc/helper_regs.h
> @@ -131,11 +131,14 @@ static inline int hreg_store_msr(CPUPPCState
> *env, target_ulong value,
> }
> /* If PR=1 then EE, IR and DR must be 1
> *
> - * Note: We only enforce this on 64-bit processors. It appears
> that
> - * 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS
> - * exploits it.
> + * Note: We only enforce this on 64-bit server processors.
> + * It appears that:
> + * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and
> MacOS
> + * exploits it.
> + * - 64-bit embedded implementations do not need any operation
> to be
> + * performed when PR is set.
> */
> - if ((env->insns_flags & PPC_64B) && ((value >> MSR_PR) & 1)) {
> + if ((env->insns_flags & PPC_SEGMENT_64B) && ((value >> MSR_PR) &
> 1)) {
> value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR);
> }
> #endif
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [PATCH] ppc: BOOK3E: nothing should be done when MSR:PR is set
2016-11-17 13:49 [Qemu-devel] [PATCH] ppc: BOOK3E: nothing should be done when MSR:PR is set Vladimir Svoboda
2016-11-17 14:53 ` Thomas Huth
2016-11-17 19:45 ` Benjamin Herrenschmidt
@ 2016-11-18 6:09 ` David Gibson
2 siblings, 0 replies; 4+ messages in thread
From: David Gibson @ 2016-11-18 6:09 UTC (permalink / raw)
To: Vladimir Svoboda; +Cc: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 1752 bytes --]
On Thu, Nov 17, 2016 at 02:49:48PM +0100, Vladimir Svoboda wrote:
> The server architecture (BOOK3S) specifies that any instruction that
> sets MSR:PR will also set MSR:EE, IR and DR.
> However there is no such behavior specification for the embedded
> architecture (BOOK3E).
>
> Signed-off-by: Vladimir Svoboda <ze.vlad@gmail.com>
Applied to ppc-for-2.8, thanks.
> ---
> target-ppc/helper_regs.h | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h
> index bb9ce60..6213816 100644
> --- a/target-ppc/helper_regs.h
> +++ b/target-ppc/helper_regs.h
> @@ -131,11 +131,14 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
> }
> /* If PR=1 then EE, IR and DR must be 1
> *
> - * Note: We only enforce this on 64-bit processors. It appears that
> - * 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS
> - * exploits it.
> + * Note: We only enforce this on 64-bit server processors.
> + * It appears that:
> + * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS
> + * exploits it.
> + * - 64-bit embedded implementations do not need any operation to be
> + * performed when PR is set.
> */
> - if ((env->insns_flags & PPC_64B) && ((value >> MSR_PR) & 1)) {
> + if ((env->insns_flags & PPC_SEGMENT_64B) && ((value >> MSR_PR) & 1)) {
> value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR);
> }
> #endif
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2016-11-18 11:01 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-11-17 13:49 [Qemu-devel] [PATCH] ppc: BOOK3E: nothing should be done when MSR:PR is set Vladimir Svoboda
2016-11-17 14:53 ` Thomas Huth
2016-11-17 19:45 ` Benjamin Herrenschmidt
2016-11-18 6:09 ` David Gibson
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.