* [PATCH 2/9] arm64: tegra: Add CPU nodes for Tegra186
2016-11-17 17:11 ` Thierry Reding
@ 2016-11-17 17:11 ` Thierry Reding
-1 siblings, 0 replies; 22+ messages in thread
From: Thierry Reding @ 2016-11-17 17:11 UTC (permalink / raw)
To: Thierry Reding
Cc: Alexandre Courbot, Jon Hunter, Stephen Warren,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Tegra186 has six CPUs: two CPUs are second generation Denver CPUs that
support ARMv8 and four CPUs are Cortex-A57 CPUs.
Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 41 ++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 6cb8ac918530..eadbfacd16c2 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -57,6 +57,47 @@
};
};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "nvidia,tegra186-denver", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x000>;
+ };
+
+ cpu@1 {
+ compatible = "nvidia,tegra186-denver", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x001>;
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a57", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x100>;
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a57", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x101>;
+ };
+
+ cpu@4 {
+ compatible = "arm,cortex-a57", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x102>;
+ };
+
+ cpu@5 {
+ compatible = "arm,cortex-a57", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x103>;
+ };
+ };
+
bpmp: bpmp {
compatible = "nvidia,tegra186-bpmp";
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
--
2.10.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 2/9] arm64: tegra: Add CPU nodes for Tegra186
@ 2016-11-17 17:11 ` Thierry Reding
0 siblings, 0 replies; 22+ messages in thread
From: Thierry Reding @ 2016-11-17 17:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
Tegra186 has six CPUs: two CPUs are second generation Denver CPUs that
support ARMv8 and four CPUs are Cortex-A57 CPUs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 41 ++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 6cb8ac918530..eadbfacd16c2 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -57,6 +57,47 @@
};
};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ compatible = "nvidia,tegra186-denver", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x000>;
+ };
+
+ cpu at 1 {
+ compatible = "nvidia,tegra186-denver", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x001>;
+ };
+
+ cpu at 2 {
+ compatible = "arm,cortex-a57", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x100>;
+ };
+
+ cpu at 3 {
+ compatible = "arm,cortex-a57", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x101>;
+ };
+
+ cpu at 4 {
+ compatible = "arm,cortex-a57", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x102>;
+ };
+
+ cpu at 5 {
+ compatible = "arm,cortex-a57", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x103>;
+ };
+ };
+
bpmp: bpmp {
compatible = "nvidia,tegra186-bpmp";
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
--
2.10.2
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 3/9] arm64: tegra: Add serial ports on Tegra186
2016-11-17 17:11 ` Thierry Reding
@ 2016-11-17 17:11 ` Thierry Reding
-1 siblings, 0 replies; 22+ messages in thread
From: Thierry Reding @ 2016-11-17 17:11 UTC (permalink / raw)
To: Thierry Reding
Cc: Alexandre Courbot, Jon Hunter, Stephen Warren,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
The initial patch only added UARTA, but there's no reason we shouldn't
be adding all of them. While at it, also specify the missing clocks and
resets for UARTA.
Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 78 ++++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index eadbfacd16c2..911f288966ba 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1,5 +1,7 @@
+#include <dt-bindings/clock/tegra186-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
+#include <dt-bindings/reset/tegra186-reset.h>
/ {
compatible = "nvidia,tegra186";
@@ -12,6 +14,58 @@
reg = <0x0 0x03100000 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_UARTA>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA186_RESET_UARTA>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uartb: serial@3110000 {
+ compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x03110000 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_UARTB>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA186_RESET_UARTB>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uartd: serial@3130000 {
+ compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x03130000 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_UARTD>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA186_RESET_UARTD>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uarte: serial@3140000 {
+ compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x03140000 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_UARTE>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA186_RESET_UARTE>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uartf: serial@3150000 {
+ compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x03150000 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_UARTF>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA186_RESET_UARTF>;
+ reset-names = "serial";
status = "disabled";
};
@@ -35,6 +89,30 @@
status = "disabled";
};
+ uartc: serial@c280000 {
+ compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x0c280000 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_UARTC>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA186_RESET_UARTC>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uartg: serial@c290000 {
+ compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x0c290000 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_UARTG>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA186_RESET_UARTG>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
sysram@30000000 {
compatible = "nvidia,tegra186-sysram", "mmio-sram";
reg = <0x0 0x30000000 0x0 0x50000>;
--
2.10.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 3/9] arm64: tegra: Add serial ports on Tegra186
@ 2016-11-17 17:11 ` Thierry Reding
0 siblings, 0 replies; 22+ messages in thread
From: Thierry Reding @ 2016-11-17 17:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
The initial patch only added UARTA, but there's no reason we shouldn't
be adding all of them. While at it, also specify the missing clocks and
resets for UARTA.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 78 ++++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index eadbfacd16c2..911f288966ba 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1,5 +1,7 @@
+#include <dt-bindings/clock/tegra186-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
+#include <dt-bindings/reset/tegra186-reset.h>
/ {
compatible = "nvidia,tegra186";
@@ -12,6 +14,58 @@
reg = <0x0 0x03100000 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_UARTA>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA186_RESET_UARTA>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uartb: serial at 3110000 {
+ compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x03110000 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_UARTB>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA186_RESET_UARTB>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uartd: serial at 3130000 {
+ compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x03130000 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_UARTD>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA186_RESET_UARTD>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uarte: serial at 3140000 {
+ compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x03140000 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_UARTE>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA186_RESET_UARTE>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uartf: serial at 3150000 {
+ compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x03150000 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_UARTF>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA186_RESET_UARTF>;
+ reset-names = "serial";
status = "disabled";
};
@@ -35,6 +89,30 @@
status = "disabled";
};
+ uartc: serial at c280000 {
+ compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x0c280000 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_UARTC>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA186_RESET_UARTC>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uartg: serial at c290000 {
+ compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x0c290000 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_UARTG>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA186_RESET_UARTG>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
sysram at 30000000 {
compatible = "nvidia,tegra186-sysram", "mmio-sram";
reg = <0x0 0x30000000 0x0 0x50000>;
--
2.10.2
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 4/9] arm64: tegra: Add I2C controllers on Tegra186
2016-11-17 17:11 ` Thierry Reding
@ 2016-11-17 17:11 ` Thierry Reding
-1 siblings, 0 replies; 22+ messages in thread
From: Thierry Reding @ 2016-11-17 17:11 UTC (permalink / raw)
To: Thierry Reding
Cc: Alexandre Courbot, Jon Hunter, Stephen Warren,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Tegra186 has a total of nine I2C controllers that are compatible with
the I2C controllers introduced in Tegra114. Two of these controllers
share pads with two DPAUX controllers (for AUX transactions).
Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 120 +++++++++++++++++++++++++++++++
1 file changed, 120 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 911f288966ba..b1a77d78d202 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -69,6 +69,100 @@
status = "disabled";
};
+ gen1_i2c: i2c@3160000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x03160000 0x0 0x10000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C1>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C1>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ cam_i2c: i2c@3180000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x03180000 0x0 0x10000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C3>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C3>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ /* shares pads with dpaux1 */
+ dp_aux_ch1_i2c: i2c@3190000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x03190000 0x0 0x10000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C4>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C4>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ /* controlled by BPMP, should not be enabled */
+ pwr_i2c: i2c@31a0000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x031a0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C5>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C5>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ /* shares pads with dpaux0 */
+ dp_aux_ch0_i2c: i2c@31b0000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x031b0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C6>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C6>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ gen7_i2c: i2c@31c0000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x031c0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C7>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C7>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ gen9_i2c: i2c@31e0000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x031e0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C9>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C9>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
gic: interrupt-controller@3881000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -89,6 +183,32 @@
status = "disabled";
};
+ gen2_i2c: i2c@c240000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x0c240000 0x0 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C2>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C2>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ gen8_i2c: i2c@c250000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x0c250000 0x0 0x10000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C8>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C8>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
uartc: serial@c280000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x0c280000 0x0 0x40>;
--
2.10.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 4/9] arm64: tegra: Add I2C controllers on Tegra186
@ 2016-11-17 17:11 ` Thierry Reding
0 siblings, 0 replies; 22+ messages in thread
From: Thierry Reding @ 2016-11-17 17:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
Tegra186 has a total of nine I2C controllers that are compatible with
the I2C controllers introduced in Tegra114. Two of these controllers
share pads with two DPAUX controllers (for AUX transactions).
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 120 +++++++++++++++++++++++++++++++
1 file changed, 120 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 911f288966ba..b1a77d78d202 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -69,6 +69,100 @@
status = "disabled";
};
+ gen1_i2c: i2c at 3160000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x03160000 0x0 0x10000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C1>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C1>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ cam_i2c: i2c at 3180000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x03180000 0x0 0x10000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C3>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C3>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ /* shares pads with dpaux1 */
+ dp_aux_ch1_i2c: i2c at 3190000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x03190000 0x0 0x10000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C4>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C4>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ /* controlled by BPMP, should not be enabled */
+ pwr_i2c: i2c at 31a0000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x031a0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C5>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C5>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ /* shares pads with dpaux0 */
+ dp_aux_ch0_i2c: i2c at 31b0000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x031b0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C6>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C6>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ gen7_i2c: i2c at 31c0000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x031c0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C7>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C7>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ gen9_i2c: i2c at 31e0000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x031e0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C9>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C9>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
gic: interrupt-controller at 3881000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -89,6 +183,32 @@
status = "disabled";
};
+ gen2_i2c: i2c at c240000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x0c240000 0x0 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C2>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C2>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ gen8_i2c: i2c at c250000 {
+ compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x0c250000 0x0 0x10000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA186_CLK_I2C8>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA186_RESET_I2C8>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
uartc: serial at c280000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x0c280000 0x0 0x40>;
--
2.10.2
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 5/9] arm64: tegra: Add SDHCI controllers on Tegra186
2016-11-17 17:11 ` Thierry Reding
@ 2016-11-17 17:11 ` Thierry Reding
-1 siblings, 0 replies; 22+ messages in thread
From: Thierry Reding @ 2016-11-17 17:11 UTC (permalink / raw)
To: Thierry Reding
Cc: Alexandre Courbot, Jon Hunter, Stephen Warren,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Tegra186 has a total of four SDHCI controllers that each support SD 4.2
(up to UHS-I speed), SDIO 4.1 (up to UHS-I speed), eSD 2.1, eMMC 5.1 and
SDHOST 4.1 (up to UHS-I speed).
Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 44 ++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index b1a77d78d202..1aca69f24fb0 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -163,6 +163,50 @@
status = "disabled";
};
+ sdmmc1: sdhci@3400000 {
+ compatible = "nvidia,tegra186-sdhci";
+ reg = <0x0 0x03400000 0x0 0x10000>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
+ clock-names = "sdhci";
+ resets = <&bpmp TEGRA186_RESET_SDMMC1>;
+ reset-names = "sdhci";
+ status = "disabled";
+ };
+
+ sdmmc2: sdhci@3420000 {
+ compatible = "nvidia,tegra186-sdhci";
+ reg = <0x0 0x03420000 0x0 0x10000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
+ clock-names = "sdhci";
+ resets = <&bpmp TEGRA186_RESET_SDMMC2>;
+ reset-names = "sdhci";
+ status = "disabled";
+ };
+
+ sdmmc3: sdhci@3440000 {
+ compatible = "nvidia,tegra186-sdhci";
+ reg = <0x0 0x03440000 0x0 0x10000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
+ clock-names = "sdhci";
+ resets = <&bpmp TEGRA186_RESET_SDMMC3>;
+ reset-names = "sdhci";
+ status = "disabled";
+ };
+
+ sdmmc4: sdhci@3460000 {
+ compatible = "nvidia,tegra186-sdhci";
+ reg = <0x0 0x03460000 0x0 0x10000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
+ clock-names = "sdhci";
+ resets = <&bpmp TEGRA186_RESET_SDMMC4>;
+ reset-names = "sdhci";
+ status = "disabled";
+ };
+
gic: interrupt-controller@3881000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.10.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 5/9] arm64: tegra: Add SDHCI controllers on Tegra186
@ 2016-11-17 17:11 ` Thierry Reding
0 siblings, 0 replies; 22+ messages in thread
From: Thierry Reding @ 2016-11-17 17:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
Tegra186 has a total of four SDHCI controllers that each support SD 4.2
(up to UHS-I speed), SDIO 4.1 (up to UHS-I speed), eSD 2.1, eMMC 5.1 and
SDHOST 4.1 (up to UHS-I speed).
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 44 ++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index b1a77d78d202..1aca69f24fb0 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -163,6 +163,50 @@
status = "disabled";
};
+ sdmmc1: sdhci at 3400000 {
+ compatible = "nvidia,tegra186-sdhci";
+ reg = <0x0 0x03400000 0x0 0x10000>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
+ clock-names = "sdhci";
+ resets = <&bpmp TEGRA186_RESET_SDMMC1>;
+ reset-names = "sdhci";
+ status = "disabled";
+ };
+
+ sdmmc2: sdhci at 3420000 {
+ compatible = "nvidia,tegra186-sdhci";
+ reg = <0x0 0x03420000 0x0 0x10000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
+ clock-names = "sdhci";
+ resets = <&bpmp TEGRA186_RESET_SDMMC2>;
+ reset-names = "sdhci";
+ status = "disabled";
+ };
+
+ sdmmc3: sdhci at 3440000 {
+ compatible = "nvidia,tegra186-sdhci";
+ reg = <0x0 0x03440000 0x0 0x10000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
+ clock-names = "sdhci";
+ resets = <&bpmp TEGRA186_RESET_SDMMC3>;
+ reset-names = "sdhci";
+ status = "disabled";
+ };
+
+ sdmmc4: sdhci at 3460000 {
+ compatible = "nvidia,tegra186-sdhci";
+ reg = <0x0 0x03460000 0x0 0x10000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
+ clock-names = "sdhci";
+ resets = <&bpmp TEGRA186_RESET_SDMMC4>;
+ reset-names = "sdhci";
+ status = "disabled";
+ };
+
gic: interrupt-controller at 3881000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.10.2
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 6/9] arm64: tegra: Add GPIO controllers on Tegra186
2016-11-17 17:11 ` Thierry Reding
@ 2016-11-17 17:11 ` Thierry Reding
-1 siblings, 0 replies; 22+ messages in thread
From: Thierry Reding @ 2016-11-17 17:11 UTC (permalink / raw)
To: Thierry Reding
Cc: Alexandre Courbot, Jon Hunter, Stephen Warren,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Tegra186 has two GPIO controllers that are no longer compatible with the
controller found on earlier generations. One of these controllers exists
in an always-on partition of the SoC whereas the other can be clock- and
powergated.
Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 1aca69f24fb0..62fa85ae0271 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1,4 +1,5 @@
#include <dt-bindings/clock/tegra186-clock.h>
+#include <dt-bindings/gpio/tegra186-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
#include <dt-bindings/reset/tegra186-reset.h>
@@ -9,6 +10,23 @@
#address-cells = <2>;
#size-cells = <2>;
+ gpio: gpio@2200000 {
+ compatible = "nvidia,tegra186-gpio";
+ reg-names = "security", "gpio";
+ reg = <0x0 0x2200000 0x0 0x10000>,
+ <0x0 0x2210000 0x0 0x10000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
uarta: serial@3100000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x03100000 0x0 0x40>;
@@ -277,6 +295,18 @@
status = "disabled";
};
+ gpio_aon: gpio@c2f0000 {
+ compatible = "nvidia,tegra186-gpio-aon";
+ reg-names = "security", "gpio";
+ reg = <0x0 0xc2f0000 0x0 0x1000>,
+ <0x0 0xc2f1000 0x0 0x1000>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
sysram@30000000 {
compatible = "nvidia,tegra186-sysram", "mmio-sram";
reg = <0x0 0x30000000 0x0 0x50000>;
--
2.10.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 6/9] arm64: tegra: Add GPIO controllers on Tegra186
@ 2016-11-17 17:11 ` Thierry Reding
0 siblings, 0 replies; 22+ messages in thread
From: Thierry Reding @ 2016-11-17 17:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
Tegra186 has two GPIO controllers that are no longer compatible with the
controller found on earlier generations. One of these controllers exists
in an always-on partition of the SoC whereas the other can be clock- and
powergated.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 1aca69f24fb0..62fa85ae0271 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1,4 +1,5 @@
#include <dt-bindings/clock/tegra186-clock.h>
+#include <dt-bindings/gpio/tegra186-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
#include <dt-bindings/reset/tegra186-reset.h>
@@ -9,6 +10,23 @@
#address-cells = <2>;
#size-cells = <2>;
+ gpio: gpio at 2200000 {
+ compatible = "nvidia,tegra186-gpio";
+ reg-names = "security", "gpio";
+ reg = <0x0 0x2200000 0x0 0x10000>,
+ <0x0 0x2210000 0x0 0x10000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
uarta: serial at 3100000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x03100000 0x0 0x40>;
@@ -277,6 +295,18 @@
status = "disabled";
};
+ gpio_aon: gpio at c2f0000 {
+ compatible = "nvidia,tegra186-gpio-aon";
+ reg-names = "security", "gpio";
+ reg = <0x0 0xc2f0000 0x0 0x1000>,
+ <0x0 0xc2f1000 0x0 0x1000>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
sysram at 30000000 {
compatible = "nvidia,tegra186-sysram", "mmio-sram";
reg = <0x0 0x30000000 0x0 0x50000>;
--
2.10.2
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 7/9] arm64: tegra: Add NVIDIA P3310 processor module support
2016-11-17 17:11 ` Thierry Reding
@ 2016-11-17 17:11 ` Thierry Reding
-1 siblings, 0 replies; 22+ messages in thread
From: Thierry Reding @ 2016-11-17 17:11 UTC (permalink / raw)
To: Thierry Reding
Cc: Alexandre Courbot, Jon Hunter, Stephen Warren,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
From: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
The NVIDIA P3310 is a processor module used in several reference designs
that features a Tegra186 SoC, 8 GiB of LPDDR4 RAM, 32 GiB eMMC and other
essentials such as ethernet, WiFi and a PMIC. It is typically connected
to an I/O board (such as the P2597) that provides the connecters needed
to hook it up to the outside world.
Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 32 ++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
create mode 100644 arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
new file mode 100644
index 000000000000..807af7b68761
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -0,0 +1,32 @@
+#include "tegra186.dtsi"
+
+/ {
+ model = "NVIDIA Tegra186 P3310 Processor Module";
+ compatible = "nvidia,p3310", "nvidia,tegra186";
+
+ aliases {
+ serial0 = &uarta;
+ };
+
+ chosen {
+ bootargs = "earlycon console=ttyS0,115200n8";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x2 0x00000000>;
+ };
+
+ serial@3100000 {
+ status = "okay";
+ };
+
+ hsp@3c00000 {
+ status = "okay";
+ };
+
+ bpmp {
+ status = "okay";
+ };
+};
--
2.10.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 7/9] arm64: tegra: Add NVIDIA P3310 processor module support
@ 2016-11-17 17:11 ` Thierry Reding
0 siblings, 0 replies; 22+ messages in thread
From: Thierry Reding @ 2016-11-17 17:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Joseph Lo <josephl@nvidia.com>
The NVIDIA P3310 is a processor module used in several reference designs
that features a Tegra186 SoC, 8 GiB of LPDDR4 RAM, 32 GiB eMMC and other
essentials such as ethernet, WiFi and a PMIC. It is typically connected
to an I/O board (such as the P2597) that provides the connecters needed
to hook it up to the outside world.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 32 ++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
create mode 100644 arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
new file mode 100644
index 000000000000..807af7b68761
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -0,0 +1,32 @@
+#include "tegra186.dtsi"
+
+/ {
+ model = "NVIDIA Tegra186 P3310 Processor Module";
+ compatible = "nvidia,p3310", "nvidia,tegra186";
+
+ aliases {
+ serial0 = &uarta;
+ };
+
+ chosen {
+ bootargs = "earlycon console=ttyS0,115200n8";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x2 0x00000000>;
+ };
+
+ serial at 3100000 {
+ status = "okay";
+ };
+
+ hsp at 3c00000 {
+ status = "okay";
+ };
+
+ bpmp {
+ status = "okay";
+ };
+};
--
2.10.2
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 8/9] arm64: tegra: Enable PSCI on P3310
2016-11-17 17:11 ` Thierry Reding
@ 2016-11-17 17:11 ` Thierry Reding
-1 siblings, 0 replies; 22+ messages in thread
From: Thierry Reding @ 2016-11-17 17:11 UTC (permalink / raw)
To: Thierry Reding
Cc: Alexandre Courbot, Jon Hunter, Stephen Warren,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
The P3310 processor module comes ships with a firmware that implements
PSCI 1.0. Enable and use it to bring up all CPUs.
Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 36 ++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
index 807af7b68761..2c158c6809a5 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -26,7 +26,43 @@
status = "okay";
};
+ cpus {
+ cpu@0 {
+ enable-method = "psci";
+ };
+
+ cpu@1 {
+ enable-method = "psci";
+ };
+
+ cpu@2 {
+ enable-method = "psci";
+ };
+
+ cpu@3 {
+ enable-method = "psci";
+ };
+
+ cpu@4 {
+ enable-method = "psci";
+ };
+
+ cpu@5 {
+ enable-method = "psci";
+ };
+ };
+
bpmp {
status = "okay";
};
+
+ psci {
+ compatible = "arm,psci-1.0";
+ status = "okay";
+ method = "smc";
+
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ cpu_suspend = <0xc4000001>;
+ };
};
--
2.10.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 8/9] arm64: tegra: Enable PSCI on P3310
@ 2016-11-17 17:11 ` Thierry Reding
0 siblings, 0 replies; 22+ messages in thread
From: Thierry Reding @ 2016-11-17 17:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
The P3310 processor module comes ships with a firmware that implements
PSCI 1.0. Enable and use it to bring up all CPUs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 36 ++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
index 807af7b68761..2c158c6809a5 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -26,7 +26,43 @@
status = "okay";
};
+ cpus {
+ cpu at 0 {
+ enable-method = "psci";
+ };
+
+ cpu at 1 {
+ enable-method = "psci";
+ };
+
+ cpu at 2 {
+ enable-method = "psci";
+ };
+
+ cpu at 3 {
+ enable-method = "psci";
+ };
+
+ cpu at 4 {
+ enable-method = "psci";
+ };
+
+ cpu at 5 {
+ enable-method = "psci";
+ };
+ };
+
bpmp {
status = "okay";
};
+
+ psci {
+ compatible = "arm,psci-1.0";
+ status = "okay";
+ method = "smc";
+
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ cpu_suspend = <0xc4000001>;
+ };
};
--
2.10.2
^ permalink raw reply related [flat|nested] 22+ messages in thread[parent not found: <20161117171131.20062-8-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH 8/9] arm64: tegra: Enable PSCI on P3310
2016-11-17 17:11 ` Thierry Reding
@ 2016-11-17 17:21 ` Sudeep Holla
-1 siblings, 0 replies; 22+ messages in thread
From: Sudeep Holla @ 2016-11-17 17:21 UTC (permalink / raw)
To: Thierry Reding
Cc: Sudeep Holla, linux-tegra-u79uwXL29TY76Z2rM5mHXA, Stephen Warren,
Alexandre Courbot,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Jon Hunter
On 17/11/16 17:11, Thierry Reding wrote:
> From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> The P3310 processor module comes ships with a firmware that implements
> PSCI 1.0. Enable and use it to bring up all CPUs.
>
> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 36 ++++++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> index 807af7b68761..2c158c6809a5 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> @@ -26,7 +26,43 @@
> status = "okay";
> };
>
> + cpus {
> + cpu@0 {
> + enable-method = "psci";
> + };
> +
> + cpu@1 {
> + enable-method = "psci";
> + };
> +
> + cpu@2 {
> + enable-method = "psci";
> + };
> +
> + cpu@3 {
> + enable-method = "psci";
> + };
> +
> + cpu@4 {
> + enable-method = "psci";
> + };
> +
> + cpu@5 {
> + enable-method = "psci";
> + };
> + };
> +
> bpmp {
> status = "okay";
> };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + status = "okay";
> + method = "smc";
[...]
> +
> + cpu_off = <0x84000002>;
> + cpu_on = <0xc4000003>;
> + cpu_suspend = <0xc4000001>;
These are applicable only for "arm,psci"(i.e. PSCI v0.1), so you need to
drop them.
--
Regards,
Sudeep
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH 8/9] arm64: tegra: Enable PSCI on P3310
@ 2016-11-17 17:21 ` Sudeep Holla
0 siblings, 0 replies; 22+ messages in thread
From: Sudeep Holla @ 2016-11-17 17:21 UTC (permalink / raw)
To: linux-arm-kernel
On 17/11/16 17:11, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> The P3310 processor module comes ships with a firmware that implements
> PSCI 1.0. Enable and use it to bring up all CPUs.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 36 ++++++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> index 807af7b68761..2c158c6809a5 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> @@ -26,7 +26,43 @@
> status = "okay";
> };
>
> + cpus {
> + cpu at 0 {
> + enable-method = "psci";
> + };
> +
> + cpu at 1 {
> + enable-method = "psci";
> + };
> +
> + cpu at 2 {
> + enable-method = "psci";
> + };
> +
> + cpu at 3 {
> + enable-method = "psci";
> + };
> +
> + cpu at 4 {
> + enable-method = "psci";
> + };
> +
> + cpu at 5 {
> + enable-method = "psci";
> + };
> + };
> +
> bpmp {
> status = "okay";
> };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + status = "okay";
> + method = "smc";
[...]
> +
> + cpu_off = <0x84000002>;
> + cpu_on = <0xc4000003>;
> + cpu_suspend = <0xc4000001>;
These are applicable only for "arm,psci"(i.e. PSCI v0.1), so you need to
drop them.
--
Regards,
Sudeep
^ permalink raw reply [flat|nested] 22+ messages in thread[parent not found: <786f354d-a1f2-f2c6-fde7-7b1af3df756c-5wv7dgnIgG8@public.gmane.org>]
* Re: [PATCH 8/9] arm64: tegra: Enable PSCI on P3310
2016-11-17 17:21 ` Sudeep Holla
@ 2016-11-17 17:33 ` Thierry Reding
-1 siblings, 0 replies; 22+ messages in thread
From: Thierry Reding @ 2016-11-17 17:33 UTC (permalink / raw)
To: Sudeep Holla
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA, Stephen Warren,
Alexandre Courbot,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Jon Hunter
[-- Attachment #1: Type: text/plain, Size: 1955 bytes --]
On Thu, Nov 17, 2016 at 05:21:34PM +0000, Sudeep Holla wrote:
>
>
> On 17/11/16 17:11, Thierry Reding wrote:
> > From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> >
> > The P3310 processor module comes ships with a firmware that implements
> > PSCI 1.0. Enable and use it to bring up all CPUs.
> >
> > Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> > ---
> > arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 36 ++++++++++++++++++++++++++
> > 1 file changed, 36 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> > index 807af7b68761..2c158c6809a5 100644
> > --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> > +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> > @@ -26,7 +26,43 @@
> > status = "okay";
> > };
> >
> > + cpus {
> > + cpu@0 {
> > + enable-method = "psci";
> > + };
> > +
> > + cpu@1 {
> > + enable-method = "psci";
> > + };
> > +
> > + cpu@2 {
> > + enable-method = "psci";
> > + };
> > +
> > + cpu@3 {
> > + enable-method = "psci";
> > + };
> > +
> > + cpu@4 {
> > + enable-method = "psci";
> > + };
> > +
> > + cpu@5 {
> > + enable-method = "psci";
> > + };
> > + };
> > +
> > bpmp {
> > status = "okay";
> > };
> > +
> > + psci {
> > + compatible = "arm,psci-1.0";
> > + status = "okay";
> > + method = "smc";
>
> [...]
>
> > +
> > + cpu_off = <0x84000002>;
> > + cpu_on = <0xc4000003>;
> > + cpu_suspend = <0xc4000001>;
>
> These are applicable only for "arm,psci"(i.e. PSCI v0.1), so you need to
> drop them.
Oh, indeed. I obviously skipped the arm,psci and arm,psci-0.2 entries in
the binding documentation and then assumed the optional properties
applied regardless of PSCI version.
Removed these and everything still works as expected.
Thanks,
Thierry
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH 8/9] arm64: tegra: Enable PSCI on P3310
@ 2016-11-17 17:33 ` Thierry Reding
0 siblings, 0 replies; 22+ messages in thread
From: Thierry Reding @ 2016-11-17 17:33 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Nov 17, 2016 at 05:21:34PM +0000, Sudeep Holla wrote:
>
>
> On 17/11/16 17:11, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> >
> > The P3310 processor module comes ships with a firmware that implements
> > PSCI 1.0. Enable and use it to bring up all CPUs.
> >
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> > arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 36 ++++++++++++++++++++++++++
> > 1 file changed, 36 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> > index 807af7b68761..2c158c6809a5 100644
> > --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> > +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
> > @@ -26,7 +26,43 @@
> > status = "okay";
> > };
> >
> > + cpus {
> > + cpu at 0 {
> > + enable-method = "psci";
> > + };
> > +
> > + cpu at 1 {
> > + enable-method = "psci";
> > + };
> > +
> > + cpu at 2 {
> > + enable-method = "psci";
> > + };
> > +
> > + cpu at 3 {
> > + enable-method = "psci";
> > + };
> > +
> > + cpu at 4 {
> > + enable-method = "psci";
> > + };
> > +
> > + cpu at 5 {
> > + enable-method = "psci";
> > + };
> > + };
> > +
> > bpmp {
> > status = "okay";
> > };
> > +
> > + psci {
> > + compatible = "arm,psci-1.0";
> > + status = "okay";
> > + method = "smc";
>
> [...]
>
> > +
> > + cpu_off = <0x84000002>;
> > + cpu_on = <0xc4000003>;
> > + cpu_suspend = <0xc4000001>;
>
> These are applicable only for "arm,psci"(i.e. PSCI v0.1), so you need to
> drop them.
Oh, indeed. I obviously skipped the arm,psci and arm,psci-0.2 entries in
the binding documentation and then assumed the optional properties
applied regardless of PSCI version.
Removed these and everything still works as expected.
Thanks,
Thierry
-------------- next part --------------
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 9/9] arm64: tegra: Add NVIDIA P2771 board support
2016-11-17 17:11 ` Thierry Reding
@ 2016-11-17 17:11 ` Thierry Reding
-1 siblings, 0 replies; 22+ messages in thread
From: Thierry Reding @ 2016-11-17 17:11 UTC (permalink / raw)
To: Thierry Reding
Cc: Alexandre Courbot, Jon Hunter, Stephen Warren,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
From: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
The NVIDIA P2771 is composed of a P3310 processor module that connects
to the P2597 I/O board. It comes with a 1200x1920 MIPI DSI panel that is
connected via the P2597's display connector and has several connectors
such as HDMI, USB 3.0, PCIe and ethernet.
Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
arch/arm64/boot/dts/nvidia/Makefile | 1 +
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 8 ++++++++
2 files changed, 9 insertions(+)
create mode 100644 arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile
index 0f7cdf3e05c1..18941458cb4d 100644
--- a/arch/arm64/boot/dts/nvidia/Makefile
+++ b/arch/arm64/boot/dts/nvidia/Makefile
@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb
+dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb
always := $(dtb-y)
clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
new file mode 100644
index 000000000000..0d3c0996d832
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
@@ -0,0 +1,8 @@
+/dts-v1/;
+
+#include "tegra186-p3310.dtsi"
+
+/ {
+ model = "NVIDIA Tegra186 P2771-0000 Development Board";
+ compatible = "nvidia,p2771-0000", "nvidia,tegra186";
+};
--
2.10.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 9/9] arm64: tegra: Add NVIDIA P2771 board support
@ 2016-11-17 17:11 ` Thierry Reding
0 siblings, 0 replies; 22+ messages in thread
From: Thierry Reding @ 2016-11-17 17:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Joseph Lo <josephl@nvidia.com>
The NVIDIA P2771 is composed of a P3310 processor module that connects
to the P2597 I/O board. It comes with a 1200x1920 MIPI DSI panel that is
connected via the P2597's display connector and has several connectors
such as HDMI, USB 3.0, PCIe and ethernet.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/Makefile | 1 +
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 8 ++++++++
2 files changed, 9 insertions(+)
create mode 100644 arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile
index 0f7cdf3e05c1..18941458cb4d 100644
--- a/arch/arm64/boot/dts/nvidia/Makefile
+++ b/arch/arm64/boot/dts/nvidia/Makefile
@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb
+dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb
always := $(dtb-y)
clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
new file mode 100644
index 000000000000..0d3c0996d832
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
@@ -0,0 +1,8 @@
+/dts-v1/;
+
+#include "tegra186-p3310.dtsi"
+
+/ {
+ model = "NVIDIA Tegra186 P2771-0000 Development Board";
+ compatible = "nvidia,p2771-0000", "nvidia,tegra186";
+};
--
2.10.2
^ permalink raw reply related [flat|nested] 22+ messages in thread