* [U-Boot] [PATCH v2 0/4] davinci: omapl138_lcdk: fix a few bugs for SPL boot
@ 2016-11-22 17:13 Fabien Parent
2016-11-22 17:13 ` [U-Boot] [PATCH v2 1/4] davinci: omapl138_lcdk: configure pll0 Fabien Parent
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Fabien Parent @ 2016-11-22 17:13 UTC (permalink / raw)
To: u-boot
This patchset tries to fix the SPL on omapl138_lcdk. With this patchset, the SPL
will be able to boot from EMMC/SPI.
The NAND support is still broken so the default u-boot.ais image still has a SPL
that is unable to load u-boot.
Change v1 .. v2:
* Don't add an AIS config file but instead configure the PLL and DDR in
the SPL. This follow what other boards are doing.
* Use new kconfig option to support EMMC boot.
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2 1/4] davinci: omapl138_lcdk: configure pll0
2016-11-22 17:13 [U-Boot] [PATCH v2 0/4] davinci: omapl138_lcdk: fix a few bugs for SPL boot Fabien Parent
@ 2016-11-22 17:13 ` Fabien Parent
2016-11-22 18:03 ` Tom Rini
2016-11-22 17:13 ` [U-Boot] [PATCH v2 2/4] davinci: omapl138_lcdk: configure ddr2 Fabien Parent
` (2 subsequent siblings)
3 siblings, 1 reply; 10+ messages in thread
From: Fabien Parent @ 2016-11-22 17:13 UTC (permalink / raw)
To: u-boot
The SPL is not able to boot properly because the PLL0 is not
configured. Configure it.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
V1 -> V2
* New patch
---
include/configs/omapl138_lcdk.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index 854fc47..ce3a8f4 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -30,6 +30,7 @@
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_DA850_PLL_INIT
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_TEXT_BASE 0xc1080000
--
2.10.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2 2/4] davinci: omapl138_lcdk: configure ddr2
2016-11-22 17:13 [U-Boot] [PATCH v2 0/4] davinci: omapl138_lcdk: fix a few bugs for SPL boot Fabien Parent
2016-11-22 17:13 ` [U-Boot] [PATCH v2 1/4] davinci: omapl138_lcdk: configure pll0 Fabien Parent
@ 2016-11-22 17:13 ` Fabien Parent
2016-11-22 18:10 ` Tom Rini
2016-11-22 17:13 ` [U-Boot] [PATCH v2 3/4] davinci: da850evm: fix empty boot method list in the SPL Fabien Parent
2016-11-22 17:13 ` [U-Boot] [PATCH v2 4/4] davinci: omapl138_lcdk: add u-boot sector for mmc/sd boot Fabien Parent
3 siblings, 1 reply; 10+ messages in thread
From: Fabien Parent @ 2016-11-22 17:13 UTC (permalink / raw)
To: u-boot
The SPL is unable to load u-boot because the DDR2 is not configured.
Configure the DDR2.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
V1 -> V2
* New patch
---
include/configs/omapl138_lcdk.h | 42 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index ce3a8f4..2cdf892 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -31,6 +31,7 @@
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_DA850_PLL_INIT
+#define CONFIG_SYS_DA850_DDR_INIT
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_TEXT_BASE 0xc1080000
@@ -80,6 +81,47 @@
#define CONFIG_SYS_DA850_PLL1_PLLM 21
/*
+ * DDR2 memory configuration
+ */
+#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
+ DV_DDR_PHY_EXT_STRBEN | \
+ (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
+ (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
+ (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
+ (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
+ (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
+ (4 << DV_DDR_SDCR_CL_SHIFT) | \
+ (3 << DV_DDR_SDCR_IBANK_SHIFT) | \
+ (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
+
+/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
+#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
+ (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \
+ (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
+ (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
+ (2 << DV_DDR_SDTMR1_WR_SHIFT) | \
+ (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \
+ (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
+ (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
+ (1 << DV_DDR_SDTMR1_WTR_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
+ (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
+ (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
+ (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
+ (10 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
+ (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
+ (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
+ (2 << DV_DDR_SDTMR2_CKE_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492
+#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
+
+/*
* Serial Driver info
*/
#define CONFIG_SYS_NS16550_SERIAL
--
2.10.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2 3/4] davinci: da850evm: fix empty boot method list in the SPL
2016-11-22 17:13 [U-Boot] [PATCH v2 0/4] davinci: omapl138_lcdk: fix a few bugs for SPL boot Fabien Parent
2016-11-22 17:13 ` [U-Boot] [PATCH v2 1/4] davinci: omapl138_lcdk: configure pll0 Fabien Parent
2016-11-22 17:13 ` [U-Boot] [PATCH v2 2/4] davinci: omapl138_lcdk: configure ddr2 Fabien Parent
@ 2016-11-22 17:13 ` Fabien Parent
2016-11-22 17:13 ` [U-Boot] [PATCH v2 4/4] davinci: omapl138_lcdk: add u-boot sector for mmc/sd boot Fabien Parent
3 siblings, 0 replies; 10+ messages in thread
From: Fabien Parent @ 2016-11-22 17:13 UTC (permalink / raw)
To: u-boot
The list of available boot method is not part of the binary which
prevent the SPL from booting u-boot or Linux.
Add the missing .u_boot_list* sections to the binary to fix it.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
v1 -> v2:
* No change
---
board/davinci/da8xxevm/u-boot-spl-da850evm.lds | 3 +++
1 file changed, 3 insertions(+)
diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
index ab4f50c..85a6be9 100644
--- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
+++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
@@ -34,6 +34,9 @@ SECTIONS
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
. = ALIGN(4);
+ .u_boot_list : { KEEP(*(SORT(.u_boot_list*))); } >.sram
+
+ . = ALIGN(4);
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
--
2.10.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2 4/4] davinci: omapl138_lcdk: add u-boot sector for mmc/sd boot
2016-11-22 17:13 [U-Boot] [PATCH v2 0/4] davinci: omapl138_lcdk: fix a few bugs for SPL boot Fabien Parent
` (2 preceding siblings ...)
2016-11-22 17:13 ` [U-Boot] [PATCH v2 3/4] davinci: da850evm: fix empty boot method list in the SPL Fabien Parent
@ 2016-11-22 17:13 ` Fabien Parent
2016-11-22 18:13 ` Tom Rini
3 siblings, 1 reply; 10+ messages in thread
From: Fabien Parent @ 2016-11-22 17:13 UTC (permalink / raw)
To: u-boot
Set the correct CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR value in order
to be able to boot from MMC/SD.
The SPL is stored at sector 0x75, while u-boot will follow at
sector 0xb5.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
v1 -> v2
* Rebased on Sam's patches, i.e. use new Kconfig option instead of setting
the value inside the config header file
---
configs/omapl138_lcdk_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index bcd1acb..4a5f435 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -9,6 +9,7 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xb5
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
# CONFIG_CMD_IMLS is not set
--
2.10.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2 1/4] davinci: omapl138_lcdk: configure pll0
2016-11-22 17:13 ` [U-Boot] [PATCH v2 1/4] davinci: omapl138_lcdk: configure pll0 Fabien Parent
@ 2016-11-22 18:03 ` Tom Rini
0 siblings, 0 replies; 10+ messages in thread
From: Tom Rini @ 2016-11-22 18:03 UTC (permalink / raw)
To: u-boot
On Tue, Nov 22, 2016 at 06:13:30PM +0100, Fabien Parent wrote:
> The SPL is not able to boot properly because the PLL0 is not
> configured. Configure it.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>
> V1 -> V2
> * New patch
>
> ---
> include/configs/omapl138_lcdk.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
> index 854fc47..ce3a8f4 100644
> --- a/include/configs/omapl138_lcdk.h
> +++ b/include/configs/omapl138_lcdk.h
> @@ -30,6 +30,7 @@
> #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
> #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
> #define CONFIG_SYS_HZ 1000
> +#define CONFIG_SYS_DA850_PLL_INIT
> #define CONFIG_SKIP_LOWLEVEL_INIT
> #define CONFIG_SYS_TEXT_BASE 0xc1080000
OK, but.. can you move this to Kconfig and migrate the small handful of
platforms that use it? That'll be real good progress here, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2 2/4] davinci: omapl138_lcdk: configure ddr2
2016-11-22 17:13 ` [U-Boot] [PATCH v2 2/4] davinci: omapl138_lcdk: configure ddr2 Fabien Parent
@ 2016-11-22 18:10 ` Tom Rini
2016-11-28 13:38 ` Fabien Parent
0 siblings, 1 reply; 10+ messages in thread
From: Tom Rini @ 2016-11-22 18:10 UTC (permalink / raw)
To: u-boot
On Tue, Nov 22, 2016 at 06:13:31PM +0100, Fabien Parent wrote:
> The SPL is unable to load u-boot because the DDR2 is not configured.
> Configure the DDR2.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>
> V1 -> V2
>
> * New patch
>
> ---
> include/configs/omapl138_lcdk.h | 42 +++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 42 insertions(+)
>
> diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
> index ce3a8f4..2cdf892 100644
> --- a/include/configs/omapl138_lcdk.h
> +++ b/include/configs/omapl138_lcdk.h
> @@ -31,6 +31,7 @@
> #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
> #define CONFIG_SYS_HZ 1000
> #define CONFIG_SYS_DA850_PLL_INIT
> +#define CONFIG_SYS_DA850_DDR_INIT
> #define CONFIG_SKIP_LOWLEVEL_INIT
> #define CONFIG_SYS_TEXT_BASE 0xc1080000
This would be "easy" to move to Kconfig, so please do.
> @@ -80,6 +81,47 @@
> #define CONFIG_SYS_DA850_PLL1_PLLM 21
>
> /*
> + * DDR2 memory configuration
> + */
> +#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
> + DV_DDR_PHY_EXT_STRBEN | \
> + (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
> +
> +#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
> + (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
> + (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
> + (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
> + (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
> + (4 << DV_DDR_SDCR_CL_SHIFT) | \
> + (3 << DV_DDR_SDCR_IBANK_SHIFT) | \
> + (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
> +
> +/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
> +#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
> +
> +#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
> + (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \
> + (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
> + (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
> + (2 << DV_DDR_SDTMR1_WR_SHIFT) | \
> + (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \
> + (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
> + (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
> + (1 << DV_DDR_SDTMR1_WTR_SHIFT))
> +
> +#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
> + (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
> + (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
> + (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
> + (10 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
> + (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
> + (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
> + (2 << DV_DDR_SDTMR2_CKE_SHIFT))
> +
> +#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492
> +#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
This is a little harder. I think this should be done more like
arch/arm/include/asm/arch-omap3/mem.h:#define where we name-space the
values that we construct based on the part (maker and size/speed). Do
you have time to look into this migration? Thanks!
--
Tom
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* [U-Boot] [PATCH v2 4/4] davinci: omapl138_lcdk: add u-boot sector for mmc/sd boot
2016-11-22 17:13 ` [U-Boot] [PATCH v2 4/4] davinci: omapl138_lcdk: add u-boot sector for mmc/sd boot Fabien Parent
@ 2016-11-22 18:13 ` Tom Rini
0 siblings, 0 replies; 10+ messages in thread
From: Tom Rini @ 2016-11-22 18:13 UTC (permalink / raw)
To: u-boot
On Tue, Nov 22, 2016 at 06:13:33PM +0100, Fabien Parent wrote:
> Set the correct CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR value in order
> to be able to boot from MMC/SD.
>
> The SPL is stored at sector 0x75, while u-boot will follow at
> sector 0xb5.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
--
Tom
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* [U-Boot] [PATCH v2 2/4] davinci: omapl138_lcdk: configure ddr2
2016-11-22 18:10 ` Tom Rini
@ 2016-11-28 13:38 ` Fabien Parent
2016-11-28 15:05 ` Tom Rini
0 siblings, 1 reply; 10+ messages in thread
From: Fabien Parent @ 2016-11-28 13:38 UTC (permalink / raw)
To: u-boot
On Tue, Nov 22, 2016 at 7:10 PM, Tom Rini <trini@konsulko.com> wrote:
> On Tue, Nov 22, 2016 at 06:13:31PM +0100, Fabien Parent wrote:
>
>> The SPL is unable to load u-boot because the DDR2 is not configured.
>> Configure the DDR2.
>>
>> Signed-off-by: Fabien Parent <fparent@baylibre.com>
>> ---
>>
>> V1 -> V2
>>
>> * New patch
>>
>> ---
>> include/configs/omapl138_lcdk.h | 42 +++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 42 insertions(+)
>>
>> diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
>> index ce3a8f4..2cdf892 100644
>> --- a/include/configs/omapl138_lcdk.h
>> +++ b/include/configs/omapl138_lcdk.h
>> @@ -31,6 +31,7 @@
>> #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
>> #define CONFIG_SYS_HZ 1000
>> #define CONFIG_SYS_DA850_PLL_INIT
>> +#define CONFIG_SYS_DA850_DDR_INIT
>> #define CONFIG_SKIP_LOWLEVEL_INIT
>> #define CONFIG_SYS_TEXT_BASE 0xc1080000
>
> This would be "easy" to move to Kconfig, so please do.
>
>> @@ -80,6 +81,47 @@
>> #define CONFIG_SYS_DA850_PLL1_PLLM 21
>>
>> /*
>> + * DDR2 memory configuration
>> + */
>> +#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
>> + DV_DDR_PHY_EXT_STRBEN | \
>> + (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
>> +
>> +#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
>> + (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
>> + (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
>> + (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
>> + (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
>> + (4 << DV_DDR_SDCR_CL_SHIFT) | \
>> + (3 << DV_DDR_SDCR_IBANK_SHIFT) | \
>> + (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
>> +
>> +/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
>> +#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
>> +
>> +#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
>> + (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \
>> + (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
>> + (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
>> + (2 << DV_DDR_SDTMR1_WR_SHIFT) | \
>> + (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \
>> + (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
>> + (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
>> + (1 << DV_DDR_SDTMR1_WTR_SHIFT))
>> +
>> +#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
>> + (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
>> + (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
>> + (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
>> + (10 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
>> + (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
>> + (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
>> + (2 << DV_DDR_SDTMR2_CKE_SHIFT))
>> +
>> +#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492
>> +#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
>
> This is a little harder. I think this should be done more like
> arch/arm/include/asm/arch-omap3/mem.h:#define where we name-space the
> values that we construct based on the part (maker and size/speed). Do
> you have time to look into this migration? Thanks!
Given that I don't have a lot of time right now, in the v3 I will just
move CONFIG_SYS_DA850_DDR_INIT to Kconfig and keep all the config in
the header file and at a later time once my current work on
OMAPl138-LCDK is over I will sent a new patchset for all the
CONFIG_SYS_DA85_DDR* options.
>
> --
> Tom
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2 2/4] davinci: omapl138_lcdk: configure ddr2
2016-11-28 13:38 ` Fabien Parent
@ 2016-11-28 15:05 ` Tom Rini
0 siblings, 0 replies; 10+ messages in thread
From: Tom Rini @ 2016-11-28 15:05 UTC (permalink / raw)
To: u-boot
On Mon, Nov 28, 2016 at 02:38:34PM +0100, Fabien Parent wrote:
> On Tue, Nov 22, 2016 at 7:10 PM, Tom Rini <trini@konsulko.com> wrote:
> > On Tue, Nov 22, 2016 at 06:13:31PM +0100, Fabien Parent wrote:
> >
> >> The SPL is unable to load u-boot because the DDR2 is not configured.
> >> Configure the DDR2.
> >>
> >> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> >> ---
> >>
> >> V1 -> V2
> >>
> >> * New patch
> >>
> >> ---
> >> include/configs/omapl138_lcdk.h | 42 +++++++++++++++++++++++++++++++++++++++++
> >> 1 file changed, 42 insertions(+)
> >>
> >> diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
> >> index ce3a8f4..2cdf892 100644
> >> --- a/include/configs/omapl138_lcdk.h
> >> +++ b/include/configs/omapl138_lcdk.h
> >> @@ -31,6 +31,7 @@
> >> #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
> >> #define CONFIG_SYS_HZ 1000
> >> #define CONFIG_SYS_DA850_PLL_INIT
> >> +#define CONFIG_SYS_DA850_DDR_INIT
> >> #define CONFIG_SKIP_LOWLEVEL_INIT
> >> #define CONFIG_SYS_TEXT_BASE 0xc1080000
> >
> > This would be "easy" to move to Kconfig, so please do.
> >
> >> @@ -80,6 +81,47 @@
> >> #define CONFIG_SYS_DA850_PLL1_PLLM 21
> >>
> >> /*
> >> + * DDR2 memory configuration
> >> + */
> >> +#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
> >> + DV_DDR_PHY_EXT_STRBEN | \
> >> + (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
> >> +
> >> +#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
> >> + (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
> >> + (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
> >> + (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
> >> + (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
> >> + (4 << DV_DDR_SDCR_CL_SHIFT) | \
> >> + (3 << DV_DDR_SDCR_IBANK_SHIFT) | \
> >> + (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
> >> +
> >> +/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
> >> +#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
> >> +
> >> +#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
> >> + (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \
> >> + (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
> >> + (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
> >> + (2 << DV_DDR_SDTMR1_WR_SHIFT) | \
> >> + (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \
> >> + (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
> >> + (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
> >> + (1 << DV_DDR_SDTMR1_WTR_SHIFT))
> >> +
> >> +#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
> >> + (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
> >> + (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
> >> + (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
> >> + (10 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
> >> + (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
> >> + (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
> >> + (2 << DV_DDR_SDTMR2_CKE_SHIFT))
> >> +
> >> +#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492
> >> +#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
> >
> > This is a little harder. I think this should be done more like
> > arch/arm/include/asm/arch-omap3/mem.h:#define where we name-space the
> > values that we construct based on the part (maker and size/speed). Do
> > you have time to look into this migration? Thanks!
>
> Given that I don't have a lot of time right now, in the v3 I will just
> move CONFIG_SYS_DA850_DDR_INIT to Kconfig and keep all the config in
> the header file and at a later time once my current work on
> OMAPl138-LCDK is over I will sent a new patchset for all the
> CONFIG_SYS_DA85_DDR* options.
OK, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2016-11-28 15:05 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-11-22 17:13 [U-Boot] [PATCH v2 0/4] davinci: omapl138_lcdk: fix a few bugs for SPL boot Fabien Parent
2016-11-22 17:13 ` [U-Boot] [PATCH v2 1/4] davinci: omapl138_lcdk: configure pll0 Fabien Parent
2016-11-22 18:03 ` Tom Rini
2016-11-22 17:13 ` [U-Boot] [PATCH v2 2/4] davinci: omapl138_lcdk: configure ddr2 Fabien Parent
2016-11-22 18:10 ` Tom Rini
2016-11-28 13:38 ` Fabien Parent
2016-11-28 15:05 ` Tom Rini
2016-11-22 17:13 ` [U-Boot] [PATCH v2 3/4] davinci: da850evm: fix empty boot method list in the SPL Fabien Parent
2016-11-22 17:13 ` [U-Boot] [PATCH v2 4/4] davinci: omapl138_lcdk: add u-boot sector for mmc/sd boot Fabien Parent
2016-11-22 18:13 ` Tom Rini
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