* [PATCH v9 00/16] mmc: sdhci-msm: Add clk-rates, DDR, HS400 support
@ 2016-11-21 6:37 ` Ritesh Harjani
0 siblings, 0 replies; 46+ messages in thread
From: Ritesh Harjani @ 2016-11-21 6:37 UTC (permalink / raw)
To: ulf.hansson, linux-mmc, adrian.hunter, sboyd, andy.gross
Cc: shawn.lin, devicetree, linux-clk, david.brown, linux-arm-msm,
georgi.djakov, alex.lemberg, mateusz.nowak, Yuliy.Izrailov,
asutoshd, david.griego, stummala, venkatg, rnayak, pramod.gurav,
jeremymc, Ritesh Harjani
Hi,
This is v9 version of the patch series which adds support for MSM8996.
Adds HS400 driver support as well.
These are tested on internal msm8996 & db410c HW.
The patch series is ready. Do we think we can apply these
patches for next now?
There are only minor changes in v9.
1. From <&xo_board 0> -> <&xo_board>.
2. Addressed Adrian minor comments on 009.
3. Other minor changes.
Older history:-
Changes from v7 -> v8 :-
1. Added patch 005 to add dt bindings for xo_clock.
2. Added patch 009 to factor out sdhci_enable_clock as discussed on v7 series.
2.a. Modified patch 010 by making use of sdhci_enable_clock.
2.b. Addressed Stephen's comment on patch 010 to call clk_set_rate unconditionally.
3. Addressed Stephen comments to remove unncessary one line comments, braces and other
minor comments.
4. Added changes from Jeremy in patch 002 for gcc-msm8994 as well for sdcc clk_rcg2_floor_ops.
minor comments.
v7 was verified on my Nexus 5X (msm8992).
Older history :-
Below are the changes in v7.
Changes from v6 -> v7 :-
1. Removed patch "clk: Add clk_hw_get_clk() helper API to be used by clk providers"
in v7 as it was not required.
2. Addressed Stephen review comments on -
"clk: qcom: Add rcg ops to return floor value closest to the requested rate"
3. Addressed comments from Stephen to add xo_clock entry in the sdhc clock node.
Using the same xo_clock entry from DT to get the clk_rate of xo_clock used in
sdhci-msm driver. Patch 04 adds this entry into DT.
Patch 05 adds the driver support for xo_clock mentioned above.
Hence there is a minor change in Patch05, which can be reviewed and taken
into the tree.
IMHO, almost all patches are almost done and are ready to be accepted.
Will below process work out?
Patches 001 & 002 :- (clock changes) - Can go via Stephen's Boyd Tree.
Patches 004 & 010 :- (DTS changes) - Can go via Andy Gross.
Patches 003, 005-009 & 011-014 :- (sdhci-msm changes) - Adrian's tree.
Please let me know in case if anything else is required on above.
Changes from v5 -> v6 :-
1. Earlier in v5 series DT node was added to get the clk-rates table
needed for sdhci-msm driver. But this is removed in this(v6) patch series
and instead the clk changes are done in the clk driver as per Rob H comment.
2. Added clk driver changes(patch 1-3) to provide floor rate values of requested
clock for sdhc client.
For following boards- apq8084, msm8996, msm8916, msm8974.
3. Other minor patch comments were addressed.
Changes from v4 -> v5 :-
1. Added HS400 sdhci-msm controller specific changes:- (Patch 10, 11, 12)
2. Addressed comment from Adrian on Patch 07 @[3].
3. Addressed comment from Arnd on Patch 03, to directly add
clk_table into sdhci_msm_host. [4]
4. Addressed comment from Bjorn to not enforce having clk-rates property
in DT for older targets based on discussion at [5]
5. Retained Acks from Adrian on patches (01 & 02 & 06) where there were no
changes made while addressing above comments.
Older history:-
This is v4 version of the patch series.
Patches 01, 02, 05 & 06 were Acked-by Adrian.
Changes from v3 -> v4 :-
1. Addressed comments from Adrian on Patch 03, 07, 08.
2. Addressed comments from Bjorn on Patch 03.
3. Added clk-rate support for sdhc DT nodes to all MSM platforms.
in Pacth 04.
4. Rebased on next branch of Ulf.
Changes from v2 -> v3 :-
1. Addded Patch 01 based on Bjorn comment[2] -
This fixes/unrolls the poor coding style of read/writes of
registers from base sdhci-msm driver.
2. Fixed/unrolled poor style of reads/writes of registers in Patch 02,
based on Bjorn comment[2]. Also changed name of flag from
use_updated_dll_reset -> use_14lpp_dll_reset.
Changes from v1->v2 :-
1. Removed patch 06 & 08 from v1 patch series[1]
(which were introducing unnecessary quirks).
Instead have implemented __sdhci_msm_set_clock version of
sdhci_set_clock in sdhci_msm driver itself in patch 07 of
this patch series.
2. Enabled extra quirk (SDHCI_QUIRK2_PRESET_VALUE_BROKEN) in
patch 05 of this patch series.
Description of patches :-
This patchset adds clk-rates & other required changes to
upstream sdhci-msm driver from codeaurora tree.
It has been tested on a db410c Dragonboard and msm8996 based
platform.
Patch 0001-0003- Adds support in qcom clk driver to return
floor value of requested clock rate instead of ceil rate
for sdhc clients.
Patch 0004- Adds updated dll sequence for newer controllers
which has minor_version >= 0x42. This is required for msm8996.
MSM controller HW recommendation is to use the base MCI clock
and directly control this MCI clock at GCC in order to
change the clk-rate.
Patches 06-08 bring in required change for this to
sdhci-msm.
MSM controller would require 2x clock rate from source
for DDR bus speed modes. Patch 09 adds this support.
Patch 0010- adds DDR support in DT for sdhc1 of msm8916.
Patches 0011-0014- Adds HS400 support to sdhci-msm.
[1]:- http://www.spinics.net/lists/linux-mmc/msg38467.html
[2]:- http://www.spinics.net/lists/linux-mmc/msg38578.html
[3]:- https://patchwork.kernel.org/patch/9289345/
[4]:- https://www.spinics.net/lists/linux-mmc/msg39107.html
[5]:- http://www.spinics.net/lists/linux-mmc/msg38749.html
[6]:- https://patchwork.kernel.org/patch/9297381/
Rajendra Nayak (2):
clk: qcom: Add rcg ops to return floor value closest to the requested
rate
clk: qcom: Move all sdcc rcgs to use clk_rcg2_floor_ops
Ritesh Harjani (12):
mmc: sdhci-msm: Change poor style writel/readl of registers
ARM: dts: Add xo to sdhc clock node on qcom platforms
dt-bindings: sdhci-msm: Add xo value
mmc: sdhci-msm: Add get_min_clock() and get_max_clock() callback
mmc: sdhci-msm: Enable few quirks
mmc: sdhci: Factor out sdhci_enable_clk
mmc: sdhci-msm: Implement set_clock callback for sdhci-msm
mmc: sdhci-msm: Add clock changes for DDR mode.
arm64: dts: qcom: msm8916: Add ddr support to sdhc1
mmc: sdhci-msm: Save the calculated tuning phase
mmc: sdhci-msm: Add calibration tuning for CDCLP533 circuit
sdhci: sdhci-msm: update dll configuration
Venkat Gopalakrishnan (2):
mmc: sdhci-msm: Update DLL reset sequence
mmc: sdhci-msm: Add HS400 platform support
.../devicetree/bindings/mmc/sdhci-msm.txt | 1 +
arch/arm/boot/dts/qcom-apq8084.dtsi | 16 +-
arch/arm/boot/dts/qcom-msm8974.dtsi | 16 +-
arch/arm64/boot/dts/qcom/msm8916.dtsi | 11 +-
arch/arm64/boot/dts/qcom/msm8996.dtsi | 9 +-
drivers/clk/qcom/clk-rcg.h | 1 +
drivers/clk/qcom/clk-rcg2.c | 76 ++-
drivers/clk/qcom/common.c | 16 +
drivers/clk/qcom/common.h | 2 +
drivers/clk/qcom/gcc-apq8084.c | 8 +-
drivers/clk/qcom/gcc-msm8916.c | 4 +-
drivers/clk/qcom/gcc-msm8974.c | 8 +-
drivers/clk/qcom/gcc-msm8994.c | 8 +-
drivers/clk/qcom/gcc-msm8996.c | 8 +-
drivers/mmc/host/sdhci-msm.c | 626 +++++++++++++++++++--
drivers/mmc/host/sdhci.c | 28 +-
drivers/mmc/host/sdhci.h | 1 +
17 files changed, 739 insertions(+), 100 deletions(-)
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply [flat|nested] 46+ messages in thread* [PATCH v9 01/16] clk: qcom: Add rcg ops to return floor value closest to the requested rate
2016-11-21 6:37 ` Ritesh Harjani
(?)
@ 2016-11-21 6:37 ` Ritesh Harjani
[not found] ` <1479710246-26676-2-git-send-email-riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
-1 siblings, 1 reply; 46+ messages in thread
From: Ritesh Harjani @ 2016-11-21 6:37 UTC (permalink / raw)
To: ulf.hansson, linux-mmc, adrian.hunter, sboyd, andy.gross
Cc: shawn.lin, devicetree, linux-clk, david.brown, linux-arm-msm,
georgi.djakov, alex.lemberg, mateusz.nowak, Yuliy.Izrailov,
asutoshd, david.griego, stummala, venkatg, rnayak, pramod.gurav,
jeremymc, Ritesh Harjani
From: Rajendra Nayak <rnayak@codeaurora.org>
The default behaviour with clk_rcg2_ops is for the
clk_round_rate()/clk_set_rate() to return/set a ceil clock
rate closest to the requested rate by looking up the corresponding
frequency table.
However, we do have some instances (mainly sdcc on various platforms)
of clients expecting a clk_set_rate() to set a floor value instead.
Add a new clk_rcg2_floor_ops to handle this for such specific
rcg instances
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
---
drivers/clk/qcom/clk-rcg.h | 1 +
drivers/clk/qcom/clk-rcg2.c | 76 +++++++++++++++++++++++++++++++++++++++------
drivers/clk/qcom/common.c | 16 ++++++++++
drivers/clk/qcom/common.h | 2 ++
4 files changed, 86 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index b904c33..1b3e8d2 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -173,6 +173,7 @@ struct clk_rcg2 {
#define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
extern const struct clk_ops clk_rcg2_ops;
+extern const struct clk_ops clk_rcg2_floor_ops;
extern const struct clk_ops clk_rcg2_shared_ops;
extern const struct clk_ops clk_edp_pixel_ops;
extern const struct clk_ops clk_byte_ops;
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index a071bba..1a0985a 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -47,6 +47,11 @@
#define N_REG 0xc
#define D_REG 0x10
+enum freq_policy {
+ FLOOR,
+ CEIL,
+};
+
static int clk_rcg2_is_enabled(struct clk_hw *hw)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
@@ -176,15 +181,26 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
return calc_rate(parent_rate, m, n, mode, hid_div);
}
-static int _freq_tbl_determine_rate(struct clk_hw *hw,
- const struct freq_tbl *f, struct clk_rate_request *req)
+static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
+ struct clk_rate_request *req,
+ enum freq_policy policy)
{
unsigned long clk_flags, rate = req->rate;
struct clk_hw *p;
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
int index;
- f = qcom_find_freq(f, rate);
+ switch (policy) {
+ case FLOOR:
+ f = qcom_find_freq_floor(f, rate);
+ break;
+ case CEIL:
+ f = qcom_find_freq(f, rate);
+ break;
+ default:
+ return -EINVAL;
+ };
+
if (!f)
return -EINVAL;
@@ -221,7 +237,15 @@ static int clk_rcg2_determine_rate(struct clk_hw *hw,
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
- return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req);
+ return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, CEIL);
+}
+
+static int clk_rcg2_determine_floor_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+
+ return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR);
}
static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
@@ -265,12 +289,23 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
return update_config(rcg);
}
-static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
+static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
+ enum freq_policy policy)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
const struct freq_tbl *f;
- f = qcom_find_freq(rcg->freq_tbl, rate);
+ switch (policy) {
+ case FLOOR:
+ f = qcom_find_freq_floor(rcg->freq_tbl, rate);
+ break;
+ case CEIL:
+ f = qcom_find_freq(rcg->freq_tbl, rate);
+ break;
+ default:
+ return -EINVAL;
+ };
+
if (!f)
return -EINVAL;
@@ -280,13 +315,25 @@ static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
- return __clk_rcg2_set_rate(hw, rate);
+ return __clk_rcg2_set_rate(hw, rate, CEIL);
+}
+
+static int clk_rcg2_set_floor_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ return __clk_rcg2_set_rate(hw, rate, FLOOR);
}
static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw,
unsigned long rate, unsigned long parent_rate, u8 index)
{
- return __clk_rcg2_set_rate(hw, rate);
+ return __clk_rcg2_set_rate(hw, rate, CEIL);
+}
+
+static int clk_rcg2_set_floor_rate_and_parent(struct clk_hw *hw,
+ unsigned long rate, unsigned long parent_rate, u8 index)
+{
+ return __clk_rcg2_set_rate(hw, rate, FLOOR);
}
const struct clk_ops clk_rcg2_ops = {
@@ -300,6 +347,17 @@ static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw,
};
EXPORT_SYMBOL_GPL(clk_rcg2_ops);
+const struct clk_ops clk_rcg2_floor_ops = {
+ .is_enabled = clk_rcg2_is_enabled,
+ .get_parent = clk_rcg2_get_parent,
+ .set_parent = clk_rcg2_set_parent,
+ .recalc_rate = clk_rcg2_recalc_rate,
+ .determine_rate = clk_rcg2_determine_floor_rate,
+ .set_rate = clk_rcg2_set_floor_rate,
+ .set_rate_and_parent = clk_rcg2_set_floor_rate_and_parent,
+};
+EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);
+
static int clk_rcg2_shared_force_enable(struct clk_hw *hw, unsigned long rate)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
@@ -323,7 +381,7 @@ static int clk_rcg2_shared_force_enable(struct clk_hw *hw, unsigned long rate)
pr_err("%s: RCG did not turn on\n", name);
/* set clock rate */
- ret = __clk_rcg2_set_rate(hw, rate);
+ ret = __clk_rcg2_set_rate(hw, rate, CEIL);
if (ret)
return ret;
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index 94569f4..cfab7b4 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -46,6 +46,22 @@ struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate)
}
EXPORT_SYMBOL_GPL(qcom_find_freq);
+const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,
+ unsigned long rate)
+{
+ const struct freq_tbl *best = NULL;
+
+ for ( ; f->freq; f++) {
+ if (rate >= f->freq)
+ best = f;
+ else
+ break;
+ }
+
+ return best;
+}
+EXPORT_SYMBOL_GPL(qcom_find_freq_floor);
+
int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, u8 src)
{
int i, num_parents = clk_hw_get_num_parents(hw);
diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
index 9fb5b8e..23c1927 100644
--- a/drivers/clk/qcom/common.h
+++ b/drivers/clk/qcom/common.h
@@ -41,6 +41,8 @@ struct qcom_cc_desc {
extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f,
unsigned long rate);
+extern const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,
+ unsigned long rate);
extern void
qcom_pll_set_fsm_mode(struct regmap *m, u32 reg, u8 bias_count, u8 lock_count);
extern int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map,
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v9 02/16] clk: qcom: Move all sdcc rcgs to use clk_rcg2_floor_ops
2016-11-21 6:37 ` Ritesh Harjani
(?)
(?)
@ 2016-11-21 6:37 ` Ritesh Harjani
2016-11-23 19:00 ` Stephen Boyd
-1 siblings, 1 reply; 46+ messages in thread
From: Ritesh Harjani @ 2016-11-21 6:37 UTC (permalink / raw)
To: ulf.hansson, linux-mmc, adrian.hunter, sboyd, andy.gross
Cc: shawn.lin, devicetree, linux-clk, david.brown, linux-arm-msm,
georgi.djakov, alex.lemberg, mateusz.nowak, Yuliy.Izrailov,
asutoshd, david.griego, stummala, venkatg, rnayak, pramod.gurav,
jeremymc, Ritesh Harjani
From: Rajendra Nayak <rnayak@codeaurora.org>
The sdcc driver for msm8996/msm8916/msm8974/msm8994 and apq8084
expects a clk_set_rate() on the sdcc rcg clk to set
a floor value of supported clk rate closest to the requested
rate, by looking up the frequency table.
So move all the sdcc rcgs on all these platforms to use the
newly introduced clk_rcg2_floor_ops
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
---
drivers/clk/qcom/gcc-apq8084.c | 8 ++++----
drivers/clk/qcom/gcc-msm8916.c | 4 ++--
drivers/clk/qcom/gcc-msm8974.c | 8 ++++----
drivers/clk/qcom/gcc-msm8994.c | 8 ++++----
drivers/clk/qcom/gcc-msm8996.c | 8 ++++----
5 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
index 070037a..486d961 100644
--- a/drivers/clk/qcom/gcc-apq8084.c
+++ b/drivers/clk/qcom/gcc-apq8084.c
@@ -1142,7 +1142,7 @@ enum {
.name = "sdcc1_apps_clk_src",
.parent_names = gcc_xo_gpll0_gpll4,
.num_parents = 3,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
@@ -1156,7 +1156,7 @@ enum {
.name = "sdcc2_apps_clk_src",
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
@@ -1170,7 +1170,7 @@ enum {
.name = "sdcc3_apps_clk_src",
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
@@ -1184,7 +1184,7 @@ enum {
.name = "sdcc4_apps_clk_src",
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index 5c4e193..628e6ca 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -1107,7 +1107,7 @@ enum {
.name = "sdcc1_apps_clk_src",
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
@@ -1132,7 +1132,7 @@ enum {
.name = "sdcc2_apps_clk_src",
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
index 0091520..348e30d 100644
--- a/drivers/clk/qcom/gcc-msm8974.c
+++ b/drivers/clk/qcom/gcc-msm8974.c
@@ -872,7 +872,7 @@ enum {
.name = "sdcc1_apps_clk_src",
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
};
static struct clk_rcg2 sdcc1_apps_clk_src = {
@@ -894,7 +894,7 @@ enum {
.name = "sdcc2_apps_clk_src",
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
@@ -908,7 +908,7 @@ enum {
.name = "sdcc3_apps_clk_src",
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
@@ -922,7 +922,7 @@ enum {
.name = "sdcc4_apps_clk_src",
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c
index 84093c1..8afd830 100644
--- a/drivers/clk/qcom/gcc-msm8994.c
+++ b/drivers/clk/qcom/gcc-msm8994.c
@@ -912,7 +912,7 @@ enum {
.name = "sdcc1_apps_clk_src",
.parent_names = gcc_xo_gpll0_gpll4,
.num_parents = 3,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
@@ -938,7 +938,7 @@ enum {
.name = "sdcc2_apps_clk_src",
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
@@ -953,7 +953,7 @@ enum {
.name = "sdcc3_apps_clk_src",
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
@@ -968,7 +968,7 @@ enum {
.name = "sdcc4_apps_clk_src",
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index e22bbc2..4b1fc17 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -460,7 +460,7 @@ enum {
.name = "sdcc1_apps_clk_src",
.parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
.num_parents = 4,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
@@ -505,7 +505,7 @@ enum {
.name = "sdcc2_apps_clk_src",
.parent_names = gcc_xo_gpll0_gpll4,
.num_parents = 3,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
@@ -519,7 +519,7 @@ enum {
.name = "sdcc3_apps_clk_src",
.parent_names = gcc_xo_gpll0_gpll4,
.num_parents = 3,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
@@ -543,7 +543,7 @@ enum {
.name = "sdcc4_apps_clk_src",
.parent_names = gcc_xo_gpll0,
.num_parents = 2,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_floor_ops,
},
};
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH v9 02/16] clk: qcom: Move all sdcc rcgs to use clk_rcg2_floor_ops
2016-11-21 6:37 ` [PATCH v9 02/16] clk: qcom: Move all sdcc rcgs to use clk_rcg2_floor_ops Ritesh Harjani
@ 2016-11-23 19:00 ` Stephen Boyd
0 siblings, 0 replies; 46+ messages in thread
From: Stephen Boyd @ 2016-11-23 19:00 UTC (permalink / raw)
To: Ritesh Harjani
Cc: ulf.hansson, linux-mmc, adrian.hunter, andy.gross, shawn.lin,
devicetree, linux-clk, david.brown, linux-arm-msm, georgi.djakov,
alex.lemberg, mateusz.nowak, Yuliy.Izrailov, asutoshd,
david.griego, stummala, venkatg, rnayak, pramod.gurav, jeremymc
On 11/21, Ritesh Harjani wrote:
> From: Rajendra Nayak <rnayak@codeaurora.org>
>
> The sdcc driver for msm8996/msm8916/msm8974/msm8994 and apq8084
> expects a clk_set_rate() on the sdcc rcg clk to set
> a floor value of supported clk rate closest to the requested
> rate, by looking up the frequency table.
> So move all the sdcc rcgs on all these platforms to use the
> newly introduced clk_rcg2_floor_ops
>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
> Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH v9 03/16] mmc: sdhci-msm: Change poor style writel/readl of registers
2016-11-21 6:37 ` Ritesh Harjani
` (2 preceding siblings ...)
(?)
@ 2016-11-21 6:37 ` Ritesh Harjani
-1 siblings, 0 replies; 46+ messages in thread
From: Ritesh Harjani @ 2016-11-21 6:37 UTC (permalink / raw)
To: ulf.hansson, linux-mmc, adrian.hunter, sboyd, andy.gross
Cc: shawn.lin, devicetree, linux-clk, david.brown, linux-arm-msm,
georgi.djakov, alex.lemberg, mateusz.nowak, Yuliy.Izrailov,
asutoshd, david.griego, stummala, venkatg, rnayak, pramod.gurav,
jeremymc, Ritesh Harjani
This patch changes the poor style of writel/readl registers
into more readable format. This avoid mixed style format
of readl/writel in sdhci-msm driver.
This patch also removes the one line comments which were present for
above writel/readl, since they were of no help.
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
---
drivers/mmc/host/sdhci-msm.c | 62 +++++++++++++++++++++++---------------------
1 file changed, 32 insertions(+), 30 deletions(-)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index b78d72f..2dcbeb0 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -138,9 +138,9 @@ static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
- /* Set CK_OUT_EN bit of DLL_CONFIG register to 1. */
- writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
- | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG);
+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config |= CORE_CK_OUT_EN;
+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
/* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
rc = msm_dll_poll_ck_out_en(host, 1);
@@ -307,6 +307,7 @@ static int msm_init_cm_dll(struct sdhci_host *host)
struct mmc_host *mmc = host->mmc;
int wait_cnt = 50;
unsigned long flags;
+ u32 config;
spin_lock_irqsave(&host->lock, flags);
@@ -315,33 +316,34 @@ static int msm_init_cm_dll(struct sdhci_host *host)
* tuning is in progress. Keeping PWRSAVE ON may
* turn off the clock.
*/
- writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC)
- & ~CORE_CLK_PWRSAVE), host->ioaddr + CORE_VENDOR_SPEC);
+ config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
+ config &= ~CORE_CLK_PWRSAVE;
+ writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
- /* Write 1 to DLL_RST bit of DLL_CONFIG register */
- writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
- | CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG);
+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config |= CORE_DLL_RST;
+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
- /* Write 1 to DLL_PDN bit of DLL_CONFIG register */
- writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
- | CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG);
+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config |= CORE_DLL_PDN;
+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
msm_cm_dll_set_freq(host);
- /* Write 0 to DLL_RST bit of DLL_CONFIG register */
- writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
- & ~CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG);
+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config &= ~CORE_DLL_RST;
+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
- /* Write 0 to DLL_PDN bit of DLL_CONFIG register */
- writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
- & ~CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG);
+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config &= ~CORE_DLL_PDN;
+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
- /* Set DLL_EN bit to 1. */
- writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
- | CORE_DLL_EN), host->ioaddr + CORE_DLL_CONFIG);
+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config |= CORE_DLL_EN;
+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
- /* Set CK_OUT_EN bit to 1. */
- writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
- | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG);
+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config |= CORE_CK_OUT_EN;
+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
/* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) &
@@ -538,7 +540,7 @@ static int sdhci_msm_probe(struct platform_device *pdev)
struct resource *core_memres;
int ret;
u16 host_version, core_minor;
- u32 core_version, caps;
+ u32 core_version, config;
u8 core_major;
host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
@@ -606,9 +608,9 @@ static int sdhci_msm_probe(struct platform_device *pdev)
goto clk_disable;
}
- /* Reset the core and Enable SDHC mode */
- writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) |
- CORE_SW_RST, msm_host->core_mem + CORE_POWER);
+ config = readl_relaxed(msm_host->core_mem + CORE_POWER);
+ config |= CORE_SW_RST;
+ writel_relaxed(config, msm_host->core_mem + CORE_POWER);
/* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
usleep_range(1000, 5000);
@@ -638,9 +640,9 @@ static int sdhci_msm_probe(struct platform_device *pdev)
* controller versions and must be explicitly enabled.
*/
if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
- caps = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
- caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
- writel_relaxed(caps, host->ioaddr +
+ config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
+ config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
+ writel_relaxed(config, host->ioaddr +
CORE_VENDOR_SPEC_CAPABILITIES0);
}
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v9 04/16] ARM: dts: Add xo to sdhc clock node on qcom platforms
2016-11-21 6:37 ` Ritesh Harjani
` (3 preceding siblings ...)
(?)
@ 2016-11-21 6:37 ` Ritesh Harjani
-1 siblings, 0 replies; 46+ messages in thread
From: Ritesh Harjani @ 2016-11-21 6:37 UTC (permalink / raw)
To: ulf.hansson, linux-mmc, adrian.hunter, sboyd, andy.gross
Cc: shawn.lin, devicetree, linux-clk, david.brown, linux-arm-msm,
georgi.djakov, alex.lemberg, mateusz.nowak, Yuliy.Izrailov,
asutoshd, david.griego, stummala, venkatg, rnayak, pramod.gurav,
jeremymc, Ritesh Harjani
Add xo entry to sdhc clock node on all qcom platforms.
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 16 ++++++++++------
arch/arm/boot/dts/qcom-msm8974.dtsi | 16 ++++++++++------
arch/arm64/boot/dts/qcom/msm8916.dtsi | 10 ++++++----
arch/arm64/boot/dts/qcom/msm8996.dtsi | 9 +++++----
4 files changed, 31 insertions(+), 20 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index 39eb7a4..80d4886 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -182,13 +182,13 @@
};
clocks {
- xo_board {
+ xo_board: xo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
};
- sleep_clk {
+ sleep_clk: sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
@@ -416,8 +416,10 @@
reg-names = "hc_mem", "core_mem";
interrupts = <0 123 0>, <0 138 0>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
- clock-names = "core", "iface";
+ clocks = <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_AHB_CLK>,
+ <&xo_board>;
+ clock-names = "core", "iface", "xo";
status = "disabled";
};
@@ -427,8 +429,10 @@
reg-names = "hc_mem", "core_mem";
interrupts = <0 125 0>, <0 221 0>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
- clock-names = "core", "iface";
+ clocks = <&gcc GCC_SDCC2_APPS_CLK>,
+ <&gcc GCC_SDCC2_AHB_CLK>,
+ <&xo_board>;
+ clock-names = "core", "iface", "xo";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index d210947..49d579f 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -220,13 +220,13 @@
};
clocks {
- xo_board {
+ xo_board: xo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
};
- sleep_clk {
+ sleep_clk: sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
@@ -558,8 +558,10 @@
reg-names = "hc_mem", "core_mem";
interrupts = <0 123 0>, <0 138 0>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
- clock-names = "core", "iface";
+ clocks = <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_AHB_CLK>,
+ <&xo_board>;
+ clock-names = "core", "iface", "xo";
status = "disabled";
};
@@ -569,8 +571,10 @@
reg-names = "hc_mem", "core_mem";
interrupts = <0 125 0>, <0 221 0>;
interrupt-names = "hc_irq", "pwr_irq";
- clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
- clock-names = "core", "iface";
+ clocks = <&gcc GCC_SDCC2_APPS_CLK>,
+ <&gcc GCC_SDCC2_AHB_CLK>,
+ <&xo_board>;
+ clock-names = "core", "iface", "xo";
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 466ca57..bd78f0c 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -512,8 +512,9 @@
interrupts = <0 123 0>, <0 138 0>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
- <&gcc GCC_SDCC1_AHB_CLK>;
- clock-names = "core", "iface";
+ <&gcc GCC_SDCC1_AHB_CLK>,
+ <&xo_board>;
+ clock-names = "core", "iface", "xo";
bus-width = <8>;
non-removable;
status = "disabled";
@@ -527,8 +528,9 @@
interrupts = <0 125 0>, <0 221 0>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
- <&gcc GCC_SDCC2_AHB_CLK>;
- clock-names = "core", "iface";
+ <&gcc GCC_SDCC2_AHB_CLK>,
+ <&xo_board>;
+ clock-names = "core", "iface", "xo";
bus-width = <4>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 338f82a..699f073 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -192,14 +192,14 @@
};
clocks {
- xo_board {
+ xo_board: xo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
clock-output-names = "xo_board";
};
- sleep_clk {
+ sleep_clk: sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32764>;
@@ -347,9 +347,10 @@
interrupts = <0 125 0>, <0 221 0>;
interrupt-names = "hc_irq", "pwr_irq";
- clock-names = "iface", "core";
+ clock-names = "iface", "core", "xo";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
- <&gcc GCC_SDCC2_APPS_CLK>;
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&xo_board>;
bus-width = <4>;
};
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v9 05/16] dt-bindings: sdhci-msm: Add xo value
2016-11-21 6:37 ` Ritesh Harjani
` (4 preceding siblings ...)
(?)
@ 2016-11-21 6:37 ` Ritesh Harjani
-1 siblings, 0 replies; 46+ messages in thread
From: Ritesh Harjani @ 2016-11-21 6:37 UTC (permalink / raw)
To: ulf.hansson, linux-mmc, adrian.hunter, sboyd, andy.gross
Cc: shawn.lin, devicetree, linux-clk, david.brown, linux-arm-msm,
georgi.djakov, alex.lemberg, mateusz.nowak, Yuliy.Izrailov,
asutoshd, david.griego, stummala, venkatg, rnayak, pramod.gurav,
jeremymc, Ritesh Harjani
Add "xo" value which is tcxo clock to sdhci-msm
DT binding properties.
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
index 485483a..0576264 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
+++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
@@ -17,6 +17,7 @@ Required properties:
"iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
"core" - SDC MMC clock (MCLK) (required)
"bus" - SDCC bus voter clock (optional)
+ "xo" - TCXO clock (optional)
Example:
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v9 06/16] mmc: sdhci-msm: Update DLL reset sequence
2016-11-21 6:37 ` Ritesh Harjani
` (5 preceding siblings ...)
(?)
@ 2016-11-21 6:37 ` Ritesh Harjani
-1 siblings, 0 replies; 46+ messages in thread
From: Ritesh Harjani @ 2016-11-21 6:37 UTC (permalink / raw)
To: ulf.hansson, linux-mmc, adrian.hunter, sboyd, andy.gross
Cc: shawn.lin, devicetree, linux-clk, david.brown, linux-arm-msm,
georgi.djakov, alex.lemberg, mateusz.nowak, Yuliy.Izrailov,
asutoshd, david.griego, stummala, venkatg, rnayak, pramod.gurav,
jeremymc, Ritesh Harjani
From: Venkat Gopalakrishnan <venkatg@codeaurora.org>
SDCC core with minor version >= 0x42 introduced new 14lpp
DLL. This has additional requirements in the reset sequence
for DLL tuning. Make necessary changes as needed.
Without this patch we see below errors on such SDHC controllers
sdhci_msm 7464900.sdhci: mmc0: DLL failed to LOCK
mmc0: tuning execution failed: -110
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
---
drivers/mmc/host/sdhci-msm.c | 60 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 2dcbeb0..fc093b8 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -59,6 +59,10 @@
#define CORE_DLL_CONFIG 0x100
#define CORE_DLL_STATUS 0x108
+#define CORE_DLL_CONFIG_2 0x1b4
+#define CORE_FLL_CYCLE_CNT BIT(18)
+#define CORE_DLL_CLOCK_DISABLE BIT(21)
+
#define CORE_VENDOR_SPEC 0x10c
#define CORE_CLK_PWRSAVE BIT(1)
@@ -77,7 +81,9 @@ struct sdhci_msm_host {
struct clk *clk; /* main SD/MMC bus clock */
struct clk *pclk; /* SDHC peripheral bus clock */
struct clk *bus_clk; /* SDHC bus voter clock */
+ struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/
struct mmc_host *mmc;
+ bool use_14lpp_dll_reset;
};
/* Platform specific tuning */
@@ -305,6 +311,8 @@ static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
static int msm_init_cm_dll(struct sdhci_host *host)
{
struct mmc_host *mmc = host->mmc;
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
int wait_cnt = 50;
unsigned long flags;
u32 config;
@@ -320,6 +328,16 @@ static int msm_init_cm_dll(struct sdhci_host *host)
config &= ~CORE_CLK_PWRSAVE;
writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
+ if (msm_host->use_14lpp_dll_reset) {
+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config &= ~CORE_CK_OUT_EN;
+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+
+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
+ config |= CORE_DLL_CLOCK_DISABLE;
+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
+ }
+
config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
config |= CORE_DLL_RST;
writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
@@ -329,6 +347,28 @@ static int msm_init_cm_dll(struct sdhci_host *host)
writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
msm_cm_dll_set_freq(host);
+ if (msm_host->use_14lpp_dll_reset &&
+ !IS_ERR_OR_NULL(msm_host->xo_clk)) {
+ u32 mclk_freq = 0;
+
+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
+ config &= CORE_FLL_CYCLE_CNT;
+ if (config)
+ mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
+ clk_get_rate(msm_host->xo_clk));
+ else
+ mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
+ clk_get_rate(msm_host->xo_clk));
+
+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
+ config &= ~(0xFF << 10);
+ config |= mclk_freq << 10;
+
+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
+ /* wait for 5us before enabling DLL clock */
+ udelay(5);
+ }
+
config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
config &= ~CORE_DLL_RST;
writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
@@ -337,6 +377,13 @@ static int msm_init_cm_dll(struct sdhci_host *host)
config &= ~CORE_DLL_PDN;
writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+ if (msm_host->use_14lpp_dll_reset) {
+ msm_cm_dll_set_freq(host);
+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
+ config &= ~CORE_DLL_CLOCK_DISABLE;
+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
+ }
+
config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
config |= CORE_DLL_EN;
writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
@@ -590,6 +637,16 @@ static int sdhci_msm_probe(struct platform_device *pdev)
goto pclk_disable;
}
+ /*
+ * xo clock is needed for FLL feature of cm_dll.
+ * In case if xo clock is not mentioned in DT, warn and proceed.
+ */
+ msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
+ if (IS_ERR(msm_host->xo_clk)) {
+ ret = PTR_ERR(msm_host->xo_clk);
+ dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret);
+ }
+
/* Vote for maximum clock rate for maximum performance */
ret = clk_set_rate(msm_host->clk, INT_MAX);
if (ret)
@@ -635,6 +692,9 @@ static int sdhci_msm_probe(struct platform_device *pdev)
dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
core_version, core_major, core_minor);
+ if (core_major == 1 && core_minor >= 0x42)
+ msm_host->use_14lpp_dll_reset = true;
+
/*
* Support for some capabilities is not advertised by newer
* controller versions and must be explicitly enabled.
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v9 07/16] mmc: sdhci-msm: Add get_min_clock() and get_max_clock() callback
2016-11-21 6:37 ` Ritesh Harjani
` (6 preceding siblings ...)
(?)
@ 2016-11-21 6:37 ` Ritesh Harjani
2017-04-26 21:44 ` Andy Gross
-1 siblings, 1 reply; 46+ messages in thread
From: Ritesh Harjani @ 2016-11-21 6:37 UTC (permalink / raw)
To: ulf.hansson, linux-mmc, adrian.hunter, sboyd, andy.gross
Cc: shawn.lin, devicetree, linux-clk, david.brown, linux-arm-msm,
georgi.djakov, alex.lemberg, mateusz.nowak, Yuliy.Izrailov,
asutoshd, david.griego, stummala, venkatg, rnayak, pramod.gurav,
jeremymc, Ritesh Harjani
This add get_min_clock() and get_max_clock() callback
for sdhci-msm. sdhci-msm min/max clocks may be different
hence implement these callbacks.
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
---
drivers/mmc/host/sdhci-msm.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index fc093b8..aaeaf47 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -68,6 +68,8 @@
#define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c
+#define SDHCI_MSM_MIN_CLOCK 400000
+
#define CDR_SELEXT_SHIFT 20
#define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
#define CMUX_SHIFT_PHASE_SHIFT 24
@@ -556,6 +558,19 @@ static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
return IRQ_HANDLED;
}
+static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
+
+ return clk_round_rate(msm_host->clk, ULONG_MAX);
+}
+
+static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
+{
+ return SDHCI_MSM_MIN_CLOCK;
+}
+
static const struct of_device_id sdhci_msm_dt_match[] = {
{ .compatible = "qcom,sdhci-msm-v4" },
{},
@@ -567,6 +582,8 @@ static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
.platform_execute_tuning = sdhci_msm_execute_tuning,
.reset = sdhci_reset,
.set_clock = sdhci_set_clock,
+ .get_min_clock = sdhci_msm_get_min_clock,
+ .get_max_clock = sdhci_msm_get_max_clock,
.set_bus_width = sdhci_set_bus_width,
.set_uhs_signaling = sdhci_msm_set_uhs_signaling,
.voltage_switch = sdhci_msm_voltage_switch,
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH v9 07/16] mmc: sdhci-msm: Add get_min_clock() and get_max_clock() callback
2016-11-21 6:37 ` [PATCH v9 07/16] mmc: sdhci-msm: Add get_min_clock() and get_max_clock() callback Ritesh Harjani
@ 2017-04-26 21:44 ` Andy Gross
2017-04-27 7:58 ` Georgi Djakov
2017-04-27 9:03 ` Ulf Hansson
0 siblings, 2 replies; 46+ messages in thread
From: Andy Gross @ 2017-04-26 21:44 UTC (permalink / raw)
To: Ritesh Harjani
Cc: ulf.hansson, linux-mmc, adrian.hunter, sboyd, shawn.lin,
devicetree, linux-clk, david.brown, linux-arm-msm, georgi.djakov,
alex.lemberg, mateusz.nowak, Yuliy.Izrailov, asutoshd,
david.griego, stummala, venkatg, rnayak, pramod.gurav, jeremymc,
stable
On Mon, Nov 21, 2016 at 12:07:17PM +0530, Ritesh Harjani wrote:
> This add get_min_clock() and get_max_clock() callback
> for sdhci-msm. sdhci-msm min/max clocks may be different
> hence implement these callbacks.
>
> Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
> Acked-by: Adrian Hunter <adrian.hunter@intel.com>
This patch needs to be picked up for stable as 4.9 is currently broken w.r.t.
MMC on Qualcomm platforms.
Fixes: d84be51d1c1d ("mmc: sdhci-msm: Enable few quirks")
Regards,
Andy Gross
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [PATCH v9 07/16] mmc: sdhci-msm: Add get_min_clock() and get_max_clock() callback
2017-04-26 21:44 ` Andy Gross
@ 2017-04-27 7:58 ` Georgi Djakov
2017-04-27 9:03 ` Ulf Hansson
1 sibling, 0 replies; 46+ messages in thread
From: Georgi Djakov @ 2017-04-27 7:58 UTC (permalink / raw)
To: Andy Gross, stable
Cc: Ritesh Harjani, ulf.hansson, linux-mmc, adrian.hunter, sboyd,
shawn.lin, devicetree, linux-clk, david.brown, linux-arm-msm,
georgi.djakov, alex.lemberg, mateusz.nowak, Yuliy.Izrailov,
asutoshd, david.griego, stummala, venkatg, rnayak, pramod.gurav,
jeremymc
On 04/27/2017 12:44 AM, Andy Gross wrote:
> On Mon, Nov 21, 2016 at 12:07:17PM +0530, Ritesh Harjani wrote:
>> This add get_min_clock() and get_max_clock() callback
>> for sdhci-msm. sdhci-msm min/max clocks may be different
>> hence implement these callbacks.
>>
>> Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
>> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
>> Acked-by: Adrian Hunter <adrian.hunter@intel.com>
>
> This patch needs to be picked up for stable as 4.9 is currently broken w.r.t.
> MMC on Qualcomm platforms.
>
> Fixes: d84be51d1c1d ("mmc: sdhci-msm: Enable few quirks")
Agree! Applying this patch (80031bdeb764) in stable fixes the
broken mmc. Otherwise the following error is seen since v4.9.22:
mmc0: Hardware doesn't specify base clock frequency.
Thanks,
Georgi
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [PATCH v9 07/16] mmc: sdhci-msm: Add get_min_clock() and get_max_clock() callback
2017-04-26 21:44 ` Andy Gross
2017-04-27 7:58 ` Georgi Djakov
@ 2017-04-27 9:03 ` Ulf Hansson
2017-04-27 9:52 ` Greg Kroah-Hartman
1 sibling, 1 reply; 46+ messages in thread
From: Ulf Hansson @ 2017-04-27 9:03 UTC (permalink / raw)
To: Andy Gross, Greg Kroah-Hartman
Cc: Ritesh Harjani, linux-mmc, Adrian Hunter, linux-arm-msm,
Georgi Djakov, Sahitya Tummala, Venkat Gopalakrishnan,
Rajendra Nayak, Pramod Gurav, jeremymc, # 4.0+
+Greg
-trimmed cc
On 26 April 2017 at 23:44, Andy Gross <andy.gross@linaro.org> wrote:
> On Mon, Nov 21, 2016 at 12:07:17PM +0530, Ritesh Harjani wrote:
>> This add get_min_clock() and get_max_clock() callback
>> for sdhci-msm. sdhci-msm min/max clocks may be different
>> hence implement these callbacks.
>>
>> Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
>> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
>> Acked-by: Adrian Hunter <adrian.hunter@intel.com>
>
> This patch needs to be picked up for stable as 4.9 is currently broken w.r.t.
> MMC on Qualcomm platforms.
>
> Fixes: d84be51d1c1d ("mmc: sdhci-msm: Enable few quirks")
>
> Regards,
>
> Andy Gross
I did a quick investigation around this.
So for some reason Greg decided to pick up the original commit,
a0e3142869d2 ("mmc: sdhci-msm: Enable few quirks"), for 4.9 stable
[1], even if that patch wasn't sent or tagged for stable.
It was a mistake, as simple as that - and I should also have spotted
it when Greg posted his stable-review series, sorry.
For clarification, the original commit a0e3142869d2 ("mmc: sdhci-msm:
Enable few quirks"), is present in 4.10 together with $subject patch.
So the regression is present only in 4.9 stable.
Greg, can you pick up @subject patch for stable according to Andy's
suggestion or you want some of us to re-post it to stable?
Kind regards
Uffe
[1]
https://www.spinics.net/lists/stable/msg167259.html
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [PATCH v9 07/16] mmc: sdhci-msm: Add get_min_clock() and get_max_clock() callback
2017-04-27 9:03 ` Ulf Hansson
@ 2017-04-27 9:52 ` Greg Kroah-Hartman
2017-04-27 10:29 ` Georgi Djakov
0 siblings, 1 reply; 46+ messages in thread
From: Greg Kroah-Hartman @ 2017-04-27 9:52 UTC (permalink / raw)
To: Ulf Hansson
Cc: Andy Gross, Ritesh Harjani, linux-mmc, Adrian Hunter,
linux-arm-msm, Georgi Djakov, Sahitya Tummala,
Venkat Gopalakrishnan, Rajendra Nayak, Pramod Gurav, jeremymc,
# 4.0+
On Thu, Apr 27, 2017 at 11:03:08AM +0200, Ulf Hansson wrote:
> +Greg
> -trimmed cc
>
> On 26 April 2017 at 23:44, Andy Gross <andy.gross@linaro.org> wrote:
> > On Mon, Nov 21, 2016 at 12:07:17PM +0530, Ritesh Harjani wrote:
> >> This add get_min_clock() and get_max_clock() callback
> >> for sdhci-msm. sdhci-msm min/max clocks may be different
> >> hence implement these callbacks.
> >>
> >> Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
> >> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
> >> Acked-by: Adrian Hunter <adrian.hunter@intel.com>
> >
> > This patch needs to be picked up for stable as 4.9 is currently broken w.r.t.
> > MMC on Qualcomm platforms.
> >
> > Fixes: d84be51d1c1d ("mmc: sdhci-msm: Enable few quirks")
> >
> > Regards,
> >
> > Andy Gross
>
> I did a quick investigation around this.
>
> So for some reason Greg decided to pick up the original commit,
> a0e3142869d2 ("mmc: sdhci-msm: Enable few quirks"), for 4.9 stable
> [1], even if that patch wasn't sent or tagged for stable.
> It was a mistake, as simple as that - and I should also have spotted
> it when Greg posted his stable-review series, sorry.
>
> For clarification, the original commit a0e3142869d2 ("mmc: sdhci-msm:
> Enable few quirks"), is present in 4.10 together with $subject patch.
> So the regression is present only in 4.9 stable.
>
> Greg, can you pick up @subject patch for stable according to Andy's
> suggestion or you want some of us to re-post it to stable?
Sorry about this. What git commit should I take for this from Linus's
tree for the 4.9-stable tree? Or if there isn't one, I'll be glad to
just revert this.
thanks,
greg k-h
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [PATCH v9 07/16] mmc: sdhci-msm: Add get_min_clock() and get_max_clock() callback
2017-04-27 9:52 ` Greg Kroah-Hartman
@ 2017-04-27 10:29 ` Georgi Djakov
2017-04-27 11:44 ` Greg Kroah-Hartman
0 siblings, 1 reply; 46+ messages in thread
From: Georgi Djakov @ 2017-04-27 10:29 UTC (permalink / raw)
To: Greg Kroah-Hartman, Ulf Hansson
Cc: Andy Gross, Ritesh Harjani, linux-mmc, Adrian Hunter,
linux-arm-msm, Sahitya Tummala, Venkat Gopalakrishnan,
Rajendra Nayak, Pramod Gurav, jeremymc, # 4.0+
On 04/27/2017 12:52 PM, Greg Kroah-Hartman wrote:
> On Thu, Apr 27, 2017 at 11:03:08AM +0200, Ulf Hansson wrote:
>> +Greg
>> -trimmed cc
>>
>> On 26 April 2017 at 23:44, Andy Gross <andy.gross@linaro.org> wrote:
>>> On Mon, Nov 21, 2016 at 12:07:17PM +0530, Ritesh Harjani wrote:
>>>> This add get_min_clock() and get_max_clock() callback
>>>> for sdhci-msm. sdhci-msm min/max clocks may be different
>>>> hence implement these callbacks.
>>>>
>>>> Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
>>>> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
>>>> Acked-by: Adrian Hunter <adrian.hunter@intel.com>
>>>
>>> This patch needs to be picked up for stable as 4.9 is currently broken w.r.t.
>>> MMC on Qualcomm platforms.
>>>
>>> Fixes: d84be51d1c1d ("mmc: sdhci-msm: Enable few quirks")
>>>
>>> Regards,
>>>
>>> Andy Gross
>>
>> I did a quick investigation around this.
>>
>> So for some reason Greg decided to pick up the original commit,
>> a0e3142869d2 ("mmc: sdhci-msm: Enable few quirks"), for 4.9 stable
>> [1], even if that patch wasn't sent or tagged for stable.
>> It was a mistake, as simple as that - and I should also have spotted
>> it when Greg posted his stable-review series, sorry.
>>
>> For clarification, the original commit a0e3142869d2 ("mmc: sdhci-msm:
>> Enable few quirks"), is present in 4.10 together with $subject patch.
>> So the regression is present only in 4.9 stable.
>>
>> Greg, can you pick up @subject patch for stable according to Andy's
>> suggestion or you want some of us to re-post it to stable?
>
> Sorry about this. What git commit should I take for this from Linus's
> tree for the 4.9-stable tree? Or if there isn't one, I'll be glad to
> just revert this.
>
Thanks Greg and Ulf,
A revert of d84be51d1c1d ("mmc: sdhci-msm: Enable few quirks") would be
the best solution.
The other option is to pick 80031bdeb764 ("mmc: sdhci-msm: Add
get_min_clock() and get_max_clock() callback").
BR,
Georgi
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [PATCH v9 07/16] mmc: sdhci-msm: Add get_min_clock() and get_max_clock() callback
2017-04-27 10:29 ` Georgi Djakov
@ 2017-04-27 11:44 ` Greg Kroah-Hartman
2017-04-27 15:34 ` Ritesh Harjani
2017-04-27 20:11 ` Andy Gross
0 siblings, 2 replies; 46+ messages in thread
From: Greg Kroah-Hartman @ 2017-04-27 11:44 UTC (permalink / raw)
To: Georgi Djakov
Cc: Ulf Hansson, Andy Gross, Ritesh Harjani, linux-mmc,
Adrian Hunter, linux-arm-msm, Sahitya Tummala,
Venkat Gopalakrishnan, Rajendra Nayak, Pramod Gurav, jeremymc,
# 4.0+
On Thu, Apr 27, 2017 at 01:29:22PM +0300, Georgi Djakov wrote:
> On 04/27/2017 12:52 PM, Greg Kroah-Hartman wrote:
> > On Thu, Apr 27, 2017 at 11:03:08AM +0200, Ulf Hansson wrote:
> >> +Greg
> >> -trimmed cc
> >>
> >> On 26 April 2017 at 23:44, Andy Gross <andy.gross@linaro.org> wrote:
> >>> On Mon, Nov 21, 2016 at 12:07:17PM +0530, Ritesh Harjani wrote:
> >>>> This add get_min_clock() and get_max_clock() callback
> >>>> for sdhci-msm. sdhci-msm min/max clocks may be different
> >>>> hence implement these callbacks.
> >>>>
> >>>> Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
> >>>> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
> >>>> Acked-by: Adrian Hunter <adrian.hunter@intel.com>
> >>>
> >>> This patch needs to be picked up for stable as 4.9 is currently broken w.r.t.
> >>> MMC on Qualcomm platforms.
> >>>
> >>> Fixes: d84be51d1c1d ("mmc: sdhci-msm: Enable few quirks")
> >>>
> >>> Regards,
> >>>
> >>> Andy Gross
> >>
> >> I did a quick investigation around this.
> >>
> >> So for some reason Greg decided to pick up the original commit,
> >> a0e3142869d2 ("mmc: sdhci-msm: Enable few quirks"), for 4.9 stable
> >> [1], even if that patch wasn't sent or tagged for stable.
> >> It was a mistake, as simple as that - and I should also have spotted
> >> it when Greg posted his stable-review series, sorry.
> >>
> >> For clarification, the original commit a0e3142869d2 ("mmc: sdhci-msm:
> >> Enable few quirks"), is present in 4.10 together with $subject patch.
> >> So the regression is present only in 4.9 stable.
> >>
> >> Greg, can you pick up @subject patch for stable according to Andy's
> >> suggestion or you want some of us to re-post it to stable?
> >
> > Sorry about this. What git commit should I take for this from Linus's
> > tree for the 4.9-stable tree? Or if there isn't one, I'll be glad to
> > just revert this.
> >
>
> Thanks Greg and Ulf,
>
> A revert of d84be51d1c1d ("mmc: sdhci-msm: Enable few quirks") would be
> the best solution.
>
> The other option is to pick 80031bdeb764 ("mmc: sdhci-msm: Add
> get_min_clock() and get_max_clock() callback").
I've reverted it now, thanks.
greg k-h
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [PATCH v9 07/16] mmc: sdhci-msm: Add get_min_clock() and get_max_clock() callback
2017-04-27 11:44 ` Greg Kroah-Hartman
@ 2017-04-27 15:34 ` Ritesh Harjani
2017-04-27 20:11 ` Andy Gross
1 sibling, 0 replies; 46+ messages in thread
From: Ritesh Harjani @ 2017-04-27 15:34 UTC (permalink / raw)
To: Greg Kroah-Hartman, Ulf Hansson
Cc: Georgi Djakov, Andy Gross, linux-mmc, Adrian Hunter,
linux-arm-msm, Sahitya Tummala, Venkat Gopalakrishnan,
Rajendra Nayak, Pramod Gurav, jeremymc, # 4.0+
On 4/27/2017 5:14 PM, Greg Kroah-Hartman wrote:
> On Thu, Apr 27, 2017 at 01:29:22PM +0300, Georgi Djakov wrote:
>> On 04/27/2017 12:52 PM, Greg Kroah-Hartman wrote:
>>> On Thu, Apr 27, 2017 at 11:03:08AM +0200, Ulf Hansson wrote:
>>>> +Greg
>>>> -trimmed cc
>>>>
>>>> On 26 April 2017 at 23:44, Andy Gross <andy.gross@linaro.org> wrote:
>>>>> On Mon, Nov 21, 2016 at 12:07:17PM +0530, Ritesh Harjani wrote:
>>>>>> This add get_min_clock() and get_max_clock() callback
>>>>>> for sdhci-msm. sdhci-msm min/max clocks may be different
>>>>>> hence implement these callbacks.
>>>>>>
>>>>>> Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
>>>>>> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
>>>>>> Acked-by: Adrian Hunter <adrian.hunter@intel.com>
>>>>>
>>>>> This patch needs to be picked up for stable as 4.9 is currently broken w.r.t.
>>>>> MMC on Qualcomm platforms.
>>>>>
>>>>> Fixes: d84be51d1c1d ("mmc: sdhci-msm: Enable few quirks")
>>>>>
>>>>> Regards,
>>>>>
>>>>> Andy Gross
>>>>
>>>> I did a quick investigation around this.
>>>>
>>>> So for some reason Greg decided to pick up the original commit,
>>>> a0e3142869d2 ("mmc: sdhci-msm: Enable few quirks"), for 4.9 stable
>>>> [1], even if that patch wasn't sent or tagged for stable.
>>>> It was a mistake, as simple as that - and I should also have spotted
>>>> it when Greg posted his stable-review series, sorry.
>>>>
>>>> For clarification, the original commit a0e3142869d2 ("mmc: sdhci-msm:
>>>> Enable few quirks"), is present in 4.10 together with $subject patch.
>>>> So the regression is present only in 4.9 stable.
>>>>
>>>> Greg, can you pick up @subject patch for stable according to Andy's
>>>> suggestion or you want some of us to re-post it to stable?
>>>
>>> Sorry about this. What git commit should I take for this from Linus's
>>> tree for the 4.9-stable tree? Or if there isn't one, I'll be glad to
>>> just revert this.
>>>
>>
>> Thanks Greg and Ulf,
>>
>> A revert of d84be51d1c1d ("mmc: sdhci-msm: Enable few quirks") would be
>> the best solution.
>>
>> The other option is to pick 80031bdeb764 ("mmc: sdhci-msm: Add
>> get_min_clock() and get_max_clock() callback").
>
> I've reverted it now, thanks.
Thanks Ulf, Greg and all.
Regards
Ritesh
>
> greg k-h
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [PATCH v9 07/16] mmc: sdhci-msm: Add get_min_clock() and get_max_clock() callback
2017-04-27 11:44 ` Greg Kroah-Hartman
2017-04-27 15:34 ` Ritesh Harjani
@ 2017-04-27 20:11 ` Andy Gross
1 sibling, 0 replies; 46+ messages in thread
From: Andy Gross @ 2017-04-27 20:11 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Georgi Djakov, Ulf Hansson, Ritesh Harjani, linux-mmc,
Adrian Hunter, linux-arm-msm, Sahitya Tummala,
Venkat Gopalakrishnan, Rajendra Nayak, Pramod Gurav, jeremymc,
# 4.0+
On Thu, Apr 27, 2017 at 01:44:41PM +0200, Greg Kroah-Hartman wrote:
> I've reverted it now, thanks.
Thanks Greg!
Regards,
Andy
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH v9 08/16] mmc: sdhci-msm: Enable few quirks
2016-11-21 6:37 ` Ritesh Harjani
` (7 preceding siblings ...)
(?)
@ 2016-11-21 6:37 ` Ritesh Harjani
-1 siblings, 0 replies; 46+ messages in thread
From: Ritesh Harjani @ 2016-11-21 6:37 UTC (permalink / raw)
To: ulf.hansson, linux-mmc, adrian.hunter, sboyd, andy.gross
Cc: shawn.lin, devicetree, linux-clk, david.brown, linux-arm-msm,
georgi.djakov, alex.lemberg, mateusz.nowak, Yuliy.Izrailov,
asutoshd, david.griego, stummala, venkatg, rnayak, pramod.gurav,
jeremymc, Ritesh Harjani
sdhc-msm controller needs this SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
& SDHCI_QUIRK2_PRESET_VALUE_BROKEN to be set. Hence setting it.
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
---
drivers/mmc/host/sdhci-msm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index aaeaf47..15a8b8e 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -592,7 +592,9 @@ static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
static const struct sdhci_pltfm_data sdhci_msm_pdata = {
.quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
SDHCI_QUIRK_NO_CARD_NO_RESET |
- SDHCI_QUIRK_SINGLE_POWER_WRITE,
+ SDHCI_QUIRK_SINGLE_POWER_WRITE |
+ SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
.ops = &sdhci_msm_ops,
};
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v9 09/16] mmc: sdhci: Factor out sdhci_enable_clk
2016-11-21 6:37 ` Ritesh Harjani
` (8 preceding siblings ...)
(?)
@ 2016-11-21 6:37 ` Ritesh Harjani
[not found] ` <1479710246-26676-10-git-send-email-riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
-1 siblings, 1 reply; 46+ messages in thread
From: Ritesh Harjani @ 2016-11-21 6:37 UTC (permalink / raw)
To: ulf.hansson, linux-mmc, adrian.hunter, sboyd, andy.gross
Cc: shawn.lin, devicetree, linux-clk, david.brown, linux-arm-msm,
georgi.djakov, alex.lemberg, mateusz.nowak, Yuliy.Izrailov,
asutoshd, david.griego, stummala, venkatg, rnayak, pramod.gurav,
jeremymc, Ritesh Harjani
Factor out sdhci_enable_clk from sdhci_set_clock
and make it EXPORT_SYMBOL so that it can be called.
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
---
drivers/mmc/host/sdhci.c | 28 +++++++++++++++++-----------
drivers/mmc/host/sdhci.h | 1 +
2 files changed, 18 insertions(+), 11 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index d08d507..62aedf1 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1344,20 +1344,10 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
}
EXPORT_SYMBOL_GPL(sdhci_calc_clk);
-void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
+void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
{
- u16 clk;
unsigned long timeout;
- host->mmc->actual_clock = 0;
-
- sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
-
- if (clock == 0)
- return;
-
- clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
-
clk |= SDHCI_CLOCK_INT_EN;
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
@@ -1378,6 +1368,22 @@ void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
clk |= SDHCI_CLOCK_CARD_EN;
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
}
+EXPORT_SYMBOL_GPL(sdhci_enable_clk);
+
+void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
+{
+ u16 clk;
+
+ host->mmc->actual_clock = 0;
+
+ sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+
+ if (clock == 0)
+ return;
+
+ clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
+ sdhci_enable_clk(host, clk);
+}
EXPORT_SYMBOL_GPL(sdhci_set_clock);
static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 9c35776..2fe9e80 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -682,6 +682,7 @@ static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host)
u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
unsigned int *actual_clock);
void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
+void sdhci_enable_clk(struct sdhci_host *host, u16 clk);
void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
unsigned short vdd);
void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v9 11/16] mmc: sdhci-msm: Add clock changes for DDR mode.
2016-11-21 6:37 ` Ritesh Harjani
` (9 preceding siblings ...)
(?)
@ 2016-11-21 6:37 ` Ritesh Harjani
-1 siblings, 0 replies; 46+ messages in thread
From: Ritesh Harjani @ 2016-11-21 6:37 UTC (permalink / raw)
To: ulf.hansson, linux-mmc, adrian.hunter, sboyd, andy.gross
Cc: shawn.lin, devicetree, linux-clk, david.brown, linux-arm-msm,
georgi.djakov, alex.lemberg, mateusz.nowak, Yuliy.Izrailov,
asutoshd, david.griego, stummala, venkatg, rnayak, pramod.gurav,
jeremymc, Ritesh Harjani
SDHC MSM controller need 2x clock for MCLK at GCC.
Hence make required changes to have 2x clock for
DDR timing modes.
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
---
drivers/mmc/host/sdhci-msm.c | 21 +++++++++++++++++----
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 00759ef..c50cee8 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -610,6 +610,7 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
+ struct mmc_ios curr_ios = host->mmc->ios;
int rc;
if (!clock) {
@@ -618,16 +619,28 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
}
spin_unlock_irq(&host->lock);
+ /*
+ * The SDHC requires internal clock frequency to be double the
+ * actual clock that will be set for DDR mode. The controller
+ * uses the faster clock(100/400MHz) for some of its parts and
+ * send the actual required clock (50/200MHz) to the card.
+ */
+ if (curr_ios.timing == MMC_TIMING_UHS_DDR50 ||
+ curr_ios.timing == MMC_TIMING_MMC_DDR52 ||
+ curr_ios.timing == MMC_TIMING_MMC_HS400)
+ clock *= 2;
rc = clk_set_rate(msm_host->clk, clock);
if (rc) {
- pr_err("%s: Failed to set clock at rate %u\n",
- mmc_hostname(host->mmc), clock);
+ pr_err("%s: Failed to set clock at rate %u at timing %d\n",
+ mmc_hostname(host->mmc), clock,
+ curr_ios.timing);
goto out_lock;
}
msm_host->clk_rate = clock;
- pr_debug("%s: Setting clock at rate %lu\n",
- mmc_hostname(host->mmc), clk_get_rate(msm_host->clk));
+ pr_debug("%s: Setting clock at rate %lu at timing %d\n",
+ mmc_hostname(host->mmc), clk_get_rate(msm_host->clk),
+ curr_ios.timing);
out_lock:
spin_lock_irq(&host->lock);
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v9 12/16] arm64: dts: qcom: msm8916: Add ddr support to sdhc1
2016-11-21 6:37 ` Ritesh Harjani
` (10 preceding siblings ...)
(?)
@ 2016-11-21 6:37 ` Ritesh Harjani
-1 siblings, 0 replies; 46+ messages in thread
From: Ritesh Harjani @ 2016-11-21 6:37 UTC (permalink / raw)
To: ulf.hansson, linux-mmc, adrian.hunter, sboyd, andy.gross
Cc: shawn.lin, devicetree, linux-clk, david.brown, linux-arm-msm,
georgi.djakov, alex.lemberg, mateusz.nowak, Yuliy.Izrailov,
asutoshd, david.griego, stummala, venkatg, rnayak, pramod.gurav,
jeremymc, Ritesh Harjani
This adds mmc-ddr-1_8v support to DT for sdhc1 of msm8916.
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index bd78f0c..971ae5a 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -515,6 +515,7 @@
<&gcc GCC_SDCC1_AHB_CLK>,
<&xo_board>;
clock-names = "core", "iface", "xo";
+ mmc-ddr-1_8v;
bus-width = <8>;
non-removable;
status = "disabled";
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v9 14/16] mmc: sdhci-msm: Save the calculated tuning phase
2016-11-21 6:37 ` Ritesh Harjani
` (11 preceding siblings ...)
(?)
@ 2016-11-21 6:37 ` Ritesh Harjani
-1 siblings, 0 replies; 46+ messages in thread
From: Ritesh Harjani @ 2016-11-21 6:37 UTC (permalink / raw)
To: ulf.hansson, linux-mmc, adrian.hunter, sboyd, andy.gross
Cc: shawn.lin, devicetree, linux-clk, david.brown, linux-arm-msm,
georgi.djakov, alex.lemberg, mateusz.nowak, Yuliy.Izrailov,
asutoshd, david.griego, stummala, venkatg, rnayak, pramod.gurav,
jeremymc, Ritesh Harjani
Save the tuning phase once the tuning is performed.
This phase value will be used while calibrating DLL
for HS400 mode.
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
---
drivers/mmc/host/sdhci-msm.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index b1888c3..f4f277b 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -75,6 +75,7 @@
#define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c
+#define INVALID_TUNING_PHASE -1
#define SDHCI_MSM_MIN_CLOCK 400000
#define CORE_FREQ_100MHZ (100 * 1000 * 1000)
@@ -97,6 +98,7 @@ struct sdhci_msm_host {
bool use_14lpp_dll_reset;
bool tuning_done;
bool calibration_done;
+ u8 saved_tuning_phase;
};
/* Platform specific tuning */
@@ -136,6 +138,9 @@ static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
u32 config;
struct mmc_host *mmc = host->mmc;
+ if (phase > 0xf)
+ return -EINVAL;
+
spin_lock_irqsave(&host->lock, flags);
config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
@@ -429,6 +434,8 @@ static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
int rc;
struct mmc_host *mmc = host->mmc;
struct mmc_ios ios = host->mmc->ios;
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
/*
* Tuning is required for SDR104, HS200 and HS400 cards and
@@ -453,6 +460,7 @@ static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
if (rc)
return rc;
+ msm_host->saved_tuning_phase = phase;
rc = mmc_send_tuning(mmc, opcode, NULL);
if (!rc) {
/* Tuning is successful at this tuning point */
@@ -799,6 +807,8 @@ static int sdhci_msm_probe(struct platform_device *pdev)
sdhci_get_of_property(pdev);
+ msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
+
/* Setup SDCC bus voter clock. */
msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
if (!IS_ERR(msm_host->bus_clk)) {
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v9 15/16] mmc: sdhci-msm: Add calibration tuning for CDCLP533 circuit
2016-11-21 6:37 ` Ritesh Harjani
` (12 preceding siblings ...)
(?)
@ 2016-11-21 6:37 ` Ritesh Harjani
-1 siblings, 0 replies; 46+ messages in thread
From: Ritesh Harjani @ 2016-11-21 6:37 UTC (permalink / raw)
To: ulf.hansson, linux-mmc, adrian.hunter, sboyd, andy.gross
Cc: shawn.lin, devicetree, linux-clk, david.brown, linux-arm-msm,
georgi.djakov, alex.lemberg, mateusz.nowak, Yuliy.Izrailov,
asutoshd, david.griego, stummala, venkatg, rnayak, pramod.gurav,
jeremymc, Ritesh Harjani
In HS400 mode a new RCLK is introduced on the interface for read data
transfers. The eMMC5.0 device transmits the read data to the host with
respect to rising and falling edges of RCLK. In order to ensure correct
operation of read data transfers in HS400 mode, the incoming RX data
needs to be sampled by delayed version of RCLK.
The CDCLP533 delay circuit shifts the RCLK by T/4. It needs to be
initialized, configured and enabled once during HS400 mode switch and
when operational voltage/clock is changed.
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
---
drivers/mmc/host/sdhci-msm.c | 151 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 151 insertions(+)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index f4f277b..5c73f7d 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -20,6 +20,7 @@
#include <linux/mmc/mmc.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
+#include <linux/iopoll.h>
#include "sdhci-pltfm.h"
@@ -58,6 +59,7 @@
#define CORE_DLL_PDN BIT(29)
#define CORE_DLL_RST BIT(30)
#define CORE_DLL_CONFIG 0x100
+#define CORE_CMD_DAT_TRACK_SEL BIT(0)
#define CORE_DLL_STATUS 0x108
#define CORE_DLL_CONFIG_2 0x1b4
@@ -73,6 +75,33 @@
#define CORE_HC_SELECT_IN_HS400 (6 << 19)
#define CORE_HC_SELECT_IN_MASK (7 << 19)
+#define CORE_CSR_CDC_CTLR_CFG0 0x130
+#define CORE_SW_TRIG_FULL_CALIB BIT(16)
+#define CORE_HW_AUTOCAL_ENA BIT(17)
+
+#define CORE_CSR_CDC_CTLR_CFG1 0x134
+#define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138
+#define CORE_TIMER_ENA BIT(16)
+
+#define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C
+#define CORE_CSR_CDC_REFCOUNT_CFG 0x140
+#define CORE_CSR_CDC_COARSE_CAL_CFG 0x144
+#define CORE_CDC_OFFSET_CFG 0x14C
+#define CORE_CSR_CDC_DELAY_CFG 0x150
+#define CORE_CDC_SLAVE_DDA_CFG 0x160
+#define CORE_CSR_CDC_STATUS0 0x164
+#define CORE_CALIBRATION_DONE BIT(0)
+
+#define CORE_CDC_ERROR_CODE_MASK 0x7000000
+
+#define CORE_CSR_CDC_GEN_CFG 0x178
+#define CORE_CDC_SWITCH_BYPASS_OFF BIT(0)
+#define CORE_CDC_SWITCH_RC_EN BIT(1)
+
+#define CORE_DDR_200_CFG 0x184
+#define CORE_CDC_T4_DLY_SEL BIT(0)
+#define CORE_START_CDC_TRAFFIC BIT(6)
+
#define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c
#define INVALID_TUNING_PHASE -1
@@ -427,6 +456,119 @@ static int msm_init_cm_dll(struct sdhci_host *host)
return 0;
}
+static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
+ u32 config, calib_done;
+ int ret;
+
+ pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
+
+ /*
+ * Retuning in HS400 (DDR mode) will fail, just reset the
+ * tuning block and restore the saved tuning phase.
+ */
+ ret = msm_init_cm_dll(host);
+ if (ret)
+ goto out;
+
+ /* Set the selected phase in delay line hw block */
+ ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
+ if (ret)
+ goto out;
+
+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config |= CORE_CMD_DAT_TRACK_SEL;
+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+
+ config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
+ config &= ~CORE_CDC_T4_DLY_SEL;
+ writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
+
+ config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
+ config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
+ writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
+
+ config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
+ config |= CORE_CDC_SWITCH_RC_EN;
+ writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
+
+ config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
+ config &= ~CORE_START_CDC_TRAFFIC;
+ writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
+
+ /*
+ * Perform CDC Register Initialization Sequence
+ *
+ * CORE_CSR_CDC_CTLR_CFG0 0x11800EC
+ * CORE_CSR_CDC_CTLR_CFG1 0x3011111
+ * CORE_CSR_CDC_CAL_TIMER_CFG0 0x1201000
+ * CORE_CSR_CDC_CAL_TIMER_CFG1 0x4
+ * CORE_CSR_CDC_REFCOUNT_CFG 0xCB732020
+ * CORE_CSR_CDC_COARSE_CAL_CFG 0xB19
+ * CORE_CSR_CDC_DELAY_CFG 0x3AC
+ * CORE_CDC_OFFSET_CFG 0x0
+ * CORE_CDC_SLAVE_DDA_CFG 0x16334
+ */
+
+ writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+ writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
+ writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
+ writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
+ writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
+ writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
+ writel_relaxed(0x3AC, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
+ writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
+ writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
+
+ /* CDC HW Calibration */
+
+ config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+ config |= CORE_SW_TRIG_FULL_CALIB;
+ writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+
+ config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+ config &= ~CORE_SW_TRIG_FULL_CALIB;
+ writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+
+ config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+ config |= CORE_HW_AUTOCAL_ENA;
+ writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+
+ config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
+ config |= CORE_TIMER_ENA;
+ writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
+
+ ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
+ calib_done,
+ (calib_done & CORE_CALIBRATION_DONE),
+ 1, 50);
+
+ if (ret == -ETIMEDOUT) {
+ pr_err("%s: %s: CDC calibration was not completed\n",
+ mmc_hostname(host->mmc), __func__);
+ goto out;
+ }
+
+ ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
+ & CORE_CDC_ERROR_CODE_MASK;
+ if (ret) {
+ pr_err("%s: %s: CDC error code %d\n",
+ mmc_hostname(host->mmc), __func__, ret);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
+ config |= CORE_START_CDC_TRAFFIC;
+ writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
+out:
+ pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
+ __func__, ret);
+ return ret;
+}
+
static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
{
int tuning_seq_cnt = 3;
@@ -567,6 +709,15 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+
+ spin_unlock_irq(&host->lock);
+ /* CDCLP533 HW calibration is only required for HS400 mode*/
+ if (host->clock > CORE_FREQ_100MHZ &&
+ msm_host->tuning_done && !msm_host->calibration_done &&
+ mmc->ios.timing == MMC_TIMING_MMC_HS400)
+ if (!sdhci_msm_cdclp533_calibration(host))
+ msm_host->calibration_done = true;
+ spin_lock_irq(&host->lock);
}
static void sdhci_msm_voltage_switch(struct sdhci_host *host)
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 46+ messages in thread[parent not found: <1479710246-26676-1-git-send-email-riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>]
* [PATCH v9 10/16] mmc: sdhci-msm: Implement set_clock callback for sdhci-msm
2016-11-21 6:37 ` Ritesh Harjani
@ 2016-11-21 6:37 ` Ritesh Harjani
-1 siblings, 0 replies; 46+ messages in thread
From: Ritesh Harjani @ 2016-11-21 6:37 UTC (permalink / raw)
To: ulf.hansson-QSEj5FYQhm4dnm+yROfE0A,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
adrian.hunter-ral2JQCrhuEAvxtiuMwx3w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, andy.gross-QSEj5FYQhm4dnm+yROfE0A
Cc: shawn.lin-TNX95d0MmH7DzftRWevZcw,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
david.brown-QSEj5FYQhm4dnm+yROfE0A,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
georgi.djakov-QSEj5FYQhm4dnm+yROfE0A,
alex.lemberg-XdAiOPVOjttBDgjK7y7TUQ,
mateusz.nowak-ral2JQCrhuEAvxtiuMwx3w,
Yuliy.Izrailov-XdAiOPVOjttBDgjK7y7TUQ,
asutoshd-sgV2jX0FEOL9JmXXK+q4OQ,
david.griego-QSEj5FYQhm4dnm+yROfE0A,
stummala-sgV2jX0FEOL9JmXXK+q4OQ, venkatg-sgV2jX0FEOL9JmXXK+q4OQ,
rnayak-sgV2jX0FEOL9JmXXK+q4OQ,
pramod.gurav-QSEj5FYQhm4dnm+yROfE0A,
jeremymc-H+wXaHxf7aLQT0dZR+AlfA, Ritesh Harjani
sdhci-msm controller may have different clk-rates for each
bus speed mode. Thus implement set_clock callback for
sdhci-msm driver.
Signed-off-by: Sahitya Tummala <stummala-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Signed-off-by: Ritesh Harjani <riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Acked-by: Adrian Hunter <adrian.hunter-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
---
drivers/mmc/host/sdhci-msm.c | 66 +++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 65 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 15a8b8e..00759ef 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -84,6 +84,7 @@ struct sdhci_msm_host {
struct clk *pclk; /* SDHC peripheral bus clock */
struct clk *bus_clk; /* SDHC bus voter clock */
struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/
+ unsigned long clk_rate;
struct mmc_host *mmc;
bool use_14lpp_dll_reset;
};
@@ -571,6 +572,69 @@ static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
return SDHCI_MSM_MIN_CLOCK;
}
+/**
+ * __sdhci_msm_set_clock - sdhci_msm clock control.
+ *
+ * Description:
+ * MSM controller does not use internal divider and
+ * instead directly control the GCC clock as per
+ * HW recommendation.
+ **/
+void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
+{
+ u16 clk;
+ /*
+ * Keep actual_clock as zero -
+ * - since there is no divider used so no need of having actual_clock.
+ * - MSM controller uses SDCLK for data timeout calculation. If
+ * actual_clock is zero, host->clock is taken for calculation.
+ */
+ host->mmc->actual_clock = 0;
+
+ sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+
+ if (clock == 0)
+ return;
+
+ /*
+ * MSM controller do not use clock divider.
+ * Thus read SDHCI_CLOCK_CONTROL and only enable
+ * clock with no divider value programmed.
+ */
+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ sdhci_enable_clk(host, clk);
+}
+
+/* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
+static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
+ int rc;
+
+ if (!clock) {
+ msm_host->clk_rate = clock;
+ goto out;
+ }
+
+ spin_unlock_irq(&host->lock);
+
+ rc = clk_set_rate(msm_host->clk, clock);
+ if (rc) {
+ pr_err("%s: Failed to set clock at rate %u\n",
+ mmc_hostname(host->mmc), clock);
+ goto out_lock;
+ }
+ msm_host->clk_rate = clock;
+ pr_debug("%s: Setting clock at rate %lu\n",
+ mmc_hostname(host->mmc), clk_get_rate(msm_host->clk));
+
+out_lock:
+ spin_lock_irq(&host->lock);
+out:
+ __sdhci_msm_set_clock(host, clock);
+}
+
static const struct of_device_id sdhci_msm_dt_match[] = {
{ .compatible = "qcom,sdhci-msm-v4" },
{},
@@ -581,7 +645,7 @@ static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
static const struct sdhci_ops sdhci_msm_ops = {
.platform_execute_tuning = sdhci_msm_execute_tuning,
.reset = sdhci_reset,
- .set_clock = sdhci_set_clock,
+ .set_clock = sdhci_msm_set_clock,
.get_min_clock = sdhci_msm_get_min_clock,
.get_max_clock = sdhci_msm_get_max_clock,
.set_bus_width = sdhci_set_bus_width,
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v9 10/16] mmc: sdhci-msm: Implement set_clock callback for sdhci-msm
@ 2016-11-21 6:37 ` Ritesh Harjani
0 siblings, 0 replies; 46+ messages in thread
From: Ritesh Harjani @ 2016-11-21 6:37 UTC (permalink / raw)
To: ulf.hansson, linux-mmc, adrian.hunter, sboyd, andy.gross
Cc: shawn.lin, devicetree, linux-clk, david.brown, linux-arm-msm,
georgi.djakov, alex.lemberg, mateusz.nowak, Yuliy.Izrailov,
asutoshd, david.griego, stummala, venkatg, rnayak, pramod.gurav,
jeremymc, Ritesh Harjani
sdhci-msm controller may have different clk-rates for each
bus speed mode. Thus implement set_clock callback for
sdhci-msm driver.
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
---
drivers/mmc/host/sdhci-msm.c | 66 +++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 65 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 15a8b8e..00759ef 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -84,6 +84,7 @@ struct sdhci_msm_host {
struct clk *pclk; /* SDHC peripheral bus clock */
struct clk *bus_clk; /* SDHC bus voter clock */
struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/
+ unsigned long clk_rate;
struct mmc_host *mmc;
bool use_14lpp_dll_reset;
};
@@ -571,6 +572,69 @@ static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
return SDHCI_MSM_MIN_CLOCK;
}
+/**
+ * __sdhci_msm_set_clock - sdhci_msm clock control.
+ *
+ * Description:
+ * MSM controller does not use internal divider and
+ * instead directly control the GCC clock as per
+ * HW recommendation.
+ **/
+void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
+{
+ u16 clk;
+ /*
+ * Keep actual_clock as zero -
+ * - since there is no divider used so no need of having actual_clock.
+ * - MSM controller uses SDCLK for data timeout calculation. If
+ * actual_clock is zero, host->clock is taken for calculation.
+ */
+ host->mmc->actual_clock = 0;
+
+ sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+
+ if (clock == 0)
+ return;
+
+ /*
+ * MSM controller do not use clock divider.
+ * Thus read SDHCI_CLOCK_CONTROL and only enable
+ * clock with no divider value programmed.
+ */
+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ sdhci_enable_clk(host, clk);
+}
+
+/* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
+static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
+ int rc;
+
+ if (!clock) {
+ msm_host->clk_rate = clock;
+ goto out;
+ }
+
+ spin_unlock_irq(&host->lock);
+
+ rc = clk_set_rate(msm_host->clk, clock);
+ if (rc) {
+ pr_err("%s: Failed to set clock at rate %u\n",
+ mmc_hostname(host->mmc), clock);
+ goto out_lock;
+ }
+ msm_host->clk_rate = clock;
+ pr_debug("%s: Setting clock at rate %lu\n",
+ mmc_hostname(host->mmc), clk_get_rate(msm_host->clk));
+
+out_lock:
+ spin_lock_irq(&host->lock);
+out:
+ __sdhci_msm_set_clock(host, clock);
+}
+
static const struct of_device_id sdhci_msm_dt_match[] = {
{ .compatible = "qcom,sdhci-msm-v4" },
{},
@@ -581,7 +645,7 @@ static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
static const struct sdhci_ops sdhci_msm_ops = {
.platform_execute_tuning = sdhci_msm_execute_tuning,
.reset = sdhci_reset,
- .set_clock = sdhci_set_clock,
+ .set_clock = sdhci_msm_set_clock,
.get_min_clock = sdhci_msm_get_min_clock,
.get_max_clock = sdhci_msm_get_max_clock,
.set_bus_width = sdhci_set_bus_width,
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v9 13/16] mmc: sdhci-msm: Add HS400 platform support
2016-11-21 6:37 ` Ritesh Harjani
@ 2016-11-21 6:37 ` Ritesh Harjani
-1 siblings, 0 replies; 46+ messages in thread
From: Ritesh Harjani @ 2016-11-21 6:37 UTC (permalink / raw)
To: ulf.hansson-QSEj5FYQhm4dnm+yROfE0A,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
adrian.hunter-ral2JQCrhuEAvxtiuMwx3w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, andy.gross-QSEj5FYQhm4dnm+yROfE0A
Cc: shawn.lin-TNX95d0MmH7DzftRWevZcw,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
david.brown-QSEj5FYQhm4dnm+yROfE0A,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
georgi.djakov-QSEj5FYQhm4dnm+yROfE0A,
alex.lemberg-XdAiOPVOjttBDgjK7y7TUQ,
mateusz.nowak-ral2JQCrhuEAvxtiuMwx3w,
Yuliy.Izrailov-XdAiOPVOjttBDgjK7y7TUQ,
asutoshd-sgV2jX0FEOL9JmXXK+q4OQ,
david.griego-QSEj5FYQhm4dnm+yROfE0A,
stummala-sgV2jX0FEOL9JmXXK+q4OQ, venkatg-sgV2jX0FEOL9JmXXK+q4OQ,
rnayak-sgV2jX0FEOL9JmXXK+q4OQ,
pramod.gurav-QSEj5FYQhm4dnm+yROfE0A,
jeremymc-H+wXaHxf7aLQT0dZR+AlfA, Ritesh Harjani
From: Venkat Gopalakrishnan <venkatg-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
The following msm platform specific changes are added to support HS400.
- Allow tuning for HS400 mode.
- Configure HS400 timing mode using the VENDOR_SPECIFIC_FUNC register.
Signed-off-by: Venkat Gopalakrishnan <venkatg-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Signed-off-by: Ritesh Harjani <riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Acked-by: Adrian Hunter <adrian.hunter-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
---
drivers/mmc/host/sdhci-msm.c | 122 +++++++++++++++++++++++++++++++++++++++----
1 file changed, 112 insertions(+), 10 deletions(-)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index c50cee8..b1888c3 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -32,6 +32,7 @@
#define HC_MODE_EN 0x1
#define CORE_POWER 0x0
#define CORE_SW_RST BIT(7)
+#define FF_CLK_SW_RST_DIS BIT(13)
#define CORE_PWRCTL_STATUS 0xdc
#define CORE_PWRCTL_MASK 0xe0
@@ -65,10 +66,17 @@
#define CORE_VENDOR_SPEC 0x10c
#define CORE_CLK_PWRSAVE BIT(1)
+#define CORE_HC_MCLK_SEL_DFLT (2 << 8)
+#define CORE_HC_MCLK_SEL_HS400 (3 << 8)
+#define CORE_HC_MCLK_SEL_MASK (3 << 8)
+#define CORE_HC_SELECT_IN_EN BIT(18)
+#define CORE_HC_SELECT_IN_HS400 (6 << 19)
+#define CORE_HC_SELECT_IN_MASK (7 << 19)
#define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c
#define SDHCI_MSM_MIN_CLOCK 400000
+#define CORE_FREQ_100MHZ (100 * 1000 * 1000)
#define CDR_SELEXT_SHIFT 20
#define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
@@ -87,6 +95,8 @@ struct sdhci_msm_host {
unsigned long clk_rate;
struct mmc_host *mmc;
bool use_14lpp_dll_reset;
+ bool tuning_done;
+ bool calibration_done;
};
/* Platform specific tuning */
@@ -174,8 +184,8 @@ static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
* Find out the greatest range of consecuitive selected
* DLL clock output phases that can be used as sampling
* setting for SD3.0 UHS-I card read operation (in SDR104
- * timing mode) or for eMMC4.5 card read operation (in HS200
- * timing mode).
+ * timing mode) or for eMMC4.5 card read operation (in
+ * HS400/HS200 timing mode).
* Select the 3/4 of the range and configure the DLL with the
* selected DLL clock output phase.
*/
@@ -424,9 +434,10 @@ static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
* Tuning is required for SDR104, HS200 and HS400 cards and
* if clock frequency is greater than 100MHz in these modes.
*/
- if (host->clock <= 100 * 1000 * 1000 ||
- !((ios.timing == MMC_TIMING_MMC_HS200) ||
- (ios.timing == MMC_TIMING_UHS_SDR104)))
+ if (host->clock <= CORE_FREQ_100MHZ ||
+ !(ios.timing == MMC_TIMING_MMC_HS400 ||
+ ios.timing == MMC_TIMING_MMC_HS200 ||
+ ios.timing == MMC_TIMING_UHS_SDR104))
return 0;
retry:
@@ -477,6 +488,8 @@ static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
rc = -EIO;
}
+ if (!rc)
+ msm_host->tuning_done = true;
return rc;
}
@@ -484,7 +497,10 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
unsigned int uhs)
{
struct mmc_host *mmc = host->mmc;
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
u16 ctrl_2;
+ u32 config;
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
/* Select Bus Speed Mode for host */
@@ -499,6 +515,7 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
case MMC_TIMING_UHS_SDR50:
ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
break;
+ case MMC_TIMING_MMC_HS400:
case MMC_TIMING_MMC_HS200:
case MMC_TIMING_UHS_SDR104:
ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
@@ -515,11 +532,29 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
* provide feedback clock, the mode selection can be any value less
* than 3'b011 in bits [2:0] of HOST CONTROL2 register.
*/
- if (host->clock <= 100000000 &&
- (uhs == MMC_TIMING_MMC_HS400 ||
- uhs == MMC_TIMING_MMC_HS200 ||
- uhs == MMC_TIMING_UHS_SDR104))
- ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+ if (host->clock <= CORE_FREQ_100MHZ) {
+ if (uhs == MMC_TIMING_MMC_HS400 ||
+ uhs == MMC_TIMING_MMC_HS200 ||
+ uhs == MMC_TIMING_UHS_SDR104)
+ ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+ /*
+ * DLL is not required for clock <= 100MHz
+ * Thus, make sure DLL it is disabled when not required
+ */
+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config |= CORE_DLL_RST;
+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+
+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config |= CORE_DLL_PDN;
+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+
+ /*
+ * The DLL needs to be restored and CDCLP533 recalibrated
+ * when the clock frequency is set back to 400MHz.
+ */
+ msm_host->calibration_done = false;
+ }
dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
@@ -611,6 +646,7 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
struct mmc_ios curr_ios = host->mmc->ios;
+ u32 config;
int rc;
if (!clock) {
@@ -629,6 +665,68 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
curr_ios.timing == MMC_TIMING_MMC_DDR52 ||
curr_ios.timing == MMC_TIMING_MMC_HS400)
clock *= 2;
+ /*
+ * In general all timing modes are controlled via UHS mode select in
+ * Host Control2 register. eMMC specific HS200/HS400 doesn't have
+ * their respective modes defined here, hence we use these values.
+ *
+ * HS200 - SDR104 (Since they both are equivalent in functionality)
+ * HS400 - This involves multiple configurations
+ * Initially SDR104 - when tuning is required as HS200
+ * Then when switching to DDR @ 400MHz (HS400) we use
+ * the vendor specific HC_SELECT_IN to control the mode.
+ *
+ * In addition to controlling the modes we also need to select the
+ * correct input clock for DLL depending on the mode.
+ *
+ * HS400 - divided clock (free running MCLK/2)
+ * All other modes - default (free running MCLK)
+ */
+ if (curr_ios.timing == MMC_TIMING_MMC_HS400) {
+ /* Select the divided clock (free running MCLK/2) */
+ config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
+ config &= ~CORE_HC_MCLK_SEL_MASK;
+ config |= CORE_HC_MCLK_SEL_HS400;
+
+ writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
+ /*
+ * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
+ * register
+ */
+ if (msm_host->tuning_done && !msm_host->calibration_done) {
+ /*
+ * Write 0x6 to HC_SELECT_IN and 1 to HC_SELECT_IN_EN
+ * field in VENDOR_SPEC_FUNC
+ */
+ config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
+ config |= CORE_HC_SELECT_IN_HS400;
+ config |= CORE_HC_SELECT_IN_EN;
+ writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
+ }
+ } else {
+ config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
+ config &= ~CORE_HC_MCLK_SEL_MASK;
+ config |= CORE_HC_MCLK_SEL_DFLT;
+ writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
+
+ /*
+ * Disable HC_SELECT_IN to be able to use the UHS mode select
+ * configuration from Host Control2 register for all other
+ * modes.
+ * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
+ * in VENDOR_SPEC_FUNC
+ */
+ config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
+ config &= ~CORE_HC_SELECT_IN_EN;
+ config &= ~CORE_HC_SELECT_IN_MASK;
+ writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
+ }
+
+ /*
+ * Make sure above writes impacting free running MCLK are completed
+ * before changing the clk_rate at GCC.
+ */
+ wmb();
rc = clk_set_rate(msm_host->clk, clock);
if (rc) {
@@ -776,6 +874,10 @@ static int sdhci_msm_probe(struct platform_device *pdev)
/* Set HC_MODE_EN bit in HC_MODE register */
writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
+ config = readl_relaxed(msm_host->core_mem + CORE_HC_MODE);
+ config |= FF_CLK_SW_RST_DIS;
+ writel_relaxed(config, msm_host->core_mem + CORE_HC_MODE);
+
host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
--
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a Linux Foundation Collaborative Project.
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^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v9 13/16] mmc: sdhci-msm: Add HS400 platform support
@ 2016-11-21 6:37 ` Ritesh Harjani
0 siblings, 0 replies; 46+ messages in thread
From: Ritesh Harjani @ 2016-11-21 6:37 UTC (permalink / raw)
To: ulf.hansson, linux-mmc, adrian.hunter, sboyd, andy.gross
Cc: shawn.lin, devicetree, linux-clk, david.brown, linux-arm-msm,
georgi.djakov, alex.lemberg, mateusz.nowak, Yuliy.Izrailov,
asutoshd, david.griego, stummala, venkatg, rnayak, pramod.gurav,
jeremymc, Ritesh Harjani
From: Venkat Gopalakrishnan <venkatg@codeaurora.org>
The following msm platform specific changes are added to support HS400.
- Allow tuning for HS400 mode.
- Configure HS400 timing mode using the VENDOR_SPECIFIC_FUNC register.
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
---
drivers/mmc/host/sdhci-msm.c | 122 +++++++++++++++++++++++++++++++++++++++----
1 file changed, 112 insertions(+), 10 deletions(-)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index c50cee8..b1888c3 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -32,6 +32,7 @@
#define HC_MODE_EN 0x1
#define CORE_POWER 0x0
#define CORE_SW_RST BIT(7)
+#define FF_CLK_SW_RST_DIS BIT(13)
#define CORE_PWRCTL_STATUS 0xdc
#define CORE_PWRCTL_MASK 0xe0
@@ -65,10 +66,17 @@
#define CORE_VENDOR_SPEC 0x10c
#define CORE_CLK_PWRSAVE BIT(1)
+#define CORE_HC_MCLK_SEL_DFLT (2 << 8)
+#define CORE_HC_MCLK_SEL_HS400 (3 << 8)
+#define CORE_HC_MCLK_SEL_MASK (3 << 8)
+#define CORE_HC_SELECT_IN_EN BIT(18)
+#define CORE_HC_SELECT_IN_HS400 (6 << 19)
+#define CORE_HC_SELECT_IN_MASK (7 << 19)
#define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c
#define SDHCI_MSM_MIN_CLOCK 400000
+#define CORE_FREQ_100MHZ (100 * 1000 * 1000)
#define CDR_SELEXT_SHIFT 20
#define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
@@ -87,6 +95,8 @@ struct sdhci_msm_host {
unsigned long clk_rate;
struct mmc_host *mmc;
bool use_14lpp_dll_reset;
+ bool tuning_done;
+ bool calibration_done;
};
/* Platform specific tuning */
@@ -174,8 +184,8 @@ static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
* Find out the greatest range of consecuitive selected
* DLL clock output phases that can be used as sampling
* setting for SD3.0 UHS-I card read operation (in SDR104
- * timing mode) or for eMMC4.5 card read operation (in HS200
- * timing mode).
+ * timing mode) or for eMMC4.5 card read operation (in
+ * HS400/HS200 timing mode).
* Select the 3/4 of the range and configure the DLL with the
* selected DLL clock output phase.
*/
@@ -424,9 +434,10 @@ static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
* Tuning is required for SDR104, HS200 and HS400 cards and
* if clock frequency is greater than 100MHz in these modes.
*/
- if (host->clock <= 100 * 1000 * 1000 ||
- !((ios.timing == MMC_TIMING_MMC_HS200) ||
- (ios.timing == MMC_TIMING_UHS_SDR104)))
+ if (host->clock <= CORE_FREQ_100MHZ ||
+ !(ios.timing == MMC_TIMING_MMC_HS400 ||
+ ios.timing == MMC_TIMING_MMC_HS200 ||
+ ios.timing == MMC_TIMING_UHS_SDR104))
return 0;
retry:
@@ -477,6 +488,8 @@ static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
rc = -EIO;
}
+ if (!rc)
+ msm_host->tuning_done = true;
return rc;
}
@@ -484,7 +497,10 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
unsigned int uhs)
{
struct mmc_host *mmc = host->mmc;
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
u16 ctrl_2;
+ u32 config;
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
/* Select Bus Speed Mode for host */
@@ -499,6 +515,7 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
case MMC_TIMING_UHS_SDR50:
ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
break;
+ case MMC_TIMING_MMC_HS400:
case MMC_TIMING_MMC_HS200:
case MMC_TIMING_UHS_SDR104:
ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
@@ -515,11 +532,29 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
* provide feedback clock, the mode selection can be any value less
* than 3'b011 in bits [2:0] of HOST CONTROL2 register.
*/
- if (host->clock <= 100000000 &&
- (uhs == MMC_TIMING_MMC_HS400 ||
- uhs == MMC_TIMING_MMC_HS200 ||
- uhs == MMC_TIMING_UHS_SDR104))
- ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+ if (host->clock <= CORE_FREQ_100MHZ) {
+ if (uhs == MMC_TIMING_MMC_HS400 ||
+ uhs == MMC_TIMING_MMC_HS200 ||
+ uhs == MMC_TIMING_UHS_SDR104)
+ ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+ /*
+ * DLL is not required for clock <= 100MHz
+ * Thus, make sure DLL it is disabled when not required
+ */
+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config |= CORE_DLL_RST;
+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+
+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config |= CORE_DLL_PDN;
+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+
+ /*
+ * The DLL needs to be restored and CDCLP533 recalibrated
+ * when the clock frequency is set back to 400MHz.
+ */
+ msm_host->calibration_done = false;
+ }
dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
@@ -611,6 +646,7 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
struct mmc_ios curr_ios = host->mmc->ios;
+ u32 config;
int rc;
if (!clock) {
@@ -629,6 +665,68 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
curr_ios.timing == MMC_TIMING_MMC_DDR52 ||
curr_ios.timing == MMC_TIMING_MMC_HS400)
clock *= 2;
+ /*
+ * In general all timing modes are controlled via UHS mode select in
+ * Host Control2 register. eMMC specific HS200/HS400 doesn't have
+ * their respective modes defined here, hence we use these values.
+ *
+ * HS200 - SDR104 (Since they both are equivalent in functionality)
+ * HS400 - This involves multiple configurations
+ * Initially SDR104 - when tuning is required as HS200
+ * Then when switching to DDR @ 400MHz (HS400) we use
+ * the vendor specific HC_SELECT_IN to control the mode.
+ *
+ * In addition to controlling the modes we also need to select the
+ * correct input clock for DLL depending on the mode.
+ *
+ * HS400 - divided clock (free running MCLK/2)
+ * All other modes - default (free running MCLK)
+ */
+ if (curr_ios.timing == MMC_TIMING_MMC_HS400) {
+ /* Select the divided clock (free running MCLK/2) */
+ config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
+ config &= ~CORE_HC_MCLK_SEL_MASK;
+ config |= CORE_HC_MCLK_SEL_HS400;
+
+ writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
+ /*
+ * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
+ * register
+ */
+ if (msm_host->tuning_done && !msm_host->calibration_done) {
+ /*
+ * Write 0x6 to HC_SELECT_IN and 1 to HC_SELECT_IN_EN
+ * field in VENDOR_SPEC_FUNC
+ */
+ config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
+ config |= CORE_HC_SELECT_IN_HS400;
+ config |= CORE_HC_SELECT_IN_EN;
+ writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
+ }
+ } else {
+ config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
+ config &= ~CORE_HC_MCLK_SEL_MASK;
+ config |= CORE_HC_MCLK_SEL_DFLT;
+ writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
+
+ /*
+ * Disable HC_SELECT_IN to be able to use the UHS mode select
+ * configuration from Host Control2 register for all other
+ * modes.
+ * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
+ * in VENDOR_SPEC_FUNC
+ */
+ config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
+ config &= ~CORE_HC_SELECT_IN_EN;
+ config &= ~CORE_HC_SELECT_IN_MASK;
+ writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
+ }
+
+ /*
+ * Make sure above writes impacting free running MCLK are completed
+ * before changing the clk_rate at GCC.
+ */
+ wmb();
rc = clk_set_rate(msm_host->clk, clock);
if (rc) {
@@ -776,6 +874,10 @@ static int sdhci_msm_probe(struct platform_device *pdev)
/* Set HC_MODE_EN bit in HC_MODE register */
writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
+ config = readl_relaxed(msm_host->core_mem + CORE_HC_MODE);
+ config |= FF_CLK_SW_RST_DIS;
+ writel_relaxed(config, msm_host->core_mem + CORE_HC_MODE);
+
host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v9 16/16] sdhci: sdhci-msm: update dll configuration
2016-11-21 6:37 ` Ritesh Harjani
@ 2016-11-21 6:37 ` Ritesh Harjani
-1 siblings, 0 replies; 46+ messages in thread
From: Ritesh Harjani @ 2016-11-21 6:37 UTC (permalink / raw)
To: ulf.hansson-QSEj5FYQhm4dnm+yROfE0A,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
adrian.hunter-ral2JQCrhuEAvxtiuMwx3w,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, andy.gross-QSEj5FYQhm4dnm+yROfE0A
Cc: shawn.lin-TNX95d0MmH7DzftRWevZcw,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
david.brown-QSEj5FYQhm4dnm+yROfE0A,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
georgi.djakov-QSEj5FYQhm4dnm+yROfE0A,
alex.lemberg-XdAiOPVOjttBDgjK7y7TUQ,
mateusz.nowak-ral2JQCrhuEAvxtiuMwx3w,
Yuliy.Izrailov-XdAiOPVOjttBDgjK7y7TUQ,
asutoshd-sgV2jX0FEOL9JmXXK+q4OQ,
david.griego-QSEj5FYQhm4dnm+yROfE0A,
stummala-sgV2jX0FEOL9JmXXK+q4OQ, venkatg-sgV2jX0FEOL9JmXXK+q4OQ,
rnayak-sgV2jX0FEOL9JmXXK+q4OQ,
pramod.gurav-QSEj5FYQhm4dnm+yROfE0A,
jeremymc-H+wXaHxf7aLQT0dZR+AlfA, Ritesh Harjani, Krishna Konda
The newer msm sdhci's cores use a different DLL hardware for HS400.
Update the configuration and calibration of the newer DLL block.
The HS400 DLL block used previously is CDC LP 533 and requires
programming multiple registers and waiting for configuration to
complete and then enable it. It has about 18 register writes and
two register reads.
The newer HS400 DLL block is SDC4 DLL and requires two register
writes for configuration and one register read to confirm that it
is initialized. There is an additional register write to enable
the power save mode for SDC4 DLL block.
Signed-off-by: Ritesh Harjani <riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Signed-off-by: Krishna Konda <kkonda-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Acked-by: Adrian Hunter <adrian.hunter-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
---
drivers/mmc/host/sdhci-msm.c | 125 ++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 123 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 5c73f7d..32879b8 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -52,6 +52,7 @@
#define INT_MASK 0xf
#define MAX_PHASES 16
#define CORE_DLL_LOCK BIT(7)
+#define CORE_DDR_DLL_LOCK BIT(11)
#define CORE_DLL_EN BIT(16)
#define CORE_CDR_EN BIT(17)
#define CORE_CK_OUT_EN BIT(18)
@@ -63,6 +64,7 @@
#define CORE_DLL_STATUS 0x108
#define CORE_DLL_CONFIG_2 0x1b4
+#define CORE_DDR_CAL_EN BIT(0)
#define CORE_FLL_CYCLE_CNT BIT(18)
#define CORE_DLL_CLOCK_DISABLE BIT(21)
@@ -101,6 +103,11 @@
#define CORE_DDR_200_CFG 0x184
#define CORE_CDC_T4_DLY_SEL BIT(0)
#define CORE_START_CDC_TRAFFIC BIT(6)
+#define CORE_VENDOR_SPEC3 0x1b0
+#define CORE_PWRSAVE_DLL BIT(3)
+
+#define CORE_DDR_CONFIG 0x1b8
+#define DDR_CONFIG_POR_VAL 0x80040853
#define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c
@@ -128,6 +135,7 @@ struct sdhci_msm_host {
bool tuning_done;
bool calibration_done;
u8 saved_tuning_phase;
+ bool use_cdclp533;
};
/* Platform specific tuning */
@@ -569,6 +577,87 @@ static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
return ret;
}
+static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
+{
+ u32 dll_status, config;
+ int ret;
+
+ pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
+
+ /*
+ * Currently the CORE_DDR_CONFIG register defaults to desired
+ * configuration on reset. Currently reprogramming the power on
+ * reset (POR) value in case it might have been modified by
+ * bootloaders. In the future, if this changes, then the desired
+ * values will need to be programmed appropriately.
+ */
+ writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + CORE_DDR_CONFIG);
+
+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
+ config |= CORE_DDR_CAL_EN;
+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
+
+ ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_DLL_STATUS,
+ dll_status,
+ (dll_status & CORE_DDR_DLL_LOCK),
+ 10, 1000);
+
+ if (ret == -ETIMEDOUT) {
+ pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
+ mmc_hostname(host->mmc), __func__);
+ goto out;
+ }
+
+ config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC3);
+ config |= CORE_PWRSAVE_DLL;
+ writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC3);
+
+ /*
+ * Drain writebuffer to ensure above DLL calibration
+ * and PWRSAVE DLL is enabled.
+ */
+ wmb();
+out:
+ pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
+ __func__, ret);
+ return ret;
+}
+
+static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
+ int ret;
+ u32 config;
+
+ pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
+
+ /*
+ * Retuning in HS400 (DDR mode) will fail, just reset the
+ * tuning block and restore the saved tuning phase.
+ */
+ ret = msm_init_cm_dll(host);
+ if (ret)
+ goto out;
+
+ /* Set the selected phase in delay line hw block */
+ ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
+ if (ret)
+ goto out;
+
+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config |= CORE_CMD_DAT_TRACK_SEL;
+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+ if (msm_host->use_cdclp533)
+ ret = sdhci_msm_cdclp533_calibration(host);
+ else
+ ret = sdhci_msm_cm_dll_sdc4_calibration(host);
+out:
+ pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
+ __func__, ret);
+ return ret;
+}
+
static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
{
int tuning_seq_cnt = 3;
@@ -715,7 +804,7 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
if (host->clock > CORE_FREQ_100MHZ &&
msm_host->tuning_done && !msm_host->calibration_done &&
mmc->ios.timing == MMC_TIMING_MMC_HS400)
- if (!sdhci_msm_cdclp533_calibration(host))
+ if (!sdhci_msm_hs400_dll_calibration(host))
msm_host->calibration_done = true;
spin_lock_irq(&host->lock);
}
@@ -805,7 +894,7 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
struct mmc_ios curr_ios = host->mmc->ios;
- u32 config;
+ u32 config, dll_lock;
int rc;
if (!clock) {
@@ -862,7 +951,32 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
config |= CORE_HC_SELECT_IN_EN;
writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
}
+ if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
+ /*
+ * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
+ * CORE_DLL_STATUS to be set. This should get set
+ * within 15 us at 200 MHz.
+ */
+ rc = readl_relaxed_poll_timeout(host->ioaddr +
+ CORE_DLL_STATUS,
+ dll_lock,
+ (dll_lock &
+ (CORE_DLL_LOCK |
+ CORE_DDR_DLL_LOCK)), 10,
+ 1000);
+ if (rc == -ETIMEDOUT)
+ pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
+ mmc_hostname(host->mmc), dll_lock);
+ }
} else {
+ if (!msm_host->use_cdclp533) {
+ config = readl_relaxed(host->ioaddr +
+ CORE_VENDOR_SPEC3);
+ config &= ~CORE_PWRSAVE_DLL;
+ writel_relaxed(config, host->ioaddr +
+ CORE_VENDOR_SPEC3);
+ }
+
config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
config &= ~CORE_HC_MCLK_SEL_MASK;
config |= CORE_HC_MCLK_SEL_DFLT;
@@ -1055,6 +1169,13 @@ static int sdhci_msm_probe(struct platform_device *pdev)
msm_host->use_14lpp_dll_reset = true;
/*
+ * SDCC 5 controller with major version 1, minor version 0x34 and later
+ * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
+ */
+ if (core_major == 1 && core_minor < 0x34)
+ msm_host->use_cdclp533 = true;
+
+ /*
* Support for some capabilities is not advertised by newer
* controller versions and must be explicitly enabled.
*/
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
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^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v9 16/16] sdhci: sdhci-msm: update dll configuration
@ 2016-11-21 6:37 ` Ritesh Harjani
0 siblings, 0 replies; 46+ messages in thread
From: Ritesh Harjani @ 2016-11-21 6:37 UTC (permalink / raw)
To: ulf.hansson, linux-mmc, adrian.hunter, sboyd, andy.gross
Cc: shawn.lin, devicetree, linux-clk, david.brown, linux-arm-msm,
georgi.djakov, alex.lemberg, mateusz.nowak, Yuliy.Izrailov,
asutoshd, david.griego, stummala, venkatg, rnayak, pramod.gurav,
jeremymc, Ritesh Harjani, Krishna Konda
The newer msm sdhci's cores use a different DLL hardware for HS400.
Update the configuration and calibration of the newer DLL block.
The HS400 DLL block used previously is CDC LP 533 and requires
programming multiple registers and waiting for configuration to
complete and then enable it. It has about 18 register writes and
two register reads.
The newer HS400 DLL block is SDC4 DLL and requires two register
writes for configuration and one register read to confirm that it
is initialized. There is an additional register write to enable
the power save mode for SDC4 DLL block.
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
---
drivers/mmc/host/sdhci-msm.c | 125 ++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 123 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 5c73f7d..32879b8 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -52,6 +52,7 @@
#define INT_MASK 0xf
#define MAX_PHASES 16
#define CORE_DLL_LOCK BIT(7)
+#define CORE_DDR_DLL_LOCK BIT(11)
#define CORE_DLL_EN BIT(16)
#define CORE_CDR_EN BIT(17)
#define CORE_CK_OUT_EN BIT(18)
@@ -63,6 +64,7 @@
#define CORE_DLL_STATUS 0x108
#define CORE_DLL_CONFIG_2 0x1b4
+#define CORE_DDR_CAL_EN BIT(0)
#define CORE_FLL_CYCLE_CNT BIT(18)
#define CORE_DLL_CLOCK_DISABLE BIT(21)
@@ -101,6 +103,11 @@
#define CORE_DDR_200_CFG 0x184
#define CORE_CDC_T4_DLY_SEL BIT(0)
#define CORE_START_CDC_TRAFFIC BIT(6)
+#define CORE_VENDOR_SPEC3 0x1b0
+#define CORE_PWRSAVE_DLL BIT(3)
+
+#define CORE_DDR_CONFIG 0x1b8
+#define DDR_CONFIG_POR_VAL 0x80040853
#define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c
@@ -128,6 +135,7 @@ struct sdhci_msm_host {
bool tuning_done;
bool calibration_done;
u8 saved_tuning_phase;
+ bool use_cdclp533;
};
/* Platform specific tuning */
@@ -569,6 +577,87 @@ static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
return ret;
}
+static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
+{
+ u32 dll_status, config;
+ int ret;
+
+ pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
+
+ /*
+ * Currently the CORE_DDR_CONFIG register defaults to desired
+ * configuration on reset. Currently reprogramming the power on
+ * reset (POR) value in case it might have been modified by
+ * bootloaders. In the future, if this changes, then the desired
+ * values will need to be programmed appropriately.
+ */
+ writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + CORE_DDR_CONFIG);
+
+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
+ config |= CORE_DDR_CAL_EN;
+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
+
+ ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_DLL_STATUS,
+ dll_status,
+ (dll_status & CORE_DDR_DLL_LOCK),
+ 10, 1000);
+
+ if (ret == -ETIMEDOUT) {
+ pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
+ mmc_hostname(host->mmc), __func__);
+ goto out;
+ }
+
+ config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC3);
+ config |= CORE_PWRSAVE_DLL;
+ writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC3);
+
+ /*
+ * Drain writebuffer to ensure above DLL calibration
+ * and PWRSAVE DLL is enabled.
+ */
+ wmb();
+out:
+ pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
+ __func__, ret);
+ return ret;
+}
+
+static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
+ int ret;
+ u32 config;
+
+ pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
+
+ /*
+ * Retuning in HS400 (DDR mode) will fail, just reset the
+ * tuning block and restore the saved tuning phase.
+ */
+ ret = msm_init_cm_dll(host);
+ if (ret)
+ goto out;
+
+ /* Set the selected phase in delay line hw block */
+ ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
+ if (ret)
+ goto out;
+
+ config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+ config |= CORE_CMD_DAT_TRACK_SEL;
+ writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+ if (msm_host->use_cdclp533)
+ ret = sdhci_msm_cdclp533_calibration(host);
+ else
+ ret = sdhci_msm_cm_dll_sdc4_calibration(host);
+out:
+ pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
+ __func__, ret);
+ return ret;
+}
+
static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
{
int tuning_seq_cnt = 3;
@@ -715,7 +804,7 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
if (host->clock > CORE_FREQ_100MHZ &&
msm_host->tuning_done && !msm_host->calibration_done &&
mmc->ios.timing == MMC_TIMING_MMC_HS400)
- if (!sdhci_msm_cdclp533_calibration(host))
+ if (!sdhci_msm_hs400_dll_calibration(host))
msm_host->calibration_done = true;
spin_lock_irq(&host->lock);
}
@@ -805,7 +894,7 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
struct mmc_ios curr_ios = host->mmc->ios;
- u32 config;
+ u32 config, dll_lock;
int rc;
if (!clock) {
@@ -862,7 +951,32 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
config |= CORE_HC_SELECT_IN_EN;
writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
}
+ if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
+ /*
+ * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
+ * CORE_DLL_STATUS to be set. This should get set
+ * within 15 us at 200 MHz.
+ */
+ rc = readl_relaxed_poll_timeout(host->ioaddr +
+ CORE_DLL_STATUS,
+ dll_lock,
+ (dll_lock &
+ (CORE_DLL_LOCK |
+ CORE_DDR_DLL_LOCK)), 10,
+ 1000);
+ if (rc == -ETIMEDOUT)
+ pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
+ mmc_hostname(host->mmc), dll_lock);
+ }
} else {
+ if (!msm_host->use_cdclp533) {
+ config = readl_relaxed(host->ioaddr +
+ CORE_VENDOR_SPEC3);
+ config &= ~CORE_PWRSAVE_DLL;
+ writel_relaxed(config, host->ioaddr +
+ CORE_VENDOR_SPEC3);
+ }
+
config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
config &= ~CORE_HC_MCLK_SEL_MASK;
config |= CORE_HC_MCLK_SEL_DFLT;
@@ -1055,6 +1169,13 @@ static int sdhci_msm_probe(struct platform_device *pdev)
msm_host->use_14lpp_dll_reset = true;
/*
+ * SDCC 5 controller with major version 1, minor version 0x34 and later
+ * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
+ */
+ if (core_major == 1 && core_minor < 0x34)
+ msm_host->use_cdclp533 = true;
+
+ /*
* Support for some capabilities is not advertised by newer
* controller versions and must be explicitly enabled.
*/
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 46+ messages in thread
* Re: [PATCH v9 00/16] mmc: sdhci-msm: Add clk-rates, DDR, HS400 support
2016-11-21 6:37 ` Ritesh Harjani
@ 2016-11-21 10:06 ` Ulf Hansson
-1 siblings, 0 replies; 46+ messages in thread
From: Ulf Hansson @ 2016-11-21 10:06 UTC (permalink / raw)
To: Ritesh Harjani
Cc: linux-mmc, Adrian Hunter, Stephen Boyd, Andy Gross, Shawn Lin,
devicetree-u79uwXL29TY76Z2rM5mHXA, linux-clk, David Brown,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA, Georgi Djakov,
Alex Lemberg, Mateusz Nowak, Yuliy Izrailov, Asutosh Das,
David Griego, Sahitya Tummala, Venkat Gopalakrishnan,
Rajendra Nayak
On 21 November 2016 at 07:37, Ritesh Harjani <riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> wrote:
> Hi,
>
> This is v9 version of the patch series which adds support for MSM8996.
> Adds HS400 driver support as well.
> These are tested on internal msm8996 & db410c HW.
>
> The patch series is ready. Do we think we can apply these
> patches for next now?
I guess the DTS changes can be picked up by Andy, so they can go via arm-soc?
Then, does the mmc changes depend on the clock changes? If so, I can
pick them as well, but then I need an ack from Stephen....
Kind regards
Uffe
>
> There are only minor changes in v9.
> 1. From <&xo_board 0> -> <&xo_board>.
> 2. Addressed Adrian minor comments on 009.
> 3. Other minor changes.
>
>
> Older history:-
>
> Changes from v7 -> v8 :-
> 1. Added patch 005 to add dt bindings for xo_clock.
> 2. Added patch 009 to factor out sdhci_enable_clock as discussed on v7 series.
> 2.a. Modified patch 010 by making use of sdhci_enable_clock.
> 2.b. Addressed Stephen's comment on patch 010 to call clk_set_rate unconditionally.
> 3. Addressed Stephen comments to remove unncessary one line comments, braces and other
> minor comments.
> 4. Added changes from Jeremy in patch 002 for gcc-msm8994 as well for sdcc clk_rcg2_floor_ops.
> minor comments.
>
> v7 was verified on my Nexus 5X (msm8992).
>
> Older history :-
> Below are the changes in v7.
>
> Changes from v6 -> v7 :-
> 1. Removed patch "clk: Add clk_hw_get_clk() helper API to be used by clk providers"
> in v7 as it was not required.
> 2. Addressed Stephen review comments on -
> "clk: qcom: Add rcg ops to return floor value closest to the requested rate"
> 3. Addressed comments from Stephen to add xo_clock entry in the sdhc clock node.
> Using the same xo_clock entry from DT to get the clk_rate of xo_clock used in
> sdhci-msm driver. Patch 04 adds this entry into DT.
> Patch 05 adds the driver support for xo_clock mentioned above.
> Hence there is a minor change in Patch05, which can be reviewed and taken
> into the tree.
>
> IMHO, almost all patches are almost done and are ready to be accepted.
> Will below process work out?
> Patches 001 & 002 :- (clock changes) - Can go via Stephen's Boyd Tree.
> Patches 004 & 010 :- (DTS changes) - Can go via Andy Gross.
> Patches 003, 005-009 & 011-014 :- (sdhci-msm changes) - Adrian's tree.
>
> Please let me know in case if anything else is required on above.
>
>
> Changes from v5 -> v6 :-
> 1. Earlier in v5 series DT node was added to get the clk-rates table
> needed for sdhci-msm driver. But this is removed in this(v6) patch series
> and instead the clk changes are done in the clk driver as per Rob H comment.
>
> 2. Added clk driver changes(patch 1-3) to provide floor rate values of requested
> clock for sdhc client.
> For following boards- apq8084, msm8996, msm8916, msm8974.
>
> 3. Other minor patch comments were addressed.
>
> Changes from v4 -> v5 :-
> 1. Added HS400 sdhci-msm controller specific changes:- (Patch 10, 11, 12)
> 2. Addressed comment from Adrian on Patch 07 @[3].
> 3. Addressed comment from Arnd on Patch 03, to directly add
> clk_table into sdhci_msm_host. [4]
> 4. Addressed comment from Bjorn to not enforce having clk-rates property
> in DT for older targets based on discussion at [5]
> 5. Retained Acks from Adrian on patches (01 & 02 & 06) where there were no
> changes made while addressing above comments.
>
> Older history:-
> This is v4 version of the patch series.
> Patches 01, 02, 05 & 06 were Acked-by Adrian.
>
> Changes from v3 -> v4 :-
> 1. Addressed comments from Adrian on Patch 03, 07, 08.
> 2. Addressed comments from Bjorn on Patch 03.
> 3. Added clk-rate support for sdhc DT nodes to all MSM platforms.
> in Pacth 04.
> 4. Rebased on next branch of Ulf.
>
> Changes from v2 -> v3 :-
> 1. Addded Patch 01 based on Bjorn comment[2] -
> This fixes/unrolls the poor coding style of read/writes of
> registers from base sdhci-msm driver.
>
> 2. Fixed/unrolled poor style of reads/writes of registers in Patch 02,
> based on Bjorn comment[2]. Also changed name of flag from
> use_updated_dll_reset -> use_14lpp_dll_reset.
>
> Changes from v1->v2 :-
> 1. Removed patch 06 & 08 from v1 patch series[1]
> (which were introducing unnecessary quirks).
> Instead have implemented __sdhci_msm_set_clock version of
> sdhci_set_clock in sdhci_msm driver itself in patch 07 of
> this patch series.
> 2. Enabled extra quirk (SDHCI_QUIRK2_PRESET_VALUE_BROKEN) in
> patch 05 of this patch series.
>
>
> Description of patches :-
> This patchset adds clk-rates & other required changes to
> upstream sdhci-msm driver from codeaurora tree.
> It has been tested on a db410c Dragonboard and msm8996 based
> platform.
>
> Patch 0001-0003- Adds support in qcom clk driver to return
> floor value of requested clock rate instead of ceil rate
> for sdhc clients.
>
> Patch 0004- Adds updated dll sequence for newer controllers
> which has minor_version >= 0x42. This is required for msm8996.
>
> MSM controller HW recommendation is to use the base MCI clock
> and directly control this MCI clock at GCC in order to
> change the clk-rate.
> Patches 06-08 bring in required change for this to
> sdhci-msm.
>
> MSM controller would require 2x clock rate from source
> for DDR bus speed modes. Patch 09 adds this support.
>
> Patch 0010- adds DDR support in DT for sdhc1 of msm8916.
>
> Patches 0011-0014- Adds HS400 support to sdhci-msm.
>
>
> [1]:- http://www.spinics.net/lists/linux-mmc/msg38467.html
> [2]:- http://www.spinics.net/lists/linux-mmc/msg38578.html
> [3]:- https://patchwork.kernel.org/patch/9289345/
> [4]:- https://www.spinics.net/lists/linux-mmc/msg39107.html
> [5]:- http://www.spinics.net/lists/linux-mmc/msg38749.html
> [6]:- https://patchwork.kernel.org/patch/9297381/
>
>
> Rajendra Nayak (2):
> clk: qcom: Add rcg ops to return floor value closest to the requested
> rate
> clk: qcom: Move all sdcc rcgs to use clk_rcg2_floor_ops
>
> Ritesh Harjani (12):
> mmc: sdhci-msm: Change poor style writel/readl of registers
> ARM: dts: Add xo to sdhc clock node on qcom platforms
> dt-bindings: sdhci-msm: Add xo value
> mmc: sdhci-msm: Add get_min_clock() and get_max_clock() callback
> mmc: sdhci-msm: Enable few quirks
> mmc: sdhci: Factor out sdhci_enable_clk
> mmc: sdhci-msm: Implement set_clock callback for sdhci-msm
> mmc: sdhci-msm: Add clock changes for DDR mode.
> arm64: dts: qcom: msm8916: Add ddr support to sdhc1
> mmc: sdhci-msm: Save the calculated tuning phase
> mmc: sdhci-msm: Add calibration tuning for CDCLP533 circuit
> sdhci: sdhci-msm: update dll configuration
>
> Venkat Gopalakrishnan (2):
> mmc: sdhci-msm: Update DLL reset sequence
> mmc: sdhci-msm: Add HS400 platform support
>
> .../devicetree/bindings/mmc/sdhci-msm.txt | 1 +
> arch/arm/boot/dts/qcom-apq8084.dtsi | 16 +-
> arch/arm/boot/dts/qcom-msm8974.dtsi | 16 +-
> arch/arm64/boot/dts/qcom/msm8916.dtsi | 11 +-
> arch/arm64/boot/dts/qcom/msm8996.dtsi | 9 +-
> drivers/clk/qcom/clk-rcg.h | 1 +
> drivers/clk/qcom/clk-rcg2.c | 76 ++-
> drivers/clk/qcom/common.c | 16 +
> drivers/clk/qcom/common.h | 2 +
> drivers/clk/qcom/gcc-apq8084.c | 8 +-
> drivers/clk/qcom/gcc-msm8916.c | 4 +-
> drivers/clk/qcom/gcc-msm8974.c | 8 +-
> drivers/clk/qcom/gcc-msm8994.c | 8 +-
> drivers/clk/qcom/gcc-msm8996.c | 8 +-
> drivers/mmc/host/sdhci-msm.c | 626 +++++++++++++++++++--
> drivers/mmc/host/sdhci.c | 28 +-
> drivers/mmc/host/sdhci.h | 1 +
> 17 files changed, 739 insertions(+), 100 deletions(-)
>
> --
> The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project.
>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH v9 00/16] mmc: sdhci-msm: Add clk-rates, DDR, HS400 support
@ 2016-11-21 10:06 ` Ulf Hansson
0 siblings, 0 replies; 46+ messages in thread
From: Ulf Hansson @ 2016-11-21 10:06 UTC (permalink / raw)
To: Ritesh Harjani
Cc: linux-mmc, Adrian Hunter, Stephen Boyd, Andy Gross, Shawn Lin,
devicetree, linux-clk, David Brown, linux-arm-msm, Georgi Djakov,
Alex Lemberg, Mateusz Nowak, Yuliy Izrailov, Asutosh Das,
David Griego, Sahitya Tummala, Venkat Gopalakrishnan,
Rajendra Nayak, Pramod Gurav, jeremymc
On 21 November 2016 at 07:37, Ritesh Harjani <riteshh@codeaurora.org> wrote:
> Hi,
>
> This is v9 version of the patch series which adds support for MSM8996.
> Adds HS400 driver support as well.
> These are tested on internal msm8996 & db410c HW.
>
> The patch series is ready. Do we think we can apply these
> patches for next now?
I guess the DTS changes can be picked up by Andy, so they can go via arm-soc?
Then, does the mmc changes depend on the clock changes? If so, I can
pick them as well, but then I need an ack from Stephen....
Kind regards
Uffe
>
> There are only minor changes in v9.
> 1. From <&xo_board 0> -> <&xo_board>.
> 2. Addressed Adrian minor comments on 009.
> 3. Other minor changes.
>
>
> Older history:-
>
> Changes from v7 -> v8 :-
> 1. Added patch 005 to add dt bindings for xo_clock.
> 2. Added patch 009 to factor out sdhci_enable_clock as discussed on v7 series.
> 2.a. Modified patch 010 by making use of sdhci_enable_clock.
> 2.b. Addressed Stephen's comment on patch 010 to call clk_set_rate unconditionally.
> 3. Addressed Stephen comments to remove unncessary one line comments, braces and other
> minor comments.
> 4. Added changes from Jeremy in patch 002 for gcc-msm8994 as well for sdcc clk_rcg2_floor_ops.
> minor comments.
>
> v7 was verified on my Nexus 5X (msm8992).
>
> Older history :-
> Below are the changes in v7.
>
> Changes from v6 -> v7 :-
> 1. Removed patch "clk: Add clk_hw_get_clk() helper API to be used by clk providers"
> in v7 as it was not required.
> 2. Addressed Stephen review comments on -
> "clk: qcom: Add rcg ops to return floor value closest to the requested rate"
> 3. Addressed comments from Stephen to add xo_clock entry in the sdhc clock node.
> Using the same xo_clock entry from DT to get the clk_rate of xo_clock used in
> sdhci-msm driver. Patch 04 adds this entry into DT.
> Patch 05 adds the driver support for xo_clock mentioned above.
> Hence there is a minor change in Patch05, which can be reviewed and taken
> into the tree.
>
> IMHO, almost all patches are almost done and are ready to be accepted.
> Will below process work out?
> Patches 001 & 002 :- (clock changes) - Can go via Stephen's Boyd Tree.
> Patches 004 & 010 :- (DTS changes) - Can go via Andy Gross.
> Patches 003, 005-009 & 011-014 :- (sdhci-msm changes) - Adrian's tree.
>
> Please let me know in case if anything else is required on above.
>
>
> Changes from v5 -> v6 :-
> 1. Earlier in v5 series DT node was added to get the clk-rates table
> needed for sdhci-msm driver. But this is removed in this(v6) patch series
> and instead the clk changes are done in the clk driver as per Rob H comment.
>
> 2. Added clk driver changes(patch 1-3) to provide floor rate values of requested
> clock for sdhc client.
> For following boards- apq8084, msm8996, msm8916, msm8974.
>
> 3. Other minor patch comments were addressed.
>
> Changes from v4 -> v5 :-
> 1. Added HS400 sdhci-msm controller specific changes:- (Patch 10, 11, 12)
> 2. Addressed comment from Adrian on Patch 07 @[3].
> 3. Addressed comment from Arnd on Patch 03, to directly add
> clk_table into sdhci_msm_host. [4]
> 4. Addressed comment from Bjorn to not enforce having clk-rates property
> in DT for older targets based on discussion at [5]
> 5. Retained Acks from Adrian on patches (01 & 02 & 06) where there were no
> changes made while addressing above comments.
>
> Older history:-
> This is v4 version of the patch series.
> Patches 01, 02, 05 & 06 were Acked-by Adrian.
>
> Changes from v3 -> v4 :-
> 1. Addressed comments from Adrian on Patch 03, 07, 08.
> 2. Addressed comments from Bjorn on Patch 03.
> 3. Added clk-rate support for sdhc DT nodes to all MSM platforms.
> in Pacth 04.
> 4. Rebased on next branch of Ulf.
>
> Changes from v2 -> v3 :-
> 1. Addded Patch 01 based on Bjorn comment[2] -
> This fixes/unrolls the poor coding style of read/writes of
> registers from base sdhci-msm driver.
>
> 2. Fixed/unrolled poor style of reads/writes of registers in Patch 02,
> based on Bjorn comment[2]. Also changed name of flag from
> use_updated_dll_reset -> use_14lpp_dll_reset.
>
> Changes from v1->v2 :-
> 1. Removed patch 06 & 08 from v1 patch series[1]
> (which were introducing unnecessary quirks).
> Instead have implemented __sdhci_msm_set_clock version of
> sdhci_set_clock in sdhci_msm driver itself in patch 07 of
> this patch series.
> 2. Enabled extra quirk (SDHCI_QUIRK2_PRESET_VALUE_BROKEN) in
> patch 05 of this patch series.
>
>
> Description of patches :-
> This patchset adds clk-rates & other required changes to
> upstream sdhci-msm driver from codeaurora tree.
> It has been tested on a db410c Dragonboard and msm8996 based
> platform.
>
> Patch 0001-0003- Adds support in qcom clk driver to return
> floor value of requested clock rate instead of ceil rate
> for sdhc clients.
>
> Patch 0004- Adds updated dll sequence for newer controllers
> which has minor_version >= 0x42. This is required for msm8996.
>
> MSM controller HW recommendation is to use the base MCI clock
> and directly control this MCI clock at GCC in order to
> change the clk-rate.
> Patches 06-08 bring in required change for this to
> sdhci-msm.
>
> MSM controller would require 2x clock rate from source
> for DDR bus speed modes. Patch 09 adds this support.
>
> Patch 0010- adds DDR support in DT for sdhc1 of msm8916.
>
> Patches 0011-0014- Adds HS400 support to sdhci-msm.
>
>
> [1]:- http://www.spinics.net/lists/linux-mmc/msg38467.html
> [2]:- http://www.spinics.net/lists/linux-mmc/msg38578.html
> [3]:- https://patchwork.kernel.org/patch/9289345/
> [4]:- https://www.spinics.net/lists/linux-mmc/msg39107.html
> [5]:- http://www.spinics.net/lists/linux-mmc/msg38749.html
> [6]:- https://patchwork.kernel.org/patch/9297381/
>
>
> Rajendra Nayak (2):
> clk: qcom: Add rcg ops to return floor value closest to the requested
> rate
> clk: qcom: Move all sdcc rcgs to use clk_rcg2_floor_ops
>
> Ritesh Harjani (12):
> mmc: sdhci-msm: Change poor style writel/readl of registers
> ARM: dts: Add xo to sdhc clock node on qcom platforms
> dt-bindings: sdhci-msm: Add xo value
> mmc: sdhci-msm: Add get_min_clock() and get_max_clock() callback
> mmc: sdhci-msm: Enable few quirks
> mmc: sdhci: Factor out sdhci_enable_clk
> mmc: sdhci-msm: Implement set_clock callback for sdhci-msm
> mmc: sdhci-msm: Add clock changes for DDR mode.
> arm64: dts: qcom: msm8916: Add ddr support to sdhc1
> mmc: sdhci-msm: Save the calculated tuning phase
> mmc: sdhci-msm: Add calibration tuning for CDCLP533 circuit
> sdhci: sdhci-msm: update dll configuration
>
> Venkat Gopalakrishnan (2):
> mmc: sdhci-msm: Update DLL reset sequence
> mmc: sdhci-msm: Add HS400 platform support
>
> .../devicetree/bindings/mmc/sdhci-msm.txt | 1 +
> arch/arm/boot/dts/qcom-apq8084.dtsi | 16 +-
> arch/arm/boot/dts/qcom-msm8974.dtsi | 16 +-
> arch/arm64/boot/dts/qcom/msm8916.dtsi | 11 +-
> arch/arm64/boot/dts/qcom/msm8996.dtsi | 9 +-
> drivers/clk/qcom/clk-rcg.h | 1 +
> drivers/clk/qcom/clk-rcg2.c | 76 ++-
> drivers/clk/qcom/common.c | 16 +
> drivers/clk/qcom/common.h | 2 +
> drivers/clk/qcom/gcc-apq8084.c | 8 +-
> drivers/clk/qcom/gcc-msm8916.c | 4 +-
> drivers/clk/qcom/gcc-msm8974.c | 8 +-
> drivers/clk/qcom/gcc-msm8994.c | 8 +-
> drivers/clk/qcom/gcc-msm8996.c | 8 +-
> drivers/mmc/host/sdhci-msm.c | 626 +++++++++++++++++++--
> drivers/mmc/host/sdhci.c | 28 +-
> drivers/mmc/host/sdhci.h | 1 +
> 17 files changed, 739 insertions(+), 100 deletions(-)
>
> --
> The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project.
>
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH v9 00/16] mmc: sdhci-msm: Add clk-rates, DDR, HS400 support
2016-11-21 10:06 ` Ulf Hansson
(?)
@ 2016-11-21 11:42 ` Ritesh Harjani
[not found] ` <d4d05fb9-8a9e-6cf2-dc63-0edbd27a9e55-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
-1 siblings, 1 reply; 46+ messages in thread
From: Ritesh Harjani @ 2016-11-21 11:42 UTC (permalink / raw)
To: Ulf Hansson, Stephen Boyd, Andy Gross
Cc: linux-mmc, Adrian Hunter, Shawn Lin, devicetree, linux-clk,
David Brown, linux-arm-msm, Georgi Djakov, Alex Lemberg,
Mateusz Nowak, Yuliy Izrailov, Asutosh Das, David Griego,
Sahitya Tummala, Venkat Gopalakrishnan, Rajendra Nayak,
Pramod Gurav, jeremymc
On 11/21/2016 3:36 PM, Ulf Hansson wrote:
> On 21 November 2016 at 07:37, Ritesh Harjani <riteshh@codeaurora.org> wrote:
>> Hi,
>>
>> This is v9 version of the patch series which adds support for MSM8996.
>> Adds HS400 driver support as well.
>> These are tested on internal msm8996 & db410c HW.
>>
>> The patch series is ready. Do we think we can apply these
>> patches for next now?
>
> I guess the DTS changes can be picked up by Andy, so they can go via arm-soc?
Yes.
>
> Then, does the mmc changes depend on the clock changes? If so, I can
> pick them as well, but then I need an ack from Stephen....
Ideal and preferable, would be that clk & mmc changes go in together.
But either ways should be fine.
>
> Kind regards
> Uffe
>
>>
>> There are only minor changes in v9.
>> 1. From <&xo_board 0> -> <&xo_board>.
>> 2. Addressed Adrian minor comments on 009.
>> 3. Other minor changes.
>>
>>
>> Older history:-
>>
>> Changes from v7 -> v8 :-
>> 1. Added patch 005 to add dt bindings for xo_clock.
>> 2. Added patch 009 to factor out sdhci_enable_clock as discussed on v7 series.
>> 2.a. Modified patch 010 by making use of sdhci_enable_clock.
>> 2.b. Addressed Stephen's comment on patch 010 to call clk_set_rate unconditionally.
>> 3. Addressed Stephen comments to remove unncessary one line comments, braces and other
>> minor comments.
>> 4. Added changes from Jeremy in patch 002 for gcc-msm8994 as well for sdcc clk_rcg2_floor_ops.
>> minor comments.
>>
>> v7 was verified on my Nexus 5X (msm8992).
>>
>> Older history :-
>> Below are the changes in v7.
>>
>> Changes from v6 -> v7 :-
>> 1. Removed patch "clk: Add clk_hw_get_clk() helper API to be used by clk providers"
>> in v7 as it was not required.
>> 2. Addressed Stephen review comments on -
>> "clk: qcom: Add rcg ops to return floor value closest to the requested rate"
>> 3. Addressed comments from Stephen to add xo_clock entry in the sdhc clock node.
>> Using the same xo_clock entry from DT to get the clk_rate of xo_clock used in
>> sdhci-msm driver. Patch 04 adds this entry into DT.
>> Patch 05 adds the driver support for xo_clock mentioned above.
>> Hence there is a minor change in Patch05, which can be reviewed and taken
>> into the tree.
>>
>> IMHO, almost all patches are almost done and are ready to be accepted.
>> Will below process work out?
>> Patches 001 & 002 :- (clock changes) - Can go via Stephen's Boyd Tree.
>> Patches 004 & 010 :- (DTS changes) - Can go via Andy Gross.
>> Patches 003, 005-009 & 011-014 :- (sdhci-msm changes) - Adrian's tree.
>>
>> Please let me know in case if anything else is required on above.
>>
>>
>> Changes from v5 -> v6 :-
>> 1. Earlier in v5 series DT node was added to get the clk-rates table
>> needed for sdhci-msm driver. But this is removed in this(v6) patch series
>> and instead the clk changes are done in the clk driver as per Rob H comment.
>>
>> 2. Added clk driver changes(patch 1-3) to provide floor rate values of requested
>> clock for sdhc client.
>> For following boards- apq8084, msm8996, msm8916, msm8974.
>>
>> 3. Other minor patch comments were addressed.
>>
>> Changes from v4 -> v5 :-
>> 1. Added HS400 sdhci-msm controller specific changes:- (Patch 10, 11, 12)
>> 2. Addressed comment from Adrian on Patch 07 @[3].
>> 3. Addressed comment from Arnd on Patch 03, to directly add
>> clk_table into sdhci_msm_host. [4]
>> 4. Addressed comment from Bjorn to not enforce having clk-rates property
>> in DT for older targets based on discussion at [5]
>> 5. Retained Acks from Adrian on patches (01 & 02 & 06) where there were no
>> changes made while addressing above comments.
>>
>> Older history:-
>> This is v4 version of the patch series.
>> Patches 01, 02, 05 & 06 were Acked-by Adrian.
>>
>> Changes from v3 -> v4 :-
>> 1. Addressed comments from Adrian on Patch 03, 07, 08.
>> 2. Addressed comments from Bjorn on Patch 03.
>> 3. Added clk-rate support for sdhc DT nodes to all MSM platforms.
>> in Pacth 04.
>> 4. Rebased on next branch of Ulf.
>>
>> Changes from v2 -> v3 :-
>> 1. Addded Patch 01 based on Bjorn comment[2] -
>> This fixes/unrolls the poor coding style of read/writes of
>> registers from base sdhci-msm driver.
>>
>> 2. Fixed/unrolled poor style of reads/writes of registers in Patch 02,
>> based on Bjorn comment[2]. Also changed name of flag from
>> use_updated_dll_reset -> use_14lpp_dll_reset.
>>
>> Changes from v1->v2 :-
>> 1. Removed patch 06 & 08 from v1 patch series[1]
>> (which were introducing unnecessary quirks).
>> Instead have implemented __sdhci_msm_set_clock version of
>> sdhci_set_clock in sdhci_msm driver itself in patch 07 of
>> this patch series.
>> 2. Enabled extra quirk (SDHCI_QUIRK2_PRESET_VALUE_BROKEN) in
>> patch 05 of this patch series.
>>
>>
>> Description of patches :-
>> This patchset adds clk-rates & other required changes to
>> upstream sdhci-msm driver from codeaurora tree.
>> It has been tested on a db410c Dragonboard and msm8996 based
>> platform.
>>
>> Patch 0001-0003- Adds support in qcom clk driver to return
>> floor value of requested clock rate instead of ceil rate
>> for sdhc clients.
>>
>> Patch 0004- Adds updated dll sequence for newer controllers
>> which has minor_version >= 0x42. This is required for msm8996.
>>
>> MSM controller HW recommendation is to use the base MCI clock
>> and directly control this MCI clock at GCC in order to
>> change the clk-rate.
>> Patches 06-08 bring in required change for this to
>> sdhci-msm.
>>
>> MSM controller would require 2x clock rate from source
>> for DDR bus speed modes. Patch 09 adds this support.
>>
>> Patch 0010- adds DDR support in DT for sdhc1 of msm8916.
>>
>> Patches 0011-0014- Adds HS400 support to sdhci-msm.
>>
>>
>> [1]:- http://www.spinics.net/lists/linux-mmc/msg38467.html
>> [2]:- http://www.spinics.net/lists/linux-mmc/msg38578.html
>> [3]:- https://patchwork.kernel.org/patch/9289345/
>> [4]:- https://www.spinics.net/lists/linux-mmc/msg39107.html
>> [5]:- http://www.spinics.net/lists/linux-mmc/msg38749.html
>> [6]:- https://patchwork.kernel.org/patch/9297381/
>>
>>
>> Rajendra Nayak (2):
>> clk: qcom: Add rcg ops to return floor value closest to the requested
>> rate
>> clk: qcom: Move all sdcc rcgs to use clk_rcg2_floor_ops
>>
>> Ritesh Harjani (12):
>> mmc: sdhci-msm: Change poor style writel/readl of registers
>> ARM: dts: Add xo to sdhc clock node on qcom platforms
>> dt-bindings: sdhci-msm: Add xo value
>> mmc: sdhci-msm: Add get_min_clock() and get_max_clock() callback
>> mmc: sdhci-msm: Enable few quirks
>> mmc: sdhci: Factor out sdhci_enable_clk
>> mmc: sdhci-msm: Implement set_clock callback for sdhci-msm
>> mmc: sdhci-msm: Add clock changes for DDR mode.
>> arm64: dts: qcom: msm8916: Add ddr support to sdhc1
>> mmc: sdhci-msm: Save the calculated tuning phase
>> mmc: sdhci-msm: Add calibration tuning for CDCLP533 circuit
>> sdhci: sdhci-msm: update dll configuration
>>
>> Venkat Gopalakrishnan (2):
>> mmc: sdhci-msm: Update DLL reset sequence
>> mmc: sdhci-msm: Add HS400 platform support
>>
>> .../devicetree/bindings/mmc/sdhci-msm.txt | 1 +
>> arch/arm/boot/dts/qcom-apq8084.dtsi | 16 +-
>> arch/arm/boot/dts/qcom-msm8974.dtsi | 16 +-
>> arch/arm64/boot/dts/qcom/msm8916.dtsi | 11 +-
>> arch/arm64/boot/dts/qcom/msm8996.dtsi | 9 +-
>> drivers/clk/qcom/clk-rcg.h | 1 +
>> drivers/clk/qcom/clk-rcg2.c | 76 ++-
>> drivers/clk/qcom/common.c | 16 +
>> drivers/clk/qcom/common.h | 2 +
>> drivers/clk/qcom/gcc-apq8084.c | 8 +-
>> drivers/clk/qcom/gcc-msm8916.c | 4 +-
>> drivers/clk/qcom/gcc-msm8974.c | 8 +-
>> drivers/clk/qcom/gcc-msm8994.c | 8 +-
>> drivers/clk/qcom/gcc-msm8996.c | 8 +-
>> drivers/mmc/host/sdhci-msm.c | 626 +++++++++++++++++++--
>> drivers/mmc/host/sdhci.c | 28 +-
>> drivers/mmc/host/sdhci.h | 1 +
>> 17 files changed, 739 insertions(+), 100 deletions(-)
>>
>> --
>> The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
>> a Linux Foundation Collaborative Project.
>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [PATCH v9 00/16] mmc: sdhci-msm: Add clk-rates, DDR, HS400 support
2016-11-21 10:06 ` Ulf Hansson
@ 2016-11-23 5:00 ` Andy Gross
-1 siblings, 0 replies; 46+ messages in thread
From: Andy Gross @ 2016-11-23 5:00 UTC (permalink / raw)
To: Ulf Hansson
Cc: Ritesh Harjani, linux-mmc, Adrian Hunter, Stephen Boyd,
Shawn Lin, devicetree, linux-clk, David Brown, linux-arm-msm,
Georgi Djakov, Alex Lemberg, Mateusz Nowak, Yuliy Izrailov,
Asutosh Das, David Griego, Sahitya Tummala,
Venkat Gopalakrishnan, Rajendra Nayak
On Mon, Nov 21, 2016 at 11:06:13AM +0100, Ulf Hansson wrote:
> On 21 November 2016 at 07:37, Ritesh Harjani <riteshh@codeaurora.org> wrote:
> > Hi,
> >
> > This is v9 version of the patch series which adds support for MSM8996.
> > Adds HS400 driver support as well.
> > These are tested on internal msm8996 & db410c HW.
> >
> > The patch series is ready. Do we think we can apply these
> > patches for next now?
>
> I guess the DTS changes can be picked up by Andy, so they can go via arm-soc?
Yeah I'll pick up the DTS change and the Documentation change.
>
> Then, does the mmc changes depend on the clock changes? If so, I can
> pick them as well, but then I need an ack from Stephen....
>
> Kind regards
> Uffe
Andy
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH v9 00/16] mmc: sdhci-msm: Add clk-rates, DDR, HS400 support
@ 2016-11-23 5:00 ` Andy Gross
0 siblings, 0 replies; 46+ messages in thread
From: Andy Gross @ 2016-11-23 5:00 UTC (permalink / raw)
To: Ulf Hansson
Cc: Ritesh Harjani, linux-mmc, Adrian Hunter, Stephen Boyd,
Shawn Lin, devicetree, linux-clk, David Brown, linux-arm-msm,
Georgi Djakov, Alex Lemberg, Mateusz Nowak, Yuliy Izrailov,
Asutosh Das, David Griego, Sahitya Tummala,
Venkat Gopalakrishnan, Rajendra Nayak, Pramod Gurav, jeremymc
On Mon, Nov 21, 2016 at 11:06:13AM +0100, Ulf Hansson wrote:
> On 21 November 2016 at 07:37, Ritesh Harjani <riteshh@codeaurora.org> wrote:
> > Hi,
> >
> > This is v9 version of the patch series which adds support for MSM8996.
> > Adds HS400 driver support as well.
> > These are tested on internal msm8996 & db410c HW.
> >
> > The patch series is ready. Do we think we can apply these
> > patches for next now?
>
> I guess the DTS changes can be picked up by Andy, so they can go via arm-soc?
Yeah I'll pick up the DTS change and the Documentation change.
>
> Then, does the mmc changes depend on the clock changes? If so, I can
> pick them as well, but then I need an ack from Stephen....
>
> Kind regards
> Uffe
Andy
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH v9 00/16] mmc: sdhci-msm: Add clk-rates, DDR, HS400 support
2016-11-23 5:00 ` Andy Gross
@ 2016-11-23 8:32 ` Ulf Hansson
-1 siblings, 0 replies; 46+ messages in thread
From: Ulf Hansson @ 2016-11-23 8:32 UTC (permalink / raw)
To: Andy Gross
Cc: Ritesh Harjani, linux-mmc, Adrian Hunter, Stephen Boyd,
Shawn Lin, devicetree, linux-clk, David Brown, linux-arm-msm,
Georgi Djakov, Alex Lemberg, Mateusz Nowak, Yuliy Izrailov,
Asutosh Das, David Griego, Sahitya Tummala,
Venkat Gopalakrishnan, Rajendra Nayak
On 23 November 2016 at 06:00, Andy Gross <andy.gross@linaro.org> wrote:
> On Mon, Nov 21, 2016 at 11:06:13AM +0100, Ulf Hansson wrote:
>> On 21 November 2016 at 07:37, Ritesh Harjani <riteshh@codeaurora.org> wrote:
>> > Hi,
>> >
>> > This is v9 version of the patch series which adds support for MSM8996.
>> > Adds HS400 driver support as well.
>> > These are tested on internal msm8996 & db410c HW.
>> >
>> > The patch series is ready. Do we think we can apply these
>> > patches for next now?
>>
>> I guess the DTS changes can be picked up by Andy, so they can go via arm-soc?
>
> Yeah I'll pick up the DTS change and the Documentation change.
Andy, I would rather like to pick the DT Documentation change via my
mmc tree. Just because I normally do that.
This one:
[PATCH v9 05/16] dt-bindings: sdhci-msm: Add xo value
Kind regards
Uffe
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH v9 00/16] mmc: sdhci-msm: Add clk-rates, DDR, HS400 support
@ 2016-11-23 8:32 ` Ulf Hansson
0 siblings, 0 replies; 46+ messages in thread
From: Ulf Hansson @ 2016-11-23 8:32 UTC (permalink / raw)
To: Andy Gross
Cc: Ritesh Harjani, linux-mmc, Adrian Hunter, Stephen Boyd,
Shawn Lin, devicetree, linux-clk, David Brown, linux-arm-msm,
Georgi Djakov, Alex Lemberg, Mateusz Nowak, Yuliy Izrailov,
Asutosh Das, David Griego, Sahitya Tummala,
Venkat Gopalakrishnan, Rajendra Nayak, Pramod Gurav, jeremymc
On 23 November 2016 at 06:00, Andy Gross <andy.gross@linaro.org> wrote:
> On Mon, Nov 21, 2016 at 11:06:13AM +0100, Ulf Hansson wrote:
>> On 21 November 2016 at 07:37, Ritesh Harjani <riteshh@codeaurora.org> wrote:
>> > Hi,
>> >
>> > This is v9 version of the patch series which adds support for MSM8996.
>> > Adds HS400 driver support as well.
>> > These are tested on internal msm8996 & db410c HW.
>> >
>> > The patch series is ready. Do we think we can apply these
>> > patches for next now?
>>
>> I guess the DTS changes can be picked up by Andy, so they can go via arm-soc?
>
> Yeah I'll pick up the DTS change and the Documentation change.
Andy, I would rather like to pick the DT Documentation change via my
mmc tree. Just because I normally do that.
This one:
[PATCH v9 05/16] dt-bindings: sdhci-msm: Add xo value
Kind regards
Uffe
^ permalink raw reply [flat|nested] 46+ messages in thread