* [U-Boot] [PATCH v2 0/3] ARM: DRA7: Add Kconfig support for selecting OPPs
@ 2016-11-23 7:24 Lokesh Vutla
2016-11-23 7:24 ` [U-Boot] [PATCH v2 1/3] ARM: OMAP4+: Add support for dynamically " Lokesh Vutla
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Lokesh Vutla @ 2016-11-23 7:24 UTC (permalink / raw)
To: u-boot
This series adds support for selecting DSPEVE, IVA, GPU OPPs via Kconfig
and fixup DT clock nodes as required.
Changes since v1:
- Added help option for Kconfig entries.
Lokesh Vutla (1):
ARM: OMAP4+: Add support for dynamically selecting OPPs
Suman Anna (2):
ARM: DRA7: Redefine voltage and efuse macros per OPP using Kconfig
ARM: DRA7: Fixup DSPEVE, IVA and GPU clock frequencies based on OPP
arch/arm/include/asm/arch-omap5/clock.h | 47 ++++++++---
arch/arm/include/asm/omap_common.h | 23 +++++-
arch/arm/mach-omap2/clocks-common.c | 116 ++++++++++++++++-----------
arch/arm/mach-omap2/omap4/hw_data.c | 24 +++---
arch/arm/mach-omap2/omap5/Kconfig | 93 ++++++++++++++++++++++
arch/arm/mach-omap2/omap5/fdt.c | 136 ++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/omap5/hw_data.c | 12 +--
board/ti/am57xx/board.c | 92 ++++++++++++++++-----
board/ti/dra7xx/evm.c | 91 ++++++++++++++++-----
9 files changed, 517 insertions(+), 117 deletions(-)
--
2.10.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2 1/3] ARM: OMAP4+: Add support for dynamically selecting OPPs
2016-11-23 7:24 [U-Boot] [PATCH v2 0/3] ARM: DRA7: Add Kconfig support for selecting OPPs Lokesh Vutla
@ 2016-11-23 7:24 ` Lokesh Vutla
2016-11-23 18:05 ` Tom Rini
2016-12-04 23:17 ` [U-Boot] [U-Boot, v2, " Tom Rini
2016-11-23 7:24 ` [U-Boot] [PATCH v2 2/3] ARM: DRA7: Redefine voltage and efuse macros per OPP using Kconfig Lokesh Vutla
2016-11-23 7:24 ` [U-Boot] [PATCH v2 3/3] ARM: DRA7: Fixup DSPEVE, IVA and GPU clock frequencies based on OPP Lokesh Vutla
2 siblings, 2 replies; 10+ messages in thread
From: Lokesh Vutla @ 2016-11-23 7:24 UTC (permalink / raw)
To: u-boot
It can be expected that different paper spins of a SoC can have
different definitions for OPP and can have their own constraints
on the boot up OPP for each voltage rail. In order to have this
flexibility, add support for dynamically selecting the OPP voltage
based on the board to handle any such exceptions.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
arch/arm/include/asm/omap_common.h | 23 ++++++-
arch/arm/mach-omap2/clocks-common.c | 116 ++++++++++++++++++++++--------------
arch/arm/mach-omap2/omap4/hw_data.c | 24 ++++----
arch/arm/mach-omap2/omap5/hw_data.c | 12 ++--
board/ti/am57xx/board.c | 92 +++++++++++++++++++++-------
board/ti/dra7xx/evm.c | 91 +++++++++++++++++++++-------
6 files changed, 254 insertions(+), 104 deletions(-)
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 605c549..00bd9fc 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -539,18 +539,26 @@ struct pmic_data {
int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data);
};
+enum {
+ OPP_LOW,
+ OPP_NOM,
+ OPP_OD,
+ OPP_HIGH,
+ NUM_OPPS,
+};
+
/**
* struct volts_efuse_data - efuse definition for voltage
* @reg: register address for efuse
* @reg_bits: Number of bits in a register address, mandatory.
*/
struct volts_efuse_data {
- u32 reg;
+ u32 reg[NUM_OPPS];
u8 reg_bits;
};
struct volts {
- u32 value;
+ u32 value[NUM_OPPS];
u32 addr;
struct volts_efuse_data efuse;
struct pmic_data *pmic;
@@ -558,6 +566,16 @@ struct volts {
u32 abb_tx_done_mask;
};
+enum {
+ VOLT_MPU,
+ VOLT_CORE,
+ VOLT_MM,
+ VOLT_GPU,
+ VOLT_EVE,
+ VOLT_IVA,
+ NUM_VOLT_RAILS,
+};
+
struct vcores_data {
struct volts mpu;
struct volts core;
@@ -612,6 +630,7 @@ void enable_usb_clocks(int index);
void disable_usb_clocks(int index);
void scale_vcores(struct vcores_data const *);
+int get_voltrail_opp(int rail_offset);
u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
diff --git a/arch/arm/mach-omap2/clocks-common.c b/arch/arm/mach-omap2/clocks-common.c
index 9b97583..84f93e7 100644
--- a/arch/arm/mach-omap2/clocks-common.c
+++ b/arch/arm/mach-omap2/clocks-common.c
@@ -477,35 +477,45 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
gpio_direction_output(pmic->gpio, 1);
}
-static u32 optimize_vcore_voltage(struct volts const *v)
+int __weak get_voltrail_opp(int rail_offset)
+{
+ /*
+ * By default return OPP_NOM for all voltage rails.
+ */
+ return OPP_NOM;
+}
+
+static u32 optimize_vcore_voltage(struct volts const *v, int opp)
{
u32 val;
- if (!v->value)
+
+ if (!v->value[opp])
return 0;
- if (!v->efuse.reg)
- return v->value;
+ if (!v->efuse.reg[opp])
+ return v->value[opp];
switch (v->efuse.reg_bits) {
case 16:
- val = readw(v->efuse.reg);
+ val = readw(v->efuse.reg[opp]);
break;
case 32:
- val = readl(v->efuse.reg);
+ val = readl(v->efuse.reg[opp]);
break;
default:
printf("Error: efuse 0x%08x bits=%d unknown\n",
- v->efuse.reg, v->efuse.reg_bits);
- return v->value;
+ v->efuse.reg[opp], v->efuse.reg_bits);
+ return v->value[opp];
}
if (!val) {
printf("Error: efuse 0x%08x bits=%d val=0, using %d\n",
- v->efuse.reg, v->efuse.reg_bits, v->value);
- return v->value;
+ v->efuse.reg[opp], v->efuse.reg_bits, v->value[opp]);
+ return v->value[opp];
}
debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n",
- __func__, v->efuse.reg, v->efuse.reg_bits, v->value, val);
+ __func__, v->efuse.reg[opp], v->efuse.reg_bits, v->value[opp],
+ val);
return val;
}
@@ -529,16 +539,19 @@ void __weak recalibrate_iodelay(void)
*/
void scale_vcores(struct vcores_data const *vcores)
{
- int i;
+ int i, opp, j, ol;
struct volts *pv = (struct volts *)vcores;
struct volts *px;
for (i=0; i<(sizeof(struct vcores_data)/sizeof(struct volts)); i++) {
- debug("%d -> ", pv->value);
- if (pv->value) {
+ opp = get_voltrail_opp(i);
+ debug("%d -> ", pv->value[opp]);
+
+ if (pv->value[opp]) {
/* Handle non-empty members only */
- pv->value = optimize_vcore_voltage(pv);
+ pv->value[opp] = optimize_vcore_voltage(pv, opp);
px = (struct volts *)vcores;
+ j = 0;
while (px < pv) {
/*
* Scan already handled non-empty members to see
@@ -547,26 +560,29 @@ void scale_vcores(struct vcores_data const *vcores)
* particular SMPS; the other group voltages are
* zeroed.
*/
- if (px->value) {
- if ((pv->pmic->i2c_slave_addr ==
- px->pmic->i2c_slave_addr) &&
- (pv->addr == px->addr)) {
- /* Same PMIC, same SMPS */
- if (pv->value > px->value)
- px->value = pv->value;
-
- pv->value = 0;
- }
- }
+ ol = get_voltrail_opp(j);
+ if (px->value[ol] &&
+ (pv->pmic->i2c_slave_addr ==
+ px->pmic->i2c_slave_addr) &&
+ (pv->addr == px->addr)) {
+ /* Same PMIC, same SMPS */
+ if (pv->value[opp] > px->value[ol])
+ px->value[ol] = pv->value[opp];
+
+ pv->value[opp] = 0;
+ }
px++;
+ j++;
}
}
- debug("%d\n", pv->value);
+ debug("%d\n", pv->value[opp]);
pv++;
}
- debug("cor: %d\n", vcores->core.value);
- do_scale_vcore(vcores->core.addr, vcores->core.value, vcores->core.pmic);
+ opp = get_voltrail_opp(VOLT_CORE);
+ debug("cor: %d\n", vcores->core.value[opp]);
+ do_scale_vcore(vcores->core.addr, vcores->core.value[opp],
+ vcores->core.pmic);
/*
* IO delay recalibration should be done immediately after
* adjusting AVS voltages for VDD_CORE_L.
@@ -577,10 +593,12 @@ void scale_vcores(struct vcores_data const *vcores)
recalibrate_iodelay();
#endif
- debug("mpu: %d\n", vcores->mpu.value);
- do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, vcores->mpu.pmic);
+ opp = get_voltrail_opp(VOLT_MPU);
+ debug("mpu: %d\n", vcores->mpu.value[opp]);
+ do_scale_vcore(vcores->mpu.addr, vcores->mpu.value[opp],
+ vcores->mpu.pmic);
/* Configure MPU ABB LDO after scale */
- abb_setup(vcores->mpu.efuse.reg,
+ abb_setup(vcores->mpu.efuse.reg[opp],
(*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
(*prcm)->prm_abbldo_mpu_setup,
(*prcm)->prm_abbldo_mpu_ctrl,
@@ -588,10 +606,12 @@ void scale_vcores(struct vcores_data const *vcores)
vcores->mpu.abb_tx_done_mask,
OMAP_ABB_FAST_OPP);
- debug("mm: %d\n", vcores->mm.value);
- do_scale_vcore(vcores->mm.addr, vcores->mm.value, vcores->mm.pmic);
+ opp = get_voltrail_opp(VOLT_MM);
+ debug("mm: %d\n", vcores->mm.value[opp]);
+ do_scale_vcore(vcores->mm.addr, vcores->mm.value[opp],
+ vcores->mm.pmic);
/* Configure MM ABB LDO after scale */
- abb_setup(vcores->mm.efuse.reg,
+ abb_setup(vcores->mm.efuse.reg[opp],
(*ctrl)->control_wkup_ldovbb_mm_voltage_ctrl,
(*prcm)->prm_abbldo_mm_setup,
(*prcm)->prm_abbldo_mm_ctrl,
@@ -599,30 +619,38 @@ void scale_vcores(struct vcores_data const *vcores)
vcores->mm.abb_tx_done_mask,
OMAP_ABB_FAST_OPP);
- debug("gpu: %d\n", vcores->gpu.value);
- do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, vcores->gpu.pmic);
+ opp = get_voltrail_opp(VOLT_GPU);
+ debug("gpu: %d\n", vcores->gpu.value[opp]);
+ do_scale_vcore(vcores->gpu.addr, vcores->gpu.value[opp],
+ vcores->gpu.pmic);
/* Configure GPU ABB LDO after scale */
- abb_setup(vcores->gpu.efuse.reg,
+ abb_setup(vcores->gpu.efuse.reg[opp],
(*ctrl)->control_wkup_ldovbb_gpu_voltage_ctrl,
(*prcm)->prm_abbldo_gpu_setup,
(*prcm)->prm_abbldo_gpu_ctrl,
(*prcm)->prm_irqstatus_mpu,
vcores->gpu.abb_tx_done_mask,
OMAP_ABB_FAST_OPP);
- debug("eve: %d\n", vcores->eve.value);
- do_scale_vcore(vcores->eve.addr, vcores->eve.value, vcores->eve.pmic);
+
+ opp = get_voltrail_opp(VOLT_EVE);
+ debug("eve: %d\n", vcores->eve.value[opp]);
+ do_scale_vcore(vcores->eve.addr, vcores->eve.value[opp],
+ vcores->eve.pmic);
/* Configure EVE ABB LDO after scale */
- abb_setup(vcores->eve.efuse.reg,
+ abb_setup(vcores->eve.efuse.reg[opp],
(*ctrl)->control_wkup_ldovbb_eve_voltage_ctrl,
(*prcm)->prm_abbldo_eve_setup,
(*prcm)->prm_abbldo_eve_ctrl,
(*prcm)->prm_irqstatus_mpu,
vcores->eve.abb_tx_done_mask,
OMAP_ABB_FAST_OPP);
- debug("iva: %d\n", vcores->iva.value);
- do_scale_vcore(vcores->iva.addr, vcores->iva.value, vcores->iva.pmic);
+
+ opp = get_voltrail_opp(VOLT_IVA);
+ debug("iva: %d\n", vcores->iva.value[opp]);
+ do_scale_vcore(vcores->iva.addr, vcores->iva.value[opp],
+ vcores->iva.pmic);
/* Configure IVA ABB LDO after scale */
- abb_setup(vcores->iva.efuse.reg,
+ abb_setup(vcores->iva.efuse.reg[opp],
(*ctrl)->control_wkup_ldovbb_iva_voltage_ctrl,
(*prcm)->prm_abbldo_iva_setup,
(*prcm)->prm_abbldo_iva_ctrl,
diff --git a/arch/arm/mach-omap2/omap4/hw_data.c b/arch/arm/mach-omap2/omap4/hw_data.c
index 02c06c1..6a4b8b9 100644
--- a/arch/arm/mach-omap2/omap4/hw_data.c
+++ b/arch/arm/mach-omap2/omap4/hw_data.c
@@ -261,43 +261,43 @@ struct pmic_data tps62361 = {
};
struct vcores_data omap4430_volts_es1 = {
- .mpu.value = 1325,
+ .mpu.value[OPP_NOM] = 1325,
.mpu.addr = SMPS_REG_ADDR_VCORE1,
.mpu.pmic = &twl6030_4430es1,
- .core.value = 1200,
+ .core.value[OPP_NOM] = 1200,
.core.addr = SMPS_REG_ADDR_VCORE3,
.core.pmic = &twl6030_4430es1,
- .mm.value = 1200,
+ .mm.value[OPP_NOM] = 1200,
.mm.addr = SMPS_REG_ADDR_VCORE2,
.mm.pmic = &twl6030_4430es1,
};
struct vcores_data omap4430_volts = {
- .mpu.value = 1325,
+ .mpu.value[OPP_NOM] = 1325,
.mpu.addr = SMPS_REG_ADDR_VCORE1,
.mpu.pmic = &twl6030,
- .core.value = 1200,
+ .core.value[OPP_NOM] = 1200,
.core.addr = SMPS_REG_ADDR_VCORE3,
.core.pmic = &twl6030,
- .mm.value = 1200,
+ .mm.value[OPP_NOM] = 1200,
.mm.addr = SMPS_REG_ADDR_VCORE2,
.mm.pmic = &twl6030,
};
struct vcores_data omap4460_volts = {
- .mpu.value = 1203,
+ .mpu.value[OPP_NOM] = 1203,
.mpu.addr = TPS62361_REG_ADDR_SET1,
.mpu.pmic = &tps62361,
- .core.value = 1200,
+ .core.value[OPP_NOM] = 1200,
.core.addr = SMPS_REG_ADDR_VCORE1,
.core.pmic = &twl6030,
- .mm.value = 1200,
+ .mm.value[OPP_NOM] = 1200,
.mm.addr = SMPS_REG_ADDR_VCORE2,
.mm.pmic = &twl6030,
};
@@ -307,15 +307,15 @@ struct vcores_data omap4460_volts = {
* voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7.
*/
struct vcores_data omap4470_volts = {
- .mpu.value = 1202,
+ .mpu.value[OPP_NOM] = 1202,
.mpu.addr = SMPS_REG_ADDR_SMPS1,
.mpu.pmic = &twl6030,
- .core.value = 1126,
+ .core.value[OPP_NOM] = 1126,
.core.addr = SMPS_REG_ADDR_SMPS2,
.core.pmic = &twl6030,
- .mm.value = 1139,
+ .mm.value[OPP_NOM] = 1139,
.mm.addr = SMPS_REG_ADDR_SMPS5,
.mm.pmic = &twl6030,
};
diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c
index fc99135..0674480 100644
--- a/arch/arm/mach-omap2/omap5/hw_data.c
+++ b/arch/arm/mach-omap2/omap5/hw_data.c
@@ -337,30 +337,30 @@ struct pmic_data tps659038 = {
};
struct vcores_data omap5430_volts = {
- .mpu.value = VDD_MPU,
+ .mpu.value[OPP_NOM] = VDD_MPU,
.mpu.addr = SMPS_REG_ADDR_12_MPU,
.mpu.pmic = &palmas,
- .core.value = VDD_CORE,
+ .core.value[OPP_NOM] = VDD_CORE,
.core.addr = SMPS_REG_ADDR_8_CORE,
.core.pmic = &palmas,
- .mm.value = VDD_MM,
+ .mm.value[OPP_NOM] = VDD_MM,
.mm.addr = SMPS_REG_ADDR_45_IVA,
.mm.pmic = &palmas,
};
struct vcores_data omap5430_volts_es2 = {
- .mpu.value = VDD_MPU_ES2,
+ .mpu.value[OPP_NOM] = VDD_MPU_ES2,
.mpu.addr = SMPS_REG_ADDR_12_MPU,
.mpu.pmic = &palmas,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
- .core.value = VDD_CORE_ES2,
+ .core.value[OPP_NOM] = VDD_CORE_ES2,
.core.addr = SMPS_REG_ADDR_8_CORE,
.core.pmic = &palmas,
- .mm.value = VDD_MM_ES2,
+ .mm.value[OPP_NOM] = VDD_MM_ES2,
.mm.addr = SMPS_REG_ADDR_45_IVA,
.mm.pmic = &palmas,
.mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK,
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index f3e3f0b..7aee28e 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -217,35 +217,47 @@ void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
}
struct vcores_data beagle_x15_volts = {
- .mpu.value = VDD_MPU_DRA7,
- .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
+ .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
+ .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
- .eve.value = VDD_EVE_DRA7,
- .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
+ .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
+ .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
+ .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
+ .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
+ .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
- .gpu.value = VDD_GPU_DRA7,
- .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
+ .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
+ .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
+ .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
+ .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
+ .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS45,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
- .core.value = VDD_CORE_DRA7,
- .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
+ .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
+ .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS659038_REG_ADDR_SMPS6,
.core.pmic = &tps659038,
- .iva.value = VDD_IVA_DRA7,
- .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
+ .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
+ .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
+ .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
+ .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
+ .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS659038_REG_ADDR_SMPS45,
.iva.pmic = &tps659038,
@@ -253,41 +265,81 @@ struct vcores_data beagle_x15_volts = {
};
struct vcores_data am572x_idk_volts = {
- .mpu.value = VDD_MPU_DRA7,
- .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
+ .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
+ .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
- .eve.value = VDD_EVE_DRA7,
- .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
+ .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
+ .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
+ .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
+ .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
+ .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
- .gpu.value = VDD_GPU_DRA7,
- .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
+ .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
+ .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
+ .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
+ .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
+ .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS6,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
- .core.value = VDD_CORE_DRA7,
- .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
+ .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
+ .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS659038_REG_ADDR_SMPS7,
.core.pmic = &tps659038,
- .iva.value = VDD_IVA_DRA7,
- .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
+ .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
+ .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
+ .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
+ .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
+ .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS659038_REG_ADDR_SMPS8,
.iva.pmic = &tps659038,
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
+int get_voltrail_opp(int rail_offset)
+{
+ int opp;
+
+ switch (rail_offset) {
+ case VOLT_MPU:
+ opp = DRA7_MPU_OPP;
+ break;
+ case VOLT_CORE:
+ opp = DRA7_CORE_OPP;
+ break;
+ case VOLT_GPU:
+ opp = DRA7_GPU_OPP;
+ break;
+ case VOLT_EVE:
+ opp = DRA7_DSPEVE_OPP;
+ break;
+ case VOLT_IVA:
+ opp = DRA7_IVA_OPP;
+ break;
+ default:
+ opp = OPP_NOM;
+ }
+
+ return opp;
+}
+
+
#ifdef CONFIG_SPL_BUILD
/* No env to setup for SPL */
static inline void setup_board_eeprom_env(void) { }
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 3c16846..e0470e9 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -308,35 +308,47 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
}
struct vcores_data dra752_volts = {
- .mpu.value = VDD_MPU_DRA7,
- .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
+ .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
+ .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
- .eve.value = VDD_EVE_DRA7,
- .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
+ .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
+ .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
+ .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
+ .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
+ .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
- .gpu.value = VDD_GPU_DRA7,
- .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
+ .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
+ .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
+ .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
+ .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
+ .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS6,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
- .core.value = VDD_CORE_DRA7,
- .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
+ .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
+ .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS659038_REG_ADDR_SMPS7,
.core.pmic = &tps659038,
- .iva.value = VDD_IVA_DRA7,
- .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
+ .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
+ .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
+ .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
+ .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
+ .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS659038_REG_ADDR_SMPS8,
.iva.pmic = &tps659038,
@@ -344,15 +356,15 @@ struct vcores_data dra752_volts = {
};
struct vcores_data dra722_volts = {
- .mpu.value = VDD_MPU_DRA7,
- .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
+ .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
+ .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS65917_REG_ADDR_SMPS1,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
- .core.value = VDD_CORE_DRA7,
- .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
+ .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
+ .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS65917_REG_ADDR_SMPS2,
.core.pmic = &tps659038,
@@ -361,28 +373,67 @@ struct vcores_data dra722_volts = {
* The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
* designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
*/
- .gpu.value = VDD_GPU_DRA7,
- .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
+ .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
+ .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
+ .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
+ .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
+ .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS65917_REG_ADDR_SMPS3,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
- .eve.value = VDD_EVE_DRA7,
- .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
+ .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
+ .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
+ .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
+ .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
+ .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS65917_REG_ADDR_SMPS3,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
- .iva.value = VDD_IVA_DRA7,
- .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
+ .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
+ .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
+ .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
+ .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
+ .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS65917_REG_ADDR_SMPS3,
.iva.pmic = &tps659038,
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
+int get_voltrail_opp(int rail_offset)
+{
+ int opp;
+
+ switch (rail_offset) {
+ case VOLT_MPU:
+ opp = DRA7_MPU_OPP;
+ break;
+ case VOLT_CORE:
+ opp = DRA7_CORE_OPP;
+ break;
+ case VOLT_GPU:
+ opp = DRA7_GPU_OPP;
+ break;
+ case VOLT_EVE:
+ opp = DRA7_DSPEVE_OPP;
+ break;
+ case VOLT_IVA:
+ opp = DRA7_IVA_OPP;
+ break;
+ default:
+ opp = OPP_NOM;
+ }
+
+ return opp;
+}
+
/**
* @brief board_init
*
--
2.10.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2 2/3] ARM: DRA7: Redefine voltage and efuse macros per OPP using Kconfig
2016-11-23 7:24 [U-Boot] [PATCH v2 0/3] ARM: DRA7: Add Kconfig support for selecting OPPs Lokesh Vutla
2016-11-23 7:24 ` [U-Boot] [PATCH v2 1/3] ARM: OMAP4+: Add support for dynamically " Lokesh Vutla
@ 2016-11-23 7:24 ` Lokesh Vutla
2016-11-23 18:06 ` Tom Rini
2016-12-04 23:18 ` [U-Boot] [U-Boot, v2, " Tom Rini
2016-11-23 7:24 ` [U-Boot] [PATCH v2 3/3] ARM: DRA7: Fixup DSPEVE, IVA and GPU clock frequencies based on OPP Lokesh Vutla
2 siblings, 2 replies; 10+ messages in thread
From: Lokesh Vutla @ 2016-11-23 7:24 UTC (permalink / raw)
To: u-boot
From: Suman Anna <s-anna@ti.com>
Redefine the macros used to define the voltage values and the
efuse register offsets based on OPP for all the voltage domains.
This is done using Kconfig macros that can be set in a defconfig
or selected during a config step. This allows a voltage domain
to be configured/set to a corresponding voltage value depending
on the OPP selection choice.
The Kconfig choices have been added for MPU, DSPEVE, IVA and GPU
voltage domains, with the MPU domain restricted to OPP_NOM. The
OPP_OD and OPP_HIGH options will be added when the support for
configuring the MPU clock frequency is added. The clock
configuration for other voltage domains is out of scope in
u-boot code.
The CORE voltage domain does not have separate voltage values
and efuse register offset at different OPPs, while the MPU
voltage domain only has different efuse register offsets for
different OPPs, but uses the same voltage value. Any different
choices of OPPs for voltage domains on common ganged-rails
is automatically taken care to select the corresponding
highest OPP voltage value.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
arch/arm/include/asm/arch-omap5/clock.h | 47 ++++++++++++-----
arch/arm/mach-omap2/omap5/Kconfig | 93 +++++++++++++++++++++++++++++++++
2 files changed, 127 insertions(+), 13 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 551c927..e8b286b 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -286,19 +286,40 @@
/* STD_FUSE_OPP_VMIN_MPU_4 */
#define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28)
-/* Common voltage and Efuse register macros */
-/* DRA74x/DRA75x/DRA72x */
-#define VDD_MPU_DRA7 VDD_MPU_DRA7_NOM
-#define VDD_CORE_DRA7 VDD_CORE_DRA7_NOM
-#define VDD_EVE_DRA7 VDD_EVE_DRA7_NOM
-#define VDD_GPU_DRA7 VDD_GPU_DRA7_NOM
-#define VDD_IVA_DRA7 VDD_IVA_DRA7_NOM
-
-#define STD_FUSE_OPP_VMIN_MPU STD_FUSE_OPP_VMIN_MPU_NOM
-#define STD_FUSE_OPP_VMIN_CORE STD_FUSE_OPP_VMIN_CORE_NOM
-#define STD_FUSE_OPP_VMIN_DSPEVE STD_FUSE_OPP_VMIN_DSPEVE_NOM
-#define STD_FUSE_OPP_VMIN_GPU STD_FUSE_OPP_VMIN_GPU_NOM
-#define STD_FUSE_OPP_VMIN_IVA STD_FUSE_OPP_VMIN_IVA_NOM
+#if defined(CONFIG_DRA7_MPU_OPP_HIGH)
+#define DRA7_MPU_OPP OPP_HIGH
+#elif defined(CONFIG_DRA7_MPU_OPP_OD)
+#define DRA7_MPU_OPP OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_MPU_OPP OPP_NOM
+#endif
+
+/* OPP_NOM only available option for CORE */
+#define DRA7_CORE_OPP OPP_NOM
+
+#if defined(CONFIG_DRA7_DSPEVE_OPP_HIGH)
+#define DRA7_DSPEVE_OPP OPP_HIGH
+#elif defined(CONFIG_DRA7_DSPEVE_OPP_OD)
+#define DRA7_DSPEVE_OPP OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_DSPEVE_OPP OPP_NOM
+#endif
+
+#if defined(CONFIG_DRA7_IVA_OPP_HIGH)
+#define DRA7_IVA_OPP OPP_HIGH
+#elif defined(CONFIG_DRA7_IVA_OPP_OD)
+#define DRA7_IVA_OPP OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_IVA_OPP OPP_NOM
+#endif
+
+#if defined(CONFIG_DRA7_GPU_OPP_HIGH)
+#define DRA7_GPU_OPP OPP_HIGH
+#elif defined(CONFIG_DRA7_GPU_OPP_OD)
+#define DRA7_GPU_OPP OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_GPU_OPP OPP_NOM
+#endif
/* Standard offset is 0.5v expressed in uv */
#define PALMAS_SMPS_BASE_VOLT_UV 500000
diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig
index 22259dc..018e584 100644
--- a/arch/arm/mach-omap2/omap5/Kconfig
+++ b/arch/arm/mach-omap2/omap5/Kconfig
@@ -86,6 +86,99 @@ config TI_SECURE_EMIF_PROTECTED_REGION_SIZE
using hardware memory firewalls. This value must be smaller than the
TI_SECURE_EMIF_TOTAL_REGION_SIZE value.
+if TARGET_DRA7XX_EVM || TARGET_AM57XX_EVM
+menu "Voltage Domain OPP selections"
+
+choice
+ prompt "MPU Voltage Domain"
+ default DRA7_MPU_OPP_NOM
+ help
+ Select the Operating Performance Point(OPP) for the MPU voltage
+ domain on DRA7xx & AM57xx SoCs.
+
+config DRA7_MPU_OPP_NOM
+ bool "OPP NOM"
+ help
+ This config option enables Normal OPP for MPU. This is the safest
+ option for booting.
+
+endchoice
+
+choice
+ prompt "DSPEVE Voltage Domain"
+ help
+ Select the Operating Performance Point(OPP) for the DSPEVE voltage
+ domain on DRA7xx & AM57xx SoCs.
+
+config DRA7_DSPEVE_OPP_NOM
+ bool "OPP NOM"
+ help
+ This config option enables Normal OPP for DSPEVE. This is the safest
+ option for booting and choose this when unsure about other OPPs .
+
+config DRA7_DSPEVE_OPP_OD
+ bool "OPP OD"
+ help
+ This config option enables Over drive OPP for DSPEVE.
+
+config DRA7_DSPEVE_OPP_HIGH
+ bool "OPP HIGH"
+ help
+ This config option enables High OPP for DSPEVE.
+
+endchoice
+
+choice
+ prompt "IVA Voltage Domain"
+ help
+ Select the Operating Performance Point(OPP) for the IVA voltage
+ domain on DRA7xx & AM57xx SoCs.
+
+config DRA7_IVA_OPP_NOM
+ bool "OPP NOM"
+ help
+ This config option enables Normal OPP for IVA. This is the safest
+ option for booting and choose this when unsure about other OPPs .
+
+config DRA7_IVA_OPP_OD
+ bool "OPP OD"
+ help
+ This config option enables Over drive OPP for IVA.
+
+config DRA7_IVA_OPP_HIGH
+ bool "OPP HIGH"
+ help
+ This config option enables High OPP for IVA.
+
+endchoice
+
+choice
+ prompt "GPU Voltage Domain"
+ help
+ Select the Operating Performance Point(OPP) for the GPU voltage
+ domain on DRA7xx & AM57xx SoCs.
+
+config DRA7_GPU_OPP_NOM
+ bool "OPP NOM"
+ help
+ This config option enables Normal OPP for GPU. This is the safest
+ option for booting and choose this when unsure about other OPPs .
+
+config DRA7_GPU_OPP_OD
+ bool "OPP OD"
+ help
+ This config option enables Over drive OPP for GPU.
+
+config DRA7_GPU_OPP_HIGH
+ bool "OPP HIGH"
+ help
+ This config option enables High OPP for GPU.
+
+endchoice
+
+endmenu
+endif
+
source "board/compulab/cm_t54/Kconfig"
source "board/ti/omap5_uevm/Kconfig"
source "board/ti/dra7xx/Kconfig"
--
2.10.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2 3/3] ARM: DRA7: Fixup DSPEVE, IVA and GPU clock frequencies based on OPP
2016-11-23 7:24 [U-Boot] [PATCH v2 0/3] ARM: DRA7: Add Kconfig support for selecting OPPs Lokesh Vutla
2016-11-23 7:24 ` [U-Boot] [PATCH v2 1/3] ARM: OMAP4+: Add support for dynamically " Lokesh Vutla
2016-11-23 7:24 ` [U-Boot] [PATCH v2 2/3] ARM: DRA7: Redefine voltage and efuse macros per OPP using Kconfig Lokesh Vutla
@ 2016-11-23 7:24 ` Lokesh Vutla
2016-11-23 18:06 ` Tom Rini
2016-12-04 23:19 ` [U-Boot] [U-Boot, v2, " Tom Rini
2 siblings, 2 replies; 10+ messages in thread
From: Lokesh Vutla @ 2016-11-23 7:24 UTC (permalink / raw)
To: u-boot
From: Suman Anna <s-anna@ti.com>
This patch adds support to update the device-tree blob to adjust the
DSP and IVA DPLL clocks pertinent to the selected OPP choice, with
the default being OPP_NOM. The voltage settings are done in u-boot,
but the actual clock configuration itself is done in kernel because
of the following reasons:
1. SoC definition constraints us to NOT to do dynamic voltage
scaling ever after the initial avs0 setting in bootloader
- so the voltage must be set in bootloader.
2. The voltage level must be set even if the IP blocks like
GPU/DSP are unused.
3. The IVA, GPU and DSP DPLLs are not essential for u-boot functionality,
and similar DPLL clock configuration code has been cleaned up in
v2014.10 u-boot release. See commit, 02c41535b6a4 ("ARM: OMAP4/5:
Remove dead code against CONFIG_SYS_CLOCKS_ENABLE_ALL").
The non-essential DPLLs are configured within the kernel during
the clock init step when parsing the device tree and creating
the clock devices. This approach meets both the u-boot and kernel
needs.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Subhajit Paul <subhajit_paul@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
arch/arm/mach-omap2/omap5/fdt.c | 136 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 136 insertions(+)
diff --git a/arch/arm/mach-omap2/omap5/fdt.c b/arch/arm/mach-omap2/omap5/fdt.c
index da8d59b..1cc516c 100644
--- a/arch/arm/mach-omap2/omap5/fdt.c
+++ b/arch/arm/mach-omap2/omap5/fdt.c
@@ -233,6 +233,141 @@ static void ft_hs_fixups(void *fdt, bd_t *bd)
}
#endif /* #ifdef CONFIG_TI_SECURE_DEVICE */
+#if defined(CONFIG_TARGET_DRA7XX_EVM) || defined(CONFIG_TARGET_AM57XX_EVM)
+#define OPP_DSP_CLK_NUM 3
+#define OPP_IVA_CLK_NUM 2
+#define OPP_GPU_CLK_NUM 2
+
+const char *dra7_opp_dsp_clk_names[OPP_DSP_CLK_NUM] = {
+ "dpll_dsp_ck",
+ "dpll_dsp_m2_ck",
+ "dpll_dsp_m3x2_ck",
+};
+
+const char *dra7_opp_iva_clk_names[OPP_IVA_CLK_NUM] = {
+ "dpll_iva_ck",
+ "dpll_iva_m2_ck",
+};
+
+const char *dra7_opp_gpu_clk_names[OPP_GPU_CLK_NUM] = {
+ "dpll_gpu_ck",
+ "dpll_gpu_m2_ck",
+};
+
+/* DSPEVE voltage domain */
+u32 dra7_opp_dsp_clk_rates[NUM_OPPS][OPP_DSP_CLK_NUM] = {
+ {}, /*OPP_LOW */
+ {600000000, 600000000, 400000000}, /* OPP_NOM */
+ {700000000, 700000000, 466666667}, /* OPP_OD */
+ {750000000, 750000000, 500000000}, /* OPP_HIGH */
+};
+
+/* IVA voltage domain */
+u32 dra7_opp_iva_clk_rates[NUM_OPPS][OPP_IVA_CLK_NUM] = {
+ {}, /* OPP_LOW */
+ {1165000000, 388333334}, /* OPP_NOM */
+ {860000000, 430000000}, /* OPP_OD */
+ {1064000000, 532000000}, /* OPP_HIGH */
+};
+
+/* GPU voltage domain */
+u32 dra7_opp_gpu_clk_rates[NUM_OPPS][OPP_GPU_CLK_NUM] = {
+ {}, /* OPP_LOW */
+ {1277000000, 425666667}, /* OPP_NOM */
+ {1000000000, 500000000}, /* OPP_OD */
+ {1064000000, 532000000}, /* OPP_HIGH */
+};
+
+static int ft_fixup_clocks(void *fdt, const char **names, u32 *rates, int num)
+{
+ int offs, node_offs, ret, i;
+ uint32_t phandle;
+
+ offs = fdt_path_offset(fdt, "/ocp/l4 at 4a000000/cm_core_aon at 5000/clocks");
+ if (offs < 0) {
+ debug("Could not find cm_core_aon clocks node path offset : %s\n",
+ fdt_strerror(offs));
+ return offs;
+ }
+
+ for (i = 0; i < num; i++) {
+ node_offs = fdt_subnode_offset(fdt, offs, names[i]);
+ if (node_offs < 0) {
+ debug("Could not find clock sub-node %s: %s\n",
+ names[i], fdt_strerror(node_offs));
+ return offs;
+ }
+
+ phandle = fdt_get_phandle(fdt, node_offs);
+ if (!phandle) {
+ debug("Could not find phandle for clock %s\n",
+ names[i]);
+ return -1;
+ }
+
+ ret = fdt_setprop_u32(fdt, node_offs, "assigned-clocks",
+ phandle);
+ if (ret < 0) {
+ debug("Could not add assigned-clocks property to clock node %s: %s\n",
+ names[i], fdt_strerror(ret));
+ return ret;
+ }
+
+ ret = fdt_setprop_u32(fdt, node_offs, "assigned-clock-rates",
+ rates[i]);
+ if (ret < 0) {
+ debug("Could not add assigned-clock-rates property to clock node %s: %s\n",
+ names[i], fdt_strerror(ret));
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static void ft_opp_clock_fixups(void *fdt, bd_t *bd)
+{
+ const char **clk_names;
+ u32 *clk_rates;
+ int ret;
+
+ if (!is_dra72x() && !is_dra7xx())
+ return;
+
+ /* fixup DSP clocks */
+ clk_names = dra7_opp_dsp_clk_names;
+ clk_rates = dra7_opp_dsp_clk_rates[get_voltrail_opp(VOLT_EVE)];
+ ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_DSP_CLK_NUM);
+ if (ret) {
+ printf("ft_fixup_clocks failed for DSP voltage domain: %s\n",
+ fdt_strerror(ret));
+ return;
+ }
+
+ /* fixup IVA clocks */
+ clk_names = dra7_opp_iva_clk_names;
+ clk_rates = dra7_opp_iva_clk_rates[get_voltrail_opp(VOLT_IVA)];
+ ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_IVA_CLK_NUM);
+ if (ret) {
+ printf("ft_fixup_clocks failed for IVA voltage domain: %s\n",
+ fdt_strerror(ret));
+ return;
+ }
+
+ /* fixup GPU clocks */
+ clk_names = dra7_opp_gpu_clk_names;
+ clk_rates = dra7_opp_gpu_clk_rates[get_voltrail_opp(VOLT_GPU)];
+ ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_GPU_CLK_NUM);
+ if (ret) {
+ printf("ft_fixup_clocks failed for GPU voltage domain: %s\n",
+ fdt_strerror(ret));
+ return;
+ }
+}
+#else
+static void ft_opp_clock_fixups(void *fdt, bd_t *bd) { }
+#endif /* CONFIG_TARGET_DRA7XX_EVM || CONFIG_TARGET_AM57XX_EVM */
+
/*
* Place for general cpu/SoC FDT fixups. Board specific
* fixups should remain in the board files which is where
@@ -241,4 +376,5 @@ static void ft_hs_fixups(void *fdt, bd_t *bd)
void ft_cpu_setup(void *fdt, bd_t *bd)
{
ft_hs_fixups(fdt, bd);
+ ft_opp_clock_fixups(fdt, bd);
}
--
2.10.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2 1/3] ARM: OMAP4+: Add support for dynamically selecting OPPs
2016-11-23 7:24 ` [U-Boot] [PATCH v2 1/3] ARM: OMAP4+: Add support for dynamically " Lokesh Vutla
@ 2016-11-23 18:05 ` Tom Rini
2016-12-04 23:17 ` [U-Boot] [U-Boot, v2, " Tom Rini
1 sibling, 0 replies; 10+ messages in thread
From: Tom Rini @ 2016-11-23 18:05 UTC (permalink / raw)
To: u-boot
On Wed, Nov 23, 2016 at 12:54:39PM +0530, Lokesh Vutla wrote:
> It can be expected that different paper spins of a SoC can have
> different definitions for OPP and can have their own constraints
> on the boot up OPP for each voltage rail. In order to have this
> flexibility, add support for dynamically selecting the OPP voltage
> based on the board to handle any such exceptions.
>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
--
Tom
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^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2 2/3] ARM: DRA7: Redefine voltage and efuse macros per OPP using Kconfig
2016-11-23 7:24 ` [U-Boot] [PATCH v2 2/3] ARM: DRA7: Redefine voltage and efuse macros per OPP using Kconfig Lokesh Vutla
@ 2016-11-23 18:06 ` Tom Rini
2016-12-04 23:18 ` [U-Boot] [U-Boot, v2, " Tom Rini
1 sibling, 0 replies; 10+ messages in thread
From: Tom Rini @ 2016-11-23 18:06 UTC (permalink / raw)
To: u-boot
On Wed, Nov 23, 2016 at 12:54:40PM +0530, Lokesh Vutla wrote:
> From: Suman Anna <s-anna@ti.com>
>
> Redefine the macros used to define the voltage values and the
> efuse register offsets based on OPP for all the voltage domains.
> This is done using Kconfig macros that can be set in a defconfig
> or selected during a config step. This allows a voltage domain
> to be configured/set to a corresponding voltage value depending
> on the OPP selection choice.
>
> The Kconfig choices have been added for MPU, DSPEVE, IVA and GPU
> voltage domains, with the MPU domain restricted to OPP_NOM. The
> OPP_OD and OPP_HIGH options will be added when the support for
> configuring the MPU clock frequency is added. The clock
> configuration for other voltage domains is out of scope in
> u-boot code.
>
> The CORE voltage domain does not have separate voltage values
> and efuse register offset at different OPPs, while the MPU
> voltage domain only has different efuse register offsets for
> different OPPs, but uses the same voltage value. Any different
> choices of OPPs for voltage domains on common ganged-rails
> is automatically taken care to select the corresponding
> highest OPP voltage value.
>
> Signed-off-by: Suman Anna <s-anna@ti.com>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
--
Tom
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^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2 3/3] ARM: DRA7: Fixup DSPEVE, IVA and GPU clock frequencies based on OPP
2016-11-23 7:24 ` [U-Boot] [PATCH v2 3/3] ARM: DRA7: Fixup DSPEVE, IVA and GPU clock frequencies based on OPP Lokesh Vutla
@ 2016-11-23 18:06 ` Tom Rini
2016-12-04 23:19 ` [U-Boot] [U-Boot, v2, " Tom Rini
1 sibling, 0 replies; 10+ messages in thread
From: Tom Rini @ 2016-11-23 18:06 UTC (permalink / raw)
To: u-boot
On Wed, Nov 23, 2016 at 12:54:41PM +0530, Lokesh Vutla wrote:
> From: Suman Anna <s-anna@ti.com>
>
> This patch adds support to update the device-tree blob to adjust the
> DSP and IVA DPLL clocks pertinent to the selected OPP choice, with
> the default being OPP_NOM. The voltage settings are done in u-boot,
> but the actual clock configuration itself is done in kernel because
> of the following reasons:
> 1. SoC definition constraints us to NOT to do dynamic voltage
> scaling ever after the initial avs0 setting in bootloader
> - so the voltage must be set in bootloader.
> 2. The voltage level must be set even if the IP blocks like
> GPU/DSP are unused.
> 3. The IVA, GPU and DSP DPLLs are not essential for u-boot functionality,
> and similar DPLL clock configuration code has been cleaned up in
> v2014.10 u-boot release. See commit, 02c41535b6a4 ("ARM: OMAP4/5:
> Remove dead code against CONFIG_SYS_CLOCKS_ENABLE_ALL").
>
> The non-essential DPLLs are configured within the kernel during
> the clock init step when parsing the device tree and creating
> the clock devices. This approach meets both the u-boot and kernel
> needs.
>
> Signed-off-by: Suman Anna <s-anna@ti.com>
> Signed-off-by: Subhajit Paul <subhajit_paul@ti.com>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
--
Tom
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^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [U-Boot, v2, 1/3] ARM: OMAP4+: Add support for dynamically selecting OPPs
2016-11-23 7:24 ` [U-Boot] [PATCH v2 1/3] ARM: OMAP4+: Add support for dynamically " Lokesh Vutla
2016-11-23 18:05 ` Tom Rini
@ 2016-12-04 23:17 ` Tom Rini
1 sibling, 0 replies; 10+ messages in thread
From: Tom Rini @ 2016-12-04 23:17 UTC (permalink / raw)
To: u-boot
On Wed, Nov 23, 2016 at 12:54:39PM +0530, Lokesh Vutla wrote:
> It can be expected that different paper spins of a SoC can have
> different definitions for OPP and can have their own constraints
> on the boot up OPP for each voltage rail. In order to have this
> flexibility, add support for dynamically selecting the OPP voltage
> based on the board to handle any such exceptions.
>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [U-Boot, v2, 2/3] ARM: DRA7: Redefine voltage and efuse macros per OPP using Kconfig
2016-11-23 7:24 ` [U-Boot] [PATCH v2 2/3] ARM: DRA7: Redefine voltage and efuse macros per OPP using Kconfig Lokesh Vutla
2016-11-23 18:06 ` Tom Rini
@ 2016-12-04 23:18 ` Tom Rini
1 sibling, 0 replies; 10+ messages in thread
From: Tom Rini @ 2016-12-04 23:18 UTC (permalink / raw)
To: u-boot
On Wed, Nov 23, 2016 at 12:54:40PM +0530, Lokesh Vutla wrote:
> From: Suman Anna <s-anna@ti.com>
>
> Redefine the macros used to define the voltage values and the
> efuse register offsets based on OPP for all the voltage domains.
> This is done using Kconfig macros that can be set in a defconfig
> or selected during a config step. This allows a voltage domain
> to be configured/set to a corresponding voltage value depending
> on the OPP selection choice.
>
> The Kconfig choices have been added for MPU, DSPEVE, IVA and GPU
> voltage domains, with the MPU domain restricted to OPP_NOM. The
> OPP_OD and OPP_HIGH options will be added when the support for
> configuring the MPU clock frequency is added. The clock
> configuration for other voltage domains is out of scope in
> u-boot code.
>
> The CORE voltage domain does not have separate voltage values
> and efuse register offset at different OPPs, while the MPU
> voltage domain only has different efuse register offsets for
> different OPPs, but uses the same voltage value. Any different
> choices of OPPs for voltage domains on common ganged-rails
> is automatically taken care to select the corresponding
> highest OPP voltage value.
>
> Signed-off-by: Suman Anna <s-anna@ti.com>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [U-Boot, v2, 3/3] ARM: DRA7: Fixup DSPEVE, IVA and GPU clock frequencies based on OPP
2016-11-23 7:24 ` [U-Boot] [PATCH v2 3/3] ARM: DRA7: Fixup DSPEVE, IVA and GPU clock frequencies based on OPP Lokesh Vutla
2016-11-23 18:06 ` Tom Rini
@ 2016-12-04 23:19 ` Tom Rini
1 sibling, 0 replies; 10+ messages in thread
From: Tom Rini @ 2016-12-04 23:19 UTC (permalink / raw)
To: u-boot
On Wed, Nov 23, 2016 at 12:54:41PM +0530, Lokesh Vutla wrote:
> From: Suman Anna <s-anna@ti.com>
>
> This patch adds support to update the device-tree blob to adjust the
> DSP and IVA DPLL clocks pertinent to the selected OPP choice, with
> the default being OPP_NOM. The voltage settings are done in u-boot,
> but the actual clock configuration itself is done in kernel because
> of the following reasons:
> 1. SoC definition constraints us to NOT to do dynamic voltage
> scaling ever after the initial avs0 setting in bootloader
> - so the voltage must be set in bootloader.
> 2. The voltage level must be set even if the IP blocks like
> GPU/DSP are unused.
> 3. The IVA, GPU and DSP DPLLs are not essential for u-boot functionality,
> and similar DPLL clock configuration code has been cleaned up in
> v2014.10 u-boot release. See commit, 02c41535b6a4 ("ARM: OMAP4/5:
> Remove dead code against CONFIG_SYS_CLOCKS_ENABLE_ALL").
>
> The non-essential DPLLs are configured within the kernel during
> the clock init step when parsing the device tree and creating
> the clock devices. This approach meets both the u-boot and kernel
> needs.
>
> Signed-off-by: Suman Anna <s-anna@ti.com>
> Signed-off-by: Subhajit Paul <subhajit_paul@ti.com>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
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^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2016-12-04 23:19 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-11-23 7:24 [U-Boot] [PATCH v2 0/3] ARM: DRA7: Add Kconfig support for selecting OPPs Lokesh Vutla
2016-11-23 7:24 ` [U-Boot] [PATCH v2 1/3] ARM: OMAP4+: Add support for dynamically " Lokesh Vutla
2016-11-23 18:05 ` Tom Rini
2016-12-04 23:17 ` [U-Boot] [U-Boot, v2, " Tom Rini
2016-11-23 7:24 ` [U-Boot] [PATCH v2 2/3] ARM: DRA7: Redefine voltage and efuse macros per OPP using Kconfig Lokesh Vutla
2016-11-23 18:06 ` Tom Rini
2016-12-04 23:18 ` [U-Boot] [U-Boot, v2, " Tom Rini
2016-11-23 7:24 ` [U-Boot] [PATCH v2 3/3] ARM: DRA7: Fixup DSPEVE, IVA and GPU clock frequencies based on OPP Lokesh Vutla
2016-11-23 18:06 ` Tom Rini
2016-12-04 23:19 ` [U-Boot] [U-Boot, v2, " Tom Rini
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