* [PATCH 01/15] drm/i915: Create a common GEN9_LP_FEATURE.
2016-11-10 15:23 [PATCH 00/15] Geminilake enabling Ander Conselvan de Oliveira
@ 2016-11-10 15:23 ` Ander Conselvan de Oliveira
2016-11-14 14:19 ` [PATCH v2] " Ander Conselvan de Oliveira
2016-11-10 15:23 ` [PATCH 02/15] drm/i915/glk: Introduce Geminilake platform definition Ander Conselvan de Oliveira
` (18 subsequent siblings)
19 siblings, 1 reply; 52+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-11-10 15:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
The following LP platform inherits a lot of this platform
So let's simplify here to re-use this later.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 47 ++++++++++++++++++++++-------------------
1 file changed, 25 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 2a419500..b8cdda1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -343,30 +343,33 @@ static const struct intel_device_info intel_skylake_gt3_info = {
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
+#define GEN9_LP_FEATURES \
+ .gen = 9, \
+ .has_hotplug = 1, \
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
+ .num_pipes = 3, \
+ .has_64bit_reloc = 1, \
+ .has_ddi = 1, \
+ .has_fpga_dbg = 1, \
+ .has_fbc = 1, \
+ .has_runtime_pm = 1, \
+ .has_pooled_eu = 0, \
+ .has_csr = 1, \
+ .has_resource_streamer = 1, \
+ .has_rc6 = 1, \
+ .has_dp_mst = 1, \
+ .has_gmbus_irq = 1, \
+ .has_hw_contexts = 1, \
+ .has_logical_ring_contexts = 1, \
+ .has_guc = 1, \
+ .ddb_size = 512, \
+ GEN_DEFAULT_PIPEOFFSETS, \
+ IVB_CURSOR_OFFSETS, \
+ BDW_COLORS
+
static const struct intel_device_info intel_broxton_info = {
.is_broxton = 1,
- .gen = 9,
- .has_hotplug = 1,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
- .num_pipes = 3,
- .has_64bit_reloc = 1,
- .has_ddi = 1,
- .has_fpga_dbg = 1,
- .has_fbc = 1,
- .has_runtime_pm = 1,
- .has_pooled_eu = 0,
- .has_csr = 1,
- .has_resource_streamer = 1,
- .has_rc6 = 1,
- .has_dp_mst = 1,
- .has_gmbus_irq = 1,
- .has_hw_contexts = 1,
- .has_logical_ring_contexts = 1,
- .has_guc = 1,
- .ddb_size = 512,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
- BDW_COLORS,
+ GEN9_LP_FEATURES,
};
static const struct intel_device_info intel_kabylake_info = {
--
2.5.5
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^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v2] drm/i915: Create a common GEN9_LP_FEATURE.
2016-11-10 15:23 ` [PATCH 01/15] drm/i915: Create a common GEN9_LP_FEATURE Ander Conselvan de Oliveira
@ 2016-11-14 14:19 ` Ander Conselvan de Oliveira
2016-11-30 14:00 ` Imre Deak
0 siblings, 1 reply; 52+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-11-14 14:19 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira, Rodrigo Vivi
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
The following LP platform inherits a lot of this platform
So let's simplify here to re-use this later.
v2: Keep ddb_size out of the new macro.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 45 ++++++++++++++++++++++-------------------
1 file changed, 24 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 70a99ce..f8b93c1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -343,30 +343,33 @@ static const struct intel_device_info intel_skylake_gt3_info = {
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
+#define GEN9_LP_FEATURES \
+ .gen = 9, \
+ .has_hotplug = 1, \
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
+ .num_pipes = 3, \
+ .has_64bit_reloc = 1, \
+ .has_ddi = 1, \
+ .has_fpga_dbg = 1, \
+ .has_fbc = 1, \
+ .has_runtime_pm = 1, \
+ .has_pooled_eu = 0, \
+ .has_csr = 1, \
+ .has_resource_streamer = 1, \
+ .has_rc6 = 1, \
+ .has_dp_mst = 1, \
+ .has_gmbus_irq = 1, \
+ .has_hw_contexts = 1, \
+ .has_logical_ring_contexts = 1, \
+ .has_guc = 1, \
+ GEN_DEFAULT_PIPEOFFSETS, \
+ IVB_CURSOR_OFFSETS, \
+ BDW_COLORS
+
static const struct intel_device_info intel_broxton_info = {
.is_broxton = 1,
- .gen = 9,
- .has_hotplug = 1,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
- .num_pipes = 3,
- .has_64bit_reloc = 1,
- .has_ddi = 1,
- .has_fpga_dbg = 1,
- .has_fbc = 1,
- .has_runtime_pm = 1,
- .has_pooled_eu = 0,
- .has_csr = 1,
- .has_resource_streamer = 1,
- .has_rc6 = 1,
- .has_dp_mst = 1,
- .has_gmbus_irq = 1,
- .has_hw_contexts = 1,
- .has_logical_ring_contexts = 1,
- .has_guc = 1,
+ GEN9_LP_FEATURES,
.ddb_size = 512,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
- BDW_COLORS,
};
static const struct intel_device_info intel_kabylake_info = {
--
2.5.5
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^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH v2] drm/i915: Create a common GEN9_LP_FEATURE.
2016-11-14 14:19 ` [PATCH v2] " Ander Conselvan de Oliveira
@ 2016-11-30 14:00 ` Imre Deak
2016-12-01 9:33 ` [PATCH v3] " Ander Conselvan de Oliveira
0 siblings, 1 reply; 52+ messages in thread
From: Imre Deak @ 2016-11-30 14:00 UTC (permalink / raw)
To: Ander Conselvan de Oliveira, intel-gfx; +Cc: Rodrigo Vivi
On ma, 2016-11-14 at 16:19 +0200, Ander Conselvan de Oliveira wrote:
> From: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> The following LP platform inherits a lot of this platform
> So let's simplify here to re-use this later.
>
> v2: Keep ddb_size out of the new macro.
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Ander Conselvan de Oliveira
> <ander.conselvan.de.oliveira@intel.com>
Needs a rebase due to new .has_decoupled_mmio, with that in
GEN9_LP_FEATURES:
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_pci.c | 45 ++++++++++++++++++++++---------
> ----------
> 1 file changed, 24 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c
> b/drivers/gpu/drm/i915/i915_pci.c
> index 70a99ce..f8b93c1 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -343,30 +343,33 @@ static const struct intel_device_info
> intel_skylake_gt3_info = {
> .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING
> | BSD2_RING,
> };
>
> +#define GEN9_LP_FEATURES \
> + .gen = 9, \
> + .has_hotplug = 1, \
> + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
> \
> + .num_pipes = 3, \
> + .has_64bit_reloc = 1, \
> + .has_ddi = 1, \
> + .has_fpga_dbg = 1, \
> + .has_fbc = 1, \
> + .has_runtime_pm = 1, \
> + .has_pooled_eu = 0, \
> + .has_csr = 1, \
> + .has_resource_streamer = 1, \
> + .has_rc6 = 1, \
> + .has_dp_mst = 1, \
> + .has_gmbus_irq = 1, \
> + .has_hw_contexts = 1, \
> + .has_logical_ring_contexts = 1, \
> + .has_guc = 1, \
> + GEN_DEFAULT_PIPEOFFSETS, \
> + IVB_CURSOR_OFFSETS, \
> + BDW_COLORS
> +
> static const struct intel_device_info intel_broxton_info = {
> .is_broxton = 1,
> - .gen = 9,
> - .has_hotplug = 1,
> - .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
> - .num_pipes = 3,
> - .has_64bit_reloc = 1,
> - .has_ddi = 1,
> - .has_fpga_dbg = 1,
> - .has_fbc = 1,
> - .has_runtime_pm = 1,
> - .has_pooled_eu = 0,
> - .has_csr = 1,
> - .has_resource_streamer = 1,
> - .has_rc6 = 1,
> - .has_dp_mst = 1,
> - .has_gmbus_irq = 1,
> - .has_hw_contexts = 1,
> - .has_logical_ring_contexts = 1,
> - .has_guc = 1,
> + GEN9_LP_FEATURES,
> .ddb_size = 512,
> - GEN_DEFAULT_PIPEOFFSETS,
> - IVB_CURSOR_OFFSETS,
> - BDW_COLORS,
> };
>
> static const struct intel_device_info intel_kabylake_info = {
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^ permalink raw reply [flat|nested] 52+ messages in thread* [PATCH v3] drm/i915: Create a common GEN9_LP_FEATURE.
2016-11-30 14:00 ` Imre Deak
@ 2016-12-01 9:33 ` Ander Conselvan de Oliveira
0 siblings, 0 replies; 52+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-12-01 9:33 UTC (permalink / raw)
To: intel-gfx, imre.deak; +Cc: Ander Conselvan de Oliveira, Rodrigo Vivi
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
The following LP platform inherits a lot of this platform
So let's simplify here to re-use this later.
v2: Keep ddb_size out of the new macro.
v3: Rebase (has_decoupled_mmio). (Imre)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 47 ++++++++++++++++++++++-------------------
1 file changed, 25 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index fce8e19..2797dec 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -343,31 +343,34 @@ static const struct intel_device_info intel_skylake_gt3_info = {
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
+#define GEN9_LP_FEATURES \
+ .gen = 9, \
+ .has_hotplug = 1, \
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
+ .num_pipes = 3, \
+ .has_64bit_reloc = 1, \
+ .has_ddi = 1, \
+ .has_fpga_dbg = 1, \
+ .has_fbc = 1, \
+ .has_runtime_pm = 1, \
+ .has_pooled_eu = 0, \
+ .has_csr = 1, \
+ .has_resource_streamer = 1, \
+ .has_rc6 = 1, \
+ .has_dp_mst = 1, \
+ .has_gmbus_irq = 1, \
+ .has_hw_contexts = 1, \
+ .has_logical_ring_contexts = 1, \
+ .has_guc = 1, \
+ .has_decoupled_mmio = 1, \
+ GEN_DEFAULT_PIPEOFFSETS, \
+ IVB_CURSOR_OFFSETS, \
+ BDW_COLORS
+
static const struct intel_device_info intel_broxton_info = {
.is_broxton = 1,
- .gen = 9,
- .has_hotplug = 1,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
- .num_pipes = 3,
- .has_64bit_reloc = 1,
- .has_ddi = 1,
- .has_fpga_dbg = 1,
- .has_fbc = 1,
- .has_runtime_pm = 1,
- .has_pooled_eu = 0,
- .has_csr = 1,
- .has_resource_streamer = 1,
- .has_rc6 = 1,
- .has_dp_mst = 1,
- .has_gmbus_irq = 1,
- .has_hw_contexts = 1,
- .has_logical_ring_contexts = 1,
- .has_guc = 1,
- .has_decoupled_mmio = 1,
+ GEN9_LP_FEATURES,
.ddb_size = 512,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
- BDW_COLORS,
};
static const struct intel_device_info intel_kabylake_info = {
--
2.5.5
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^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 02/15] drm/i915/glk: Introduce Geminilake platform definition
2016-11-10 15:23 [PATCH 00/15] Geminilake enabling Ander Conselvan de Oliveira
2016-11-10 15:23 ` [PATCH 01/15] drm/i915: Create a common GEN9_LP_FEATURE Ander Conselvan de Oliveira
@ 2016-11-10 15:23 ` Ander Conselvan de Oliveira
2016-11-10 16:40 ` Jani Nikula
2016-11-10 23:18 ` Matt Roper
2016-11-10 15:23 ` [PATCH 03/15] drm/i915/glk: Add Geminilake PCI IDs Ander Conselvan de Oliveira
` (17 subsequent siblings)
19 siblings, 2 replies; 52+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-11-10 15:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
Geminilake is an Intel® Processor containing Intel® HD Graphics
following Broxton.
Let's start by adding the platform definition. PCI IDs and plaform
specific code will follow.
v2: Rebase (don't allow dev to be used with the new macro).
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 6 ++++++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4735b417..8a99e6e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -667,6 +667,7 @@ struct intel_csr {
func(is_broadwell); \
func(is_skylake); \
func(is_broxton); \
+ func(is_geminilake); \
func(is_kabylake); \
func(is_preliminary); \
/* Keep has_* in alphabetical order */ \
@@ -2756,6 +2757,7 @@ struct drm_i915_cmd_table {
#define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
#define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
#define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
+#define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.is_geminilake)
#define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
#define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b8cdda1..dc2ba3f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -372,6 +372,12 @@ static const struct intel_device_info intel_broxton_info = {
GEN9_LP_FEATURES,
};
+static const struct intel_device_info intel_geminilake_info = {
+ .is_preliminary = 1,
+ .is_geminilake = 1,
+ GEN9_LP_FEATURES,
+};
+
static const struct intel_device_info intel_kabylake_info = {
BDW_FEATURES,
.is_kabylake = 1,
--
2.5.5
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^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 02/15] drm/i915/glk: Introduce Geminilake platform definition
2016-11-10 15:23 ` [PATCH 02/15] drm/i915/glk: Introduce Geminilake platform definition Ander Conselvan de Oliveira
@ 2016-11-10 16:40 ` Jani Nikula
2016-11-10 17:03 ` Rodrigo Vivi
2016-11-10 23:18 ` Matt Roper
1 sibling, 1 reply; 52+ messages in thread
From: Jani Nikula @ 2016-11-10 16:40 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
On Thu, 10 Nov 2016, Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> wrote:
> Geminilake is an Intel® Processor containing Intel® HD Graphics
> following Broxton.
>
> Let's start by adding the platform definition. PCI IDs and plaform
> specific code will follow.
>
> v2: Rebase (don't allow dev to be used with the new macro).
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_pci.c | 6 ++++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4735b417..8a99e6e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -667,6 +667,7 @@ struct intel_csr {
> func(is_broadwell); \
> func(is_skylake); \
> func(is_broxton); \
> + func(is_geminilake); \
> func(is_kabylake); \
> func(is_preliminary); \
> /* Keep has_* in alphabetical order */ \
> @@ -2756,6 +2757,7 @@ struct drm_i915_cmd_table {
> #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
> #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
> #define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
> +#define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.is_geminilake)
> #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
> #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index b8cdda1..dc2ba3f 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -372,6 +372,12 @@ static const struct intel_device_info intel_broxton_info = {
> GEN9_LP_FEATURES,
> };
>
> +static const struct intel_device_info intel_geminilake_info = {
> + .is_preliminary = 1,
I'd like to push [1] pretty soon now that Daniel gave his reviewed-by,
and we currently don't have anything in preliminary, until these patches
get merged. If you need to resend the series again for some other
reason, let me know so I'll push that first and you can rebase this
patch; it's rather trivial. Otherwise, I'll rebase my patch on top of
this series once it's been pushed. Sound okay?
BR
Jani.
[1] http://patchwork.freedesktop.org/patch/msgid/1477909108-18696-1-git-send-email-jani.nikula@intel.com
> + .is_geminilake = 1,
> + GEN9_LP_FEATURES,
> +};
> +
> static const struct intel_device_info intel_kabylake_info = {
> BDW_FEATURES,
> .is_kabylake = 1,
--
Jani Nikula, Intel Open Source Technology Center
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^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH 02/15] drm/i915/glk: Introduce Geminilake platform definition
2016-11-10 16:40 ` Jani Nikula
@ 2016-11-10 17:03 ` Rodrigo Vivi
2016-11-11 13:34 ` Ander Conselvan De Oliveira
0 siblings, 1 reply; 52+ messages in thread
From: Rodrigo Vivi @ 2016-11-10 17:03 UTC (permalink / raw)
To: Jani Nikula; +Cc: Ander Conselvan de Oliveira, intel-gfx
Yep, it is probably better to merge Jani patch before while no platform
is using that flag, but one way or another feel free to use:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
On Thu, Nov 10, 2016 at 06:40:29PM +0200, Jani Nikula wrote:
> On Thu, 10 Nov 2016, Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> wrote:
> > Geminilake is an Intel® Processor containing Intel® HD Graphics
> > following Broxton.
> >
> > Let's start by adding the platform definition. PCI IDs and plaform
> > specific code will follow.
> >
> > v2: Rebase (don't allow dev to be used with the new macro).
> > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 2 ++
> > drivers/gpu/drm/i915/i915_pci.c | 6 ++++++
> > 2 files changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 4735b417..8a99e6e 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -667,6 +667,7 @@ struct intel_csr {
> > func(is_broadwell); \
> > func(is_skylake); \
> > func(is_broxton); \
> > + func(is_geminilake); \
> > func(is_kabylake); \
> > func(is_preliminary); \
> > /* Keep has_* in alphabetical order */ \
> > @@ -2756,6 +2757,7 @@ struct drm_i915_cmd_table {
> > #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
> > #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
> > #define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
> > +#define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.is_geminilake)
> > #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
> > #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
> > #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > index b8cdda1..dc2ba3f 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -372,6 +372,12 @@ static const struct intel_device_info intel_broxton_info = {
> > GEN9_LP_FEATURES,
> > };
> >
> > +static const struct intel_device_info intel_geminilake_info = {
> > + .is_preliminary = 1,
>
> I'd like to push [1] pretty soon now that Daniel gave his reviewed-by,
> and we currently don't have anything in preliminary, until these patches
> get merged. If you need to resend the series again for some other
> reason, let me know so I'll push that first and you can rebase this
> patch; it's rather trivial. Otherwise, I'll rebase my patch on top of
> this series once it's been pushed. Sound okay?
>
> BR
> Jani.
>
>
> [1] http://patchwork.freedesktop.org/patch/msgid/1477909108-18696-1-git-send-email-jani.nikula@intel.com
>
>
> > + .is_geminilake = 1,
> > + GEN9_LP_FEATURES,
> > +};
> > +
> > static const struct intel_device_info intel_kabylake_info = {
> > BDW_FEATURES,
> > .is_kabylake = 1,
>
> --
> Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH 02/15] drm/i915/glk: Introduce Geminilake platform definition
2016-11-10 17:03 ` Rodrigo Vivi
@ 2016-11-11 13:34 ` Ander Conselvan De Oliveira
0 siblings, 0 replies; 52+ messages in thread
From: Ander Conselvan De Oliveira @ 2016-11-11 13:34 UTC (permalink / raw)
To: Rodrigo Vivi, Jani Nikula; +Cc: intel-gfx
On Thu, 2016-11-10 at 09:03 -0800, Rodrigo Vivi wrote:
> Yep, it is probably better to merge Jani patch before while no platform
> is using that flag, but one way or another feel free to use:
Agreed. I'll send an updated version of the first two patches because of the
ddb_size that is wrong, so I can rebase while at it.
Ander
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> On Thu, Nov 10, 2016 at 06:40:29PM +0200, Jani Nikula wrote:
> >
> > On Thu, 10 Nov 2016, Ander Conselvan de Oliveira <ander.conselvan.de.oliveir
> > a@intel.com> wrote:
> > >
> > > Geminilake is an Intel® Processor containing Intel® HD Graphics
> > > following Broxton.
> > >
> > > Let's start by adding the platform definition. PCI IDs and plaform
> > > specific code will follow.
> > >
> > > v2: Rebase (don't allow dev to be used with the new macro).
> > > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@in
> > > tel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_drv.h | 2 ++
> > > drivers/gpu/drm/i915/i915_pci.c | 6 ++++++
> > > 2 files changed, 8 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h
> > > index 4735b417..8a99e6e 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -667,6 +667,7 @@ struct intel_csr {
> > > func(is_broadwell); \
> > > func(is_skylake); \
> > > func(is_broxton); \
> > > + func(is_geminilake); \
> > > func(is_kabylake); \
> > > func(is_preliminary); \
> > > /* Keep has_* in alphabetical order */ \
> > > @@ -2756,6 +2757,7 @@ struct drm_i915_cmd_table {
> > > #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
> > > #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
> > > #define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
> > > +#define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.is_geminilake)
> > > #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
> > > #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
> > > #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> > > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > > b/drivers/gpu/drm/i915/i915_pci.c
> > > index b8cdda1..dc2ba3f 100644
> > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > @@ -372,6 +372,12 @@ static const struct intel_device_info
> > > intel_broxton_info = {
> > > GEN9_LP_FEATURES,
> > > };
> > >
> > > +static const struct intel_device_info intel_geminilake_info = {
> > > + .is_preliminary = 1,
> > I'd like to push [1] pretty soon now that Daniel gave his reviewed-by,
> > and we currently don't have anything in preliminary, until these patches
> > get merged. If you need to resend the series again for some other
> > reason, let me know so I'll push that first and you can rebase this
> > patch; it's rather trivial. Otherwise, I'll rebase my patch on top of
> > this series once it's been pushed. Sound okay?
> >
> > BR
> > Jani.
> >
> >
> > [1] http://patchwork.freedesktop.org/patch/msgid/1477909108-18696-1-git-send
> > -email-jani.nikula@intel.com
> >
> >
> > >
> > > + .is_geminilake = 1,
> > > + GEN9_LP_FEATURES,
> > > +};
> > > +
> > > static const struct intel_device_info intel_kabylake_info = {
> > > BDW_FEATURES,
> > > .is_kabylake = 1,
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 02/15] drm/i915/glk: Introduce Geminilake platform definition
2016-11-10 15:23 ` [PATCH 02/15] drm/i915/glk: Introduce Geminilake platform definition Ander Conselvan de Oliveira
2016-11-10 16:40 ` Jani Nikula
@ 2016-11-10 23:18 ` Matt Roper
2016-11-14 14:24 ` [PATCH v2 01/13] drm/i915/glk: Add Geminilake PCI IDs Ander Conselvan de Oliveira
2016-11-14 14:25 ` [PATCH v3] drm/i915/glk: Introduce Geminilake platform definition Ander Conselvan de Oliveira
1 sibling, 2 replies; 52+ messages in thread
From: Matt Roper @ 2016-11-10 23:18 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
On Thu, Nov 10, 2016 at 05:23:07PM +0200, Ander Conselvan de Oliveira wrote:
> Geminilake is an Intel® Processor containing Intel® HD Graphics
> following Broxton.
>
> Let's start by adding the platform definition. PCI IDs and plaform
> specific code will follow.
>
> v2: Rebase (don't allow dev to be used with the new macro).
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_pci.c | 6 ++++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4735b417..8a99e6e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -667,6 +667,7 @@ struct intel_csr {
> func(is_broadwell); \
> func(is_skylake); \
> func(is_broxton); \
> + func(is_geminilake); \
> func(is_kabylake); \
> func(is_preliminary); \
> /* Keep has_* in alphabetical order */ \
> @@ -2756,6 +2757,7 @@ struct drm_i915_cmd_table {
> #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
> #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
> #define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
> +#define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.is_geminilake)
> #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
> #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index b8cdda1..dc2ba3f 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -372,6 +372,12 @@ static const struct intel_device_info intel_broxton_info = {
> GEN9_LP_FEATURES,
> };
>
> +static const struct intel_device_info intel_geminilake_info = {
> + .is_preliminary = 1,
> + .is_geminilake = 1,
> + GEN9_LP_FEATURES,
Just a drive-by comment, but I think you need to update the .ddb_size
from GEN9_LP_FEATURES as well. Leaving BXT's value here is "safe" but
will make it very difficult to actually enable the additional planes
this platform has without exceeding the watermark limits.
Matt
> +};
> +
> static const struct intel_device_info intel_kabylake_info = {
> BDW_FEATURES,
> .is_kabylake = 1,
> --
> 2.5.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* [PATCH v2 01/13] drm/i915/glk: Add Geminilake PCI IDs
2016-11-10 23:18 ` Matt Roper
@ 2016-11-14 14:24 ` Ander Conselvan de Oliveira
2016-11-14 14:29 ` Ander Conselvan De Oliveira
2016-11-14 14:25 ` [PATCH v3] drm/i915/glk: Introduce Geminilake platform definition Ander Conselvan de Oliveira
1 sibling, 1 reply; 52+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-11-14 14:24 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
v2: Add new 0x3185 ID. (Joonas)
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include/drm/i915_pciids.h | 4 ++++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 2c9645f..e03f558 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -436,6 +436,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
INTEL_BXT_IDS(&intel_broxton_info),
+ INTEL_GLK_IDS(&intel_geminilake_info),
INTEL_KBL_GT1_IDS(&intel_kabylake_info),
INTEL_KBL_GT2_IDS(&intel_kabylake_info),
INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 0d5f426..540be9f 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -292,6 +292,10 @@
INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */
+#define INTEL_GLK_IDS(info) \
+ INTEL_VGA_DEVICE(0x3184, info), \
+ INTEL_VGA_DEVICE(0x3185, info)
+
#define INTEL_KBL_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
--
2.5.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH v2 01/13] drm/i915/glk: Add Geminilake PCI IDs
2016-11-14 14:24 ` [PATCH v2 01/13] drm/i915/glk: Add Geminilake PCI IDs Ander Conselvan de Oliveira
@ 2016-11-14 14:29 ` Ander Conselvan De Oliveira
0 siblings, 0 replies; 52+ messages in thread
From: Ander Conselvan De Oliveira @ 2016-11-14 14:29 UTC (permalink / raw)
To: intel-gfx
I forgot to pass -1 to git send-email, that's why this patch ended up here.
Please ignore.
On Mon, 2016-11-14 at 16:24 +0200, Ander Conselvan de Oliveira wrote:
> v2: Add new 0x3185 ID. (Joonas)
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.
> com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> include/drm/i915_pciids.h | 4 ++++
> 2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 2c9645f..e03f558 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -436,6 +436,7 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
> INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
> INTEL_BXT_IDS(&intel_broxton_info),
> + INTEL_GLK_IDS(&intel_geminilake_info),
> INTEL_KBL_GT1_IDS(&intel_kabylake_info),
> INTEL_KBL_GT2_IDS(&intel_kabylake_info),
> INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 0d5f426..540be9f 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -292,6 +292,10 @@
> INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
> INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */
>
> +#define INTEL_GLK_IDS(info) \
> + INTEL_VGA_DEVICE(0x3184, info), \
> + INTEL_VGA_DEVICE(0x3185, info)
> +
> #define INTEL_KBL_GT1_IDS(info) \
> INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
> INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v3] drm/i915/glk: Introduce Geminilake platform definition
2016-11-10 23:18 ` Matt Roper
2016-11-14 14:24 ` [PATCH v2 01/13] drm/i915/glk: Add Geminilake PCI IDs Ander Conselvan de Oliveira
@ 2016-11-14 14:25 ` Ander Conselvan de Oliveira
1 sibling, 0 replies; 52+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-11-14 14:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
Geminilake is an Intel® Processor containing Intel® HD Graphics
following Broxton.
Let's start by adding the platform definition. PCI IDs and plaform
specific code will follow.
v2: Rebase (don't allow dev to be used with the new macro).
v3: Update ddb size. (Matt)
Rebase on s/preliminary_hw/alpha/
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 7 +++++++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c4a14de..29a2d2a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -654,6 +654,7 @@ struct intel_csr {
func(is_broadwell); \
func(is_skylake); \
func(is_broxton); \
+ func(is_geminilake); \
func(is_kabylake); \
func(is_alpha_support); \
/* Keep has_* in alphabetical order */ \
@@ -2432,6 +2433,7 @@ struct drm_i915_cmd_table {
#define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
#define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
#define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
+#define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.is_geminilake)
#define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
#define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f8b93c1..2c9645f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -372,6 +372,13 @@ static const struct intel_device_info intel_broxton_info = {
.ddb_size = 512,
};
+static const struct intel_device_info intel_geminilake_info = {
+ .is_alpha_support = 1,
+ .is_geminilake = 1,
+ GEN9_LP_FEATURES,
+ .ddb_size = 1024,
+};
+
static const struct intel_device_info intel_kabylake_info = {
BDW_FEATURES,
.is_kabylake = 1,
--
2.5.5
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH 03/15] drm/i915/glk: Add Geminilake PCI IDs
2016-11-10 15:23 [PATCH 00/15] Geminilake enabling Ander Conselvan de Oliveira
2016-11-10 15:23 ` [PATCH 01/15] drm/i915: Create a common GEN9_LP_FEATURE Ander Conselvan de Oliveira
2016-11-10 15:23 ` [PATCH 02/15] drm/i915/glk: Introduce Geminilake platform definition Ander Conselvan de Oliveira
@ 2016-11-10 15:23 ` Ander Conselvan de Oliveira
2016-11-10 17:03 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 04/15] drm/i915/glk: Add a IS_GEN9_LP() macro Ander Conselvan de Oliveira
` (16 subsequent siblings)
19 siblings, 1 reply; 52+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-11-10 15:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
v2: Add new 0x3185 ID. (Joonas)
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include/drm/i915_pciids.h | 4 ++++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index dc2ba3f..1b188e1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -435,6 +435,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
INTEL_BXT_IDS(&intel_broxton_info),
+ INTEL_GLK_IDS(&intel_geminilake_info),
INTEL_KBL_GT1_IDS(&intel_kabylake_info),
INTEL_KBL_GT2_IDS(&intel_kabylake_info),
INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 0d5f426..540be9f 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -292,6 +292,10 @@
INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */
+#define INTEL_GLK_IDS(info) \
+ INTEL_VGA_DEVICE(0x3184, info), \
+ INTEL_VGA_DEVICE(0x3185, info)
+
#define INTEL_KBL_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
--
2.5.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 03/15] drm/i915/glk: Add Geminilake PCI IDs
2016-11-10 15:23 ` [PATCH 03/15] drm/i915/glk: Add Geminilake PCI IDs Ander Conselvan de Oliveira
@ 2016-11-10 17:03 ` Rodrigo Vivi
0 siblings, 0 replies; 52+ messages in thread
From: Rodrigo Vivi @ 2016-11-10 17:03 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
On Thu, Nov 10, 2016 at 05:23:08PM +0200, Ander Conselvan de Oliveira wrote:
> v2: Add new 0x3185 ID. (Joonas)
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> include/drm/i915_pciids.h | 4 ++++
> 2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index dc2ba3f..1b188e1 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -435,6 +435,7 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
> INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
> INTEL_BXT_IDS(&intel_broxton_info),
> + INTEL_GLK_IDS(&intel_geminilake_info),
> INTEL_KBL_GT1_IDS(&intel_kabylake_info),
> INTEL_KBL_GT2_IDS(&intel_kabylake_info),
> INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 0d5f426..540be9f 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -292,6 +292,10 @@
> INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
> INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */
>
> +#define INTEL_GLK_IDS(info) \
> + INTEL_VGA_DEVICE(0x3184, info), \
> + INTEL_VGA_DEVICE(0x3185, info)
> +
> #define INTEL_KBL_GT1_IDS(info) \
> INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
> INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
> --
> 2.5.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 04/15] drm/i915/glk: Add a IS_GEN9_LP() macro
2016-11-10 15:23 [PATCH 00/15] Geminilake enabling Ander Conselvan de Oliveira
` (2 preceding siblings ...)
2016-11-10 15:23 ` [PATCH 03/15] drm/i915/glk: Add Geminilake PCI IDs Ander Conselvan de Oliveira
@ 2016-11-10 15:23 ` Ander Conselvan de Oliveira
2016-11-10 15:23 ` [PATCH 05/15] drm/i915/glk: Reuse broxton code for geminilake Ander Conselvan de Oliveira
` (15 subsequent siblings)
19 siblings, 0 replies; 52+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-11-10 15:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
Broxton and Geminilake are both gen9lp platforms. To avoid adding
IS_GEMINILAKE() checks everywhere alongside the IS_BROXTON() ones, add a
IS_GEN9_LP() macro.
v2: Rename macro parameter to dev_priv. (Joonas)
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/i915_pci.c | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8a99e6e..4bb745a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -669,6 +669,7 @@ struct intel_csr {
func(is_broxton); \
func(is_geminilake); \
func(is_kabylake); \
+ func(is_lp); \
func(is_preliminary); \
/* Keep has_* in alphabetical order */ \
func(has_64bit_reloc); \
@@ -2844,6 +2845,8 @@ struct drm_i915_cmd_table {
#define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
#define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
+#define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && INTEL_INFO(dev_priv)->is_lp)
+
#define ENGINE_MASK(id) BIT(id)
#define RENDER_RING ENGINE_MASK(RCS)
#define BSD_RING ENGINE_MASK(VCS)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 1b188e1..3801f8b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -345,6 +345,7 @@ static const struct intel_device_info intel_skylake_gt3_info = {
#define GEN9_LP_FEATURES \
.gen = 9, \
+ .is_lp = 1, \
.has_hotplug = 1, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
.num_pipes = 3, \
--
2.5.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 05/15] drm/i915/glk: Reuse broxton code for geminilake
2016-11-10 15:23 [PATCH 00/15] Geminilake enabling Ander Conselvan de Oliveira
` (3 preceding siblings ...)
2016-11-10 15:23 ` [PATCH 04/15] drm/i915/glk: Add a IS_GEN9_LP() macro Ander Conselvan de Oliveira
@ 2016-11-10 15:23 ` Ander Conselvan de Oliveira
2016-11-10 17:08 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 06/15] drm/i915/glk: Force DDI initialization Ander Conselvan de Oliveira
` (14 subsequent siblings)
19 siblings, 1 reply; 52+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-11-10 15:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
Geminilake is mostly backwards compatible with broxton, so change most
of the IS_BROXTON() checks to IS_GEN9_LP(). Differences between the
platforms will be implemented in follow-up patches.
v2: Don't reuse broxton's path in intel_update_max_cdclk().
Don't set plane count as in broxton.
v3: Rebase
v4: Include the check intel_bios_is_port_hpd_inverted().
Commit message.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 ++++++------
drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++----
drivers/gpu/drm/i915/i915_irq.c | 10 +++++-----
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
drivers/gpu/drm/i915/intel_bios.c | 2 +-
drivers/gpu/drm/i915/intel_ddi.c | 10 +++++-----
drivers/gpu/drm/i915/intel_display.c | 8 ++++----
drivers/gpu/drm/i915/intel_dp.c | 20 ++++++++++----------
drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
drivers/gpu/drm/i915/intel_dsi.c | 28 ++++++++++++++--------------
drivers/gpu/drm/i915/intel_dsi_pll.c | 12 ++++++------
drivers/gpu/drm/i915/intel_hdmi.c | 6 +++---
drivers/gpu/drm/i915/intel_i2c.c | 4 ++--
drivers/gpu/drm/i915/intel_mocs.c | 2 +-
drivers/gpu/drm/i915/intel_panel.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 6 +++---
drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
17 files changed, 71 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index c9465fb..c190195 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1128,7 +1128,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
int max_freq;
rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
} else {
@@ -1224,7 +1224,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
seq_printf(m, "Down threshold: %d%%\n",
dev_priv->rps.down_threshold);
- max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
+ max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
rp_state_cap >> 16) & 0xff;
max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
GEN9_FREQ_SCALER : 1);
@@ -1237,7 +1237,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
intel_gpu_freq(dev_priv, max_freq));
- max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
+ max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
rp_state_cap >> 0) & 0xff;
max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
GEN9_FREQ_SCALER : 1);
@@ -2789,7 +2789,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
I915_READ(SKL_CSR_DC3_DC5_COUNT));
seq_printf(m, "DC5 -> DC6 count: %d\n",
I915_READ(SKL_CSR_DC5_DC6_COUNT));
- } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
+ } else if (IS_GEN9_LP(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
seq_printf(m, "DC3 -> DC5 count: %d\n",
I915_READ(BXT_CSR_DC3_DC5_COUNT));
}
@@ -5185,7 +5185,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
/* BXT has a single slice and at most 3 subslices. */
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
s_max = 1;
ss_max = 3;
}
@@ -5219,7 +5219,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
for (ss = 0; ss < ss_max; ss++) {
unsigned int eu_cnt;
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
/* skip disabled subslice */
continue;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 7531bca..9132f9e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -377,7 +377,7 @@ static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr)
/* There are only few exceptions for gen >=6. chv and bxt.
* And we are not sure about the latter so play safe for now.
*/
- if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
+ if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
drm_clflush_virt_range(vaddr, PAGE_SIZE);
kunmap_atomic(vaddr);
@@ -2946,7 +2946,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
* resort to an uncached mapping. The WC issue is easily caught by the
* readback check when writing GTT PTE entries.
*/
- if (IS_BROXTON(to_i915(ggtt->base.dev)))
+ if (IS_GEN9_LP(to_i915(ggtt->base.dev)))
ggtt->gsm = ioremap_nocache(phys_addr, size);
else
ggtt->gsm = ioremap_wc(phys_addr, size);
@@ -3078,7 +3078,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
- if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
+ if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
chv_setup_private_ppat(dev_priv);
else
bdw_setup_private_ppat(dev_priv);
@@ -3319,7 +3319,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
ggtt->base.closed = false;
if (INTEL_INFO(dev)->gen >= 8) {
- if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
+ if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
chv_setup_private_ppat(dev_priv);
else
bdw_setup_private_ppat(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6d7505b..081b3b7 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2435,7 +2435,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
found = true;
}
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
if (tmp_mask) {
bxt_hpd_irq_handler(dev_priv, tmp_mask,
@@ -2451,7 +2451,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
}
}
- if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
+ if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
gmbus_irq_handler(dev_priv);
found = true;
}
@@ -3379,7 +3379,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
GEN9_AUX_CHANNEL_D;
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
de_port_masked |= BXT_DE_PORT_GMBUS;
} else {
de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
@@ -3390,7 +3390,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
GEN8_PIPE_FIFO_UNDERRUN;
de_port_enables = de_port_masked;
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
else if (IS_BROADWELL(dev_priv))
de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
@@ -4215,7 +4215,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
dev->driver->irq_uninstall = gen8_irq_uninstall;
dev->driver->enable_vblank = gen8_enable_vblank;
dev->driver->disable_vblank = gen8_disable_vblank;
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3361d7f..1be2a7d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2920,7 +2920,7 @@ enum skl_disp_power_wells {
#define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
#define INTERVAL_0_833_US(us) (((us) * 6) / 5)
#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
- (IS_BROXTON(dev_priv) ? \
+ (IS_GEN9_LP(dev_priv) ? \
INTERVAL_0_833_US(us) : \
INTERVAL_1_33_US(us)) : \
INTERVAL_1_28_US(us))
@@ -2929,7 +2929,7 @@ enum skl_disp_power_wells {
#define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3)
#define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6)
#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN9(dev_priv) ? \
- (IS_BROXTON(dev_priv) ? \
+ (IS_GEN9_LP(dev_priv) ? \
INTERVAL_0_833_TO_US(interval) : \
INTERVAL_1_33_TO_US(interval)) : \
INTERVAL_1_28_TO_US(interval))
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 5ab646e..bd705f9 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1765,7 +1765,7 @@ intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
{
int i;
- if (WARN_ON_ONCE(!IS_BROXTON(dev_priv)))
+ if (WARN_ON_ONCE(!IS_GEN9_LP(dev_priv)))
return false;
for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 938ac4d..dcad209 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -442,7 +442,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
return hdmi_level;
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
@@ -1091,7 +1091,7 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
hsw_ddi_clock_get(encoder, pipe_config);
else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
skl_ddi_clock_get(encoder, pipe_config);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
bxt_ddi_clock_get(encoder, pipe_config);
}
@@ -1153,7 +1153,7 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
return skl_ddi_pll_select(intel_crtc, crtc_state,
intel_encoder);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
return bxt_ddi_pll_select(intel_crtc, crtc_state,
intel_encoder);
else
@@ -1643,7 +1643,7 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
skl_ddi_set_iboost(encoder, level);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
return DDI_BUF_TRANS_SELECT(level);
@@ -2246,7 +2246,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
* configuration so that we use the proper lane count for our
* calculations.
*/
- if (IS_BROXTON(dev_priv) && port == PORT_A) {
+ if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 92ab01f..c6ffe0a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -614,12 +614,12 @@ static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
INTELPllInvalid("m1 out of range\n");
if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
- !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
+ !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
if (clock->m1 <= clock->m2)
INTELPllInvalid("m1 <= m2\n");
if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
- !IS_BROXTON(dev_priv)) {
+ !IS_GEN9_LP(dev_priv)) {
if (clock->p < limit->p.min || limit->p.max < clock->p)
INTELPllInvalid("p out of range\n");
if (clock->m < limit->m.min || limit->m.max < clock->m)
@@ -10679,7 +10679,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
skylake_get_ddi_pll(dev_priv, port, pipe_config);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
bxt_get_ddi_pll(dev_priv, port, pipe_config);
else
haswell_get_ddi_pll(dev_priv, port, pipe_config);
@@ -10725,7 +10725,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
- if (IS_BROXTON(dev_priv) &&
+ if (IS_GEN9_LP(dev_priv) &&
bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
WARN_ON(active);
active = true;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9df331b..71e5f3d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -233,7 +233,7 @@ intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
int size;
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
*source_rates = bxt_rates;
size = ARRAY_SIZE(bxt_rates);
} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
@@ -688,7 +688,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
memset(regs, 0, sizeof(*regs));
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
pps_idx = bxt_power_sequencer_idx(intel_dp);
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
pps_idx = vlv_power_sequencer_pipe(intel_dp);
@@ -697,7 +697,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
regs->pp_stat = PP_STATUS(pps_idx);
regs->pp_on = PP_ON_DELAYS(pps_idx);
regs->pp_off = PP_OFF_DELAYS(pps_idx);
- if (!IS_BROXTON(dev_priv))
+ if (!IS_GEN9_LP(dev_priv))
regs->pp_div = PP_DIVISOR(pps_idx);
}
@@ -2983,7 +2983,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = to_i915(dev);
enum port port = dp_to_dig_port(intel_dp)->port;
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
else if (INTEL_INFO(dev)->gen >= 9) {
if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
@@ -4299,7 +4299,7 @@ static bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
return ibx_digital_port_connected(dev_priv, port);
else if (HAS_PCH_SPLIT(dev_priv))
return cpt_digital_port_connected(dev_priv, port);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
return bxt_digital_port_connected(dev_priv, port);
else if (IS_GM45(dev_priv))
return gm45_digital_port_connected(dev_priv, port);
@@ -4931,7 +4931,7 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
pp_on = I915_READ(regs.pp_on);
pp_off = I915_READ(regs.pp_off);
- if (!IS_BROXTON(dev_priv)) {
+ if (!IS_GEN9_LP(dev_priv)) {
I915_WRITE(regs.pp_ctrl, pp_ctl);
pp_div = I915_READ(regs.pp_div);
}
@@ -4949,7 +4949,7 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
PANEL_POWER_DOWN_DELAY_SHIFT;
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
BXT_POWER_CYCLE_DELAY_SHIFT;
if (tmp > 0)
@@ -5080,7 +5080,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
(seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
/* Compute the divisor for the pp clock, simply match the Bspec
* formula. */
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
pp_div = I915_READ(regs.pp_ctrl);
pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
@@ -5106,7 +5106,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
I915_WRITE(regs.pp_on, pp_on);
I915_WRITE(regs.pp_off, pp_off);
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
I915_WRITE(regs.pp_ctrl, pp_div);
else
I915_WRITE(regs.pp_div, pp_div);
@@ -5114,7 +5114,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
I915_READ(regs.pp_on),
I915_READ(regs.pp_off),
- IS_BROXTON(dev_priv) ?
+ IS_GEN9_LP(dev_priv) ?
(I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
I915_READ(regs.pp_div));
}
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 21853a1..8205c1c 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1861,7 +1861,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
dpll_mgr = &skl_pll_mgr;
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
dpll_mgr = &bxt_pll_mgr;
else if (HAS_DDI(dev_priv))
dpll_mgr = &hsw_pll_mgr;
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 4e0d025..4e19fbc 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -340,7 +340,7 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
/* DSI uses short packets for sync events, so clear mode flags for DSI */
adjusted_mode->flags = 0;
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
/* Dual link goes to DSI transcoder A. */
if (intel_dsi->ports == BIT(PORT_C))
pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
@@ -441,7 +441,7 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_dsi_device_ready(encoder);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
bxt_dsi_device_ready(encoder);
}
@@ -464,7 +464,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
}
for_each_dsi_port(port, intel_dsi->ports) {
- i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
+ i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
u32 temp;
@@ -494,7 +494,7 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
enum port port;
for_each_dsi_port(port, intel_dsi->ports) {
- i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
+ i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
u32 temp;
@@ -663,7 +663,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
DRM_DEBUG_KMS("\n");
for_each_dsi_port(port, intel_dsi->ports) {
/* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
- i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
+ i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
u32 val;
@@ -755,12 +755,12 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
* configuration, otherwise accessing DSI registers will hang the
* machine. See BSpec North Display Engine registers/MIPI[BXT].
*/
- if (IS_BROXTON(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
+ if (IS_GEN9_LP(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
goto out_put_power;
/* XXX: this only works for one DSI output */
for_each_dsi_port(port, intel_dsi->ports) {
- i915_reg_t ctrl_reg = IS_BROXTON(dev_priv) ?
+ i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
@@ -785,7 +785,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
continue;
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
u32 tmp = I915_READ(MIPI_CTRL(port));
tmp &= BXT_PIPE_SELECT_MASK;
tmp >>= BXT_PIPE_SELECT_SHIFT;
@@ -973,7 +973,7 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
u32 pclk;
DRM_DEBUG_KMS("\n");
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
bxt_dsi_get_pipe_config(encoder, pipe_config);
pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
@@ -1065,7 +1065,7 @@ static void set_dsi_timings(struct drm_encoder *encoder,
hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
for_each_dsi_port(port, intel_dsi->ports) {
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
/*
* Program hdisplay and vdisplay on MIPI transcoder.
* This is different from calculated hactive and
@@ -1152,7 +1152,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
tmp &= ~READ_REQUEST_PRIORITY_MASK;
I915_WRITE(MIPI_CTRL(port), tmp |
READ_REQUEST_PRIORITY_HIGH);
- } else if (IS_BROXTON(dev_priv)) {
+ } else if (IS_GEN9_LP(dev_priv)) {
enum pipe pipe = intel_crtc->pipe;
tmp = I915_READ(MIPI_CTRL(port));
@@ -1241,7 +1241,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
I915_WRITE(MIPI_INIT_COUNT(port),
txclkesc(intel_dsi->escape_clk_div, 100));
- if (IS_BROXTON(dev_priv) && (!intel_dsi->dual_link)) {
+ if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
/*
* BXT spec says write MIPI_INIT_COUNT for
* both the ports, even if only one is
@@ -1451,7 +1451,7 @@ void intel_dsi_init(struct drm_device *dev)
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
- } else if (IS_BROXTON(dev_priv)) {
+ } else if (IS_GEN9_LP(dev_priv)) {
dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
} else {
DRM_ERROR("Unsupported Mipi device to reg base");
@@ -1492,7 +1492,7 @@ void intel_dsi_init(struct drm_device *dev)
* On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
* port C. BXT isn't limited like this.
*/
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
else if (port == PORT_A)
intel_encoder->crtc_mask = BIT(PIPE_A);
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 56eff60..cf8c1b0 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -351,7 +351,7 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
struct intel_crtc_state *config)
{
- if (IS_BROXTON(to_i915(encoder->base.dev)))
+ if (IS_GEN9_LP(to_i915(encoder->base.dev)))
return bxt_dsi_get_pclk(encoder, pipe_bpp, config);
else
return vlv_dsi_get_pclk(encoder, pipe_bpp, config);
@@ -504,7 +504,7 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
{
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
return bxt_dsi_pll_is_enabled(dev_priv);
MISSING_CASE(INTEL_DEVID(dev_priv));
@@ -519,7 +519,7 @@ int intel_compute_dsi_pll(struct intel_encoder *encoder,
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return vlv_compute_dsi_pll(encoder, config);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
return bxt_compute_dsi_pll(encoder, config);
return -ENODEV;
@@ -532,7 +532,7 @@ void intel_enable_dsi_pll(struct intel_encoder *encoder,
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_enable_dsi_pll(encoder, config);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
bxt_enable_dsi_pll(encoder, config);
}
@@ -542,7 +542,7 @@ void intel_disable_dsi_pll(struct intel_encoder *encoder)
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_disable_dsi_pll(encoder);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
bxt_disable_dsi_pll(encoder);
}
@@ -566,7 +566,7 @@ void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
bxt_dsi_reset_clocks(encoder, port);
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_dsi_reset_clocks(encoder, port);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 35ada4e..6e385a1 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1249,7 +1249,7 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
return MODE_CLOCK_HIGH;
/* BXT DPLL can't generate 223-240 MHz */
- if (IS_BROXTON(dev_priv) && clock > 223333 && clock < 240000)
+ if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
return MODE_CLOCK_RANGE;
/* CHV DPLL can't generate 216-240 MHz */
@@ -1815,13 +1815,13 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
switch (port) {
case PORT_B:
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
ddc_pin = GMBUS_PIN_1_BXT;
else
ddc_pin = GMBUS_PIN_DPB;
break;
case PORT_C:
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
ddc_pin = GMBUS_PIN_2_BXT;
else
ddc_pin = GMBUS_PIN_DPC;
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 83f260b..1606e31 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -72,7 +72,7 @@ static const struct gmbus_pin gmbus_pins_bxt[] = {
static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
unsigned int pin)
{
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
return &gmbus_pins_bxt[pin];
else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
return &gmbus_pins_skl[pin];
@@ -87,7 +87,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
{
unsigned int size;
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
size = ARRAY_SIZE(gmbus_pins_bxt);
else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
size = ARRAY_SIZE(gmbus_pins_skl);
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 80bb924..eed0707 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -182,7 +182,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
table->size = ARRAY_SIZE(skylake_mocs_table);
table->table = skylake_mocs_table;
result = true;
- } else if (IS_BROXTON(dev_priv)) {
+ } else if (IS_GEN9_LP(dev_priv)) {
table->size = ARRAY_SIZE(broxton_mocs_table);
table->table = broxton_mocs_table;
result = true;
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index be4b4d5..bf2899d 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1756,7 +1756,7 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
intel_dsi_dcs_init_backlight_funcs(connector) == 0)
return;
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
panel->backlight.setup = bxt_setup_backlight;
panel->backlight.enable = bxt_enable_backlight;
panel->backlight.disable = bxt_disable_backlight;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 88e28c9..325fd3f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5232,7 +5232,7 @@ int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
if (!enable_rc6)
return 0;
- if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
DRM_INFO("RC6 disabled by BIOS\n");
return 0;
}
@@ -5266,7 +5266,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
/* All of these values are in units of 50MHz */
/* static values from HW: RP0 > RP1 > RPn (min_freq) */
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
@@ -7646,7 +7646,7 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
dev_priv->display.init_clock_gating = skylake_init_clock_gating;
else if (IS_KABYLAKE(dev_priv))
dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
dev_priv->display.init_clock_gating = bxt_init_clock_gating;
else if (IS_BROADWELL(dev_priv))
dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 0599408..697574f 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -530,7 +530,7 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
u32 mask;
mask = DC_STATE_EN_UPTO_DC5;
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
mask |= DC_STATE_EN_DC9;
else
mask |= DC_STATE_EN_UPTO_DC6;
@@ -911,7 +911,7 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
gen9_assert_dbuf_enabled(dev_priv);
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
bxt_verify_ddi_phy_power_wells(dev_priv);
}
@@ -2170,7 +2170,7 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
max_dc = 2;
mask = 0;
- } else if (IS_BROXTON(dev_priv)) {
+ } else if (IS_GEN9_LP(dev_priv)) {
max_dc = 1;
/*
* DC9 has a separate HW flow from the rest of the DC states,
--
2.5.5
_______________________________________________
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^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 05/15] drm/i915/glk: Reuse broxton code for geminilake
2016-11-10 15:23 ` [PATCH 05/15] drm/i915/glk: Reuse broxton code for geminilake Ander Conselvan de Oliveira
@ 2016-11-10 17:08 ` Rodrigo Vivi
2016-11-11 13:52 ` [PATCH v2] " Ander Conselvan de Oliveira
0 siblings, 1 reply; 52+ messages in thread
From: Rodrigo Vivi @ 2016-11-10 17:08 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
On Thu, Nov 10, 2016 at 05:23:10PM +0200, Ander Conselvan de Oliveira wrote:
> Geminilake is mostly backwards compatible with broxton, so change most
> of the IS_BROXTON() checks to IS_GEN9_LP(). Differences between the
> platforms will be implemented in follow-up patches.
>
> v2: Don't reuse broxton's path in intel_update_max_cdclk().
> Don't set plane count as in broxton.
>
> v3: Rebase
>
> v4: Include the check intel_bios_is_port_hpd_inverted().
> Commit message.
>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 12 ++++++------
> drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++----
> drivers/gpu/drm/i915/i915_irq.c | 10 +++++-----
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> drivers/gpu/drm/i915/intel_bios.c | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c | 10 +++++-----
> drivers/gpu/drm/i915/intel_display.c | 8 ++++----
> drivers/gpu/drm/i915/intel_dp.c | 20 ++++++++++----------
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
> drivers/gpu/drm/i915/intel_dsi.c | 28 ++++++++++++++--------------
> drivers/gpu/drm/i915/intel_dsi_pll.c | 12 ++++++------
> drivers/gpu/drm/i915/intel_hdmi.c | 6 +++---
> drivers/gpu/drm/i915/intel_i2c.c | 4 ++--
> drivers/gpu/drm/i915/intel_mocs.c | 2 +-
> drivers/gpu/drm/i915/intel_panel.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 6 +++---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
> 17 files changed, 71 insertions(+), 71 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index c9465fb..c190195 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1128,7 +1128,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> int max_freq;
>
> rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
> gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
> } else {
> @@ -1224,7 +1224,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> seq_printf(m, "Down threshold: %d%%\n",
> dev_priv->rps.down_threshold);
>
> - max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
> + max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
> rp_state_cap >> 16) & 0xff;
> max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
> GEN9_FREQ_SCALER : 1);
> @@ -1237,7 +1237,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
> intel_gpu_freq(dev_priv, max_freq));
>
> - max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
> + max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
> rp_state_cap >> 0) & 0xff;
> max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
> GEN9_FREQ_SCALER : 1);
> @@ -2789,7 +2789,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> I915_READ(SKL_CSR_DC3_DC5_COUNT));
> seq_printf(m, "DC5 -> DC6 count: %d\n",
> I915_READ(SKL_CSR_DC5_DC6_COUNT));
> - } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
> + } else if (IS_GEN9_LP(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
glk DMC is version 1,1. But anyway tests here shows this register is always zero even
on cases we are sure that DC5 is really working. So better to leave without it for now while we don't know what register address shows the counter on GLK.
> seq_printf(m, "DC3 -> DC5 count: %d\n",
> I915_READ(BXT_CSR_DC3_DC5_COUNT));
> }
> @@ -5185,7 +5185,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
>
> /* BXT has a single slice and at most 3 subslices. */
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> s_max = 1;
> ss_max = 3;
> }
> @@ -5219,7 +5219,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> for (ss = 0; ss < ss_max; ss++) {
> unsigned int eu_cnt;
>
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> /* skip disabled subslice */
> continue;
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 7531bca..9132f9e 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -377,7 +377,7 @@ static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr)
> /* There are only few exceptions for gen >=6. chv and bxt.
> * And we are not sure about the latter so play safe for now.
> */
> - if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> + if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
> drm_clflush_virt_range(vaddr, PAGE_SIZE);
>
> kunmap_atomic(vaddr);
> @@ -2946,7 +2946,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
> * resort to an uncached mapping. The WC issue is easily caught by the
> * readback check when writing GTT PTE entries.
> */
> - if (IS_BROXTON(to_i915(ggtt->base.dev)))
> + if (IS_GEN9_LP(to_i915(ggtt->base.dev)))
> ggtt->gsm = ioremap_nocache(phys_addr, size);
> else
> ggtt->gsm = ioremap_wc(phys_addr, size);
> @@ -3078,7 +3078,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
>
> ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
>
> - if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> + if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
> chv_setup_private_ppat(dev_priv);
> else
> bdw_setup_private_ppat(dev_priv);
> @@ -3319,7 +3319,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
> ggtt->base.closed = false;
>
> if (INTEL_INFO(dev)->gen >= 8) {
> - if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> + if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
> chv_setup_private_ppat(dev_priv);
> else
> bdw_setup_private_ppat(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 6d7505b..081b3b7 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2435,7 +2435,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> found = true;
> }
>
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
> if (tmp_mask) {
> bxt_hpd_irq_handler(dev_priv, tmp_mask,
> @@ -2451,7 +2451,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> }
> }
>
> - if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
> + if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
> gmbus_irq_handler(dev_priv);
> found = true;
> }
> @@ -3379,7 +3379,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
> de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
> GEN9_AUX_CHANNEL_D;
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> de_port_masked |= BXT_DE_PORT_GMBUS;
> } else {
> de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
> @@ -3390,7 +3390,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> GEN8_PIPE_FIFO_UNDERRUN;
>
> de_port_enables = de_port_masked;
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
> else if (IS_BROADWELL(dev_priv))
> de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
> @@ -4215,7 +4215,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> dev->driver->irq_uninstall = gen8_irq_uninstall;
> dev->driver->enable_vblank = gen8_enable_vblank;
> dev->driver->disable_vblank = gen8_disable_vblank;
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
> else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
> dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3361d7f..1be2a7d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2920,7 +2920,7 @@ enum skl_disp_power_wells {
> #define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
> #define INTERVAL_0_833_US(us) (((us) * 6) / 5)
> #define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
> - (IS_BROXTON(dev_priv) ? \
> + (IS_GEN9_LP(dev_priv) ? \
> INTERVAL_0_833_US(us) : \
> INTERVAL_1_33_US(us)) : \
> INTERVAL_1_28_US(us))
> @@ -2929,7 +2929,7 @@ enum skl_disp_power_wells {
> #define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3)
> #define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6)
> #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN9(dev_priv) ? \
> - (IS_BROXTON(dev_priv) ? \
> + (IS_GEN9_LP(dev_priv) ? \
> INTERVAL_0_833_TO_US(interval) : \
> INTERVAL_1_33_TO_US(interval)) : \
> INTERVAL_1_28_TO_US(interval))
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 5ab646e..bd705f9 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -1765,7 +1765,7 @@ intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
> {
> int i;
>
> - if (WARN_ON_ONCE(!IS_BROXTON(dev_priv)))
> + if (WARN_ON_ONCE(!IS_GEN9_LP(dev_priv)))
> return false;
>
> for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 938ac4d..dcad209 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -442,7 +442,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
>
> hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
>
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> return hdmi_level;
>
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> @@ -1091,7 +1091,7 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
> hsw_ddi_clock_get(encoder, pipe_config);
> else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> skl_ddi_clock_get(encoder, pipe_config);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> bxt_ddi_clock_get(encoder, pipe_config);
> }
>
> @@ -1153,7 +1153,7 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> return skl_ddi_pll_select(intel_crtc, crtc_state,
> intel_encoder);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> return bxt_ddi_pll_select(intel_crtc, crtc_state,
> intel_encoder);
> else
> @@ -1643,7 +1643,7 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
>
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> skl_ddi_set_iboost(encoder, level);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
>
> return DDI_BUF_TRANS_SELECT(level);
> @@ -2246,7 +2246,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
> * configuration so that we use the proper lane count for our
> * calculations.
> */
> - if (IS_BROXTON(dev_priv) && port == PORT_A) {
> + if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
> if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
> DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
> intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 92ab01f..c6ffe0a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -614,12 +614,12 @@ static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
> INTELPllInvalid("m1 out of range\n");
>
> if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
> - !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
> + !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
> if (clock->m1 <= clock->m2)
> INTELPllInvalid("m1 <= m2\n");
>
> if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> - !IS_BROXTON(dev_priv)) {
> + !IS_GEN9_LP(dev_priv)) {
> if (clock->p < limit->p.min || limit->p.max < clock->p)
> INTELPllInvalid("p out of range\n");
> if (clock->m < limit->m.min || limit->m.max < clock->m)
> @@ -10679,7 +10679,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
>
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> skylake_get_ddi_pll(dev_priv, port, pipe_config);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> bxt_get_ddi_pll(dev_priv, port, pipe_config);
> else
> haswell_get_ddi_pll(dev_priv, port, pipe_config);
> @@ -10725,7 +10725,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
>
> active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
>
> - if (IS_BROXTON(dev_priv) &&
> + if (IS_GEN9_LP(dev_priv) &&
> bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
> WARN_ON(active);
> active = true;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 9df331b..71e5f3d 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -233,7 +233,7 @@ intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
> struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> int size;
>
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> *source_rates = bxt_rates;
> size = ARRAY_SIZE(bxt_rates);
> } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> @@ -688,7 +688,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
>
> memset(regs, 0, sizeof(*regs));
>
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> pps_idx = bxt_power_sequencer_idx(intel_dp);
> else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> pps_idx = vlv_power_sequencer_pipe(intel_dp);
> @@ -697,7 +697,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
> regs->pp_stat = PP_STATUS(pps_idx);
> regs->pp_on = PP_ON_DELAYS(pps_idx);
> regs->pp_off = PP_OFF_DELAYS(pps_idx);
> - if (!IS_BROXTON(dev_priv))
> + if (!IS_GEN9_LP(dev_priv))
> regs->pp_div = PP_DIVISOR(pps_idx);
> }
>
> @@ -2983,7 +2983,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
> struct drm_i915_private *dev_priv = to_i915(dev);
> enum port port = dp_to_dig_port(intel_dp)->port;
>
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> else if (INTEL_INFO(dev)->gen >= 9) {
> if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
> @@ -4299,7 +4299,7 @@ static bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
> return ibx_digital_port_connected(dev_priv, port);
> else if (HAS_PCH_SPLIT(dev_priv))
> return cpt_digital_port_connected(dev_priv, port);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> return bxt_digital_port_connected(dev_priv, port);
> else if (IS_GM45(dev_priv))
> return gm45_digital_port_connected(dev_priv, port);
> @@ -4931,7 +4931,7 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
>
> pp_on = I915_READ(regs.pp_on);
> pp_off = I915_READ(regs.pp_off);
> - if (!IS_BROXTON(dev_priv)) {
> + if (!IS_GEN9_LP(dev_priv)) {
> I915_WRITE(regs.pp_ctrl, pp_ctl);
> pp_div = I915_READ(regs.pp_div);
> }
> @@ -4949,7 +4949,7 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
> seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
> PANEL_POWER_DOWN_DELAY_SHIFT;
>
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
> BXT_POWER_CYCLE_DELAY_SHIFT;
> if (tmp > 0)
> @@ -5080,7 +5080,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> /* Compute the divisor for the pp clock, simply match the Bspec
> * formula. */
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> pp_div = I915_READ(regs.pp_ctrl);
> pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
> pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
> @@ -5106,7 +5106,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
>
> I915_WRITE(regs.pp_on, pp_on);
> I915_WRITE(regs.pp_off, pp_off);
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> I915_WRITE(regs.pp_ctrl, pp_div);
> else
> I915_WRITE(regs.pp_div, pp_div);
> @@ -5114,7 +5114,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
> I915_READ(regs.pp_on),
> I915_READ(regs.pp_off),
> - IS_BROXTON(dev_priv) ?
> + IS_GEN9_LP(dev_priv) ?
> (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
> I915_READ(regs.pp_div));
> }
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 21853a1..8205c1c 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1861,7 +1861,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
>
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> dpll_mgr = &skl_pll_mgr;
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> dpll_mgr = &bxt_pll_mgr;
> else if (HAS_DDI(dev_priv))
> dpll_mgr = &hsw_pll_mgr;
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 4e0d025..4e19fbc 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -340,7 +340,7 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
> /* DSI uses short packets for sync events, so clear mode flags for DSI */
> adjusted_mode->flags = 0;
>
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> /* Dual link goes to DSI transcoder A. */
> if (intel_dsi->ports == BIT(PORT_C))
> pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
> @@ -441,7 +441,7 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_dsi_device_ready(encoder);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> bxt_dsi_device_ready(encoder);
> }
>
> @@ -464,7 +464,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
> }
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> + i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> u32 temp;
>
> @@ -494,7 +494,7 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
> enum port port;
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> + i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> u32 temp;
>
> @@ -663,7 +663,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> DRM_DEBUG_KMS("\n");
> for_each_dsi_port(port, intel_dsi->ports) {
> /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
> - i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> + i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
> u32 val;
>
> @@ -755,12 +755,12 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
> * configuration, otherwise accessing DSI registers will hang the
> * machine. See BSpec North Display Engine registers/MIPI[BXT].
> */
> - if (IS_BROXTON(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
> + if (IS_GEN9_LP(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
> goto out_put_power;
>
> /* XXX: this only works for one DSI output */
> for_each_dsi_port(port, intel_dsi->ports) {
> - i915_reg_t ctrl_reg = IS_BROXTON(dev_priv) ?
> + i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
>
> @@ -785,7 +785,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
> if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
> continue;
>
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> u32 tmp = I915_READ(MIPI_CTRL(port));
> tmp &= BXT_PIPE_SELECT_MASK;
> tmp >>= BXT_PIPE_SELECT_SHIFT;
> @@ -973,7 +973,7 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
> u32 pclk;
> DRM_DEBUG_KMS("\n");
>
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> bxt_dsi_get_pipe_config(encoder, pipe_config);
>
> pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
> @@ -1065,7 +1065,7 @@ static void set_dsi_timings(struct drm_encoder *encoder,
> hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> /*
> * Program hdisplay and vdisplay on MIPI transcoder.
> * This is different from calculated hactive and
> @@ -1152,7 +1152,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
> tmp &= ~READ_REQUEST_PRIORITY_MASK;
> I915_WRITE(MIPI_CTRL(port), tmp |
> READ_REQUEST_PRIORITY_HIGH);
> - } else if (IS_BROXTON(dev_priv)) {
> + } else if (IS_GEN9_LP(dev_priv)) {
> enum pipe pipe = intel_crtc->pipe;
>
> tmp = I915_READ(MIPI_CTRL(port));
> @@ -1241,7 +1241,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
> I915_WRITE(MIPI_INIT_COUNT(port),
> txclkesc(intel_dsi->escape_clk_div, 100));
>
> - if (IS_BROXTON(dev_priv) && (!intel_dsi->dual_link)) {
> + if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
> /*
> * BXT spec says write MIPI_INIT_COUNT for
> * both the ports, even if only one is
> @@ -1451,7 +1451,7 @@ void intel_dsi_init(struct drm_device *dev)
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
> - } else if (IS_BROXTON(dev_priv)) {
> + } else if (IS_GEN9_LP(dev_priv)) {
> dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
> } else {
> DRM_ERROR("Unsupported Mipi device to reg base");
> @@ -1492,7 +1492,7 @@ void intel_dsi_init(struct drm_device *dev)
> * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
> * port C. BXT isn't limited like this.
> */
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
> else if (port == PORT_A)
> intel_encoder->crtc_mask = BIT(PIPE_A);
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 56eff60..cf8c1b0 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -351,7 +351,7 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
> u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
> struct intel_crtc_state *config)
> {
> - if (IS_BROXTON(to_i915(encoder->base.dev)))
> + if (IS_GEN9_LP(to_i915(encoder->base.dev)))
> return bxt_dsi_get_pclk(encoder, pipe_bpp, config);
> else
> return vlv_dsi_get_pclk(encoder, pipe_bpp, config);
> @@ -504,7 +504,7 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
>
> bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
> {
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> return bxt_dsi_pll_is_enabled(dev_priv);
>
> MISSING_CASE(INTEL_DEVID(dev_priv));
> @@ -519,7 +519,7 @@ int intel_compute_dsi_pll(struct intel_encoder *encoder,
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> return vlv_compute_dsi_pll(encoder, config);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> return bxt_compute_dsi_pll(encoder, config);
>
> return -ENODEV;
> @@ -532,7 +532,7 @@ void intel_enable_dsi_pll(struct intel_encoder *encoder,
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_enable_dsi_pll(encoder, config);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> bxt_enable_dsi_pll(encoder, config);
> }
>
> @@ -542,7 +542,7 @@ void intel_disable_dsi_pll(struct intel_encoder *encoder)
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_disable_dsi_pll(encoder);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> bxt_disable_dsi_pll(encoder);
> }
>
> @@ -566,7 +566,7 @@ void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> bxt_dsi_reset_clocks(encoder, port);
> else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_dsi_reset_clocks(encoder, port);
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 35ada4e..6e385a1 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1249,7 +1249,7 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
> return MODE_CLOCK_HIGH;
>
> /* BXT DPLL can't generate 223-240 MHz */
> - if (IS_BROXTON(dev_priv) && clock > 223333 && clock < 240000)
> + if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
> return MODE_CLOCK_RANGE;
>
> /* CHV DPLL can't generate 216-240 MHz */
> @@ -1815,13 +1815,13 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
>
> switch (port) {
> case PORT_B:
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> ddc_pin = GMBUS_PIN_1_BXT;
> else
> ddc_pin = GMBUS_PIN_DPB;
> break;
> case PORT_C:
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> ddc_pin = GMBUS_PIN_2_BXT;
> else
> ddc_pin = GMBUS_PIN_DPC;
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index 83f260b..1606e31 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -72,7 +72,7 @@ static const struct gmbus_pin gmbus_pins_bxt[] = {
> static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
> unsigned int pin)
> {
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> return &gmbus_pins_bxt[pin];
> else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> return &gmbus_pins_skl[pin];
> @@ -87,7 +87,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
> {
> unsigned int size;
>
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> size = ARRAY_SIZE(gmbus_pins_bxt);
> else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> size = ARRAY_SIZE(gmbus_pins_skl);
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> index 80bb924..eed0707 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -182,7 +182,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
> table->size = ARRAY_SIZE(skylake_mocs_table);
> table->table = skylake_mocs_table;
> result = true;
> - } else if (IS_BROXTON(dev_priv)) {
> + } else if (IS_GEN9_LP(dev_priv)) {
> table->size = ARRAY_SIZE(broxton_mocs_table);
> table->table = broxton_mocs_table;
> result = true;
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index be4b4d5..bf2899d 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -1756,7 +1756,7 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
> intel_dsi_dcs_init_backlight_funcs(connector) == 0)
> return;
>
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> panel->backlight.setup = bxt_setup_backlight;
> panel->backlight.enable = bxt_enable_backlight;
> panel->backlight.disable = bxt_disable_backlight;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 88e28c9..325fd3f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5232,7 +5232,7 @@ int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
> if (!enable_rc6)
> return 0;
>
> - if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
> DRM_INFO("RC6 disabled by BIOS\n");
> return 0;
> }
> @@ -5266,7 +5266,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
> /* All of these values are in units of 50MHz */
>
> /* static values from HW: RP0 > RP1 > RPn (min_freq) */
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
> dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
> dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
> @@ -7646,7 +7646,7 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
> dev_priv->display.init_clock_gating = skylake_init_clock_gating;
> else if (IS_KABYLAKE(dev_priv))
> dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> dev_priv->display.init_clock_gating = bxt_init_clock_gating;
> else if (IS_BROADWELL(dev_priv))
> dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 0599408..697574f 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -530,7 +530,7 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
> u32 mask;
>
> mask = DC_STATE_EN_UPTO_DC5;
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> mask |= DC_STATE_EN_DC9;
> else
> mask |= DC_STATE_EN_UPTO_DC6;
> @@ -911,7 +911,7 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
>
> gen9_assert_dbuf_enabled(dev_priv);
>
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> bxt_verify_ddi_phy_power_wells(dev_priv);
> }
>
> @@ -2170,7 +2170,7 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> max_dc = 2;
> mask = 0;
> - } else if (IS_BROXTON(dev_priv)) {
> + } else if (IS_GEN9_LP(dev_priv)) {
> max_dc = 1;
> /*
> * DC9 has a separate HW flow from the rest of the DC states,
> --
> 2.5.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* [PATCH v2] drm/i915/glk: Reuse broxton code for geminilake
2016-11-10 17:08 ` Rodrigo Vivi
@ 2016-11-11 13:52 ` Ander Conselvan de Oliveira
2016-11-11 15:26 ` kbuild test robot
2016-11-29 15:47 ` [PATCH v3] " Ander Conselvan de Oliveira
0 siblings, 2 replies; 52+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-11-11 13:52 UTC (permalink / raw)
To: intel-gfx, rodrigo.vivi; +Cc: Ander Conselvan de Oliveira
Geminilake is mostly backwards compatible with broxton, so change most
of the IS_BROXTON() checks to IS_GEN9_LP(). Differences between the
platforms will be implemented in follow-up patches.
v2: Don't reuse broxton's path in intel_update_max_cdclk().
Don't set plane count as in broxton.
v3: Rebase
v4: Include the check intel_bios_is_port_hpd_inverted().
Commit message.
v5: Leave i915_dmc_info() out; glk's csr version != bxt's. (Rodrigo)
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 10 +++++-----
drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++----
drivers/gpu/drm/i915/i915_irq.c | 10 +++++-----
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
drivers/gpu/drm/i915/intel_bios.c | 2 +-
drivers/gpu/drm/i915/intel_ddi.c | 10 +++++-----
drivers/gpu/drm/i915/intel_display.c | 8 ++++----
drivers/gpu/drm/i915/intel_dp.c | 20 ++++++++++----------
drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
drivers/gpu/drm/i915/intel_dsi.c | 28 ++++++++++++++--------------
drivers/gpu/drm/i915/intel_dsi_pll.c | 12 ++++++------
drivers/gpu/drm/i915/intel_hdmi.c | 6 +++---
drivers/gpu/drm/i915/intel_i2c.c | 4 ++--
drivers/gpu/drm/i915/intel_mocs.c | 2 +-
drivers/gpu/drm/i915/intel_panel.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 6 +++---
drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
17 files changed, 70 insertions(+), 70 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b681d42..5d349d6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1128,7 +1128,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
int max_freq;
rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
} else {
@@ -1224,7 +1224,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
seq_printf(m, "Down threshold: %d%%\n",
dev_priv->rps.down_threshold);
- max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
+ max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
rp_state_cap >> 16) & 0xff;
max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
GEN9_FREQ_SCALER : 1);
@@ -1237,7 +1237,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
intel_gpu_freq(dev_priv, max_freq));
- max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
+ max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
rp_state_cap >> 0) & 0xff;
max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
GEN9_FREQ_SCALER : 1);
@@ -5185,7 +5185,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
/* BXT has a single slice and at most 3 subslices. */
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
s_max = 1;
ss_max = 3;
}
@@ -5219,7 +5219,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
for (ss = 0; ss < ss_max; ss++) {
unsigned int eu_cnt;
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
/* skip disabled subslice */
continue;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a5fafa3..36483a2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -377,7 +377,7 @@ static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr)
/* There are only few exceptions for gen >=6. chv and bxt.
* And we are not sure about the latter so play safe for now.
*/
- if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
+ if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
drm_clflush_virt_range(vaddr, PAGE_SIZE);
kunmap_atomic(vaddr);
@@ -2946,7 +2946,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
* resort to an uncached mapping. The WC issue is easily caught by the
* readback check when writing GTT PTE entries.
*/
- if (IS_BROXTON(to_i915(ggtt->base.dev)))
+ if (IS_GEN9_LP(to_i915(ggtt->base.dev)))
ggtt->gsm = ioremap_nocache(phys_addr, size);
else
ggtt->gsm = ioremap_wc(phys_addr, size);
@@ -3078,7 +3078,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
- if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
+ if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
chv_setup_private_ppat(dev_priv);
else
bdw_setup_private_ppat(dev_priv);
@@ -3319,7 +3319,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
ggtt->base.closed = false;
if (INTEL_INFO(dev)->gen >= 8) {
- if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
+ if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
chv_setup_private_ppat(dev_priv);
else
bdw_setup_private_ppat(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6d7505b..081b3b7 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2435,7 +2435,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
found = true;
}
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
if (tmp_mask) {
bxt_hpd_irq_handler(dev_priv, tmp_mask,
@@ -2451,7 +2451,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
}
}
- if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
+ if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
gmbus_irq_handler(dev_priv);
found = true;
}
@@ -3379,7 +3379,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
GEN9_AUX_CHANNEL_D;
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
de_port_masked |= BXT_DE_PORT_GMBUS;
} else {
de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
@@ -3390,7 +3390,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
GEN8_PIPE_FIFO_UNDERRUN;
de_port_enables = de_port_masked;
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
else if (IS_BROADWELL(dev_priv))
de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
@@ -4215,7 +4215,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
dev->driver->irq_uninstall = gen8_irq_uninstall;
dev->driver->enable_vblank = gen8_enable_vblank;
dev->driver->disable_vblank = gen8_disable_vblank;
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3361d7f..1be2a7d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2920,7 +2920,7 @@ enum skl_disp_power_wells {
#define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
#define INTERVAL_0_833_US(us) (((us) * 6) / 5)
#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
- (IS_BROXTON(dev_priv) ? \
+ (IS_GEN9_LP(dev_priv) ? \
INTERVAL_0_833_US(us) : \
INTERVAL_1_33_US(us)) : \
INTERVAL_1_28_US(us))
@@ -2929,7 +2929,7 @@ enum skl_disp_power_wells {
#define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3)
#define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6)
#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN9(dev_priv) ? \
- (IS_BROXTON(dev_priv) ? \
+ (IS_GEN9_LP(dev_priv) ? \
INTERVAL_0_833_TO_US(interval) : \
INTERVAL_1_33_TO_US(interval)) : \
INTERVAL_1_28_TO_US(interval))
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 5ab646e..bd705f9 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1765,7 +1765,7 @@ intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
{
int i;
- if (WARN_ON_ONCE(!IS_BROXTON(dev_priv)))
+ if (WARN_ON_ONCE(!IS_GEN9_LP(dev_priv)))
return false;
for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0ad4e16..a129ffa 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -442,7 +442,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
return hdmi_level;
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
@@ -1091,7 +1091,7 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
hsw_ddi_clock_get(encoder, pipe_config);
else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
skl_ddi_clock_get(encoder, pipe_config);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
bxt_ddi_clock_get(encoder, pipe_config);
}
@@ -1153,7 +1153,7 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
return skl_ddi_pll_select(intel_crtc, crtc_state,
intel_encoder);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
return bxt_ddi_pll_select(intel_crtc, crtc_state,
intel_encoder);
else
@@ -1643,7 +1643,7 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
skl_ddi_set_iboost(encoder, level);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
return DDI_BUF_TRANS_SELECT(level);
@@ -2246,7 +2246,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
* configuration so that we use the proper lane count for our
* calculations.
*/
- if (IS_BROXTON(dev_priv) && port == PORT_A) {
+ if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 01dbf1b..723ff9d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -614,12 +614,12 @@ static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
INTELPllInvalid("m1 out of range\n");
if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
- !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
+ !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
if (clock->m1 <= clock->m2)
INTELPllInvalid("m1 <= m2\n");
if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
- !IS_BROXTON(dev_priv)) {
+ !IS_GEN9_LP(dev_priv)) {
if (clock->p < limit->p.min || limit->p.max < clock->p)
INTELPllInvalid("p out of range\n");
if (clock->m < limit->m.min || limit->m.max < clock->m)
@@ -10675,7 +10675,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
skylake_get_ddi_pll(dev_priv, port, pipe_config);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
bxt_get_ddi_pll(dev_priv, port, pipe_config);
else
haswell_get_ddi_pll(dev_priv, port, pipe_config);
@@ -10721,7 +10721,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
- if (IS_BROXTON(dev_priv) &&
+ if (IS_GEN9_LP(dev_priv) &&
bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
WARN_ON(active);
active = true;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 117a714..675e103 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -233,7 +233,7 @@ intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
int size;
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
*source_rates = bxt_rates;
size = ARRAY_SIZE(bxt_rates);
} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
@@ -688,7 +688,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
memset(regs, 0, sizeof(*regs));
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
pps_idx = bxt_power_sequencer_idx(intel_dp);
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
pps_idx = vlv_power_sequencer_pipe(intel_dp);
@@ -697,7 +697,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
regs->pp_stat = PP_STATUS(pps_idx);
regs->pp_on = PP_ON_DELAYS(pps_idx);
regs->pp_off = PP_OFF_DELAYS(pps_idx);
- if (!IS_BROXTON(dev_priv))
+ if (!IS_GEN9_LP(dev_priv))
regs->pp_div = PP_DIVISOR(pps_idx);
}
@@ -2984,7 +2984,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = to_i915(dev);
enum port port = dp_to_dig_port(intel_dp)->port;
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
else if (INTEL_INFO(dev)->gen >= 9) {
if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
@@ -4300,7 +4300,7 @@ static bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
return ibx_digital_port_connected(dev_priv, port);
else if (HAS_PCH_SPLIT(dev_priv))
return cpt_digital_port_connected(dev_priv, port);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
return bxt_digital_port_connected(dev_priv, port);
else if (IS_GM45(dev_priv))
return gm45_digital_port_connected(dev_priv, port);
@@ -4932,7 +4932,7 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
pp_on = I915_READ(regs.pp_on);
pp_off = I915_READ(regs.pp_off);
- if (!IS_BROXTON(dev_priv)) {
+ if (!IS_GEN9_LP(dev_priv)) {
I915_WRITE(regs.pp_ctrl, pp_ctl);
pp_div = I915_READ(regs.pp_div);
}
@@ -4950,7 +4950,7 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
PANEL_POWER_DOWN_DELAY_SHIFT;
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
BXT_POWER_CYCLE_DELAY_SHIFT;
if (tmp > 0)
@@ -5081,7 +5081,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
(seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
/* Compute the divisor for the pp clock, simply match the Bspec
* formula. */
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
pp_div = I915_READ(regs.pp_ctrl);
pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
@@ -5107,7 +5107,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
I915_WRITE(regs.pp_on, pp_on);
I915_WRITE(regs.pp_off, pp_off);
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
I915_WRITE(regs.pp_ctrl, pp_div);
else
I915_WRITE(regs.pp_div, pp_div);
@@ -5115,7 +5115,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
I915_READ(regs.pp_on),
I915_READ(regs.pp_off),
- IS_BROXTON(dev_priv) ?
+ IS_GEN9_LP(dev_priv) ?
(I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
I915_READ(regs.pp_div));
}
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 21853a1..8205c1c 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1861,7 +1861,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
dpll_mgr = &skl_pll_mgr;
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
dpll_mgr = &bxt_pll_mgr;
else if (HAS_DDI(dev_priv))
dpll_mgr = &hsw_pll_mgr;
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 4e0d025..4e19fbc 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -340,7 +340,7 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
/* DSI uses short packets for sync events, so clear mode flags for DSI */
adjusted_mode->flags = 0;
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
/* Dual link goes to DSI transcoder A. */
if (intel_dsi->ports == BIT(PORT_C))
pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
@@ -441,7 +441,7 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_dsi_device_ready(encoder);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
bxt_dsi_device_ready(encoder);
}
@@ -464,7 +464,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
}
for_each_dsi_port(port, intel_dsi->ports) {
- i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
+ i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
u32 temp;
@@ -494,7 +494,7 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
enum port port;
for_each_dsi_port(port, intel_dsi->ports) {
- i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
+ i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
u32 temp;
@@ -663,7 +663,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
DRM_DEBUG_KMS("\n");
for_each_dsi_port(port, intel_dsi->ports) {
/* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
- i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
+ i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
u32 val;
@@ -755,12 +755,12 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
* configuration, otherwise accessing DSI registers will hang the
* machine. See BSpec North Display Engine registers/MIPI[BXT].
*/
- if (IS_BROXTON(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
+ if (IS_GEN9_LP(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
goto out_put_power;
/* XXX: this only works for one DSI output */
for_each_dsi_port(port, intel_dsi->ports) {
- i915_reg_t ctrl_reg = IS_BROXTON(dev_priv) ?
+ i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
@@ -785,7 +785,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
continue;
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
u32 tmp = I915_READ(MIPI_CTRL(port));
tmp &= BXT_PIPE_SELECT_MASK;
tmp >>= BXT_PIPE_SELECT_SHIFT;
@@ -973,7 +973,7 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
u32 pclk;
DRM_DEBUG_KMS("\n");
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
bxt_dsi_get_pipe_config(encoder, pipe_config);
pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
@@ -1065,7 +1065,7 @@ static void set_dsi_timings(struct drm_encoder *encoder,
hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
for_each_dsi_port(port, intel_dsi->ports) {
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
/*
* Program hdisplay and vdisplay on MIPI transcoder.
* This is different from calculated hactive and
@@ -1152,7 +1152,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
tmp &= ~READ_REQUEST_PRIORITY_MASK;
I915_WRITE(MIPI_CTRL(port), tmp |
READ_REQUEST_PRIORITY_HIGH);
- } else if (IS_BROXTON(dev_priv)) {
+ } else if (IS_GEN9_LP(dev_priv)) {
enum pipe pipe = intel_crtc->pipe;
tmp = I915_READ(MIPI_CTRL(port));
@@ -1241,7 +1241,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
I915_WRITE(MIPI_INIT_COUNT(port),
txclkesc(intel_dsi->escape_clk_div, 100));
- if (IS_BROXTON(dev_priv) && (!intel_dsi->dual_link)) {
+ if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
/*
* BXT spec says write MIPI_INIT_COUNT for
* both the ports, even if only one is
@@ -1451,7 +1451,7 @@ void intel_dsi_init(struct drm_device *dev)
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
- } else if (IS_BROXTON(dev_priv)) {
+ } else if (IS_GEN9_LP(dev_priv)) {
dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
} else {
DRM_ERROR("Unsupported Mipi device to reg base");
@@ -1492,7 +1492,7 @@ void intel_dsi_init(struct drm_device *dev)
* On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
* port C. BXT isn't limited like this.
*/
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
else if (port == PORT_A)
intel_encoder->crtc_mask = BIT(PIPE_A);
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 56eff60..cf8c1b0 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -351,7 +351,7 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
struct intel_crtc_state *config)
{
- if (IS_BROXTON(to_i915(encoder->base.dev)))
+ if (IS_GEN9_LP(to_i915(encoder->base.dev)))
return bxt_dsi_get_pclk(encoder, pipe_bpp, config);
else
return vlv_dsi_get_pclk(encoder, pipe_bpp, config);
@@ -504,7 +504,7 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
{
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
return bxt_dsi_pll_is_enabled(dev_priv);
MISSING_CASE(INTEL_DEVID(dev_priv));
@@ -519,7 +519,7 @@ int intel_compute_dsi_pll(struct intel_encoder *encoder,
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return vlv_compute_dsi_pll(encoder, config);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
return bxt_compute_dsi_pll(encoder, config);
return -ENODEV;
@@ -532,7 +532,7 @@ void intel_enable_dsi_pll(struct intel_encoder *encoder,
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_enable_dsi_pll(encoder, config);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
bxt_enable_dsi_pll(encoder, config);
}
@@ -542,7 +542,7 @@ void intel_disable_dsi_pll(struct intel_encoder *encoder)
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_disable_dsi_pll(encoder);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
bxt_disable_dsi_pll(encoder);
}
@@ -566,7 +566,7 @@ void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
bxt_dsi_reset_clocks(encoder, port);
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_dsi_reset_clocks(encoder, port);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index fb88e32..034ec1a2 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1246,7 +1246,7 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
return MODE_CLOCK_HIGH;
/* BXT DPLL can't generate 223-240 MHz */
- if (IS_BROXTON(dev_priv) && clock > 223333 && clock < 240000)
+ if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
return MODE_CLOCK_RANGE;
/* CHV DPLL can't generate 216-240 MHz */
@@ -1809,13 +1809,13 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
switch (port) {
case PORT_B:
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
ddc_pin = GMBUS_PIN_1_BXT;
else
ddc_pin = GMBUS_PIN_DPB;
break;
case PORT_C:
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
ddc_pin = GMBUS_PIN_2_BXT;
else
ddc_pin = GMBUS_PIN_DPC;
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 83f260b..1606e31 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -72,7 +72,7 @@ static const struct gmbus_pin gmbus_pins_bxt[] = {
static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
unsigned int pin)
{
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
return &gmbus_pins_bxt[pin];
else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
return &gmbus_pins_skl[pin];
@@ -87,7 +87,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
{
unsigned int size;
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
size = ARRAY_SIZE(gmbus_pins_bxt);
else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
size = ARRAY_SIZE(gmbus_pins_skl);
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 80bb924..eed0707 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -182,7 +182,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
table->size = ARRAY_SIZE(skylake_mocs_table);
table->table = skylake_mocs_table;
result = true;
- } else if (IS_BROXTON(dev_priv)) {
+ } else if (IS_GEN9_LP(dev_priv)) {
table->size = ARRAY_SIZE(broxton_mocs_table);
table->table = broxton_mocs_table;
result = true;
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index be4b4d5..bf2899d 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1756,7 +1756,7 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
intel_dsi_dcs_init_backlight_funcs(connector) == 0)
return;
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
panel->backlight.setup = bxt_setup_backlight;
panel->backlight.enable = bxt_enable_backlight;
panel->backlight.disable = bxt_disable_backlight;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cc9e0c0..dcf5cd4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5228,7 +5228,7 @@ int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
if (!enable_rc6)
return 0;
- if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
DRM_INFO("RC6 disabled by BIOS\n");
return 0;
}
@@ -5262,7 +5262,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
/* All of these values are in units of 50MHz */
/* static values from HW: RP0 > RP1 > RPn (min_freq) */
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
@@ -7642,7 +7642,7 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
dev_priv->display.init_clock_gating = skylake_init_clock_gating;
else if (IS_KABYLAKE(dev_priv))
dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
dev_priv->display.init_clock_gating = bxt_init_clock_gating;
else if (IS_BROADWELL(dev_priv))
dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 0599408..697574f 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -530,7 +530,7 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
u32 mask;
mask = DC_STATE_EN_UPTO_DC5;
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
mask |= DC_STATE_EN_DC9;
else
mask |= DC_STATE_EN_UPTO_DC6;
@@ -911,7 +911,7 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
gen9_assert_dbuf_enabled(dev_priv);
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
bxt_verify_ddi_phy_power_wells(dev_priv);
}
@@ -2170,7 +2170,7 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
max_dc = 2;
mask = 0;
- } else if (IS_BROXTON(dev_priv)) {
+ } else if (IS_GEN9_LP(dev_priv)) {
max_dc = 1;
/*
* DC9 has a separate HW flow from the rest of the DC states,
--
2.5.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH v2] drm/i915/glk: Reuse broxton code for geminilake
2016-11-11 13:52 ` [PATCH v2] " Ander Conselvan de Oliveira
@ 2016-11-11 15:26 ` kbuild test robot
2016-11-29 15:47 ` [PATCH v3] " Ander Conselvan de Oliveira
1 sibling, 0 replies; 52+ messages in thread
From: kbuild test robot @ 2016-11-11 15:26 UTC (permalink / raw)
Cc: intel-gfx, kbuild-all, Ander Conselvan de Oliveira
[-- Attachment #1: Type: text/plain, Size: 2089 bytes --]
Hi Ander,
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20161111]
[cannot apply to v4.9-rc4]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Ander-Conselvan-de-Oliveira/drm-i915-glk-Reuse-broxton-code-for-geminilake/20161111-223125
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-i1-201645 (attached as .config)
compiler: gcc-4.8 (Debian 4.8.4-1) 4.8.4
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/intel_pm.c: In function 'gen6_set_rps_thresholds':
>> drivers/gpu/drm/i915/intel_pm.c:4888:2: error: implicit declaration of function 'IS_GEN9_LP' [-Werror=implicit-function-declaration]
I915_WRITE(GEN6_RP_UP_EI,
^
cc1: some warnings being treated as errors
vim +/IS_GEN9_LP +4888 drivers/gpu/drm/i915/intel_pm.c
dd75fdc8 Chris Wilson 2013-09-25 4882 /* Downclock if less than 60% busy over 32ms */
8a586437 Akash Goel 2015-03-06 4883 ei_down = 32000;
8a586437 Akash Goel 2015-03-06 4884 threshold_down = 60;
8a586437 Akash Goel 2015-03-06 4885 break;
8a586437 Akash Goel 2015-03-06 4886 }
8a586437 Akash Goel 2015-03-06 4887
8a586437 Akash Goel 2015-03-06 @4888 I915_WRITE(GEN6_RP_UP_EI,
8a586437 Akash Goel 2015-03-06 4889 GT_INTERVAL_FROM_US(dev_priv, ei_up));
8a586437 Akash Goel 2015-03-06 4890 I915_WRITE(GEN6_RP_UP_THRESHOLD,
a72b5623 Chris Wilson 2016-07-02 4891 GT_INTERVAL_FROM_US(dev_priv,
:::::: The code at line 4888 was first introduced by commit
:::::: 8a5864377b12b7c0a7a8e20cb33ef7ccc679d657 drm/i915/skl: Restructured the gen6_set_rps_thresholds function
:::::: TO: Akash Goel <akash.goel@intel.com>
:::::: CC: Daniel Vetter <daniel.vetter@ffwll.ch>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 33686 bytes --]
[-- Attachment #3: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* [PATCH v3] drm/i915/glk: Reuse broxton code for geminilake
2016-11-11 13:52 ` [PATCH v2] " Ander Conselvan de Oliveira
2016-11-11 15:26 ` kbuild test robot
@ 2016-11-29 15:47 ` Ander Conselvan de Oliveira
2016-12-02 1:06 ` Rodrigo Vivi
1 sibling, 1 reply; 52+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-11-29 15:47 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira, Rodrigo Vivi
Geminilake is mostly backwards compatible with broxton, so change most
of the IS_BROXTON() checks to IS_GEN9_LP(). Differences between the
platforms will be implemented in follow-up patches.
v2: Don't reuse broxton's path in intel_update_max_cdclk().
Don't set plane count as in broxton.
v3: Rebase
v4: Include the check intel_bios_is_port_hpd_inverted().
Commit message.
v5: Leave i915_dmc_info() out; glk's csr version != bxt's. (Rodrigo)
v6: Rebase.
v7: Convert a few mode IS_BROXTON() occurances in pps, ddi, dsi and pll
code. (Rodrigo)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 10 +++++-----
drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++----
drivers/gpu/drm/i915/i915_irq.c | 10 +++++-----
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
drivers/gpu/drm/i915/intel_bios.c | 2 +-
drivers/gpu/drm/i915/intel_ddi.c | 18 +++++++++---------
drivers/gpu/drm/i915/intel_display.c | 12 ++++++------
drivers/gpu/drm/i915/intel_dp.c | 24 ++++++++++++------------
drivers/gpu/drm/i915/intel_dpio_phy.c | 1 -
drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
drivers/gpu/drm/i915/intel_dsi.c | 30 +++++++++++++++---------------
drivers/gpu/drm/i915/intel_dsi_pll.c | 12 ++++++------
drivers/gpu/drm/i915/intel_hdmi.c | 6 +++---
drivers/gpu/drm/i915/intel_i2c.c | 4 ++--
drivers/gpu/drm/i915/intel_mocs.c | 2 +-
drivers/gpu/drm/i915/intel_panel.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 6 +++---
drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
18 files changed, 79 insertions(+), 80 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 8eb8c29..6c17d39 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1108,7 +1108,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
int max_freq;
rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
} else {
@@ -1204,7 +1204,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
seq_printf(m, "Down threshold: %d%%\n",
dev_priv->rps.down_threshold);
- max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
+ max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
rp_state_cap >> 16) & 0xff;
max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
GEN9_FREQ_SCALER : 1);
@@ -1217,7 +1217,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
intel_gpu_freq(dev_priv, max_freq));
- max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
+ max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
rp_state_cap >> 0) & 0xff;
max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
GEN9_FREQ_SCALER : 1);
@@ -5169,7 +5169,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
/* BXT has a single slice and at most 3 subslices. */
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
s_max = 1;
ss_max = 3;
}
@@ -5203,7 +5203,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
for (ss = 0; ss < ss_max; ss++) {
unsigned int eu_cnt;
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
/* skip disabled subslice */
continue;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 6cee707..e721a6f 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -372,7 +372,7 @@ static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr)
/* There are only few exceptions for gen >=6. chv and bxt.
* And we are not sure about the latter so play safe for now.
*/
- if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
+ if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
drm_clflush_virt_range(vaddr, PAGE_SIZE);
kunmap_atomic(vaddr);
@@ -2940,7 +2940,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
* resort to an uncached mapping. The WC issue is easily caught by the
* readback check when writing GTT PTE entries.
*/
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
ggtt->gsm = ioremap_nocache(phys_addr, size);
else
ggtt->gsm = ioremap_wc(phys_addr, size);
@@ -3070,7 +3070,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
- if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
+ if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
chv_setup_private_ppat(dev_priv);
else
bdw_setup_private_ppat(dev_priv);
@@ -3310,7 +3310,7 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
ggtt->base.closed = false;
if (INTEL_GEN(dev_priv) >= 8) {
- if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
+ if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
chv_setup_private_ppat(dev_priv);
else
bdw_setup_private_ppat(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0b119b9..a0e70f5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2435,7 +2435,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
found = true;
}
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
if (tmp_mask) {
bxt_hpd_irq_handler(dev_priv, tmp_mask,
@@ -2451,7 +2451,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
}
}
- if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
+ if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
gmbus_irq_handler(dev_priv);
found = true;
}
@@ -3375,7 +3375,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
GEN9_AUX_CHANNEL_D;
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
de_port_masked |= BXT_DE_PORT_GMBUS;
} else {
de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
@@ -3386,7 +3386,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
GEN8_PIPE_FIFO_UNDERRUN;
de_port_enables = de_port_masked;
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
else if (IS_BROADWELL(dev_priv))
de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
@@ -4211,7 +4211,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
dev->driver->irq_uninstall = gen8_irq_uninstall;
dev->driver->enable_vblank = gen8_enable_vblank;
dev->driver->disable_vblank = gen8_disable_vblank;
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6747d68..1dec207 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3256,7 +3256,7 @@ enum skl_disp_power_wells {
#define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
#define INTERVAL_0_833_US(us) (((us) * 6) / 5)
#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
- (IS_BROXTON(dev_priv) ? \
+ (IS_GEN9_LP(dev_priv) ? \
INTERVAL_0_833_US(us) : \
INTERVAL_1_33_US(us)) : \
INTERVAL_1_28_US(us))
@@ -3265,7 +3265,7 @@ enum skl_disp_power_wells {
#define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3)
#define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6)
#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN9(dev_priv) ? \
- (IS_BROXTON(dev_priv) ? \
+ (IS_GEN9_LP(dev_priv) ? \
INTERVAL_0_833_TO_US(interval) : \
INTERVAL_1_33_TO_US(interval)) : \
INTERVAL_1_28_TO_US(interval))
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 7ffab1a..eaade27 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1779,7 +1779,7 @@ intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
{
int i;
- if (WARN_ON_ONCE(!IS_BROXTON(dev_priv)))
+ if (WARN_ON_ONCE(!IS_GEN9_LP(dev_priv)))
return false;
for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f8e939d..3133e57 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -442,7 +442,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
return hdmi_level;
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
@@ -484,7 +484,7 @@ void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
const struct ddi_buf_trans *ddi_translations_edp;
const struct ddi_buf_trans *ddi_translations;
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
return;
if (IS_KABYLAKE(dev_priv)) {
@@ -567,7 +567,7 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
enum port port = intel_ddi_get_encoder_port(encoder);
const struct ddi_buf_trans *ddi_translations_hdmi;
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
return;
hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
@@ -1091,7 +1091,7 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
hsw_ddi_clock_get(encoder, pipe_config);
else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
skl_ddi_clock_get(encoder, pipe_config);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
bxt_ddi_clock_get(encoder, pipe_config);
}
@@ -1153,7 +1153,7 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
return skl_ddi_pll_select(intel_crtc, crtc_state,
intel_encoder);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
return bxt_ddi_pll_select(intel_crtc, crtc_state,
intel_encoder);
else
@@ -1643,7 +1643,7 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
skl_ddi_set_iboost(encoder, level);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
return DDI_BUF_TRANS_SELECT(level);
@@ -1716,7 +1716,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
intel_prepare_hdmi_ddi_buffers(encoder);
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
skl_ddi_set_iboost(encoder, level);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
bxt_ddi_vswing_sequence(dev_priv, level, port,
INTEL_OUTPUT_HDMI);
@@ -2127,7 +2127,7 @@ intel_ddi_get_link_dpll(struct intel_dp *intel_dp, int clock)
struct intel_shared_dpll_config tmp_pll_config;
enum intel_dpll_id dpll_id;
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
dpll_id = (enum intel_dpll_id)dig_port->port;
/*
* Select the required PLL. This works for platforms where
@@ -2244,7 +2244,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
* configuration so that we use the proper lane count for our
* calculations.
*/
- if (IS_BROXTON(dev_priv) && port == PORT_A) {
+ if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 15f48a0..418941b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -614,12 +614,12 @@ static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
INTELPllInvalid("m1 out of range\n");
if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
- !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
+ !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
if (clock->m1 <= clock->m2)
INTELPllInvalid("m1 <= m2\n");
if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
- !IS_BROXTON(dev_priv)) {
+ !IS_GEN9_LP(dev_priv)) {
if (clock->p < limit->p.min || limit->p.max < clock->p)
INTELPllInvalid("p out of range\n");
if (clock->m < limit->m.min || limit->m.max < clock->m)
@@ -10641,7 +10641,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
skylake_get_ddi_pll(dev_priv, port, pipe_config);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
bxt_get_ddi_pll(dev_priv, port, pipe_config);
else
haswell_get_ddi_pll(dev_priv, port, pipe_config);
@@ -10686,7 +10686,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
- if (IS_BROXTON(dev_priv) &&
+ if (IS_GEN9_LP(dev_priv) &&
bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
WARN_ON(active);
active = true;
@@ -12784,7 +12784,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
pipe_config->ips_enabled, pipe_config->double_wide);
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
"pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
"pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
@@ -15478,7 +15478,7 @@ void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
static void intel_pps_init(struct drm_i915_private *dev_priv)
{
- if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
+ if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
dev_priv->pps_mmio_base = PCH_PPS_BASE;
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
dev_priv->pps_mmio_base = VLV_PPS_BASE;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9dfbde4..1f2420c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -233,7 +233,7 @@ intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
int size;
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
*source_rates = bxt_rates;
size = ARRAY_SIZE(bxt_rates);
} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
@@ -645,7 +645,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
struct intel_encoder *encoder;
if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
- !IS_BROXTON(dev_priv)))
+ !IS_GEN9_LP(dev_priv)))
return;
/*
@@ -665,7 +665,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
continue;
intel_dp = enc_to_intel_dp(&encoder->base);
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
intel_dp->pps_reset = true;
else
intel_dp->pps_pipe = INVALID_PIPE;
@@ -688,7 +688,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
memset(regs, 0, sizeof(*regs));
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
pps_idx = bxt_power_sequencer_idx(intel_dp);
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
pps_idx = vlv_power_sequencer_pipe(intel_dp);
@@ -697,7 +697,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
regs->pp_stat = PP_STATUS(pps_idx);
regs->pp_on = PP_ON_DELAYS(pps_idx);
regs->pp_off = PP_OFF_DELAYS(pps_idx);
- if (!IS_BROXTON(dev_priv))
+ if (!IS_GEN9_LP(dev_priv))
regs->pp_div = PP_DIVISOR(pps_idx);
}
@@ -2984,7 +2984,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
enum port port = dp_to_dig_port(intel_dp)->port;
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
else if (INTEL_GEN(dev_priv) >= 9) {
if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
@@ -4300,7 +4300,7 @@ static bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
return ibx_digital_port_connected(dev_priv, port);
else if (HAS_PCH_SPLIT(dev_priv))
return cpt_digital_port_connected(dev_priv, port);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
return bxt_digital_port_connected(dev_priv, port);
else if (IS_GM45(dev_priv))
return gm45_digital_port_connected(dev_priv, port);
@@ -4929,7 +4929,7 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
pp_on = I915_READ(regs.pp_on);
pp_off = I915_READ(regs.pp_off);
- if (!IS_BROXTON(dev_priv)) {
+ if (!IS_GEN9_LP(dev_priv)) {
I915_WRITE(regs.pp_ctrl, pp_ctl);
pp_div = I915_READ(regs.pp_div);
}
@@ -4947,7 +4947,7 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
PANEL_POWER_DOWN_DELAY_SHIFT;
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
BXT_POWER_CYCLE_DELAY_SHIFT;
if (tmp > 0)
@@ -5078,7 +5078,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
(seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
/* Compute the divisor for the pp clock, simply match the Bspec
* formula. */
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
pp_div = I915_READ(regs.pp_ctrl);
pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
@@ -5104,7 +5104,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
I915_WRITE(regs.pp_on, pp_on);
I915_WRITE(regs.pp_off, pp_off);
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
I915_WRITE(regs.pp_ctrl, pp_div);
else
I915_WRITE(regs.pp_div, pp_div);
@@ -5112,7 +5112,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
I915_READ(regs.pp_on),
I915_READ(regs.pp_off),
- IS_BROXTON(dev_priv) ?
+ IS_GEN9_LP(dev_priv) ?
(I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
I915_READ(regs.pp_div));
}
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 7a8e82d..8c62dea 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -317,7 +317,6 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
"won't reprogram it\n", phy);
-
return;
}
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 58a756f..976d390 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1860,7 +1860,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
dpll_mgr = &skl_pll_mgr;
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
dpll_mgr = &bxt_pll_mgr;
else if (HAS_DDI(dev_priv))
dpll_mgr = &hsw_pll_mgr;
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 3bc6213..0668bbe 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -340,7 +340,7 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
/* DSI uses short packets for sync events, so clear mode flags for DSI */
adjusted_mode->flags = 0;
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
/* Dual link goes to DSI transcoder A. */
if (intel_dsi->ports == BIT(PORT_C))
pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
@@ -441,7 +441,7 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_dsi_device_ready(encoder);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
bxt_dsi_device_ready(encoder);
}
@@ -464,7 +464,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
}
for_each_dsi_port(port, intel_dsi->ports) {
- i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
+ i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
u32 temp;
@@ -497,7 +497,7 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
enum port port;
for_each_dsi_port(port, intel_dsi->ports) {
- i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
+ i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
u32 temp;
@@ -666,7 +666,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
DRM_DEBUG_KMS("\n");
for_each_dsi_port(port, intel_dsi->ports) {
/* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
- i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
+ i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
u32 val;
@@ -758,12 +758,12 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
* configuration, otherwise accessing DSI registers will hang the
* machine. See BSpec North Display Engine registers/MIPI[BXT].
*/
- if (IS_BROXTON(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
+ if (IS_GEN9_LP(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
goto out_put_power;
/* XXX: this only works for one DSI output */
for_each_dsi_port(port, intel_dsi->ports) {
- i915_reg_t ctrl_reg = IS_BROXTON(dev_priv) ?
+ i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
@@ -788,7 +788,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
continue;
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
u32 tmp = I915_READ(MIPI_CTRL(port));
tmp &= BXT_PIPE_SELECT_MASK;
tmp >>= BXT_PIPE_SELECT_SHIFT;
@@ -976,7 +976,7 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
u32 pclk;
DRM_DEBUG_KMS("\n");
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
bxt_dsi_get_pipe_config(encoder, pipe_config);
pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
@@ -1068,7 +1068,7 @@ static void set_dsi_timings(struct drm_encoder *encoder,
hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
for_each_dsi_port(port, intel_dsi->ports) {
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
/*
* Program hdisplay and vdisplay on MIPI transcoder.
* This is different from calculated hactive and
@@ -1155,7 +1155,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
tmp &= ~READ_REQUEST_PRIORITY_MASK;
I915_WRITE(MIPI_CTRL(port), tmp |
READ_REQUEST_PRIORITY_HIGH);
- } else if (IS_BROXTON(dev_priv)) {
+ } else if (IS_GEN9_LP(dev_priv)) {
enum pipe pipe = intel_crtc->pipe;
tmp = I915_READ(MIPI_CTRL(port));
@@ -1193,7 +1193,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
if (intel_dsi->clock_stop)
tmp |= CLOCKSTOP;
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
tmp |= BXT_DPHY_DEFEATURE_EN;
if (!is_cmd_mode(intel_dsi))
tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
@@ -1244,7 +1244,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
I915_WRITE(MIPI_INIT_COUNT(port),
txclkesc(intel_dsi->escape_clk_div, 100));
- if (IS_BROXTON(dev_priv) && (!intel_dsi->dual_link)) {
+ if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
/*
* BXT spec says write MIPI_INIT_COUNT for
* both the ports, even if only one is
@@ -1454,7 +1454,7 @@ void intel_dsi_init(struct drm_i915_private *dev_priv)
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
- } else if (IS_BROXTON(dev_priv)) {
+ } else if (IS_GEN9_LP(dev_priv)) {
dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
} else {
DRM_ERROR("Unsupported Mipi device to reg base");
@@ -1495,7 +1495,7 @@ void intel_dsi_init(struct drm_i915_private *dev_priv)
* On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
* port C. BXT isn't limited like this.
*/
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
else if (port == PORT_A)
intel_encoder->crtc_mask = BIT(PIPE_A);
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 56eff60..cf8c1b0 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -351,7 +351,7 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
struct intel_crtc_state *config)
{
- if (IS_BROXTON(to_i915(encoder->base.dev)))
+ if (IS_GEN9_LP(to_i915(encoder->base.dev)))
return bxt_dsi_get_pclk(encoder, pipe_bpp, config);
else
return vlv_dsi_get_pclk(encoder, pipe_bpp, config);
@@ -504,7 +504,7 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
{
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
return bxt_dsi_pll_is_enabled(dev_priv);
MISSING_CASE(INTEL_DEVID(dev_priv));
@@ -519,7 +519,7 @@ int intel_compute_dsi_pll(struct intel_encoder *encoder,
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return vlv_compute_dsi_pll(encoder, config);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
return bxt_compute_dsi_pll(encoder, config);
return -ENODEV;
@@ -532,7 +532,7 @@ void intel_enable_dsi_pll(struct intel_encoder *encoder,
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_enable_dsi_pll(encoder, config);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
bxt_enable_dsi_pll(encoder, config);
}
@@ -542,7 +542,7 @@ void intel_disable_dsi_pll(struct intel_encoder *encoder)
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_disable_dsi_pll(encoder);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
bxt_disable_dsi_pll(encoder);
}
@@ -566,7 +566,7 @@ void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
bxt_dsi_reset_clocks(encoder, port);
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_dsi_reset_clocks(encoder, port);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 374e38a..0bcfead 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1251,7 +1251,7 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
return MODE_CLOCK_HIGH;
/* BXT DPLL can't generate 223-240 MHz */
- if (IS_BROXTON(dev_priv) && clock > 223333 && clock < 240000)
+ if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
return MODE_CLOCK_RANGE;
/* CHV DPLL can't generate 216-240 MHz */
@@ -1809,13 +1809,13 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
switch (port) {
case PORT_B:
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
ddc_pin = GMBUS_PIN_1_BXT;
else
ddc_pin = GMBUS_PIN_DPB;
break;
case PORT_C:
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
ddc_pin = GMBUS_PIN_2_BXT;
else
ddc_pin = GMBUS_PIN_DPC;
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 83f260b..1606e31 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -72,7 +72,7 @@ static const struct gmbus_pin gmbus_pins_bxt[] = {
static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
unsigned int pin)
{
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
return &gmbus_pins_bxt[pin];
else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
return &gmbus_pins_skl[pin];
@@ -87,7 +87,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
{
unsigned int size;
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
size = ARRAY_SIZE(gmbus_pins_bxt);
else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
size = ARRAY_SIZE(gmbus_pins_skl);
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 80bb924..eed0707 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -182,7 +182,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
table->size = ARRAY_SIZE(skylake_mocs_table);
table->table = skylake_mocs_table;
result = true;
- } else if (IS_BROXTON(dev_priv)) {
+ } else if (IS_GEN9_LP(dev_priv)) {
table->size = ARRAY_SIZE(broxton_mocs_table);
table->table = broxton_mocs_table;
result = true;
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 08ab6d7..3578b40 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1756,7 +1756,7 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
intel_dsi_dcs_init_backlight_funcs(connector) == 0)
return;
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
panel->backlight.setup = bxt_setup_backlight;
panel->backlight.enable = bxt_enable_backlight;
panel->backlight.disable = bxt_disable_backlight;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 29b6653..0b17a4f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5208,7 +5208,7 @@ int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
if (!enable_rc6)
return 0;
- if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
DRM_INFO("RC6 disabled by BIOS\n");
return 0;
}
@@ -5242,7 +5242,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
/* All of these values are in units of 50MHz */
/* static values from HW: RP0 > RP1 > RPn (min_freq) */
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
@@ -7622,7 +7622,7 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
dev_priv->display.init_clock_gating = skylake_init_clock_gating;
else if (IS_KABYLAKE(dev_priv))
dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
dev_priv->display.init_clock_gating = bxt_init_clock_gating;
else if (IS_BROADWELL(dev_priv))
dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 356c662..66ab1c8 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -530,7 +530,7 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
u32 mask;
mask = DC_STATE_EN_UPTO_DC5;
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
mask |= DC_STATE_EN_DC9;
else
mask |= DC_STATE_EN_UPTO_DC6;
@@ -911,7 +911,7 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
gen9_assert_dbuf_enabled(dev_priv);
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
bxt_verify_ddi_phy_power_wells(dev_priv);
}
@@ -2170,7 +2170,7 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
max_dc = 2;
mask = 0;
- } else if (IS_BROXTON(dev_priv)) {
+ } else if (IS_GEN9_LP(dev_priv)) {
max_dc = 1;
/*
* DC9 has a separate HW flow from the rest of the DC states,
--
2.5.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH v3] drm/i915/glk: Reuse broxton code for geminilake
2016-11-29 15:47 ` [PATCH v3] " Ander Conselvan de Oliveira
@ 2016-12-02 1:06 ` Rodrigo Vivi
2016-12-02 8:27 ` Ander Conselvan De Oliveira
0 siblings, 1 reply; 52+ messages in thread
From: Rodrigo Vivi @ 2016-12-02 1:06 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx, Rodrigo Vivi
A reviewed backwards because I was willing to check if all ifs were in place.
I missed the ones from i915_drv.c
*** i915_drv.c:
i915_drm_suspend_late[1500] fw_csr = !IS_GEN9_LP(dev_priv) &&
i915_drm_suspend_late[1513] if (IS_GEN9_LP(dev_priv))
i915_drm_resume_early[1721] if (IS_GEN9_LP(dev_priv)) {
i915_drm_resume_early[1731] if (IS_GEN9_LP(dev_priv) ||
intel_runtime_suspend[2354] if (IS_GEN9_LP(dev_priv)) {
intel_runtime_resume[2439] if (IS_GEN9_LP(dev_priv)) {
The ones that I had added with the patch
"drm/i915/glk: Add missing bits to allow runtime pm suspend on GLK."
Feel free to squash all those into this patch if you like. However I believe that before that one we need Anusha's dmc load patch that is one that I'm also missing on this series here, right?
So any option works for me and if you decide to move with this feel free to use
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
And please let me know what are your plans with this runtime_pm related patches and if you need anything from me.
Thanks,
Rodrigo.
On Tue, Nov 29, 2016 at 05:47:12PM +0200, Ander Conselvan de Oliveira wrote:
> Geminilake is mostly backwards compatible with broxton, so change most
> of the IS_BROXTON() checks to IS_GEN9_LP(). Differences between the
> platforms will be implemented in follow-up patches.
>
> v2: Don't reuse broxton's path in intel_update_max_cdclk().
> Don't set plane count as in broxton.
>
> v3: Rebase
>
> v4: Include the check intel_bios_is_port_hpd_inverted().
> Commit message.
>
> v5: Leave i915_dmc_info() out; glk's csr version != bxt's. (Rodrigo)
>
> v6: Rebase.
>
> v7: Convert a few mode IS_BROXTON() occurances in pps, ddi, dsi and pll
> code. (Rodrigo)
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 10 +++++-----
> drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++----
> drivers/gpu/drm/i915/i915_irq.c | 10 +++++-----
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> drivers/gpu/drm/i915/intel_bios.c | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c | 18 +++++++++---------
> drivers/gpu/drm/i915/intel_display.c | 12 ++++++------
> drivers/gpu/drm/i915/intel_dp.c | 24 ++++++++++++------------
> drivers/gpu/drm/i915/intel_dpio_phy.c | 1 -
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
> drivers/gpu/drm/i915/intel_dsi.c | 30 +++++++++++++++---------------
> drivers/gpu/drm/i915/intel_dsi_pll.c | 12 ++++++------
> drivers/gpu/drm/i915/intel_hdmi.c | 6 +++---
> drivers/gpu/drm/i915/intel_i2c.c | 4 ++--
> drivers/gpu/drm/i915/intel_mocs.c | 2 +-
> drivers/gpu/drm/i915/intel_panel.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 6 +++---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
> 18 files changed, 79 insertions(+), 80 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 8eb8c29..6c17d39 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1108,7 +1108,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> int max_freq;
>
> rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
> gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
> } else {
> @@ -1204,7 +1204,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> seq_printf(m, "Down threshold: %d%%\n",
> dev_priv->rps.down_threshold);
>
> - max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
> + max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
> rp_state_cap >> 16) & 0xff;
> max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
> GEN9_FREQ_SCALER : 1);
> @@ -1217,7 +1217,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
> intel_gpu_freq(dev_priv, max_freq));
>
> - max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
> + max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
> rp_state_cap >> 0) & 0xff;
> max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
> GEN9_FREQ_SCALER : 1);
> @@ -5169,7 +5169,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
>
> /* BXT has a single slice and at most 3 subslices. */
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> s_max = 1;
> ss_max = 3;
> }
> @@ -5203,7 +5203,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> for (ss = 0; ss < ss_max; ss++) {
> unsigned int eu_cnt;
>
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> /* skip disabled subslice */
> continue;
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 6cee707..e721a6f 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -372,7 +372,7 @@ static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr)
> /* There are only few exceptions for gen >=6. chv and bxt.
> * And we are not sure about the latter so play safe for now.
> */
> - if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> + if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
> drm_clflush_virt_range(vaddr, PAGE_SIZE);
>
> kunmap_atomic(vaddr);
> @@ -2940,7 +2940,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
> * resort to an uncached mapping. The WC issue is easily caught by the
> * readback check when writing GTT PTE entries.
> */
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> ggtt->gsm = ioremap_nocache(phys_addr, size);
> else
> ggtt->gsm = ioremap_wc(phys_addr, size);
> @@ -3070,7 +3070,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
>
> ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
>
> - if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> + if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
> chv_setup_private_ppat(dev_priv);
> else
> bdw_setup_private_ppat(dev_priv);
> @@ -3310,7 +3310,7 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
> ggtt->base.closed = false;
>
> if (INTEL_GEN(dev_priv) >= 8) {
> - if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> + if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
> chv_setup_private_ppat(dev_priv);
> else
> bdw_setup_private_ppat(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 0b119b9..a0e70f5 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2435,7 +2435,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> found = true;
> }
>
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
> if (tmp_mask) {
> bxt_hpd_irq_handler(dev_priv, tmp_mask,
> @@ -2451,7 +2451,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> }
> }
>
> - if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
> + if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
> gmbus_irq_handler(dev_priv);
> found = true;
> }
> @@ -3375,7 +3375,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
> de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
> GEN9_AUX_CHANNEL_D;
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> de_port_masked |= BXT_DE_PORT_GMBUS;
> } else {
> de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
> @@ -3386,7 +3386,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> GEN8_PIPE_FIFO_UNDERRUN;
>
> de_port_enables = de_port_masked;
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
> else if (IS_BROADWELL(dev_priv))
> de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
> @@ -4211,7 +4211,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> dev->driver->irq_uninstall = gen8_irq_uninstall;
> dev->driver->enable_vblank = gen8_enable_vblank;
> dev->driver->disable_vblank = gen8_disable_vblank;
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
> else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
> dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6747d68..1dec207 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3256,7 +3256,7 @@ enum skl_disp_power_wells {
> #define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
> #define INTERVAL_0_833_US(us) (((us) * 6) / 5)
> #define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
> - (IS_BROXTON(dev_priv) ? \
> + (IS_GEN9_LP(dev_priv) ? \
> INTERVAL_0_833_US(us) : \
> INTERVAL_1_33_US(us)) : \
> INTERVAL_1_28_US(us))
> @@ -3265,7 +3265,7 @@ enum skl_disp_power_wells {
> #define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3)
> #define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6)
> #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN9(dev_priv) ? \
> - (IS_BROXTON(dev_priv) ? \
> + (IS_GEN9_LP(dev_priv) ? \
> INTERVAL_0_833_TO_US(interval) : \
> INTERVAL_1_33_TO_US(interval)) : \
> INTERVAL_1_28_TO_US(interval))
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 7ffab1a..eaade27 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -1779,7 +1779,7 @@ intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
> {
> int i;
>
> - if (WARN_ON_ONCE(!IS_BROXTON(dev_priv)))
> + if (WARN_ON_ONCE(!IS_GEN9_LP(dev_priv)))
> return false;
>
> for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index f8e939d..3133e57 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -442,7 +442,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
>
> hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
>
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> return hdmi_level;
>
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> @@ -484,7 +484,7 @@ void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
> const struct ddi_buf_trans *ddi_translations_edp;
> const struct ddi_buf_trans *ddi_translations;
>
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> return;
>
> if (IS_KABYLAKE(dev_priv)) {
> @@ -567,7 +567,7 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
> enum port port = intel_ddi_get_encoder_port(encoder);
> const struct ddi_buf_trans *ddi_translations_hdmi;
>
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> return;
>
> hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
> @@ -1091,7 +1091,7 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
> hsw_ddi_clock_get(encoder, pipe_config);
> else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> skl_ddi_clock_get(encoder, pipe_config);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> bxt_ddi_clock_get(encoder, pipe_config);
> }
>
> @@ -1153,7 +1153,7 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> return skl_ddi_pll_select(intel_crtc, crtc_state,
> intel_encoder);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> return bxt_ddi_pll_select(intel_crtc, crtc_state,
> intel_encoder);
> else
> @@ -1643,7 +1643,7 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
>
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> skl_ddi_set_iboost(encoder, level);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
>
> return DDI_BUF_TRANS_SELECT(level);
> @@ -1716,7 +1716,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
> intel_prepare_hdmi_ddi_buffers(encoder);
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> skl_ddi_set_iboost(encoder, level);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> bxt_ddi_vswing_sequence(dev_priv, level, port,
> INTEL_OUTPUT_HDMI);
>
> @@ -2127,7 +2127,7 @@ intel_ddi_get_link_dpll(struct intel_dp *intel_dp, int clock)
> struct intel_shared_dpll_config tmp_pll_config;
> enum intel_dpll_id dpll_id;
>
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> dpll_id = (enum intel_dpll_id)dig_port->port;
> /*
> * Select the required PLL. This works for platforms where
> @@ -2244,7 +2244,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> * configuration so that we use the proper lane count for our
> * calculations.
> */
> - if (IS_BROXTON(dev_priv) && port == PORT_A) {
> + if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
> if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
> DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
> intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 15f48a0..418941b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -614,12 +614,12 @@ static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
> INTELPllInvalid("m1 out of range\n");
>
> if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
> - !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
> + !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
> if (clock->m1 <= clock->m2)
> INTELPllInvalid("m1 <= m2\n");
>
> if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> - !IS_BROXTON(dev_priv)) {
> + !IS_GEN9_LP(dev_priv)) {
> if (clock->p < limit->p.min || limit->p.max < clock->p)
> INTELPllInvalid("p out of range\n");
> if (clock->m < limit->m.min || limit->m.max < clock->m)
> @@ -10641,7 +10641,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
>
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> skylake_get_ddi_pll(dev_priv, port, pipe_config);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> bxt_get_ddi_pll(dev_priv, port, pipe_config);
> else
> haswell_get_ddi_pll(dev_priv, port, pipe_config);
> @@ -10686,7 +10686,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
>
> active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
>
> - if (IS_BROXTON(dev_priv) &&
> + if (IS_GEN9_LP(dev_priv) &&
> bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
> WARN_ON(active);
> active = true;
> @@ -12784,7 +12784,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
> DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
> pipe_config->ips_enabled, pipe_config->double_wide);
>
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
> "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
> "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
> @@ -15478,7 +15478,7 @@ void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
>
> static void intel_pps_init(struct drm_i915_private *dev_priv)
> {
> - if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
> + if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
> dev_priv->pps_mmio_base = PCH_PPS_BASE;
> else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> dev_priv->pps_mmio_base = VLV_PPS_BASE;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 9dfbde4..1f2420c 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -233,7 +233,7 @@ intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
> struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> int size;
>
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> *source_rates = bxt_rates;
> size = ARRAY_SIZE(bxt_rates);
> } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> @@ -645,7 +645,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
> struct intel_encoder *encoder;
>
> if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> - !IS_BROXTON(dev_priv)))
> + !IS_GEN9_LP(dev_priv)))
> return;
>
> /*
> @@ -665,7 +665,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
> continue;
>
> intel_dp = enc_to_intel_dp(&encoder->base);
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> intel_dp->pps_reset = true;
> else
> intel_dp->pps_pipe = INVALID_PIPE;
> @@ -688,7 +688,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
>
> memset(regs, 0, sizeof(*regs));
>
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> pps_idx = bxt_power_sequencer_idx(intel_dp);
> else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> pps_idx = vlv_power_sequencer_pipe(intel_dp);
> @@ -697,7 +697,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
> regs->pp_stat = PP_STATUS(pps_idx);
> regs->pp_on = PP_ON_DELAYS(pps_idx);
> regs->pp_off = PP_OFF_DELAYS(pps_idx);
> - if (!IS_BROXTON(dev_priv))
> + if (!IS_GEN9_LP(dev_priv))
> regs->pp_div = PP_DIVISOR(pps_idx);
> }
>
> @@ -2984,7 +2984,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
> struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
> enum port port = dp_to_dig_port(intel_dp)->port;
>
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> else if (INTEL_GEN(dev_priv) >= 9) {
> if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
> @@ -4300,7 +4300,7 @@ static bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
> return ibx_digital_port_connected(dev_priv, port);
> else if (HAS_PCH_SPLIT(dev_priv))
> return cpt_digital_port_connected(dev_priv, port);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> return bxt_digital_port_connected(dev_priv, port);
> else if (IS_GM45(dev_priv))
> return gm45_digital_port_connected(dev_priv, port);
> @@ -4929,7 +4929,7 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
>
> pp_on = I915_READ(regs.pp_on);
> pp_off = I915_READ(regs.pp_off);
> - if (!IS_BROXTON(dev_priv)) {
> + if (!IS_GEN9_LP(dev_priv)) {
> I915_WRITE(regs.pp_ctrl, pp_ctl);
> pp_div = I915_READ(regs.pp_div);
> }
> @@ -4947,7 +4947,7 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
> seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
> PANEL_POWER_DOWN_DELAY_SHIFT;
>
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
> BXT_POWER_CYCLE_DELAY_SHIFT;
> if (tmp > 0)
> @@ -5078,7 +5078,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> /* Compute the divisor for the pp clock, simply match the Bspec
> * formula. */
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> pp_div = I915_READ(regs.pp_ctrl);
> pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
> pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
> @@ -5104,7 +5104,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
>
> I915_WRITE(regs.pp_on, pp_on);
> I915_WRITE(regs.pp_off, pp_off);
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> I915_WRITE(regs.pp_ctrl, pp_div);
> else
> I915_WRITE(regs.pp_div, pp_div);
> @@ -5112,7 +5112,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
> I915_READ(regs.pp_on),
> I915_READ(regs.pp_off),
> - IS_BROXTON(dev_priv) ?
> + IS_GEN9_LP(dev_priv) ?
> (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
> I915_READ(regs.pp_div));
> }
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index 7a8e82d..8c62dea 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -317,7 +317,6 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
> if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
> DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
> "won't reprogram it\n", phy);
> -
> return;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 58a756f..976d390 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1860,7 +1860,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
>
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> dpll_mgr = &skl_pll_mgr;
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> dpll_mgr = &bxt_pll_mgr;
> else if (HAS_DDI(dev_priv))
> dpll_mgr = &hsw_pll_mgr;
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 3bc6213..0668bbe 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -340,7 +340,7 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
> /* DSI uses short packets for sync events, so clear mode flags for DSI */
> adjusted_mode->flags = 0;
>
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> /* Dual link goes to DSI transcoder A. */
> if (intel_dsi->ports == BIT(PORT_C))
> pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
> @@ -441,7 +441,7 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_dsi_device_ready(encoder);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> bxt_dsi_device_ready(encoder);
> }
>
> @@ -464,7 +464,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
> }
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> + i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> u32 temp;
>
> @@ -497,7 +497,7 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
> enum port port;
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> + i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> u32 temp;
>
> @@ -666,7 +666,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> DRM_DEBUG_KMS("\n");
> for_each_dsi_port(port, intel_dsi->ports) {
> /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
> - i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> + i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
> u32 val;
>
> @@ -758,12 +758,12 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
> * configuration, otherwise accessing DSI registers will hang the
> * machine. See BSpec North Display Engine registers/MIPI[BXT].
> */
> - if (IS_BROXTON(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
> + if (IS_GEN9_LP(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
> goto out_put_power;
>
> /* XXX: this only works for one DSI output */
> for_each_dsi_port(port, intel_dsi->ports) {
> - i915_reg_t ctrl_reg = IS_BROXTON(dev_priv) ?
> + i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
>
> @@ -788,7 +788,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
> if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
> continue;
>
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> u32 tmp = I915_READ(MIPI_CTRL(port));
> tmp &= BXT_PIPE_SELECT_MASK;
> tmp >>= BXT_PIPE_SELECT_SHIFT;
> @@ -976,7 +976,7 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
> u32 pclk;
> DRM_DEBUG_KMS("\n");
>
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> bxt_dsi_get_pipe_config(encoder, pipe_config);
>
> pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
> @@ -1068,7 +1068,7 @@ static void set_dsi_timings(struct drm_encoder *encoder,
> hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> /*
> * Program hdisplay and vdisplay on MIPI transcoder.
> * This is different from calculated hactive and
> @@ -1155,7 +1155,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
> tmp &= ~READ_REQUEST_PRIORITY_MASK;
> I915_WRITE(MIPI_CTRL(port), tmp |
> READ_REQUEST_PRIORITY_HIGH);
> - } else if (IS_BROXTON(dev_priv)) {
> + } else if (IS_GEN9_LP(dev_priv)) {
> enum pipe pipe = intel_crtc->pipe;
>
> tmp = I915_READ(MIPI_CTRL(port));
> @@ -1193,7 +1193,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
> if (intel_dsi->clock_stop)
> tmp |= CLOCKSTOP;
>
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> tmp |= BXT_DPHY_DEFEATURE_EN;
> if (!is_cmd_mode(intel_dsi))
> tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
> @@ -1244,7 +1244,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
> I915_WRITE(MIPI_INIT_COUNT(port),
> txclkesc(intel_dsi->escape_clk_div, 100));
>
> - if (IS_BROXTON(dev_priv) && (!intel_dsi->dual_link)) {
> + if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
> /*
> * BXT spec says write MIPI_INIT_COUNT for
> * both the ports, even if only one is
> @@ -1454,7 +1454,7 @@ void intel_dsi_init(struct drm_i915_private *dev_priv)
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
> - } else if (IS_BROXTON(dev_priv)) {
> + } else if (IS_GEN9_LP(dev_priv)) {
> dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
> } else {
> DRM_ERROR("Unsupported Mipi device to reg base");
> @@ -1495,7 +1495,7 @@ void intel_dsi_init(struct drm_i915_private *dev_priv)
> * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
> * port C. BXT isn't limited like this.
> */
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
> else if (port == PORT_A)
> intel_encoder->crtc_mask = BIT(PIPE_A);
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 56eff60..cf8c1b0 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -351,7 +351,7 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
> u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
> struct intel_crtc_state *config)
> {
> - if (IS_BROXTON(to_i915(encoder->base.dev)))
> + if (IS_GEN9_LP(to_i915(encoder->base.dev)))
> return bxt_dsi_get_pclk(encoder, pipe_bpp, config);
> else
> return vlv_dsi_get_pclk(encoder, pipe_bpp, config);
> @@ -504,7 +504,7 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
>
> bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
> {
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> return bxt_dsi_pll_is_enabled(dev_priv);
>
> MISSING_CASE(INTEL_DEVID(dev_priv));
> @@ -519,7 +519,7 @@ int intel_compute_dsi_pll(struct intel_encoder *encoder,
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> return vlv_compute_dsi_pll(encoder, config);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> return bxt_compute_dsi_pll(encoder, config);
>
> return -ENODEV;
> @@ -532,7 +532,7 @@ void intel_enable_dsi_pll(struct intel_encoder *encoder,
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_enable_dsi_pll(encoder, config);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> bxt_enable_dsi_pll(encoder, config);
> }
>
> @@ -542,7 +542,7 @@ void intel_disable_dsi_pll(struct intel_encoder *encoder)
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_disable_dsi_pll(encoder);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> bxt_disable_dsi_pll(encoder);
> }
>
> @@ -566,7 +566,7 @@ void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> bxt_dsi_reset_clocks(encoder, port);
> else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_dsi_reset_clocks(encoder, port);
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 374e38a..0bcfead 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1251,7 +1251,7 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
> return MODE_CLOCK_HIGH;
>
> /* BXT DPLL can't generate 223-240 MHz */
> - if (IS_BROXTON(dev_priv) && clock > 223333 && clock < 240000)
> + if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
> return MODE_CLOCK_RANGE;
>
> /* CHV DPLL can't generate 216-240 MHz */
> @@ -1809,13 +1809,13 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
>
> switch (port) {
> case PORT_B:
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> ddc_pin = GMBUS_PIN_1_BXT;
> else
> ddc_pin = GMBUS_PIN_DPB;
> break;
> case PORT_C:
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> ddc_pin = GMBUS_PIN_2_BXT;
> else
> ddc_pin = GMBUS_PIN_DPC;
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index 83f260b..1606e31 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -72,7 +72,7 @@ static const struct gmbus_pin gmbus_pins_bxt[] = {
> static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
> unsigned int pin)
> {
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> return &gmbus_pins_bxt[pin];
> else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> return &gmbus_pins_skl[pin];
> @@ -87,7 +87,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
> {
> unsigned int size;
>
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> size = ARRAY_SIZE(gmbus_pins_bxt);
> else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> size = ARRAY_SIZE(gmbus_pins_skl);
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> index 80bb924..eed0707 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -182,7 +182,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
> table->size = ARRAY_SIZE(skylake_mocs_table);
> table->table = skylake_mocs_table;
> result = true;
> - } else if (IS_BROXTON(dev_priv)) {
> + } else if (IS_GEN9_LP(dev_priv)) {
> table->size = ARRAY_SIZE(broxton_mocs_table);
> table->table = broxton_mocs_table;
> result = true;
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index 08ab6d7..3578b40 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -1756,7 +1756,7 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
> intel_dsi_dcs_init_backlight_funcs(connector) == 0)
> return;
>
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> panel->backlight.setup = bxt_setup_backlight;
> panel->backlight.enable = bxt_enable_backlight;
> panel->backlight.disable = bxt_disable_backlight;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 29b6653..0b17a4f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5208,7 +5208,7 @@ int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
> if (!enable_rc6)
> return 0;
>
> - if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
> DRM_INFO("RC6 disabled by BIOS\n");
> return 0;
> }
> @@ -5242,7 +5242,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
> /* All of these values are in units of 50MHz */
>
> /* static values from HW: RP0 > RP1 > RPn (min_freq) */
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
> dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
> dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
> @@ -7622,7 +7622,7 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
> dev_priv->display.init_clock_gating = skylake_init_clock_gating;
> else if (IS_KABYLAKE(dev_priv))
> dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> dev_priv->display.init_clock_gating = bxt_init_clock_gating;
> else if (IS_BROADWELL(dev_priv))
> dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 356c662..66ab1c8 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -530,7 +530,7 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
> u32 mask;
>
> mask = DC_STATE_EN_UPTO_DC5;
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> mask |= DC_STATE_EN_DC9;
> else
> mask |= DC_STATE_EN_UPTO_DC6;
> @@ -911,7 +911,7 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
>
> gen9_assert_dbuf_enabled(dev_priv);
>
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> bxt_verify_ddi_phy_power_wells(dev_priv);
> }
>
> @@ -2170,7 +2170,7 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> max_dc = 2;
> mask = 0;
> - } else if (IS_BROXTON(dev_priv)) {
> + } else if (IS_GEN9_LP(dev_priv)) {
> max_dc = 1;
> /*
> * DC9 has a separate HW flow from the rest of the DC states,
> --
> 2.5.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH v3] drm/i915/glk: Reuse broxton code for geminilake
2016-12-02 1:06 ` Rodrigo Vivi
@ 2016-12-02 8:27 ` Ander Conselvan De Oliveira
2016-12-02 18:46 ` Vivi, Rodrigo
0 siblings, 1 reply; 52+ messages in thread
From: Ander Conselvan De Oliveira @ 2016-12-02 8:27 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, Rodrigo Vivi
On Thu, 2016-12-01 at 17:06 -0800, Rodrigo Vivi wrote:
> A reviewed backwards because I was willing to check if all ifs were in place.
>
> I missed the ones from i915_drv.c
>
> *** i915_drv.c:
> i915_drm_suspend_late[1500] fw_csr = !IS_GEN9_LP(dev_priv) &&
> i915_drm_suspend_late[1513] if (IS_GEN9_LP(dev_priv))
> i915_drm_resume_early[1721] if (IS_GEN9_LP(dev_priv)) {
> i915_drm_resume_early[1731] if (IS_GEN9_LP(dev_priv) ||
> intel_runtime_suspend[2354] if (IS_GEN9_LP(dev_priv)) {
> intel_runtime_resume[2439] if (IS_GEN9_LP(dev_priv)) {
>
> The ones that I had added with the patch
> "drm/i915/glk: Add missing bits to allow runtime pm suspend on GLK."
>
> Feel free to squash all those into this patch if you like. However I believe
> that before that one we need Anusha's dmc load patch that is one that I'm also
> missing on this series here, right?
>
> So any option works for me and if you decide to move with this feel free to
> use
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> And please let me know what are your plans with this runtime_pm related
> patches and if you need anything from me.
I was planning to do those as a follow up once this series is merged. I didn't
want to make it any bigger to make review easier.
Ander
>
> Thanks,
> Rodrigo.
>
> On Tue, Nov 29, 2016 at 05:47:12PM +0200, Ander Conselvan de Oliveira wrote:
> >
> > Geminilake is mostly backwards compatible with broxton, so change most
> > of the IS_BROXTON() checks to IS_GEN9_LP(). Differences between the
> > platforms will be implemented in follow-up patches.
> >
> > v2: Don't reuse broxton's path in intel_update_max_cdclk().
> > Don't set plane count as in broxton.
> >
> > v3: Rebase
> >
> > v4: Include the check intel_bios_is_port_hpd_inverted().
> > Commit message.
> >
> > v5: Leave i915_dmc_info() out; glk's csr version != bxt's. (Rodrigo)
> >
> > v6: Rebase.
> >
> > v7: Convert a few mode IS_BROXTON() occurances in pps, ddi, dsi and pll
> > code. (Rodrigo)
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@inte
> > l.com>
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 10 +++++-----
> > drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++----
> > drivers/gpu/drm/i915/i915_irq.c | 10 +++++-----
> > drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> > drivers/gpu/drm/i915/intel_bios.c | 2 +-
> > drivers/gpu/drm/i915/intel_ddi.c | 18 +++++++++---------
> > drivers/gpu/drm/i915/intel_display.c | 12 ++++++------
> > drivers/gpu/drm/i915/intel_dp.c | 24 ++++++++++++------------
> > drivers/gpu/drm/i915/intel_dpio_phy.c | 1 -
> > drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
> > drivers/gpu/drm/i915/intel_dsi.c | 30 +++++++++++++++---------------
> > drivers/gpu/drm/i915/intel_dsi_pll.c | 12 ++++++------
> > drivers/gpu/drm/i915/intel_hdmi.c | 6 +++---
> > drivers/gpu/drm/i915/intel_i2c.c | 4 ++--
> > drivers/gpu/drm/i915/intel_mocs.c | 2 +-
> > drivers/gpu/drm/i915/intel_panel.c | 2 +-
> > drivers/gpu/drm/i915/intel_pm.c | 6 +++---
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
> > 18 files changed, 79 insertions(+), 80 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 8eb8c29..6c17d39 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -1108,7 +1108,7 @@ static int i915_frequency_info(struct seq_file *m,
> > void *unused)
> > int max_freq;
> >
> > rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
> > - if (IS_BROXTON(dev_priv)) {
> > + if (IS_GEN9_LP(dev_priv)) {
> > rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
> > gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
> > } else {
> > @@ -1204,7 +1204,7 @@ static int i915_frequency_info(struct seq_file *m,
> > void *unused)
> > seq_printf(m, "Down threshold: %d%%\n",
> > dev_priv->rps.down_threshold);
> >
> > - max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
> > + max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
> > rp_state_cap >> 16) & 0xff;
> > max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)
> > ?
> > GEN9_FREQ_SCALER : 1);
> > @@ -1217,7 +1217,7 @@ static int i915_frequency_info(struct seq_file *m,
> > void *unused)
> > seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
> > intel_gpu_freq(dev_priv, max_freq));
> >
> > - max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
> > + max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
> > rp_state_cap >> 0) & 0xff;
> > max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)
> > ?
> > GEN9_FREQ_SCALER : 1);
> > @@ -5169,7 +5169,7 @@ static void gen9_sseu_device_status(struct
> > drm_i915_private *dev_priv,
> > u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
> >
> > /* BXT has a single slice and at most 3 subslices. */
> > - if (IS_BROXTON(dev_priv)) {
> > + if (IS_GEN9_LP(dev_priv)) {
> > s_max = 1;
> > ss_max = 3;
> > }
> > @@ -5203,7 +5203,7 @@ static void gen9_sseu_device_status(struct
> > drm_i915_private *dev_priv,
> > for (ss = 0; ss < ss_max; ss++) {
> > unsigned int eu_cnt;
> >
> > - if (IS_BROXTON(dev_priv)) {
> > + if (IS_GEN9_LP(dev_priv)) {
> > if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> > /* skip disabled subslice */
> > continue;
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > index 6cee707..e721a6f 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > @@ -372,7 +372,7 @@ static void kunmap_page_dma(struct drm_i915_private
> > *dev_priv, void *vaddr)
> > /* There are only few exceptions for gen >=6. chv and bxt.
> > * And we are not sure about the latter so play safe for now.
> > */
> > - if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> > + if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
> > drm_clflush_virt_range(vaddr, PAGE_SIZE);
> >
> > kunmap_atomic(vaddr);
> > @@ -2940,7 +2940,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt,
> > u64 size)
> > * resort to an uncached mapping. The WC issue is easily caught by
> > the
> > * readback check when writing GTT PTE entries.
> > */
> > - if (IS_BROXTON(dev_priv))
> > + if (IS_GEN9_LP(dev_priv))
> > ggtt->gsm = ioremap_nocache(phys_addr, size);
> > else
> > ggtt->gsm = ioremap_wc(phys_addr, size);
> > @@ -3070,7 +3070,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
> >
> > ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
> >
> > - if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> > + if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
> > chv_setup_private_ppat(dev_priv);
> > else
> > bdw_setup_private_ppat(dev_priv);
> > @@ -3310,7 +3310,7 @@ void i915_gem_restore_gtt_mappings(struct
> > drm_i915_private *dev_priv)
> > ggtt->base.closed = false;
> >
> > if (INTEL_GEN(dev_priv) >= 8) {
> > - if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> > + if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
> > chv_setup_private_ppat(dev_priv);
> > else
> > bdw_setup_private_ppat(dev_priv);
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 0b119b9..a0e70f5 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -2435,7 +2435,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv,
> > u32 master_ctl)
> > found = true;
> > }
> >
> > - if (IS_BROXTON(dev_priv)) {
> > + if (IS_GEN9_LP(dev_priv)) {
> > tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
> > if (tmp_mask) {
> > bxt_hpd_irq_handler(dev_priv,
> > tmp_mask,
> > @@ -2451,7 +2451,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv,
> > u32 master_ctl)
> > }
> > }
> >
> > - if (IS_BROXTON(dev_priv) && (iir &
> > BXT_DE_PORT_GMBUS)) {
> > + if (IS_GEN9_LP(dev_priv) && (iir &
> > BXT_DE_PORT_GMBUS)) {
> > gmbus_irq_handler(dev_priv);
> > found = true;
> > }
> > @@ -3375,7 +3375,7 @@ static void gen8_de_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
> > de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
> > GEN9_AUX_CHANNEL_D;
> > - if (IS_BROXTON(dev_priv))
> > + if (IS_GEN9_LP(dev_priv))
> > de_port_masked |= BXT_DE_PORT_GMBUS;
> > } else {
> > de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
> > @@ -3386,7 +3386,7 @@ static void gen8_de_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > GEN8_PIPE_FIFO_UNDERRUN;
> >
> > de_port_enables = de_port_masked;
> > - if (IS_BROXTON(dev_priv))
> > + if (IS_GEN9_LP(dev_priv))
> > de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
> > else if (IS_BROADWELL(dev_priv))
> > de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
> > @@ -4211,7 +4211,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> > dev->driver->irq_uninstall = gen8_irq_uninstall;
> > dev->driver->enable_vblank = gen8_enable_vblank;
> > dev->driver->disable_vblank = gen8_disable_vblank;
> > - if (IS_BROXTON(dev_priv))
> > + if (IS_GEN9_LP(dev_priv))
> > dev_priv->display.hpd_irq_setup =
> > bxt_hpd_irq_setup;
> > else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
> > dev_priv->display.hpd_irq_setup =
> > spt_hpd_irq_setup;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 6747d68..1dec207 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3256,7 +3256,7 @@ enum skl_disp_power_wells {
> > #define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
> > #define INTERVAL_0_833_US(us) (((us) * 6) / 5)
> > #define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
> > - (IS_BROXTON(dev_priv) ? \
> > + (IS_GEN9_LP(dev_priv) ? \
> > INTERVAL_0_833_US(us) : \
> > INTERVAL_1_33_US(us)) : \
> > INTERVAL_1_28_US(us))
> > @@ -3265,7 +3265,7 @@ enum skl_disp_power_wells {
> > #define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3)
> > #define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6)
> > #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN9(dev_priv) ? \
> > - (IS_BROXTON(dev_priv) ? \
> > + (IS_GEN9_LP(dev_priv) ? \
> > INTERVAL_0_833_TO_US(interval) : \
> > INTERVAL_1_33_TO_US(interval)) : \
> > INTERVAL_1_28_TO_US(interval))
> > diff --git a/drivers/gpu/drm/i915/intel_bios.c
> > b/drivers/gpu/drm/i915/intel_bios.c
> > index 7ffab1a..eaade27 100644
> > --- a/drivers/gpu/drm/i915/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/intel_bios.c
> > @@ -1779,7 +1779,7 @@ intel_bios_is_port_hpd_inverted(struct
> > drm_i915_private *dev_priv,
> > {
> > int i;
> >
> > - if (WARN_ON_ONCE(!IS_BROXTON(dev_priv)))
> > + if (WARN_ON_ONCE(!IS_GEN9_LP(dev_priv)))
> > return false;
> >
> > for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index f8e939d..3133e57 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -442,7 +442,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private
> > *dev_priv, enum port por
> >
> > hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
> >
> > - if (IS_BROXTON(dev_priv))
> > + if (IS_GEN9_LP(dev_priv))
> > return hdmi_level;
> >
> > if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> > @@ -484,7 +484,7 @@ void intel_prepare_dp_ddi_buffers(struct intel_encoder
> > *encoder)
> > const struct ddi_buf_trans *ddi_translations_edp;
> > const struct ddi_buf_trans *ddi_translations;
> >
> > - if (IS_BROXTON(dev_priv))
> > + if (IS_GEN9_LP(dev_priv))
> > return;
> >
> > if (IS_KABYLAKE(dev_priv)) {
> > @@ -567,7 +567,7 @@ static void intel_prepare_hdmi_ddi_buffers(struct
> > intel_encoder *encoder)
> > enum port port = intel_ddi_get_encoder_port(encoder);
> > const struct ddi_buf_trans *ddi_translations_hdmi;
> >
> > - if (IS_BROXTON(dev_priv))
> > + if (IS_GEN9_LP(dev_priv))
> > return;
> >
> > hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
> > @@ -1091,7 +1091,7 @@ void intel_ddi_clock_get(struct intel_encoder
> > *encoder,
> > hsw_ddi_clock_get(encoder, pipe_config);
> > else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> > skl_ddi_clock_get(encoder, pipe_config);
> > - else if (IS_BROXTON(dev_priv))
> > + else if (IS_GEN9_LP(dev_priv))
> > bxt_ddi_clock_get(encoder, pipe_config);
> > }
> >
> > @@ -1153,7 +1153,7 @@ bool intel_ddi_pll_select(struct intel_crtc
> > *intel_crtc,
> > if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> > return skl_ddi_pll_select(intel_crtc, crtc_state,
> > intel_encoder);
> > - else if (IS_BROXTON(dev_priv))
> > + else if (IS_GEN9_LP(dev_priv))
> > return bxt_ddi_pll_select(intel_crtc, crtc_state,
> > intel_encoder);
> > else
> > @@ -1643,7 +1643,7 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
> >
> > if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> > skl_ddi_set_iboost(encoder, level);
> > - else if (IS_BROXTON(dev_priv))
> > + else if (IS_GEN9_LP(dev_priv))
> > bxt_ddi_vswing_sequence(dev_priv, level, port, encoder-
> > >type);
> >
> > return DDI_BUF_TRANS_SELECT(level);
> > @@ -1716,7 +1716,7 @@ static void intel_ddi_pre_enable_hdmi(struct
> > intel_encoder *encoder,
> > intel_prepare_hdmi_ddi_buffers(encoder);
> > if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> > skl_ddi_set_iboost(encoder, level);
> > - else if (IS_BROXTON(dev_priv))
> > + else if (IS_GEN9_LP(dev_priv))
> > bxt_ddi_vswing_sequence(dev_priv, level, port,
> > INTEL_OUTPUT_HDMI);
> >
> > @@ -2127,7 +2127,7 @@ intel_ddi_get_link_dpll(struct intel_dp *intel_dp, int
> > clock)
> > struct intel_shared_dpll_config tmp_pll_config;
> > enum intel_dpll_id dpll_id;
> >
> > - if (IS_BROXTON(dev_priv)) {
> > + if (IS_GEN9_LP(dev_priv)) {
> > dpll_id = (enum intel_dpll_id)dig_port->port;
> > /*
> > * Select the required PLL. This works for platforms where
> > @@ -2244,7 +2244,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> > enum port port)
> > * configuration so that we use the proper lane count for our
> > * calculations.
> > */
> > - if (IS_BROXTON(dev_priv) && port == PORT_A) {
> > + if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
> > if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
> > DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES
> > for port A; fixing\n");
> > intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 15f48a0..418941b 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -614,12 +614,12 @@ static bool intel_PLL_is_valid(struct drm_i915_private
> > *dev_priv,
> > INTELPllInvalid("m1 out of range\n");
> >
> > if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
> > - !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
> > + !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
> > if (clock->m1 <= clock->m2)
> > INTELPllInvalid("m1 <= m2\n");
> >
> > if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> > - !IS_BROXTON(dev_priv)) {
> > + !IS_GEN9_LP(dev_priv)) {
> > if (clock->p < limit->p.min || limit->p.max < clock->p)
> > INTELPllInvalid("p out of range\n");
> > if (clock->m < limit->m.min || limit->m.max < clock->m)
> > @@ -10641,7 +10641,7 @@ static void haswell_get_ddi_port_state(struct
> > intel_crtc *crtc,
> >
> > if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> > skylake_get_ddi_pll(dev_priv, port, pipe_config);
> > - else if (IS_BROXTON(dev_priv))
> > + else if (IS_GEN9_LP(dev_priv))
> > bxt_get_ddi_pll(dev_priv, port, pipe_config);
> > else
> > haswell_get_ddi_pll(dev_priv, port, pipe_config);
> > @@ -10686,7 +10686,7 @@ static bool haswell_get_pipe_config(struct
> > intel_crtc *crtc,
> >
> > active = hsw_get_transcoder_state(crtc, pipe_config,
> > &power_domain_mask);
> >
> > - if (IS_BROXTON(dev_priv) &&
> > + if (IS_GEN9_LP(dev_priv) &&
> > bxt_get_dsi_transcoder_state(crtc, pipe_config,
> > &power_domain_mask)) {
> > WARN_ON(active);
> > active = true;
> > @@ -12784,7 +12784,7 @@ static void intel_dump_pipe_config(struct intel_crtc
> > *crtc,
> > DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
> > pipe_config->ips_enabled, pipe_config->double_wide);
> >
> > - if (IS_BROXTON(dev_priv)) {
> > + if (IS_GEN9_LP(dev_priv)) {
> > DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
> > "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3:
> > 0x%x, "
> > "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10:
> > 0x%x, pcsdw12: 0x%x\n",
> > @@ -15478,7 +15478,7 @@ void intel_pps_unlock_regs_wa(struct
> > drm_i915_private *dev_priv)
> >
> > static void intel_pps_init(struct drm_i915_private *dev_priv)
> > {
> > - if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
> > + if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
> > dev_priv->pps_mmio_base = PCH_PPS_BASE;
> > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > dev_priv->pps_mmio_base = VLV_PPS_BASE;
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 9dfbde4..1f2420c 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -233,7 +233,7 @@ intel_dp_source_rates(struct intel_dp *intel_dp, const
> > int **source_rates)
> > struct drm_i915_private *dev_priv = to_i915(dig_port-
> > >base.base.dev);
> > int size;
> >
> > - if (IS_BROXTON(dev_priv)) {
> > + if (IS_GEN9_LP(dev_priv)) {
> > *source_rates = bxt_rates;
> > size = ARRAY_SIZE(bxt_rates);
> > } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> > @@ -645,7 +645,7 @@ void intel_power_sequencer_reset(struct drm_i915_private
> > *dev_priv)
> > struct intel_encoder *encoder;
> >
> > if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> > - !IS_BROXTON(dev_priv)))
> > + !IS_GEN9_LP(dev_priv)))
> > return;
> >
> > /*
> > @@ -665,7 +665,7 @@ void intel_power_sequencer_reset(struct drm_i915_private
> > *dev_priv)
> > continue;
> >
> > intel_dp = enc_to_intel_dp(&encoder->base);
> > - if (IS_BROXTON(dev_priv))
> > + if (IS_GEN9_LP(dev_priv))
> > intel_dp->pps_reset = true;
> > else
> > intel_dp->pps_pipe = INVALID_PIPE;
> > @@ -688,7 +688,7 @@ static void intel_pps_get_registers(struct
> > drm_i915_private *dev_priv,
> >
> > memset(regs, 0, sizeof(*regs));
> >
> > - if (IS_BROXTON(dev_priv))
> > + if (IS_GEN9_LP(dev_priv))
> > pps_idx = bxt_power_sequencer_idx(intel_dp);
> > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > pps_idx = vlv_power_sequencer_pipe(intel_dp);
> > @@ -697,7 +697,7 @@ static void intel_pps_get_registers(struct
> > drm_i915_private *dev_priv,
> > regs->pp_stat = PP_STATUS(pps_idx);
> > regs->pp_on = PP_ON_DELAYS(pps_idx);
> > regs->pp_off = PP_OFF_DELAYS(pps_idx);
> > - if (!IS_BROXTON(dev_priv))
> > + if (!IS_GEN9_LP(dev_priv))
> > regs->pp_div = PP_DIVISOR(pps_idx);
> > }
> >
> > @@ -2984,7 +2984,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
> > struct drm_i915_private *dev_priv =
> > to_i915(intel_dp_to_dev(intel_dp));
> > enum port port = dp_to_dig_port(intel_dp)->port;
> >
> > - if (IS_BROXTON(dev_priv))
> > + if (IS_GEN9_LP(dev_priv))
> > return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> > else if (INTEL_GEN(dev_priv) >= 9) {
> > if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
> > @@ -4300,7 +4300,7 @@ static bool intel_digital_port_connected(struct
> > drm_i915_private *dev_priv,
> > return ibx_digital_port_connected(dev_priv, port);
> > else if (HAS_PCH_SPLIT(dev_priv))
> > return cpt_digital_port_connected(dev_priv, port);
> > - else if (IS_BROXTON(dev_priv))
> > + else if (IS_GEN9_LP(dev_priv))
> > return bxt_digital_port_connected(dev_priv, port);
> > else if (IS_GM45(dev_priv))
> > return gm45_digital_port_connected(dev_priv, port);
> > @@ -4929,7 +4929,7 @@ intel_pps_readout_hw_state(struct drm_i915_private
> > *dev_priv,
> >
> > pp_on = I915_READ(regs.pp_on);
> > pp_off = I915_READ(regs.pp_off);
> > - if (!IS_BROXTON(dev_priv)) {
> > + if (!IS_GEN9_LP(dev_priv)) {
> > I915_WRITE(regs.pp_ctrl, pp_ctl);
> > pp_div = I915_READ(regs.pp_div);
> > }
> > @@ -4947,7 +4947,7 @@ intel_pps_readout_hw_state(struct drm_i915_private
> > *dev_priv,
> > seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
> > PANEL_POWER_DOWN_DELAY_SHIFT;
> >
> > - if (IS_BROXTON(dev_priv)) {
> > + if (IS_GEN9_LP(dev_priv)) {
> > u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
> > BXT_POWER_CYCLE_DELAY_SHIFT;
> > if (tmp > 0)
> > @@ -5078,7 +5078,7 @@ intel_dp_init_panel_power_sequencer_registers(struct
> > drm_device *dev,
> > (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> > /* Compute the divisor for the pp clock, simply match the Bspec
> > * formula. */
> > - if (IS_BROXTON(dev_priv)) {
> > + if (IS_GEN9_LP(dev_priv)) {
> > pp_div = I915_READ(regs.pp_ctrl);
> > pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
> > pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
> > @@ -5104,7 +5104,7 @@ intel_dp_init_panel_power_sequencer_registers(struct
> > drm_device *dev,
> >
> > I915_WRITE(regs.pp_on, pp_on);
> > I915_WRITE(regs.pp_off, pp_off);
> > - if (IS_BROXTON(dev_priv))
> > + if (IS_GEN9_LP(dev_priv))
> > I915_WRITE(regs.pp_ctrl, pp_div);
> > else
> > I915_WRITE(regs.pp_div, pp_div);
> > @@ -5112,7 +5112,7 @@ intel_dp_init_panel_power_sequencer_registers(struct
> > drm_device *dev,
> > DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x,
> > PP_OFF %#x, PP_DIV %#x\n",
> > I915_READ(regs.pp_on),
> > I915_READ(regs.pp_off),
> > - IS_BROXTON(dev_priv) ?
> > + IS_GEN9_LP(dev_priv) ?
> > (I915_READ(regs.pp_ctrl) &
> > BXT_POWER_CYCLE_DELAY_MASK) :
> > I915_READ(regs.pp_div));
> > }
> > diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c
> > b/drivers/gpu/drm/i915/intel_dpio_phy.c
> > index 7a8e82d..8c62dea 100644
> > --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> > +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> > @@ -317,7 +317,6 @@ static void _bxt_ddi_phy_init(struct drm_i915_private
> > *dev_priv,
> > if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
> > DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
> > "won't reprogram it\n", phy);
> > -
> > return;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > index 58a756f..976d390 100644
> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > @@ -1860,7 +1860,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
> >
> > if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> > dpll_mgr = &skl_pll_mgr;
> > - else if (IS_BROXTON(dev_priv))
> > + else if (IS_GEN9_LP(dev_priv))
> > dpll_mgr = &bxt_pll_mgr;
> > else if (HAS_DDI(dev_priv))
> > dpll_mgr = &hsw_pll_mgr;
> > diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> > b/drivers/gpu/drm/i915/intel_dsi.c
> > index 3bc6213..0668bbe 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > @@ -340,7 +340,7 @@ static bool intel_dsi_compute_config(struct
> > intel_encoder *encoder,
> > /* DSI uses short packets for sync events, so clear mode flags for
> > DSI */
> > adjusted_mode->flags = 0;
> >
> > - if (IS_BROXTON(dev_priv)) {
> > + if (IS_GEN9_LP(dev_priv)) {
> > /* Dual link goes to DSI transcoder A. */
> > if (intel_dsi->ports == BIT(PORT_C))
> > pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
> > @@ -441,7 +441,7 @@ static void intel_dsi_device_ready(struct intel_encoder
> > *encoder)
> >
> > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > vlv_dsi_device_ready(encoder);
> > - else if (IS_BROXTON(dev_priv))
> > + else if (IS_GEN9_LP(dev_priv))
> > bxt_dsi_device_ready(encoder);
> > }
> >
> > @@ -464,7 +464,7 @@ static void intel_dsi_port_enable(struct intel_encoder
> > *encoder)
> > }
> >
> > for_each_dsi_port(port, intel_dsi->ports) {
> > - i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> > + i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
> > BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> > u32 temp;
> >
> > @@ -497,7 +497,7 @@ static void intel_dsi_port_disable(struct intel_encoder
> > *encoder)
> > enum port port;
> >
> > for_each_dsi_port(port, intel_dsi->ports) {
> > - i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> > + i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
> > BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> > u32 temp;
> >
> > @@ -666,7 +666,7 @@ static void intel_dsi_clear_device_ready(struct
> > intel_encoder *encoder)
> > DRM_DEBUG_KMS("\n");
> > for_each_dsi_port(port, intel_dsi->ports) {
> > /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV
> > */
> > - i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> > + i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
> > BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
> > u32 val;
> >
> > @@ -758,12 +758,12 @@ static bool intel_dsi_get_hw_state(struct
> > intel_encoder *encoder,
> > * configuration, otherwise accessing DSI registers will hang the
> > * machine. See BSpec North Display Engine registers/MIPI[BXT].
> > */
> > - if (IS_BROXTON(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
> > + if (IS_GEN9_LP(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
> > goto out_put_power;
> >
> > /* XXX: this only works for one DSI output */
> > for_each_dsi_port(port, intel_dsi->ports) {
> > - i915_reg_t ctrl_reg = IS_BROXTON(dev_priv) ?
> > + i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
> > BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> > bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
> >
> > @@ -788,7 +788,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder
> > *encoder,
> > if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
> > continue;
> >
> > - if (IS_BROXTON(dev_priv)) {
> > + if (IS_GEN9_LP(dev_priv)) {
> > u32 tmp = I915_READ(MIPI_CTRL(port));
> > tmp &= BXT_PIPE_SELECT_MASK;
> > tmp >>= BXT_PIPE_SELECT_SHIFT;
> > @@ -976,7 +976,7 @@ static void intel_dsi_get_config(struct intel_encoder
> > *encoder,
> > u32 pclk;
> > DRM_DEBUG_KMS("\n");
> >
> > - if (IS_BROXTON(dev_priv))
> > + if (IS_GEN9_LP(dev_priv))
> > bxt_dsi_get_pipe_config(encoder, pipe_config);
> >
> > pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
> > @@ -1068,7 +1068,7 @@ static void set_dsi_timings(struct drm_encoder
> > *encoder,
> > hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi-
> > >burst_mode_ratio);
> >
> > for_each_dsi_port(port, intel_dsi->ports) {
> > - if (IS_BROXTON(dev_priv)) {
> > + if (IS_GEN9_LP(dev_priv)) {
> > /*
> > * Program hdisplay and vdisplay on MIPI
> > transcoder.
> > * This is different from calculated hactive and
> > @@ -1155,7 +1155,7 @@ static void intel_dsi_prepare(struct intel_encoder
> > *intel_encoder,
> > tmp &= ~READ_REQUEST_PRIORITY_MASK;
> > I915_WRITE(MIPI_CTRL(port), tmp |
> > READ_REQUEST_PRIORITY_HIGH);
> > - } else if (IS_BROXTON(dev_priv)) {
> > + } else if (IS_GEN9_LP(dev_priv)) {
> > enum pipe pipe = intel_crtc->pipe;
> >
> > tmp = I915_READ(MIPI_CTRL(port));
> > @@ -1193,7 +1193,7 @@ static void intel_dsi_prepare(struct intel_encoder
> > *intel_encoder,
> > if (intel_dsi->clock_stop)
> > tmp |= CLOCKSTOP;
> >
> > - if (IS_BROXTON(dev_priv)) {
> > + if (IS_GEN9_LP(dev_priv)) {
> > tmp |= BXT_DPHY_DEFEATURE_EN;
> > if (!is_cmd_mode(intel_dsi))
> > tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
> > @@ -1244,7 +1244,7 @@ static void intel_dsi_prepare(struct intel_encoder
> > *intel_encoder,
> > I915_WRITE(MIPI_INIT_COUNT(port),
> > txclkesc(intel_dsi->escape_clk_div, 100));
> >
> > - if (IS_BROXTON(dev_priv) && (!intel_dsi->dual_link)) {
> > + if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
> > /*
> > * BXT spec says write MIPI_INIT_COUNT for
> > * both the ports, even if only one is
> > @@ -1454,7 +1454,7 @@ void intel_dsi_init(struct drm_i915_private *dev_priv)
> >
> > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> > dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
> > - } else if (IS_BROXTON(dev_priv)) {
> > + } else if (IS_GEN9_LP(dev_priv)) {
> > dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
> > } else {
> > DRM_ERROR("Unsupported Mipi device to reg base");
> > @@ -1495,7 +1495,7 @@ void intel_dsi_init(struct drm_i915_private *dev_priv)
> > * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI
> > DSI
> > * port C. BXT isn't limited like this.
> > */
> > - if (IS_BROXTON(dev_priv))
> > + if (IS_GEN9_LP(dev_priv))
> > intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) |
> > BIT(PIPE_C);
> > else if (port == PORT_A)
> > intel_encoder->crtc_mask = BIT(PIPE_A);
> > diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
> > b/drivers/gpu/drm/i915/intel_dsi_pll.c
> > index 56eff60..cf8c1b0 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> > @@ -351,7 +351,7 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder
> > *encoder, int pipe_bpp,
> > u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
> > struct intel_crtc_state *config)
> > {
> > - if (IS_BROXTON(to_i915(encoder->base.dev)))
> > + if (IS_GEN9_LP(to_i915(encoder->base.dev)))
> > return bxt_dsi_get_pclk(encoder, pipe_bpp, config);
> > else
> > return vlv_dsi_get_pclk(encoder, pipe_bpp, config);
> > @@ -504,7 +504,7 @@ static void bxt_enable_dsi_pll(struct intel_encoder
> > *encoder,
> >
> > bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
> > {
> > - if (IS_BROXTON(dev_priv))
> > + if (IS_GEN9_LP(dev_priv))
> > return bxt_dsi_pll_is_enabled(dev_priv);
> >
> > MISSING_CASE(INTEL_DEVID(dev_priv));
> > @@ -519,7 +519,7 @@ int intel_compute_dsi_pll(struct intel_encoder *encoder,
> >
> > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > return vlv_compute_dsi_pll(encoder, config);
> > - else if (IS_BROXTON(dev_priv))
> > + else if (IS_GEN9_LP(dev_priv))
> > return bxt_compute_dsi_pll(encoder, config);
> >
> > return -ENODEV;
> > @@ -532,7 +532,7 @@ void intel_enable_dsi_pll(struct intel_encoder *encoder,
> >
> > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > vlv_enable_dsi_pll(encoder, config);
> > - else if (IS_BROXTON(dev_priv))
> > + else if (IS_GEN9_LP(dev_priv))
> > bxt_enable_dsi_pll(encoder, config);
> > }
> >
> > @@ -542,7 +542,7 @@ void intel_disable_dsi_pll(struct intel_encoder
> > *encoder)
> >
> > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > vlv_disable_dsi_pll(encoder);
> > - else if (IS_BROXTON(dev_priv))
> > + else if (IS_GEN9_LP(dev_priv))
> > bxt_disable_dsi_pll(encoder);
> > }
> >
> > @@ -566,7 +566,7 @@ void intel_dsi_reset_clocks(struct intel_encoder
> > *encoder, enum port port)
> > {
> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >
> > - if (IS_BROXTON(dev_priv))
> > + if (IS_GEN9_LP(dev_priv))
> > bxt_dsi_reset_clocks(encoder, port);
> > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > vlv_dsi_reset_clocks(encoder, port);
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> > b/drivers/gpu/drm/i915/intel_hdmi.c
> > index 374e38a..0bcfead 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -1251,7 +1251,7 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
> > return MODE_CLOCK_HIGH;
> >
> > /* BXT DPLL can't generate 223-240 MHz */
> > - if (IS_BROXTON(dev_priv) && clock > 223333 && clock < 240000)
> > + if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
> > return MODE_CLOCK_RANGE;
> >
> > /* CHV DPLL can't generate 216-240 MHz */
> > @@ -1809,13 +1809,13 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private
> > *dev_priv,
> >
> > switch (port) {
> > case PORT_B:
> > - if (IS_BROXTON(dev_priv))
> > + if (IS_GEN9_LP(dev_priv))
> > ddc_pin = GMBUS_PIN_1_BXT;
> > else
> > ddc_pin = GMBUS_PIN_DPB;
> > break;
> > case PORT_C:
> > - if (IS_BROXTON(dev_priv))
> > + if (IS_GEN9_LP(dev_priv))
> > ddc_pin = GMBUS_PIN_2_BXT;
> > else
> > ddc_pin = GMBUS_PIN_DPC;
> > diff --git a/drivers/gpu/drm/i915/intel_i2c.c
> > b/drivers/gpu/drm/i915/intel_i2c.c
> > index 83f260b..1606e31 100644
> > --- a/drivers/gpu/drm/i915/intel_i2c.c
> > +++ b/drivers/gpu/drm/i915/intel_i2c.c
> > @@ -72,7 +72,7 @@ static const struct gmbus_pin gmbus_pins_bxt[] = {
> > static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private
> > *dev_priv,
> > unsigned int pin)
> > {
> > - if (IS_BROXTON(dev_priv))
> > + if (IS_GEN9_LP(dev_priv))
> > return &gmbus_pins_bxt[pin];
> > else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> > return &gmbus_pins_skl[pin];
> > @@ -87,7 +87,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private
> > *dev_priv,
> > {
> > unsigned int size;
> >
> > - if (IS_BROXTON(dev_priv))
> > + if (IS_GEN9_LP(dev_priv))
> > size = ARRAY_SIZE(gmbus_pins_bxt);
> > else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> > size = ARRAY_SIZE(gmbus_pins_skl);
> > diff --git a/drivers/gpu/drm/i915/intel_mocs.c
> > b/drivers/gpu/drm/i915/intel_mocs.c
> > index 80bb924..eed0707 100644
> > --- a/drivers/gpu/drm/i915/intel_mocs.c
> > +++ b/drivers/gpu/drm/i915/intel_mocs.c
> > @@ -182,7 +182,7 @@ static bool get_mocs_settings(struct drm_i915_private
> > *dev_priv,
> > table->size = ARRAY_SIZE(skylake_mocs_table);
> > table->table = skylake_mocs_table;
> > result = true;
> > - } else if (IS_BROXTON(dev_priv)) {
> > + } else if (IS_GEN9_LP(dev_priv)) {
> > table->size = ARRAY_SIZE(broxton_mocs_table);
> > table->table = broxton_mocs_table;
> > result = true;
> > diff --git a/drivers/gpu/drm/i915/intel_panel.c
> > b/drivers/gpu/drm/i915/intel_panel.c
> > index 08ab6d7..3578b40 100644
> > --- a/drivers/gpu/drm/i915/intel_panel.c
> > +++ b/drivers/gpu/drm/i915/intel_panel.c
> > @@ -1756,7 +1756,7 @@ intel_panel_init_backlight_funcs(struct intel_panel
> > *panel)
> > intel_dsi_dcs_init_backlight_funcs(connector) == 0)
> > return;
> >
> > - if (IS_BROXTON(dev_priv)) {
> > + if (IS_GEN9_LP(dev_priv)) {
> > panel->backlight.setup = bxt_setup_backlight;
> > panel->backlight.enable = bxt_enable_backlight;
> > panel->backlight.disable = bxt_disable_backlight;
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 29b6653..0b17a4f 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5208,7 +5208,7 @@ int sanitize_rc6_option(struct drm_i915_private
> > *dev_priv, int enable_rc6)
> > if (!enable_rc6)
> > return 0;
> >
> > - if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
> > + if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
> > DRM_INFO("RC6 disabled by BIOS\n");
> > return 0;
> > }
> > @@ -5242,7 +5242,7 @@ static void gen6_init_rps_frequencies(struct
> > drm_i915_private *dev_priv)
> > /* All of these values are in units of 50MHz */
> >
> > /* static values from HW: RP0 > RP1 > RPn (min_freq) */
> > - if (IS_BROXTON(dev_priv)) {
> > + if (IS_GEN9_LP(dev_priv)) {
> > u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
> > dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
> > dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
> > @@ -7622,7 +7622,7 @@ void intel_init_clock_gating_hooks(struct
> > drm_i915_private *dev_priv)
> > dev_priv->display.init_clock_gating =
> > skylake_init_clock_gating;
> > else if (IS_KABYLAKE(dev_priv))
> > dev_priv->display.init_clock_gating =
> > kabylake_init_clock_gating;
> > - else if (IS_BROXTON(dev_priv))
> > + else if (IS_GEN9_LP(dev_priv))
> > dev_priv->display.init_clock_gating =
> > bxt_init_clock_gating;
> > else if (IS_BROADWELL(dev_priv))
> > dev_priv->display.init_clock_gating =
> > broadwell_init_clock_gating;
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 356c662..66ab1c8 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -530,7 +530,7 @@ static u32 gen9_dc_mask(struct drm_i915_private
> > *dev_priv)
> > u32 mask;
> >
> > mask = DC_STATE_EN_UPTO_DC5;
> > - if (IS_BROXTON(dev_priv))
> > + if (IS_GEN9_LP(dev_priv))
> > mask |= DC_STATE_EN_DC9;
> > else
> > mask |= DC_STATE_EN_UPTO_DC6;
> > @@ -911,7 +911,7 @@ static void gen9_dc_off_power_well_enable(struct
> > drm_i915_private *dev_priv,
> >
> > gen9_assert_dbuf_enabled(dev_priv);
> >
> > - if (IS_BROXTON(dev_priv))
> > + if (IS_GEN9_LP(dev_priv))
> > bxt_verify_ddi_phy_power_wells(dev_priv);
> > }
> >
> > @@ -2170,7 +2170,7 @@ static uint32_t get_allowed_dc_mask(const struct
> > drm_i915_private *dev_priv,
> > if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> > max_dc = 2;
> > mask = 0;
> > - } else if (IS_BROXTON(dev_priv)) {
> > + } else if (IS_GEN9_LP(dev_priv)) {
> > max_dc = 1;
> > /*
> > * DC9 has a separate HW flow from the rest of the DC
> > states,
> > --
> > 2.5.5
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH v3] drm/i915/glk: Reuse broxton code for geminilake
2016-12-02 8:27 ` Ander Conselvan De Oliveira
@ 2016-12-02 18:46 ` Vivi, Rodrigo
0 siblings, 0 replies; 52+ messages in thread
From: Vivi, Rodrigo @ 2016-12-02 18:46 UTC (permalink / raw)
To: conselvan2; +Cc: intel-gfx
On Fri, 2016-12-02 at 10:27 +0200, Ander Conselvan De Oliveira wrote:
> On Thu, 2016-12-01 at 17:06 -0800, Rodrigo Vivi wrote:
> > A reviewed backwards because I was willing to check if all ifs were in place.
> >
> > I missed the ones from i915_drv.c
> >
> > *** i915_drv.c:
> > i915_drm_suspend_late[1500] fw_csr = !IS_GEN9_LP(dev_priv) &&
> > i915_drm_suspend_late[1513] if (IS_GEN9_LP(dev_priv))
> > i915_drm_resume_early[1721] if (IS_GEN9_LP(dev_priv)) {
> > i915_drm_resume_early[1731] if (IS_GEN9_LP(dev_priv) ||
> > intel_runtime_suspend[2354] if (IS_GEN9_LP(dev_priv)) {
> > intel_runtime_resume[2439] if (IS_GEN9_LP(dev_priv)) {
> >
> > The ones that I had added with the patch
> > "drm/i915/glk: Add missing bits to allow runtime pm suspend on GLK."
> >
> > Feel free to squash all those into this patch if you like. However I believe
> > that before that one we need Anusha's dmc load patch that is one that I'm also
> > missing on this series here, right?
> >
> > So any option works for me and if you decide to move with this feel free to
> > use
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >
> > And please let me know what are your plans with this runtime_pm related
> > patches and if you need anything from me.
>
> I was planning to do those as a follow up once this series is merged. I didn't
> want to make it any bigger to make review easier.
yep. Makes sense. Good idea.
>
> Ander
>
> >
> > Thanks,
> > Rodrigo.
> >
> > On Tue, Nov 29, 2016 at 05:47:12PM +0200, Ander Conselvan de Oliveira wrote:
> > >
> > > Geminilake is mostly backwards compatible with broxton, so change most
> > > of the IS_BROXTON() checks to IS_GEN9_LP(). Differences between the
> > > platforms will be implemented in follow-up patches.
> > >
> > > v2: Don't reuse broxton's path in intel_update_max_cdclk().
> > > Don't set plane count as in broxton.
> > >
> > > v3: Rebase
> > >
> > > v4: Include the check intel_bios_is_port_hpd_inverted().
> > > Commit message.
> > >
> > > v5: Leave i915_dmc_info() out; glk's csr version != bxt's. (Rodrigo)
> > >
> > > v6: Rebase.
> > >
> > > v7: Convert a few mode IS_BROXTON() occurances in pps, ddi, dsi and pll
> > > code. (Rodrigo)
> > >
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@inte
> > > l.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_debugfs.c | 10 +++++-----
> > > drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++----
> > > drivers/gpu/drm/i915/i915_irq.c | 10 +++++-----
> > > drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> > > drivers/gpu/drm/i915/intel_bios.c | 2 +-
> > > drivers/gpu/drm/i915/intel_ddi.c | 18 +++++++++---------
> > > drivers/gpu/drm/i915/intel_display.c | 12 ++++++------
> > > drivers/gpu/drm/i915/intel_dp.c | 24 ++++++++++++------------
> > > drivers/gpu/drm/i915/intel_dpio_phy.c | 1 -
> > > drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
> > > drivers/gpu/drm/i915/intel_dsi.c | 30 +++++++++++++++---------------
> > > drivers/gpu/drm/i915/intel_dsi_pll.c | 12 ++++++------
> > > drivers/gpu/drm/i915/intel_hdmi.c | 6 +++---
> > > drivers/gpu/drm/i915/intel_i2c.c | 4 ++--
> > > drivers/gpu/drm/i915/intel_mocs.c | 2 +-
> > > drivers/gpu/drm/i915/intel_panel.c | 2 +-
> > > drivers/gpu/drm/i915/intel_pm.c | 6 +++---
> > > drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
> > > 18 files changed, 79 insertions(+), 80 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > > b/drivers/gpu/drm/i915/i915_debugfs.c
> > > index 8eb8c29..6c17d39 100644
> > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > @@ -1108,7 +1108,7 @@ static int i915_frequency_info(struct seq_file *m,
> > > void *unused)
> > > int max_freq;
> > >
> > > rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
> > > - if (IS_BROXTON(dev_priv)) {
> > > + if (IS_GEN9_LP(dev_priv)) {
> > > rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
> > > gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
> > > } else {
> > > @@ -1204,7 +1204,7 @@ static int i915_frequency_info(struct seq_file *m,
> > > void *unused)
> > > seq_printf(m, "Down threshold: %d%%\n",
> > > dev_priv->rps.down_threshold);
> > >
> > > - max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
> > > + max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
> > > rp_state_cap >> 16) & 0xff;
> > > max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)
> > > ?
> > > GEN9_FREQ_SCALER : 1);
> > > @@ -1217,7 +1217,7 @@ static int i915_frequency_info(struct seq_file *m,
> > > void *unused)
> > > seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
> > > intel_gpu_freq(dev_priv, max_freq));
> > >
> > > - max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
> > > + max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
> > > rp_state_cap >> 0) & 0xff;
> > > max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)
> > > ?
> > > GEN9_FREQ_SCALER : 1);
> > > @@ -5169,7 +5169,7 @@ static void gen9_sseu_device_status(struct
> > > drm_i915_private *dev_priv,
> > > u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
> > >
> > > /* BXT has a single slice and at most 3 subslices. */
> > > - if (IS_BROXTON(dev_priv)) {
> > > + if (IS_GEN9_LP(dev_priv)) {
> > > s_max = 1;
> > > ss_max = 3;
> > > }
> > > @@ -5203,7 +5203,7 @@ static void gen9_sseu_device_status(struct
> > > drm_i915_private *dev_priv,
> > > for (ss = 0; ss < ss_max; ss++) {
> > > unsigned int eu_cnt;
> > >
> > > - if (IS_BROXTON(dev_priv)) {
> > > + if (IS_GEN9_LP(dev_priv)) {
> > > if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> > > /* skip disabled subslice */
> > > continue;
> > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > index 6cee707..e721a6f 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > @@ -372,7 +372,7 @@ static void kunmap_page_dma(struct drm_i915_private
> > > *dev_priv, void *vaddr)
> > > /* There are only few exceptions for gen >=6. chv and bxt.
> > > * And we are not sure about the latter so play safe for now.
> > > */
> > > - if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> > > + if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
> > > drm_clflush_virt_range(vaddr, PAGE_SIZE);
> > >
> > > kunmap_atomic(vaddr);
> > > @@ -2940,7 +2940,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt,
> > > u64 size)
> > > * resort to an uncached mapping. The WC issue is easily caught by
> > > the
> > > * readback check when writing GTT PTE entries.
> > > */
> > > - if (IS_BROXTON(dev_priv))
> > > + if (IS_GEN9_LP(dev_priv))
> > > ggtt->gsm = ioremap_nocache(phys_addr, size);
> > > else
> > > ggtt->gsm = ioremap_wc(phys_addr, size);
> > > @@ -3070,7 +3070,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
> > >
> > > ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
> > >
> > > - if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> > > + if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
> > > chv_setup_private_ppat(dev_priv);
> > > else
> > > bdw_setup_private_ppat(dev_priv);
> > > @@ -3310,7 +3310,7 @@ void i915_gem_restore_gtt_mappings(struct
> > > drm_i915_private *dev_priv)
> > > ggtt->base.closed = false;
> > >
> > > if (INTEL_GEN(dev_priv) >= 8) {
> > > - if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> > > + if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
> > > chv_setup_private_ppat(dev_priv);
> > > else
> > > bdw_setup_private_ppat(dev_priv);
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > b/drivers/gpu/drm/i915/i915_irq.c
> > > index 0b119b9..a0e70f5 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -2435,7 +2435,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv,
> > > u32 master_ctl)
> > > found = true;
> > > }
> > >
> > > - if (IS_BROXTON(dev_priv)) {
> > > + if (IS_GEN9_LP(dev_priv)) {
> > > tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
> > > if (tmp_mask) {
> > > bxt_hpd_irq_handler(dev_priv,
> > > tmp_mask,
> > > @@ -2451,7 +2451,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv,
> > > u32 master_ctl)
> > > }
> > > }
> > >
> > > - if (IS_BROXTON(dev_priv) && (iir &
> > > BXT_DE_PORT_GMBUS)) {
> > > + if (IS_GEN9_LP(dev_priv) && (iir &
> > > BXT_DE_PORT_GMBUS)) {
> > > gmbus_irq_handler(dev_priv);
> > > found = true;
> > > }
> > > @@ -3375,7 +3375,7 @@ static void gen8_de_irq_postinstall(struct
> > > drm_i915_private *dev_priv)
> > > GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
> > > de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
> > > GEN9_AUX_CHANNEL_D;
> > > - if (IS_BROXTON(dev_priv))
> > > + if (IS_GEN9_LP(dev_priv))
> > > de_port_masked |= BXT_DE_PORT_GMBUS;
> > > } else {
> > > de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
> > > @@ -3386,7 +3386,7 @@ static void gen8_de_irq_postinstall(struct
> > > drm_i915_private *dev_priv)
> > > GEN8_PIPE_FIFO_UNDERRUN;
> > >
> > > de_port_enables = de_port_masked;
> > > - if (IS_BROXTON(dev_priv))
> > > + if (IS_GEN9_LP(dev_priv))
> > > de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
> > > else if (IS_BROADWELL(dev_priv))
> > > de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
> > > @@ -4211,7 +4211,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> > > dev->driver->irq_uninstall = gen8_irq_uninstall;
> > > dev->driver->enable_vblank = gen8_enable_vblank;
> > > dev->driver->disable_vblank = gen8_disable_vblank;
> > > - if (IS_BROXTON(dev_priv))
> > > + if (IS_GEN9_LP(dev_priv))
> > > dev_priv->display.hpd_irq_setup =
> > > bxt_hpd_irq_setup;
> > > else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
> > > dev_priv->display.hpd_irq_setup =
> > > spt_hpd_irq_setup;
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 6747d68..1dec207 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -3256,7 +3256,7 @@ enum skl_disp_power_wells {
> > > #define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
> > > #define INTERVAL_0_833_US(us) (((us) * 6) / 5)
> > > #define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
> > > - (IS_BROXTON(dev_priv) ? \
> > > + (IS_GEN9_LP(dev_priv) ? \
> > > INTERVAL_0_833_US(us) : \
> > > INTERVAL_1_33_US(us)) : \
> > > INTERVAL_1_28_US(us))
> > > @@ -3265,7 +3265,7 @@ enum skl_disp_power_wells {
> > > #define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3)
> > > #define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6)
> > > #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN9(dev_priv) ? \
> > > - (IS_BROXTON(dev_priv) ? \
> > > + (IS_GEN9_LP(dev_priv) ? \
> > > INTERVAL_0_833_TO_US(interval) : \
> > > INTERVAL_1_33_TO_US(interval)) : \
> > > INTERVAL_1_28_TO_US(interval))
> > > diff --git a/drivers/gpu/drm/i915/intel_bios.c
> > > b/drivers/gpu/drm/i915/intel_bios.c
> > > index 7ffab1a..eaade27 100644
> > > --- a/drivers/gpu/drm/i915/intel_bios.c
> > > +++ b/drivers/gpu/drm/i915/intel_bios.c
> > > @@ -1779,7 +1779,7 @@ intel_bios_is_port_hpd_inverted(struct
> > > drm_i915_private *dev_priv,
> > > {
> > > int i;
> > >
> > > - if (WARN_ON_ONCE(!IS_BROXTON(dev_priv)))
> > > + if (WARN_ON_ONCE(!IS_GEN9_LP(dev_priv)))
> > > return false;
> > >
> > > for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
> > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > > b/drivers/gpu/drm/i915/intel_ddi.c
> > > index f8e939d..3133e57 100644
> > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > @@ -442,7 +442,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private
> > > *dev_priv, enum port por
> > >
> > > hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
> > >
> > > - if (IS_BROXTON(dev_priv))
> > > + if (IS_GEN9_LP(dev_priv))
> > > return hdmi_level;
> > >
> > > if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> > > @@ -484,7 +484,7 @@ void intel_prepare_dp_ddi_buffers(struct intel_encoder
> > > *encoder)
> > > const struct ddi_buf_trans *ddi_translations_edp;
> > > const struct ddi_buf_trans *ddi_translations;
> > >
> > > - if (IS_BROXTON(dev_priv))
> > > + if (IS_GEN9_LP(dev_priv))
> > > return;
> > >
> > > if (IS_KABYLAKE(dev_priv)) {
> > > @@ -567,7 +567,7 @@ static void intel_prepare_hdmi_ddi_buffers(struct
> > > intel_encoder *encoder)
> > > enum port port = intel_ddi_get_encoder_port(encoder);
> > > const struct ddi_buf_trans *ddi_translations_hdmi;
> > >
> > > - if (IS_BROXTON(dev_priv))
> > > + if (IS_GEN9_LP(dev_priv))
> > > return;
> > >
> > > hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
> > > @@ -1091,7 +1091,7 @@ void intel_ddi_clock_get(struct intel_encoder
> > > *encoder,
> > > hsw_ddi_clock_get(encoder, pipe_config);
> > > else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> > > skl_ddi_clock_get(encoder, pipe_config);
> > > - else if (IS_BROXTON(dev_priv))
> > > + else if (IS_GEN9_LP(dev_priv))
> > > bxt_ddi_clock_get(encoder, pipe_config);
> > > }
> > >
> > > @@ -1153,7 +1153,7 @@ bool intel_ddi_pll_select(struct intel_crtc
> > > *intel_crtc,
> > > if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> > > return skl_ddi_pll_select(intel_crtc, crtc_state,
> > > intel_encoder);
> > > - else if (IS_BROXTON(dev_priv))
> > > + else if (IS_GEN9_LP(dev_priv))
> > > return bxt_ddi_pll_select(intel_crtc, crtc_state,
> > > intel_encoder);
> > > else
> > > @@ -1643,7 +1643,7 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
> > >
> > > if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> > > skl_ddi_set_iboost(encoder, level);
> > > - else if (IS_BROXTON(dev_priv))
> > > + else if (IS_GEN9_LP(dev_priv))
> > > bxt_ddi_vswing_sequence(dev_priv, level, port, encoder-
> > > >type);
> > >
> > > return DDI_BUF_TRANS_SELECT(level);
> > > @@ -1716,7 +1716,7 @@ static void intel_ddi_pre_enable_hdmi(struct
> > > intel_encoder *encoder,
> > > intel_prepare_hdmi_ddi_buffers(encoder);
> > > if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> > > skl_ddi_set_iboost(encoder, level);
> > > - else if (IS_BROXTON(dev_priv))
> > > + else if (IS_GEN9_LP(dev_priv))
> > > bxt_ddi_vswing_sequence(dev_priv, level, port,
> > > INTEL_OUTPUT_HDMI);
> > >
> > > @@ -2127,7 +2127,7 @@ intel_ddi_get_link_dpll(struct intel_dp *intel_dp, int
> > > clock)
> > > struct intel_shared_dpll_config tmp_pll_config;
> > > enum intel_dpll_id dpll_id;
> > >
> > > - if (IS_BROXTON(dev_priv)) {
> > > + if (IS_GEN9_LP(dev_priv)) {
> > > dpll_id = (enum intel_dpll_id)dig_port->port;
> > > /*
> > > * Select the required PLL. This works for platforms where
> > > @@ -2244,7 +2244,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> > > enum port port)
> > > * configuration so that we use the proper lane count for our
> > > * calculations.
> > > */
> > > - if (IS_BROXTON(dev_priv) && port == PORT_A) {
> > > + if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
> > > if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
> > > DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES
> > > for port A; fixing\n");
> > > intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index 15f48a0..418941b 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -614,12 +614,12 @@ static bool intel_PLL_is_valid(struct drm_i915_private
> > > *dev_priv,
> > > INTELPllInvalid("m1 out of range\n");
> > >
> > > if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
> > > - !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
> > > + !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
> > > if (clock->m1 <= clock->m2)
> > > INTELPllInvalid("m1 <= m2\n");
> > >
> > > if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> > > - !IS_BROXTON(dev_priv)) {
> > > + !IS_GEN9_LP(dev_priv)) {
> > > if (clock->p < limit->p.min || limit->p.max < clock->p)
> > > INTELPllInvalid("p out of range\n");
> > > if (clock->m < limit->m.min || limit->m.max < clock->m)
> > > @@ -10641,7 +10641,7 @@ static void haswell_get_ddi_port_state(struct
> > > intel_crtc *crtc,
> > >
> > > if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> > > skylake_get_ddi_pll(dev_priv, port, pipe_config);
> > > - else if (IS_BROXTON(dev_priv))
> > > + else if (IS_GEN9_LP(dev_priv))
> > > bxt_get_ddi_pll(dev_priv, port, pipe_config);
> > > else
> > > haswell_get_ddi_pll(dev_priv, port, pipe_config);
> > > @@ -10686,7 +10686,7 @@ static bool haswell_get_pipe_config(struct
> > > intel_crtc *crtc,
> > >
> > > active = hsw_get_transcoder_state(crtc, pipe_config,
> > > &power_domain_mask);
> > >
> > > - if (IS_BROXTON(dev_priv) &&
> > > + if (IS_GEN9_LP(dev_priv) &&
> > > bxt_get_dsi_transcoder_state(crtc, pipe_config,
> > > &power_domain_mask)) {
> > > WARN_ON(active);
> > > active = true;
> > > @@ -12784,7 +12784,7 @@ static void intel_dump_pipe_config(struct intel_crtc
> > > *crtc,
> > > DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
> > > pipe_config->ips_enabled, pipe_config->double_wide);
> > >
> > > - if (IS_BROXTON(dev_priv)) {
> > > + if (IS_GEN9_LP(dev_priv)) {
> > > DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
> > > "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3:
> > > 0x%x, "
> > > "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10:
> > > 0x%x, pcsdw12: 0x%x\n",
> > > @@ -15478,7 +15478,7 @@ void intel_pps_unlock_regs_wa(struct
> > > drm_i915_private *dev_priv)
> > >
> > > static void intel_pps_init(struct drm_i915_private *dev_priv)
> > > {
> > > - if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
> > > + if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
> > > dev_priv->pps_mmio_base = PCH_PPS_BASE;
> > > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > > dev_priv->pps_mmio_base = VLV_PPS_BASE;
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > b/drivers/gpu/drm/i915/intel_dp.c
> > > index 9dfbde4..1f2420c 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -233,7 +233,7 @@ intel_dp_source_rates(struct intel_dp *intel_dp, const
> > > int **source_rates)
> > > struct drm_i915_private *dev_priv = to_i915(dig_port-
> > > >base.base.dev);
> > > int size;
> > >
> > > - if (IS_BROXTON(dev_priv)) {
> > > + if (IS_GEN9_LP(dev_priv)) {
> > > *source_rates = bxt_rates;
> > > size = ARRAY_SIZE(bxt_rates);
> > > } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> > > @@ -645,7 +645,7 @@ void intel_power_sequencer_reset(struct drm_i915_private
> > > *dev_priv)
> > > struct intel_encoder *encoder;
> > >
> > > if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> > > - !IS_BROXTON(dev_priv)))
> > > + !IS_GEN9_LP(dev_priv)))
> > > return;
> > >
> > > /*
> > > @@ -665,7 +665,7 @@ void intel_power_sequencer_reset(struct drm_i915_private
> > > *dev_priv)
> > > continue;
> > >
> > > intel_dp = enc_to_intel_dp(&encoder->base);
> > > - if (IS_BROXTON(dev_priv))
> > > + if (IS_GEN9_LP(dev_priv))
> > > intel_dp->pps_reset = true;
> > > else
> > > intel_dp->pps_pipe = INVALID_PIPE;
> > > @@ -688,7 +688,7 @@ static void intel_pps_get_registers(struct
> > > drm_i915_private *dev_priv,
> > >
> > > memset(regs, 0, sizeof(*regs));
> > >
> > > - if (IS_BROXTON(dev_priv))
> > > + if (IS_GEN9_LP(dev_priv))
> > > pps_idx = bxt_power_sequencer_idx(intel_dp);
> > > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > > pps_idx = vlv_power_sequencer_pipe(intel_dp);
> > > @@ -697,7 +697,7 @@ static void intel_pps_get_registers(struct
> > > drm_i915_private *dev_priv,
> > > regs->pp_stat = PP_STATUS(pps_idx);
> > > regs->pp_on = PP_ON_DELAYS(pps_idx);
> > > regs->pp_off = PP_OFF_DELAYS(pps_idx);
> > > - if (!IS_BROXTON(dev_priv))
> > > + if (!IS_GEN9_LP(dev_priv))
> > > regs->pp_div = PP_DIVISOR(pps_idx);
> > > }
> > >
> > > @@ -2984,7 +2984,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
> > > struct drm_i915_private *dev_priv =
> > > to_i915(intel_dp_to_dev(intel_dp));
> > > enum port port = dp_to_dig_port(intel_dp)->port;
> > >
> > > - if (IS_BROXTON(dev_priv))
> > > + if (IS_GEN9_LP(dev_priv))
> > > return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> > > else if (INTEL_GEN(dev_priv) >= 9) {
> > > if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
> > > @@ -4300,7 +4300,7 @@ static bool intel_digital_port_connected(struct
> > > drm_i915_private *dev_priv,
> > > return ibx_digital_port_connected(dev_priv, port);
> > > else if (HAS_PCH_SPLIT(dev_priv))
> > > return cpt_digital_port_connected(dev_priv, port);
> > > - else if (IS_BROXTON(dev_priv))
> > > + else if (IS_GEN9_LP(dev_priv))
> > > return bxt_digital_port_connected(dev_priv, port);
> > > else if (IS_GM45(dev_priv))
> > > return gm45_digital_port_connected(dev_priv, port);
> > > @@ -4929,7 +4929,7 @@ intel_pps_readout_hw_state(struct drm_i915_private
> > > *dev_priv,
> > >
> > > pp_on = I915_READ(regs.pp_on);
> > > pp_off = I915_READ(regs.pp_off);
> > > - if (!IS_BROXTON(dev_priv)) {
> > > + if (!IS_GEN9_LP(dev_priv)) {
> > > I915_WRITE(regs.pp_ctrl, pp_ctl);
> > > pp_div = I915_READ(regs.pp_div);
> > > }
> > > @@ -4947,7 +4947,7 @@ intel_pps_readout_hw_state(struct drm_i915_private
> > > *dev_priv,
> > > seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
> > > PANEL_POWER_DOWN_DELAY_SHIFT;
> > >
> > > - if (IS_BROXTON(dev_priv)) {
> > > + if (IS_GEN9_LP(dev_priv)) {
> > > u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
> > > BXT_POWER_CYCLE_DELAY_SHIFT;
> > > if (tmp > 0)
> > > @@ -5078,7 +5078,7 @@ intel_dp_init_panel_power_sequencer_registers(struct
> > > drm_device *dev,
> > > (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> > > /* Compute the divisor for the pp clock, simply match the Bspec
> > > * formula. */
> > > - if (IS_BROXTON(dev_priv)) {
> > > + if (IS_GEN9_LP(dev_priv)) {
> > > pp_div = I915_READ(regs.pp_ctrl);
> > > pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
> > > pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
> > > @@ -5104,7 +5104,7 @@ intel_dp_init_panel_power_sequencer_registers(struct
> > > drm_device *dev,
> > >
> > > I915_WRITE(regs.pp_on, pp_on);
> > > I915_WRITE(regs.pp_off, pp_off);
> > > - if (IS_BROXTON(dev_priv))
> > > + if (IS_GEN9_LP(dev_priv))
> > > I915_WRITE(regs.pp_ctrl, pp_div);
> > > else
> > > I915_WRITE(regs.pp_div, pp_div);
> > > @@ -5112,7 +5112,7 @@ intel_dp_init_panel_power_sequencer_registers(struct
> > > drm_device *dev,
> > > DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x,
> > > PP_OFF %#x, PP_DIV %#x\n",
> > > I915_READ(regs.pp_on),
> > > I915_READ(regs.pp_off),
> > > - IS_BROXTON(dev_priv) ?
> > > + IS_GEN9_LP(dev_priv) ?
> > > (I915_READ(regs.pp_ctrl) &
> > > BXT_POWER_CYCLE_DELAY_MASK) :
> > > I915_READ(regs.pp_div));
> > > }
> > > diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c
> > > b/drivers/gpu/drm/i915/intel_dpio_phy.c
> > > index 7a8e82d..8c62dea 100644
> > > --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> > > +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> > > @@ -317,7 +317,6 @@ static void _bxt_ddi_phy_init(struct drm_i915_private
> > > *dev_priv,
> > > if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
> > > DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
> > > "won't reprogram it\n", phy);
> > > -
> > > return;
> > > }
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > > b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > > index 58a756f..976d390 100644
> > > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > > @@ -1860,7 +1860,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
> > >
> > > if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> > > dpll_mgr = &skl_pll_mgr;
> > > - else if (IS_BROXTON(dev_priv))
> > > + else if (IS_GEN9_LP(dev_priv))
> > > dpll_mgr = &bxt_pll_mgr;
> > > else if (HAS_DDI(dev_priv))
> > > dpll_mgr = &hsw_pll_mgr;
> > > diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> > > b/drivers/gpu/drm/i915/intel_dsi.c
> > > index 3bc6213..0668bbe 100644
> > > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > > @@ -340,7 +340,7 @@ static bool intel_dsi_compute_config(struct
> > > intel_encoder *encoder,
> > > /* DSI uses short packets for sync events, so clear mode flags for
> > > DSI */
> > > adjusted_mode->flags = 0;
> > >
> > > - if (IS_BROXTON(dev_priv)) {
> > > + if (IS_GEN9_LP(dev_priv)) {
> > > /* Dual link goes to DSI transcoder A. */
> > > if (intel_dsi->ports == BIT(PORT_C))
> > > pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
> > > @@ -441,7 +441,7 @@ static void intel_dsi_device_ready(struct intel_encoder
> > > *encoder)
> > >
> > > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > > vlv_dsi_device_ready(encoder);
> > > - else if (IS_BROXTON(dev_priv))
> > > + else if (IS_GEN9_LP(dev_priv))
> > > bxt_dsi_device_ready(encoder);
> > > }
> > >
> > > @@ -464,7 +464,7 @@ static void intel_dsi_port_enable(struct intel_encoder
> > > *encoder)
> > > }
> > >
> > > for_each_dsi_port(port, intel_dsi->ports) {
> > > - i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> > > + i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
> > > BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> > > u32 temp;
> > >
> > > @@ -497,7 +497,7 @@ static void intel_dsi_port_disable(struct intel_encoder
> > > *encoder)
> > > enum port port;
> > >
> > > for_each_dsi_port(port, intel_dsi->ports) {
> > > - i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> > > + i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
> > > BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> > > u32 temp;
> > >
> > > @@ -666,7 +666,7 @@ static void intel_dsi_clear_device_ready(struct
> > > intel_encoder *encoder)
> > > DRM_DEBUG_KMS("\n");
> > > for_each_dsi_port(port, intel_dsi->ports) {
> > > /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV
> > > */
> > > - i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> > > + i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
> > > BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
> > > u32 val;
> > >
> > > @@ -758,12 +758,12 @@ static bool intel_dsi_get_hw_state(struct
> > > intel_encoder *encoder,
> > > * configuration, otherwise accessing DSI registers will hang the
> > > * machine. See BSpec North Display Engine registers/MIPI[BXT].
> > > */
> > > - if (IS_BROXTON(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
> > > + if (IS_GEN9_LP(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
> > > goto out_put_power;
> > >
> > > /* XXX: this only works for one DSI output */
> > > for_each_dsi_port(port, intel_dsi->ports) {
> > > - i915_reg_t ctrl_reg = IS_BROXTON(dev_priv) ?
> > > + i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
> > > BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> > > bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
> > >
> > > @@ -788,7 +788,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder
> > > *encoder,
> > > if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
> > > continue;
> > >
> > > - if (IS_BROXTON(dev_priv)) {
> > > + if (IS_GEN9_LP(dev_priv)) {
> > > u32 tmp = I915_READ(MIPI_CTRL(port));
> > > tmp &= BXT_PIPE_SELECT_MASK;
> > > tmp >>= BXT_PIPE_SELECT_SHIFT;
> > > @@ -976,7 +976,7 @@ static void intel_dsi_get_config(struct intel_encoder
> > > *encoder,
> > > u32 pclk;
> > > DRM_DEBUG_KMS("\n");
> > >
> > > - if (IS_BROXTON(dev_priv))
> > > + if (IS_GEN9_LP(dev_priv))
> > > bxt_dsi_get_pipe_config(encoder, pipe_config);
> > >
> > > pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
> > > @@ -1068,7 +1068,7 @@ static void set_dsi_timings(struct drm_encoder
> > > *encoder,
> > > hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi-
> > > >burst_mode_ratio);
> > >
> > > for_each_dsi_port(port, intel_dsi->ports) {
> > > - if (IS_BROXTON(dev_priv)) {
> > > + if (IS_GEN9_LP(dev_priv)) {
> > > /*
> > > * Program hdisplay and vdisplay on MIPI
> > > transcoder.
> > > * This is different from calculated hactive and
> > > @@ -1155,7 +1155,7 @@ static void intel_dsi_prepare(struct intel_encoder
> > > *intel_encoder,
> > > tmp &= ~READ_REQUEST_PRIORITY_MASK;
> > > I915_WRITE(MIPI_CTRL(port), tmp |
> > > READ_REQUEST_PRIORITY_HIGH);
> > > - } else if (IS_BROXTON(dev_priv)) {
> > > + } else if (IS_GEN9_LP(dev_priv)) {
> > > enum pipe pipe = intel_crtc->pipe;
> > >
> > > tmp = I915_READ(MIPI_CTRL(port));
> > > @@ -1193,7 +1193,7 @@ static void intel_dsi_prepare(struct intel_encoder
> > > *intel_encoder,
> > > if (intel_dsi->clock_stop)
> > > tmp |= CLOCKSTOP;
> > >
> > > - if (IS_BROXTON(dev_priv)) {
> > > + if (IS_GEN9_LP(dev_priv)) {
> > > tmp |= BXT_DPHY_DEFEATURE_EN;
> > > if (!is_cmd_mode(intel_dsi))
> > > tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
> > > @@ -1244,7 +1244,7 @@ static void intel_dsi_prepare(struct intel_encoder
> > > *intel_encoder,
> > > I915_WRITE(MIPI_INIT_COUNT(port),
> > > txclkesc(intel_dsi->escape_clk_div, 100));
> > >
> > > - if (IS_BROXTON(dev_priv) && (!intel_dsi->dual_link)) {
> > > + if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
> > > /*
> > > * BXT spec says write MIPI_INIT_COUNT for
> > > * both the ports, even if only one is
> > > @@ -1454,7 +1454,7 @@ void intel_dsi_init(struct drm_i915_private *dev_priv)
> > >
> > > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> > > dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
> > > - } else if (IS_BROXTON(dev_priv)) {
> > > + } else if (IS_GEN9_LP(dev_priv)) {
> > > dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
> > > } else {
> > > DRM_ERROR("Unsupported Mipi device to reg base");
> > > @@ -1495,7 +1495,7 @@ void intel_dsi_init(struct drm_i915_private *dev_priv)
> > > * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI
> > > DSI
> > > * port C. BXT isn't limited like this.
> > > */
> > > - if (IS_BROXTON(dev_priv))
> > > + if (IS_GEN9_LP(dev_priv))
> > > intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) |
> > > BIT(PIPE_C);
> > > else if (port == PORT_A)
> > > intel_encoder->crtc_mask = BIT(PIPE_A);
> > > diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
> > > b/drivers/gpu/drm/i915/intel_dsi_pll.c
> > > index 56eff60..cf8c1b0 100644
> > > --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> > > +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> > > @@ -351,7 +351,7 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder
> > > *encoder, int pipe_bpp,
> > > u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
> > > struct intel_crtc_state *config)
> > > {
> > > - if (IS_BROXTON(to_i915(encoder->base.dev)))
> > > + if (IS_GEN9_LP(to_i915(encoder->base.dev)))
> > > return bxt_dsi_get_pclk(encoder, pipe_bpp, config);
> > > else
> > > return vlv_dsi_get_pclk(encoder, pipe_bpp, config);
> > > @@ -504,7 +504,7 @@ static void bxt_enable_dsi_pll(struct intel_encoder
> > > *encoder,
> > >
> > > bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
> > > {
> > > - if (IS_BROXTON(dev_priv))
> > > + if (IS_GEN9_LP(dev_priv))
> > > return bxt_dsi_pll_is_enabled(dev_priv);
> > >
> > > MISSING_CASE(INTEL_DEVID(dev_priv));
> > > @@ -519,7 +519,7 @@ int intel_compute_dsi_pll(struct intel_encoder *encoder,
> > >
> > > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > > return vlv_compute_dsi_pll(encoder, config);
> > > - else if (IS_BROXTON(dev_priv))
> > > + else if (IS_GEN9_LP(dev_priv))
> > > return bxt_compute_dsi_pll(encoder, config);
> > >
> > > return -ENODEV;
> > > @@ -532,7 +532,7 @@ void intel_enable_dsi_pll(struct intel_encoder *encoder,
> > >
> > > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > > vlv_enable_dsi_pll(encoder, config);
> > > - else if (IS_BROXTON(dev_priv))
> > > + else if (IS_GEN9_LP(dev_priv))
> > > bxt_enable_dsi_pll(encoder, config);
> > > }
> > >
> > > @@ -542,7 +542,7 @@ void intel_disable_dsi_pll(struct intel_encoder
> > > *encoder)
> > >
> > > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > > vlv_disable_dsi_pll(encoder);
> > > - else if (IS_BROXTON(dev_priv))
> > > + else if (IS_GEN9_LP(dev_priv))
> > > bxt_disable_dsi_pll(encoder);
> > > }
> > >
> > > @@ -566,7 +566,7 @@ void intel_dsi_reset_clocks(struct intel_encoder
> > > *encoder, enum port port)
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > >
> > > - if (IS_BROXTON(dev_priv))
> > > + if (IS_GEN9_LP(dev_priv))
> > > bxt_dsi_reset_clocks(encoder, port);
> > > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > > vlv_dsi_reset_clocks(encoder, port);
> > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> > > b/drivers/gpu/drm/i915/intel_hdmi.c
> > > index 374e38a..0bcfead 100644
> > > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > > @@ -1251,7 +1251,7 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
> > > return MODE_CLOCK_HIGH;
> > >
> > > /* BXT DPLL can't generate 223-240 MHz */
> > > - if (IS_BROXTON(dev_priv) && clock > 223333 && clock < 240000)
> > > + if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
> > > return MODE_CLOCK_RANGE;
> > >
> > > /* CHV DPLL can't generate 216-240 MHz */
> > > @@ -1809,13 +1809,13 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private
> > > *dev_priv,
> > >
> > > switch (port) {
> > > case PORT_B:
> > > - if (IS_BROXTON(dev_priv))
> > > + if (IS_GEN9_LP(dev_priv))
> > > ddc_pin = GMBUS_PIN_1_BXT;
> > > else
> > > ddc_pin = GMBUS_PIN_DPB;
> > > break;
> > > case PORT_C:
> > > - if (IS_BROXTON(dev_priv))
> > > + if (IS_GEN9_LP(dev_priv))
> > > ddc_pin = GMBUS_PIN_2_BXT;
> > > else
> > > ddc_pin = GMBUS_PIN_DPC;
> > > diff --git a/drivers/gpu/drm/i915/intel_i2c.c
> > > b/drivers/gpu/drm/i915/intel_i2c.c
> > > index 83f260b..1606e31 100644
> > > --- a/drivers/gpu/drm/i915/intel_i2c.c
> > > +++ b/drivers/gpu/drm/i915/intel_i2c.c
> > > @@ -72,7 +72,7 @@ static const struct gmbus_pin gmbus_pins_bxt[] = {
> > > static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private
> > > *dev_priv,
> > > unsigned int pin)
> > > {
> > > - if (IS_BROXTON(dev_priv))
> > > + if (IS_GEN9_LP(dev_priv))
> > > return &gmbus_pins_bxt[pin];
> > > else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> > > return &gmbus_pins_skl[pin];
> > > @@ -87,7 +87,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private
> > > *dev_priv,
> > > {
> > > unsigned int size;
> > >
> > > - if (IS_BROXTON(dev_priv))
> > > + if (IS_GEN9_LP(dev_priv))
> > > size = ARRAY_SIZE(gmbus_pins_bxt);
> > > else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> > > size = ARRAY_SIZE(gmbus_pins_skl);
> > > diff --git a/drivers/gpu/drm/i915/intel_mocs.c
> > > b/drivers/gpu/drm/i915/intel_mocs.c
> > > index 80bb924..eed0707 100644
> > > --- a/drivers/gpu/drm/i915/intel_mocs.c
> > > +++ b/drivers/gpu/drm/i915/intel_mocs.c
> > > @@ -182,7 +182,7 @@ static bool get_mocs_settings(struct drm_i915_private
> > > *dev_priv,
> > > table->size = ARRAY_SIZE(skylake_mocs_table);
> > > table->table = skylake_mocs_table;
> > > result = true;
> > > - } else if (IS_BROXTON(dev_priv)) {
> > > + } else if (IS_GEN9_LP(dev_priv)) {
> > > table->size = ARRAY_SIZE(broxton_mocs_table);
> > > table->table = broxton_mocs_table;
> > > result = true;
> > > diff --git a/drivers/gpu/drm/i915/intel_panel.c
> > > b/drivers/gpu/drm/i915/intel_panel.c
> > > index 08ab6d7..3578b40 100644
> > > --- a/drivers/gpu/drm/i915/intel_panel.c
> > > +++ b/drivers/gpu/drm/i915/intel_panel.c
> > > @@ -1756,7 +1756,7 @@ intel_panel_init_backlight_funcs(struct intel_panel
> > > *panel)
> > > intel_dsi_dcs_init_backlight_funcs(connector) == 0)
> > > return;
> > >
> > > - if (IS_BROXTON(dev_priv)) {
> > > + if (IS_GEN9_LP(dev_priv)) {
> > > panel->backlight.setup = bxt_setup_backlight;
> > > panel->backlight.enable = bxt_enable_backlight;
> > > panel->backlight.disable = bxt_disable_backlight;
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > b/drivers/gpu/drm/i915/intel_pm.c
> > > index 29b6653..0b17a4f 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -5208,7 +5208,7 @@ int sanitize_rc6_option(struct drm_i915_private
> > > *dev_priv, int enable_rc6)
> > > if (!enable_rc6)
> > > return 0;
> > >
> > > - if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
> > > + if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
> > > DRM_INFO("RC6 disabled by BIOS\n");
> > > return 0;
> > > }
> > > @@ -5242,7 +5242,7 @@ static void gen6_init_rps_frequencies(struct
> > > drm_i915_private *dev_priv)
> > > /* All of these values are in units of 50MHz */
> > >
> > > /* static values from HW: RP0 > RP1 > RPn (min_freq) */
> > > - if (IS_BROXTON(dev_priv)) {
> > > + if (IS_GEN9_LP(dev_priv)) {
> > > u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
> > > dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
> > > dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
> > > @@ -7622,7 +7622,7 @@ void intel_init_clock_gating_hooks(struct
> > > drm_i915_private *dev_priv)
> > > dev_priv->display.init_clock_gating =
> > > skylake_init_clock_gating;
> > > else if (IS_KABYLAKE(dev_priv))
> > > dev_priv->display.init_clock_gating =
> > > kabylake_init_clock_gating;
> > > - else if (IS_BROXTON(dev_priv))
> > > + else if (IS_GEN9_LP(dev_priv))
> > > dev_priv->display.init_clock_gating =
> > > bxt_init_clock_gating;
> > > else if (IS_BROADWELL(dev_priv))
> > > dev_priv->display.init_clock_gating =
> > > broadwell_init_clock_gating;
> > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > index 356c662..66ab1c8 100644
> > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > @@ -530,7 +530,7 @@ static u32 gen9_dc_mask(struct drm_i915_private
> > > *dev_priv)
> > > u32 mask;
> > >
> > > mask = DC_STATE_EN_UPTO_DC5;
> > > - if (IS_BROXTON(dev_priv))
> > > + if (IS_GEN9_LP(dev_priv))
> > > mask |= DC_STATE_EN_DC9;
> > > else
> > > mask |= DC_STATE_EN_UPTO_DC6;
> > > @@ -911,7 +911,7 @@ static void gen9_dc_off_power_well_enable(struct
> > > drm_i915_private *dev_priv,
> > >
> > > gen9_assert_dbuf_enabled(dev_priv);
> > >
> > > - if (IS_BROXTON(dev_priv))
> > > + if (IS_GEN9_LP(dev_priv))
> > > bxt_verify_ddi_phy_power_wells(dev_priv);
> > > }
> > >
> > > @@ -2170,7 +2170,7 @@ static uint32_t get_allowed_dc_mask(const struct
> > > drm_i915_private *dev_priv,
> > > if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> > > max_dc = 2;
> > > mask = 0;
> > > - } else if (IS_BROXTON(dev_priv)) {
> > > + } else if (IS_GEN9_LP(dev_priv)) {
> > > max_dc = 1;
> > > /*
> > > * DC9 has a separate HW flow from the rest of the DC
> > > states,
> > > --
> > > 2.5.5
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 06/15] drm/i915/glk: Force DDI initialization.
2016-11-10 15:23 [PATCH 00/15] Geminilake enabling Ander Conselvan de Oliveira
` (4 preceding siblings ...)
2016-11-10 15:23 ` [PATCH 05/15] drm/i915/glk: Reuse broxton code for geminilake Ander Conselvan de Oliveira
@ 2016-11-10 15:23 ` Ander Conselvan de Oliveira
2016-12-02 0:52 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 07/15] drm/i915/glk: Set DDI PHY lane lane optimization for Geminilake too Ander Conselvan de Oliveira
` (13 subsequent siblings)
19 siblings, 1 reply; 52+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-11-10 15:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira, Rodrigo Vivi
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
As for BXT, GLK doesn't support port detection through SFUSE_STRAP, so
let's force DDI initialization in order to get HDMI and DP.
v2: Use dev_priv instead of dev. (Tvrtko)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c6ffe0a..4069a6e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15491,7 +15491,7 @@ static void intel_setup_outputs(struct drm_device *dev)
if (intel_crt_present(dev))
intel_crt_init(dev);
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEN9_LP(dev_priv)) {
/*
* FIXME: Broxton doesn't support port detection via the
* DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
--
2.5.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 06/15] drm/i915/glk: Force DDI initialization.
2016-11-10 15:23 ` [PATCH 06/15] drm/i915/glk: Force DDI initialization Ander Conselvan de Oliveira
@ 2016-12-02 0:52 ` Rodrigo Vivi
2016-12-02 8:16 ` Ander Conselvan De Oliveira
0 siblings, 1 reply; 52+ messages in thread
From: Rodrigo Vivi @ 2016-12-02 0:52 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx, Rodrigo Vivi
This could also be squashed or reviewed-by you...
either works for me, I just cannot review the patch that I'm listed as author ;)
On Thu, Nov 10, 2016 at 05:23:11PM +0200, Ander Conselvan de Oliveira wrote:
> From: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> As for BXT, GLK doesn't support port detection through SFUSE_STRAP, so
> let's force DDI initialization in order to get HDMI and DP.
>
> v2: Use dev_priv instead of dev. (Tvrtko)
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c6ffe0a..4069a6e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -15491,7 +15491,7 @@ static void intel_setup_outputs(struct drm_device *dev)
> if (intel_crt_present(dev))
> intel_crt_init(dev);
>
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> /*
> * FIXME: Broxton doesn't support port detection via the
> * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
> --
> 2.5.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH 06/15] drm/i915/glk: Force DDI initialization.
2016-12-02 0:52 ` Rodrigo Vivi
@ 2016-12-02 8:16 ` Ander Conselvan De Oliveira
0 siblings, 0 replies; 52+ messages in thread
From: Ander Conselvan De Oliveira @ 2016-12-02 8:16 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, Rodrigo Vivi
On Thu, 2016-12-01 at 16:52 -0800, Rodrigo Vivi wrote:
> This could also be squashed or reviewed-by you...
> either works for me, I just cannot review the patch that I'm listed as author
> ;)
I had a vague recollection of editing this patch, hence why I didn't add my own
R-b. But it was just a rebase, so
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
But I'll squash this into the patch 5.
Ander
> On Thu, Nov 10, 2016 at 05:23:11PM +0200, Ander Conselvan de Oliveira wrote:
> >
> > From: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >
> > As for BXT, GLK doesn't support port detection through SFUSE_STRAP, so
> > let's force DDI initialization in order to get HDMI and DP.
> >
> > v2: Use dev_priv instead of dev. (Tvrtko)
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@inte
> > l.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index c6ffe0a..4069a6e 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -15491,7 +15491,7 @@ static void intel_setup_outputs(struct drm_device
> > *dev)
> > if (intel_crt_present(dev))
> > intel_crt_init(dev);
> >
> > - if (IS_BROXTON(dev_priv)) {
> > + if (IS_GEN9_LP(dev_priv)) {
> > /*
> > * FIXME: Broxton doesn't support port detection via the
> > * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way
> > to
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 07/15] drm/i915/glk: Set DDI PHY lane lane optimization for Geminilake too
2016-11-10 15:23 [PATCH 00/15] Geminilake enabling Ander Conselvan de Oliveira
` (5 preceding siblings ...)
2016-11-10 15:23 ` [PATCH 06/15] drm/i915/glk: Force DDI initialization Ander Conselvan de Oliveira
@ 2016-11-10 15:23 ` Ander Conselvan de Oliveira
2016-12-02 0:50 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 08/15] drm/i915/glk: Add power wells for Geminilake Ander Conselvan de Oliveira
` (12 subsequent siblings)
19 siblings, 1 reply; 52+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-11-10 15:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
Geminilake uses the same lane latency optimization masks and registers
as Broxton, so reuse the code with that platform too.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index dcad209..aec8265 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1429,7 +1429,7 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
out:
- if (ret && IS_BROXTON(dev_priv)) {
+ if (ret && IS_GEN9_LP(dev_priv)) {
tmp = I915_READ(BXT_PHY_CTL(port));
if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
@@ -2044,7 +2044,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
intel_ddi_clock_get(encoder, pipe_config);
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
pipe_config->lane_lat_optim_mask =
bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
}
@@ -2068,7 +2068,7 @@ static bool intel_ddi_compute_config(struct intel_encoder *encoder,
else
ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
- if (IS_BROXTON(dev_priv) && ret)
+ if (IS_GEN9_LP(dev_priv) && ret)
pipe_config->lane_lat_optim_mask =
bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
pipe_config->lane_count);
@@ -2225,7 +2225,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
intel_encoder->compute_config = intel_ddi_compute_config;
intel_encoder->enable = intel_enable_ddi;
- if (IS_BROXTON(dev_priv))
+ if (IS_GEN9_LP(dev_priv))
intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
intel_encoder->pre_enable = intel_ddi_pre_enable;
intel_encoder->disable = intel_disable_ddi;
--
2.5.5
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^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 07/15] drm/i915/glk: Set DDI PHY lane lane optimization for Geminilake too
2016-11-10 15:23 ` [PATCH 07/15] drm/i915/glk: Set DDI PHY lane lane optimization for Geminilake too Ander Conselvan de Oliveira
@ 2016-12-02 0:50 ` Rodrigo Vivi
0 siblings, 0 replies; 52+ messages in thread
From: Rodrigo Vivi @ 2016-12-02 0:50 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
This could be squashed to the other bit patch with s/broxton/gen9_lp...
but anyway
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
On Thu, Nov 10, 2016 at 05:23:12PM +0200, Ander Conselvan de Oliveira wrote:
> Geminilake uses the same lane latency optimization masks and registers
> as Broxton, so reuse the code with that platform too.
>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index dcad209..aec8265 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1429,7 +1429,7 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
> DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
>
> out:
> - if (ret && IS_BROXTON(dev_priv)) {
> + if (ret && IS_GEN9_LP(dev_priv)) {
> tmp = I915_READ(BXT_PHY_CTL(port));
> if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
> BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
> @@ -2044,7 +2044,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>
> intel_ddi_clock_get(encoder, pipe_config);
>
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> pipe_config->lane_lat_optim_mask =
> bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
> }
> @@ -2068,7 +2068,7 @@ static bool intel_ddi_compute_config(struct intel_encoder *encoder,
> else
> ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
>
> - if (IS_BROXTON(dev_priv) && ret)
> + if (IS_GEN9_LP(dev_priv) && ret)
> pipe_config->lane_lat_optim_mask =
> bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
> pipe_config->lane_count);
> @@ -2225,7 +2225,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
>
> intel_encoder->compute_config = intel_ddi_compute_config;
> intel_encoder->enable = intel_enable_ddi;
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
> intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
> intel_encoder->pre_enable = intel_ddi_pre_enable;
> intel_encoder->disable = intel_disable_ddi;
> --
> 2.5.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 08/15] drm/i915/glk: Add power wells for Geminilake
2016-11-10 15:23 [PATCH 00/15] Geminilake enabling Ander Conselvan de Oliveira
` (6 preceding siblings ...)
2016-11-10 15:23 ` [PATCH 07/15] drm/i915/glk: Set DDI PHY lane lane optimization for Geminilake too Ander Conselvan de Oliveira
@ 2016-11-10 15:23 ` Ander Conselvan de Oliveira
2016-12-02 0:48 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 09/15] drm/i915/glk: Implement Geminilake DDI init sequence Ander Conselvan de Oliveira
` (11 subsequent siblings)
19 siblings, 1 reply; 52+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-11-10 15:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
Geminilake has power wells are similar to SKL, but with the misc IO well
being split into separate AUX IO wells.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_runtime_pm.c | 114 +++++++++++++++++++++++++++++++-
2 files changed, 117 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1be2a7d..78a3347 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -708,9 +708,15 @@ enum skl_disp_power_wells {
/* These numbers are fixed and must match the position of the pw bits */
SKL_DISP_PW_MISC_IO,
SKL_DISP_PW_DDI_A_E,
+ GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
SKL_DISP_PW_DDI_B,
SKL_DISP_PW_DDI_C,
SKL_DISP_PW_DDI_D,
+
+ GLK_DISP_PW_AUX_A = 8,
+ GLK_DISP_PW_AUX_B,
+ GLK_DISP_PW_AUX_C,
+
SKL_DISP_PW_1 = 14,
SKL_DISP_PW_2,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 697574f..683c15b 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -453,6 +453,45 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
BIT(POWER_DOMAIN_AUX_C) | \
BIT(POWER_DOMAIN_INIT))
+#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
+ BIT(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT(POWER_DOMAIN_PIPE_B) | \
+ BIT(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT(POWER_DOMAIN_PIPE_C) | \
+ BIT(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT(POWER_DOMAIN_AUX_B) | \
+ BIT(POWER_DOMAIN_AUX_C) | \
+ BIT(POWER_DOMAIN_AUDIO) | \
+ BIT(POWER_DOMAIN_VGA) | \
+ BIT(POWER_DOMAIN_INIT))
+#define GLK_DISPLAY_DDI_A_POWER_DOMAINS ( \
+ BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
+ BIT(POWER_DOMAIN_INIT))
+#define GLK_DISPLAY_DDI_B_POWER_DOMAINS ( \
+ BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT(POWER_DOMAIN_INIT))
+#define GLK_DISPLAY_DDI_C_POWER_DOMAINS ( \
+ BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT(POWER_DOMAIN_INIT))
+#define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \
+ BIT(POWER_DOMAIN_AUX_A) | \
+ BIT(POWER_DOMAIN_INIT))
+#define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \
+ BIT(POWER_DOMAIN_AUX_B) | \
+ BIT(POWER_DOMAIN_INIT))
+#define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \
+ BIT(POWER_DOMAIN_AUX_C) | \
+ BIT(POWER_DOMAIN_INIT))
+#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
+ BIT(POWER_DOMAIN_MODESET) | \
+ BIT(POWER_DOMAIN_AUX_A) | \
+ BIT(POWER_DOMAIN_INIT))
+
static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
{
WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
@@ -694,7 +733,7 @@ gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv,
}
static void skl_set_power_well(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well, bool enable)
+ struct i915_power_well *power_well, bool enable)
{
uint32_t tmp, fuse_status;
uint32_t req_mask, state_mask;
@@ -720,11 +759,14 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
return;
}
break;
- case SKL_DISP_PW_DDI_A_E:
+ case SKL_DISP_PW_MISC_IO:
+ case SKL_DISP_PW_DDI_A_E: /* GLK_DISP_PW_DDI_A */
case SKL_DISP_PW_DDI_B:
case SKL_DISP_PW_DDI_C:
case SKL_DISP_PW_DDI_D:
- case SKL_DISP_PW_MISC_IO:
+ case GLK_DISP_PW_AUX_A:
+ case GLK_DISP_PW_AUX_B:
+ case GLK_DISP_PW_AUX_C:
break;
default:
WARN(1, "Unknown power well %lu\n", power_well->id);
@@ -2150,6 +2192,70 @@ static struct i915_power_well bxt_power_wells[] = {
},
};
+static struct i915_power_well glk_power_wells[] = {
+ {
+ .name = "always-on",
+ .always_on = 1,
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ },
+ {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .domains = 0,
+ .ops = &skl_power_well_ops,
+ .id = SKL_DISP_PW_1,
+ },
+ {
+ .name = "DC off",
+ .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .id = SKL_DISP_PW_DC_OFF,
+ },
+ {
+ .name = "power well 2",
+ .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
+ .ops = &skl_power_well_ops,
+ .id = SKL_DISP_PW_2,
+ },
+ {
+ .name = "AUX A",
+ .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
+ .ops = &skl_power_well_ops,
+ .id = GLK_DISP_PW_AUX_A,
+ },
+ {
+ .name = "AUX B",
+ .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
+ .ops = &skl_power_well_ops,
+ .id = GLK_DISP_PW_AUX_B,
+ },
+ {
+ .name = "AUX C",
+ .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
+ .ops = &skl_power_well_ops,
+ .id = GLK_DISP_PW_AUX_C,
+ },
+ {
+ .name = "DDI A power well",
+ .domains = GLK_DISPLAY_DDI_A_POWER_DOMAINS,
+ .ops = &skl_power_well_ops,
+ .id = GLK_DISP_PW_DDI_A,
+ },
+ {
+ .name = "DDI B power well",
+ .domains = GLK_DISPLAY_DDI_B_POWER_DOMAINS,
+ .ops = &skl_power_well_ops,
+ .id = SKL_DISP_PW_DDI_B,
+ },
+ {
+ .name = "DDI C power well",
+ .domains = GLK_DISPLAY_DDI_C_POWER_DOMAINS,
+ .ops = &skl_power_well_ops,
+ .id = SKL_DISP_PW_DDI_C,
+ },
+};
+
static int
sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
int disable_power_well)
@@ -2246,6 +2352,8 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
set_power_wells(power_domains, skl_power_wells);
} else if (IS_BROXTON(dev_priv)) {
set_power_wells(power_domains, bxt_power_wells);
+ } else if (IS_GEMINILAKE(dev_priv)) {
+ set_power_wells(power_domains, glk_power_wells);
} else if (IS_CHERRYVIEW(dev_priv)) {
set_power_wells(power_domains, chv_power_wells);
} else if (IS_VALLEYVIEW(dev_priv)) {
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 08/15] drm/i915/glk: Add power wells for Geminilake
2016-11-10 15:23 ` [PATCH 08/15] drm/i915/glk: Add power wells for Geminilake Ander Conselvan de Oliveira
@ 2016-12-02 0:48 ` Rodrigo Vivi
0 siblings, 0 replies; 52+ messages in thread
From: Rodrigo Vivi @ 2016-12-02 0:48 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
On Thu, Nov 10, 2016 at 05:23:13PM +0200, Ander Conselvan de Oliveira wrote:
> Geminilake has power wells are similar to SKL, but with the misc IO well
> being split into separate AUX IO wells.
>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 6 ++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 114 +++++++++++++++++++++++++++++++-
> 2 files changed, 117 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1be2a7d..78a3347 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -708,9 +708,15 @@ enum skl_disp_power_wells {
> /* These numbers are fixed and must match the position of the pw bits */
> SKL_DISP_PW_MISC_IO,
> SKL_DISP_PW_DDI_A_E,
> + GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
> SKL_DISP_PW_DDI_B,
> SKL_DISP_PW_DDI_C,
> SKL_DISP_PW_DDI_D,
> +
> + GLK_DISP_PW_AUX_A = 8,
> + GLK_DISP_PW_AUX_B,
> + GLK_DISP_PW_AUX_C,
> +
> SKL_DISP_PW_1 = 14,
> SKL_DISP_PW_2,
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 697574f..683c15b 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -453,6 +453,45 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
> BIT(POWER_DOMAIN_AUX_C) | \
> BIT(POWER_DOMAIN_INIT))
>
> +#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> + BIT(POWER_DOMAIN_TRANSCODER_A) | \
> + BIT(POWER_DOMAIN_PIPE_B) | \
> + BIT(POWER_DOMAIN_TRANSCODER_B) | \
> + BIT(POWER_DOMAIN_PIPE_C) | \
> + BIT(POWER_DOMAIN_TRANSCODER_C) | \
> + BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> + BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT(POWER_DOMAIN_AUX_B) | \
> + BIT(POWER_DOMAIN_AUX_C) | \
> + BIT(POWER_DOMAIN_AUDIO) | \
> + BIT(POWER_DOMAIN_VGA) | \
> + BIT(POWER_DOMAIN_INIT))
> +#define GLK_DISPLAY_DDI_A_POWER_DOMAINS ( \
> + BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
> + BIT(POWER_DOMAIN_INIT))
> +#define GLK_DISPLAY_DDI_B_POWER_DOMAINS ( \
> + BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT(POWER_DOMAIN_INIT))
> +#define GLK_DISPLAY_DDI_C_POWER_DOMAINS ( \
> + BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT(POWER_DOMAIN_INIT))
> +#define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \
> + BIT(POWER_DOMAIN_AUX_A) | \
> + BIT(POWER_DOMAIN_INIT))
> +#define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \
> + BIT(POWER_DOMAIN_AUX_B) | \
> + BIT(POWER_DOMAIN_INIT))
> +#define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \
> + BIT(POWER_DOMAIN_AUX_C) | \
> + BIT(POWER_DOMAIN_INIT))
> +#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> + GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> + BIT(POWER_DOMAIN_MODESET) | \
> + BIT(POWER_DOMAIN_AUX_A) | \
> + BIT(POWER_DOMAIN_INIT))
> +
> static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
> {
> WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
> @@ -694,7 +733,7 @@ gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv,
> }
>
> static void skl_set_power_well(struct drm_i915_private *dev_priv,
> - struct i915_power_well *power_well, bool enable)
> + struct i915_power_well *power_well, bool enable)
> {
> uint32_t tmp, fuse_status;
> uint32_t req_mask, state_mask;
> @@ -720,11 +759,14 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> return;
> }
> break;
> - case SKL_DISP_PW_DDI_A_E:
> + case SKL_DISP_PW_MISC_IO:
> + case SKL_DISP_PW_DDI_A_E: /* GLK_DISP_PW_DDI_A */
> case SKL_DISP_PW_DDI_B:
> case SKL_DISP_PW_DDI_C:
> case SKL_DISP_PW_DDI_D:
> - case SKL_DISP_PW_MISC_IO:
> + case GLK_DISP_PW_AUX_A:
> + case GLK_DISP_PW_AUX_B:
> + case GLK_DISP_PW_AUX_C:
> break;
> default:
> WARN(1, "Unknown power well %lu\n", power_well->id);
> @@ -2150,6 +2192,70 @@ static struct i915_power_well bxt_power_wells[] = {
> },
> };
>
> +static struct i915_power_well glk_power_wells[] = {
> + {
> + .name = "always-on",
> + .always_on = 1,
> + .domains = POWER_DOMAIN_MASK,
> + .ops = &i9xx_always_on_power_well_ops,
> + },
> + {
> + .name = "power well 1",
> + /* Handled by the DMC firmware */
> + .domains = 0,
> + .ops = &skl_power_well_ops,
> + .id = SKL_DISP_PW_1,
> + },
> + {
> + .name = "DC off",
> + .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .ops = &gen9_dc_off_power_well_ops,
> + .id = SKL_DISP_PW_DC_OFF,
> + },
> + {
> + .name = "power well 2",
> + .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> + .ops = &skl_power_well_ops,
> + .id = SKL_DISP_PW_2,
> + },
> + {
> + .name = "AUX A",
> + .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
> + .ops = &skl_power_well_ops,
> + .id = GLK_DISP_PW_AUX_A,
> + },
> + {
> + .name = "AUX B",
> + .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
> + .ops = &skl_power_well_ops,
> + .id = GLK_DISP_PW_AUX_B,
> + },
> + {
> + .name = "AUX C",
> + .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
> + .ops = &skl_power_well_ops,
> + .id = GLK_DISP_PW_AUX_C,
> + },
> + {
> + .name = "DDI A power well",
> + .domains = GLK_DISPLAY_DDI_A_POWER_DOMAINS,
> + .ops = &skl_power_well_ops,
> + .id = GLK_DISP_PW_DDI_A,
> + },
> + {
> + .name = "DDI B power well",
> + .domains = GLK_DISPLAY_DDI_B_POWER_DOMAINS,
> + .ops = &skl_power_well_ops,
> + .id = SKL_DISP_PW_DDI_B,
> + },
> + {
> + .name = "DDI C power well",
> + .domains = GLK_DISPLAY_DDI_C_POWER_DOMAINS,
> + .ops = &skl_power_well_ops,
> + .id = SKL_DISP_PW_DDI_C,
> + },
> +};
> +
> static int
> sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
> int disable_power_well)
> @@ -2246,6 +2352,8 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> set_power_wells(power_domains, skl_power_wells);
> } else if (IS_BROXTON(dev_priv)) {
> set_power_wells(power_domains, bxt_power_wells);
> + } else if (IS_GEMINILAKE(dev_priv)) {
> + set_power_wells(power_domains, glk_power_wells);
> } else if (IS_CHERRYVIEW(dev_priv)) {
> set_power_wells(power_domains, chv_power_wells);
> } else if (IS_VALLEYVIEW(dev_priv)) {
> --
> 2.5.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 09/15] drm/i915/glk: Implement Geminilake DDI init sequence
2016-11-10 15:23 [PATCH 00/15] Geminilake enabling Ander Conselvan de Oliveira
` (7 preceding siblings ...)
2016-11-10 15:23 ` [PATCH 08/15] drm/i915/glk: Add power wells for Geminilake Ander Conselvan de Oliveira
@ 2016-11-10 15:23 ` Ander Conselvan de Oliveira
2016-11-11 1:27 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 10/15] drm/i915/glk: Set DCC delay range 2 in PLL enable sequence Ander Conselvan de Oliveira
` (10 subsequent siblings)
19 siblings, 1 reply; 52+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-11-10 15:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
Implement the DDI initsequence and add information about the different
phys in GLK.
v2: Rebase on the move of phys to be power wells.
v3: Rebase on addition of struct bxt_ddi_phy_info.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 5 +-
drivers/gpu/drm/i915/i915_reg.h | 17 +++--
drivers/gpu/drm/i915/intel_dpio_phy.c | 114 +++++++++++++++++++++++++++-----
drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 39 +++++++++++
5 files changed, 155 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4bb745a..f497396 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -207,7 +207,8 @@ enum dpio_channel {
enum dpio_phy {
DPIO_PHY0,
- DPIO_PHY1
+ DPIO_PHY1,
+ DPIO_PHY2,
};
enum intel_display_power_domain {
@@ -3888,7 +3889,7 @@ u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
/* intel_dpio_phy.c */
-void bxt_port_to_phy_channel(enum port port,
+void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
enum dpio_phy *phy, enum dpio_channel *ch);
void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
enum port port, u32 margin, u32 scale,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 78a3347..d78a3e6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -62,6 +62,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \
(port) == PORT_B ? (b) : (c))
#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PORT3(pipe, a, b, c))
+#define _PHY3(phy, a, b, c) ((phy) == DPIO_PHY0 ? (a) : \
+ (phy) == DPIO_PHY1 ? (b) : (c))
+#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
#define _MASKED_FIELD(mask, value) ({ \
if (__builtin_constant_p(mask)) \
@@ -726,6 +729,7 @@ enum skl_disp_power_wells {
BXT_DPIO_CMN_A,
BXT_DPIO_CMN_BC,
+ GLK_DPIO_CMN_C,
};
#define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
@@ -1194,8 +1198,10 @@ enum skl_disp_power_wells {
/* BXT PHY registers */
#define _BXT_PHY0_BASE 0x6C000
#define _BXT_PHY1_BASE 0x162000
-#define BXT_PHY_BASE(phy) _PIPE((phy), _BXT_PHY0_BASE, \
- _BXT_PHY1_BASE)
+#define _BXT_PHY2_BASE 0x163000
+#define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \
+ _BXT_PHY1_BASE, \
+ _BXT_PHY2_BASE)
#define _BXT_PHY(phy, reg) \
_MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
@@ -1207,7 +1213,6 @@ enum skl_disp_power_wells {
_MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
-#define GT_DISPLAY_POWER_ON(phy) (1 << (phy))
#define _BXT_PHY_CTL_DDI_A 0x64C00
#define _BXT_PHY_CTL_DDI_B 0x64C10
@@ -1220,9 +1225,11 @@ enum skl_disp_power_wells {
#define _PHY_CTL_FAMILY_EDP 0x64C80
#define _PHY_CTL_FAMILY_DDI 0x64C90
+#define _PHY_CTL_FAMILY_DDI_C 0x64CA0
#define COMMON_RESET_DIS (1 << 31)
-#define BXT_PHY_CTL_FAMILY(phy) _MMIO_PIPE((phy), _PHY_CTL_FAMILY_DDI, \
- _PHY_CTL_FAMILY_EDP)
+#define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
+ _PHY_CTL_FAMILY_EDP, \
+ _PHY_CTL_FAMILY_DDI_C)
/* BXT PHY PLL registers */
#define _PORT_PLL_A 0x46074
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index 7a8e82d..4ff601d 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -131,6 +131,18 @@ struct bxt_ddi_phy_info {
enum dpio_phy rcomp_phy;
/**
+ * @reset_delay: delay in us to wait before setting the common reset
+ * bit in BXT_PHY_CTL_FAMILY, which effectively enables the phy.
+ */
+ int reset_delay;
+
+ /**
+ * @pwron_mask: Mask with the appropriate bit set that would cause the
+ * punit to power this phy if written to BXT_P_CR_GT_DISP_PWRON.
+ */
+ u32 pwron_mask;
+
+ /**
* @channel: struct containing per channel information.
*/
struct {
@@ -145,6 +157,7 @@ static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
[DPIO_PHY0] = {
.dual_channel = true,
.rcomp_phy = DPIO_PHY1,
+ .pwron_mask = BIT(0),
.channel = {
[DPIO_CH0] = { .port = PORT_B },
@@ -154,6 +167,7 @@ static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
[DPIO_PHY1] = {
.dual_channel = false,
.rcomp_phy = -1,
+ .pwron_mask = BIT(1),
.channel = {
[DPIO_CH0] = { .port = PORT_A },
@@ -161,20 +175,77 @@ static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
},
};
+static const struct bxt_ddi_phy_info glk_ddi_phy_info[] = {
+ [DPIO_PHY0] = {
+ .dual_channel = false,
+ .rcomp_phy = DPIO_PHY1,
+ .pwron_mask = BIT(0),
+ .reset_delay = 20,
+
+ .channel = {
+ [DPIO_CH0] = { .port = PORT_B },
+ }
+ },
+ [DPIO_PHY1] = {
+ .dual_channel = false,
+ .rcomp_phy = -1,
+ .pwron_mask = BIT(3),
+ .reset_delay = 20,
+
+ .channel = {
+ [DPIO_CH0] = { .port = PORT_A },
+ }
+ },
+ [DPIO_PHY2] = {
+ .dual_channel = false,
+ .rcomp_phy = DPIO_PHY1,
+ .pwron_mask = BIT(1),
+ .reset_delay = 20,
+
+ .channel = {
+ [DPIO_CH0] = { .port = PORT_C },
+ }
+ },
+};
+
static u32 bxt_phy_port_mask(const struct bxt_ddi_phy_info *phy_info)
{
return (phy_info->dual_channel * BIT(phy_info->channel[DPIO_CH1].port)) |
BIT(phy_info->channel[DPIO_CH0].port);
}
-void bxt_port_to_phy_channel(enum port port,
+static const struct bxt_ddi_phy_info *
+bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count)
+{
+ if (IS_GEMINILAKE(dev_priv)) {
+ *count = ARRAY_SIZE(glk_ddi_phy_info);
+ return glk_ddi_phy_info;
+ } else {
+ *count = ARRAY_SIZE(bxt_ddi_phy_info);
+ return bxt_ddi_phy_info;
+ }
+}
+
+static const struct bxt_ddi_phy_info *
+bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+{
+ int count;
+ const struct bxt_ddi_phy_info *phy_list =
+ bxt_get_phy_list(dev_priv, &count);
+
+ return &phy_list[phy];
+}
+
+void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
enum dpio_phy *phy, enum dpio_channel *ch)
{
- const struct bxt_ddi_phy_info *phy_info;
- int i;
+ const struct bxt_ddi_phy_info *phy_info, *phys;
+ int i, count;
+
+ phys = bxt_get_phy_list(dev_priv, &count);
- for (i = 0; i < ARRAY_SIZE(bxt_ddi_phy_info); i++) {
- phy_info = &bxt_ddi_phy_info[i];
+ for (i = 0; i < count; i++) {
+ phy_info = &phys[i];
if (port == phy_info->channel[DPIO_CH0].port) {
*phy = i;
@@ -203,7 +274,7 @@ void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
enum dpio_phy phy;
enum dpio_channel ch;
- bxt_port_to_phy_channel(port, &phy, &ch);
+ bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
/*
* While we write to the group register to program all lanes at once we
@@ -241,10 +312,12 @@ void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
enum dpio_phy phy)
{
- const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
+ const struct bxt_ddi_phy_info *phy_info;
enum port port;
- if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
+ phy_info = bxt_get_phy_info(dev_priv, phy);
+
+ if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))
return false;
if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
@@ -306,9 +379,11 @@ static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
enum dpio_phy phy)
{
- const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
+ const struct bxt_ddi_phy_info *phy_info;
u32 val;
+ phy_info = bxt_get_phy_info(dev_priv, phy);
+
if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
/* Still read out the GRC value for state verification */
if (phy_info->rcomp_phy != -1)
@@ -326,7 +401,7 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
}
val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
- val |= GT_DISPLAY_POWER_ON(phy);
+ val |= phy_info->pwron_mask;
I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
/*
@@ -384,6 +459,9 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
I915_WRITE(BXT_PORT_REF_DW8(phy), val);
}
+ if (phy_info->reset_delay)
+ udelay(phy_info->reset_delay);
+
val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
val |= COMMON_RESET_DIS;
I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
@@ -395,20 +473,24 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
{
+ const struct bxt_ddi_phy_info *phy_info;
uint32_t val;
+ phy_info = bxt_get_phy_info(dev_priv, phy);
+
val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
val &= ~COMMON_RESET_DIS;
I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
- val &= ~GT_DISPLAY_POWER_ON(phy);
+ val &= ~phy_info->pwron_mask;
I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
}
void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
{
- const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
+ const struct bxt_ddi_phy_info *phy_info =
+ bxt_get_phy_info(dev_priv, phy);
enum dpio_phy rcomp_phy = phy_info->rcomp_phy;
bool was_enabled;
@@ -461,10 +543,12 @@ __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
enum dpio_phy phy)
{
- const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
+ const struct bxt_ddi_phy_info *phy_info;
uint32_t mask;
bool ok;
+ phy_info = bxt_get_phy_info(dev_priv, phy);
+
#define _CHK(reg, mask, exp, fmt, ...) \
__phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \
## __VA_ARGS__)
@@ -540,7 +624,7 @@ void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
enum dpio_channel ch;
int lane;
- bxt_port_to_phy_channel(port, &phy, &ch);
+ bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
for (lane = 0; lane < 4; lane++) {
u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));
@@ -568,7 +652,7 @@ bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
int lane;
uint8_t mask;
- bxt_port_to_phy_channel(port, &phy, &ch);
+ bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
mask = 0;
for (lane = 0; lane < 4; lane++) {
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 8205c1c..0311fd4 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1374,7 +1374,7 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
enum dpio_phy phy;
enum dpio_channel ch;
- bxt_port_to_phy_channel(port, &phy, &ch);
+ bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
/* Non-SSC reference */
temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
@@ -1492,7 +1492,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
enum dpio_phy phy;
enum dpio_channel ch;
- bxt_port_to_phy_channel(port, &phy, &ch);
+ bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
return false;
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 683c15b..30d5112 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -477,6 +477,18 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
#define GLK_DISPLAY_DDI_C_POWER_DOMAINS ( \
BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
BIT(POWER_DOMAIN_INIT))
+#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \
+ BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
+ BIT(POWER_DOMAIN_AUX_A) | \
+ BIT(POWER_DOMAIN_INIT))
+#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \
+ BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT(POWER_DOMAIN_AUX_B) | \
+ BIT(POWER_DOMAIN_INIT))
+#define GLK_DPIO_CMN_C_POWER_DOMAINS ( \
+ BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT(POWER_DOMAIN_AUX_C) | \
+ BIT(POWER_DOMAIN_INIT))
#define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \
BIT(POWER_DOMAIN_AUX_A) | \
BIT(POWER_DOMAIN_INIT))
@@ -926,6 +938,12 @@ static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC);
if (power_well->count > 0)
bxt_ddi_phy_verify_state(dev_priv, power_well->data);
+
+ if (IS_GEMINILAKE(dev_priv)) {
+ power_well = lookup_power_well(dev_priv, GLK_DPIO_CMN_C);
+ if (power_well->count > 0)
+ bxt_ddi_phy_verify_state(dev_priv, power_well->data);
+ }
}
static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
@@ -2219,6 +2237,27 @@ static struct i915_power_well glk_power_wells[] = {
.id = SKL_DISP_PW_2,
},
{
+ .name = "dpio-common-a",
+ .domains = GLK_DPIO_CMN_A_POWER_DOMAINS,
+ .ops = &bxt_dpio_cmn_power_well_ops,
+ .id = BXT_DPIO_CMN_A,
+ .data = DPIO_PHY1,
+ },
+ {
+ .name = "dpio-common-b",
+ .domains = GLK_DPIO_CMN_B_POWER_DOMAINS,
+ .ops = &bxt_dpio_cmn_power_well_ops,
+ .id = BXT_DPIO_CMN_BC,
+ .data = DPIO_PHY0,
+ },
+ {
+ .name = "dpio-common-c",
+ .domains = GLK_DPIO_CMN_C_POWER_DOMAINS,
+ .ops = &bxt_dpio_cmn_power_well_ops,
+ .id = GLK_DPIO_CMN_C,
+ .data = DPIO_PHY2,
+ },
+ {
.name = "AUX A",
.domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
.ops = &skl_power_well_ops,
--
2.5.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 09/15] drm/i915/glk: Implement Geminilake DDI init sequence
2016-11-10 15:23 ` [PATCH 09/15] drm/i915/glk: Implement Geminilake DDI init sequence Ander Conselvan de Oliveira
@ 2016-11-11 1:27 ` Rodrigo Vivi
0 siblings, 0 replies; 52+ messages in thread
From: Rodrigo Vivi @ 2016-11-11 1:27 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
On Thu, Nov 10, 2016 at 05:23:14PM +0200, Ander Conselvan de Oliveira wrote:
> Implement the DDI initsequence and add information about the different
> phys in GLK.
>
> v2: Rebase on the move of phys to be power wells.
>
> v3: Rebase on addition of struct bxt_ddi_phy_info.
>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 5 +-
> drivers/gpu/drm/i915/i915_reg.h | 17 +++--
> drivers/gpu/drm/i915/intel_dpio_phy.c | 114 +++++++++++++++++++++++++++-----
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 39 +++++++++++
> 5 files changed, 155 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4bb745a..f497396 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -207,7 +207,8 @@ enum dpio_channel {
>
> enum dpio_phy {
> DPIO_PHY0,
> - DPIO_PHY1
> + DPIO_PHY1,
> + DPIO_PHY2,
> };
>
> enum intel_display_power_domain {
> @@ -3888,7 +3889,7 @@ u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
> void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>
> /* intel_dpio_phy.c */
> -void bxt_port_to_phy_channel(enum port port,
> +void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
> enum dpio_phy *phy, enum dpio_channel *ch);
> void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
> enum port port, u32 margin, u32 scale,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 78a3347..d78a3e6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -62,6 +62,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \
> (port) == PORT_B ? (b) : (c))
> #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PORT3(pipe, a, b, c))
> +#define _PHY3(phy, a, b, c) ((phy) == DPIO_PHY0 ? (a) : \
> + (phy) == DPIO_PHY1 ? (b) : (c))
> +#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
>
> #define _MASKED_FIELD(mask, value) ({ \
> if (__builtin_constant_p(mask)) \
> @@ -726,6 +729,7 @@ enum skl_disp_power_wells {
>
> BXT_DPIO_CMN_A,
> BXT_DPIO_CMN_BC,
> + GLK_DPIO_CMN_C,
> };
>
> #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
> @@ -1194,8 +1198,10 @@ enum skl_disp_power_wells {
> /* BXT PHY registers */
> #define _BXT_PHY0_BASE 0x6C000
> #define _BXT_PHY1_BASE 0x162000
> -#define BXT_PHY_BASE(phy) _PIPE((phy), _BXT_PHY0_BASE, \
> - _BXT_PHY1_BASE)
> +#define _BXT_PHY2_BASE 0x163000
> +#define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \
> + _BXT_PHY1_BASE, \
> + _BXT_PHY2_BASE)
>
> #define _BXT_PHY(phy, reg) \
> _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
> @@ -1207,7 +1213,6 @@ enum skl_disp_power_wells {
> _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
>
> #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
> -#define GT_DISPLAY_POWER_ON(phy) (1 << (phy))
>
> #define _BXT_PHY_CTL_DDI_A 0x64C00
> #define _BXT_PHY_CTL_DDI_B 0x64C10
> @@ -1220,9 +1225,11 @@ enum skl_disp_power_wells {
>
> #define _PHY_CTL_FAMILY_EDP 0x64C80
> #define _PHY_CTL_FAMILY_DDI 0x64C90
> +#define _PHY_CTL_FAMILY_DDI_C 0x64CA0
> #define COMMON_RESET_DIS (1 << 31)
> -#define BXT_PHY_CTL_FAMILY(phy) _MMIO_PIPE((phy), _PHY_CTL_FAMILY_DDI, \
> - _PHY_CTL_FAMILY_EDP)
> +#define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
> + _PHY_CTL_FAMILY_EDP, \
> + _PHY_CTL_FAMILY_DDI_C)
>
> /* BXT PHY PLL registers */
> #define _PORT_PLL_A 0x46074
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index 7a8e82d..4ff601d 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -131,6 +131,18 @@ struct bxt_ddi_phy_info {
> enum dpio_phy rcomp_phy;
>
> /**
> + * @reset_delay: delay in us to wait before setting the common reset
> + * bit in BXT_PHY_CTL_FAMILY, which effectively enables the phy.
> + */
> + int reset_delay;
> +
> + /**
> + * @pwron_mask: Mask with the appropriate bit set that would cause the
> + * punit to power this phy if written to BXT_P_CR_GT_DISP_PWRON.
> + */
> + u32 pwron_mask;
> +
> + /**
> * @channel: struct containing per channel information.
> */
> struct {
> @@ -145,6 +157,7 @@ static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
> [DPIO_PHY0] = {
> .dual_channel = true,
> .rcomp_phy = DPIO_PHY1,
> + .pwron_mask = BIT(0),
>
> .channel = {
> [DPIO_CH0] = { .port = PORT_B },
> @@ -154,6 +167,7 @@ static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
> [DPIO_PHY1] = {
> .dual_channel = false,
> .rcomp_phy = -1,
> + .pwron_mask = BIT(1),
>
> .channel = {
> [DPIO_CH0] = { .port = PORT_A },
> @@ -161,20 +175,77 @@ static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
> },
> };
>
> +static const struct bxt_ddi_phy_info glk_ddi_phy_info[] = {
> + [DPIO_PHY0] = {
> + .dual_channel = false,
> + .rcomp_phy = DPIO_PHY1,
> + .pwron_mask = BIT(0),
> + .reset_delay = 20,
> +
> + .channel = {
> + [DPIO_CH0] = { .port = PORT_B },
> + }
> + },
> + [DPIO_PHY1] = {
> + .dual_channel = false,
> + .rcomp_phy = -1,
> + .pwron_mask = BIT(3),
> + .reset_delay = 20,
> +
> + .channel = {
> + [DPIO_CH0] = { .port = PORT_A },
> + }
> + },
> + [DPIO_PHY2] = {
> + .dual_channel = false,
> + .rcomp_phy = DPIO_PHY1,
> + .pwron_mask = BIT(1),
> + .reset_delay = 20,
> +
> + .channel = {
> + [DPIO_CH0] = { .port = PORT_C },
> + }
> + },
> +};
> +
> static u32 bxt_phy_port_mask(const struct bxt_ddi_phy_info *phy_info)
> {
> return (phy_info->dual_channel * BIT(phy_info->channel[DPIO_CH1].port)) |
> BIT(phy_info->channel[DPIO_CH0].port);
> }
>
> -void bxt_port_to_phy_channel(enum port port,
> +static const struct bxt_ddi_phy_info *
> +bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count)
> +{
> + if (IS_GEMINILAKE(dev_priv)) {
> + *count = ARRAY_SIZE(glk_ddi_phy_info);
> + return glk_ddi_phy_info;
> + } else {
> + *count = ARRAY_SIZE(bxt_ddi_phy_info);
> + return bxt_ddi_phy_info;
> + }
> +}
> +
> +static const struct bxt_ddi_phy_info *
> +bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy)
> +{
> + int count;
> + const struct bxt_ddi_phy_info *phy_list =
> + bxt_get_phy_list(dev_priv, &count);
> +
> + return &phy_list[phy];
> +}
> +
> +void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
> enum dpio_phy *phy, enum dpio_channel *ch)
> {
> - const struct bxt_ddi_phy_info *phy_info;
> - int i;
> + const struct bxt_ddi_phy_info *phy_info, *phys;
> + int i, count;
> +
> + phys = bxt_get_phy_list(dev_priv, &count);
>
> - for (i = 0; i < ARRAY_SIZE(bxt_ddi_phy_info); i++) {
> - phy_info = &bxt_ddi_phy_info[i];
> + for (i = 0; i < count; i++) {
> + phy_info = &phys[i];
>
> if (port == phy_info->channel[DPIO_CH0].port) {
> *phy = i;
> @@ -203,7 +274,7 @@ void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
> enum dpio_phy phy;
> enum dpio_channel ch;
>
> - bxt_port_to_phy_channel(port, &phy, &ch);
> + bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
>
> /*
> * While we write to the group register to program all lanes at once we
> @@ -241,10 +312,12 @@ void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
> bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
> enum dpio_phy phy)
> {
> - const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
> + const struct bxt_ddi_phy_info *phy_info;
> enum port port;
>
> - if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
> + phy_info = bxt_get_phy_info(dev_priv, phy);
> +
> + if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))
> return false;
>
> if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
> @@ -306,9 +379,11 @@ static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
> static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
> enum dpio_phy phy)
> {
> - const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
> + const struct bxt_ddi_phy_info *phy_info;
> u32 val;
>
> + phy_info = bxt_get_phy_info(dev_priv, phy);
> +
> if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
> /* Still read out the GRC value for state verification */
> if (phy_info->rcomp_phy != -1)
> @@ -326,7 +401,7 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
> }
>
> val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
> - val |= GT_DISPLAY_POWER_ON(phy);
> + val |= phy_info->pwron_mask;
> I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
>
> /*
> @@ -384,6 +459,9 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
> I915_WRITE(BXT_PORT_REF_DW8(phy), val);
> }
>
> + if (phy_info->reset_delay)
> + udelay(phy_info->reset_delay);
> +
> val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
> val |= COMMON_RESET_DIS;
> I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
> @@ -395,20 +473,24 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
>
> void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
> {
> + const struct bxt_ddi_phy_info *phy_info;
> uint32_t val;
>
> + phy_info = bxt_get_phy_info(dev_priv, phy);
> +
> val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
> val &= ~COMMON_RESET_DIS;
> I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
>
> val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
> - val &= ~GT_DISPLAY_POWER_ON(phy);
> + val &= ~phy_info->pwron_mask;
> I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
> }
>
> void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
> {
> - const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
> + const struct bxt_ddi_phy_info *phy_info =
> + bxt_get_phy_info(dev_priv, phy);
> enum dpio_phy rcomp_phy = phy_info->rcomp_phy;
> bool was_enabled;
>
> @@ -461,10 +543,12 @@ __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
> bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
> enum dpio_phy phy)
> {
> - const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy];
> + const struct bxt_ddi_phy_info *phy_info;
> uint32_t mask;
> bool ok;
>
> + phy_info = bxt_get_phy_info(dev_priv, phy);
> +
> #define _CHK(reg, mask, exp, fmt, ...) \
> __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \
> ## __VA_ARGS__)
> @@ -540,7 +624,7 @@ void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
> enum dpio_channel ch;
> int lane;
>
> - bxt_port_to_phy_channel(port, &phy, &ch);
> + bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
>
> for (lane = 0; lane < 4; lane++) {
> u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));
> @@ -568,7 +652,7 @@ bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
> int lane;
> uint8_t mask;
>
> - bxt_port_to_phy_channel(port, &phy, &ch);
> + bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
>
> mask = 0;
> for (lane = 0; lane < 4; lane++) {
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 8205c1c..0311fd4 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1374,7 +1374,7 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
> enum dpio_phy phy;
> enum dpio_channel ch;
>
> - bxt_port_to_phy_channel(port, &phy, &ch);
> + bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
>
> /* Non-SSC reference */
> temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
> @@ -1492,7 +1492,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
> enum dpio_phy phy;
> enum dpio_channel ch;
>
> - bxt_port_to_phy_channel(port, &phy, &ch);
> + bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
>
> if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
> return false;
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 683c15b..30d5112 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -477,6 +477,18 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
> #define GLK_DISPLAY_DDI_C_POWER_DOMAINS ( \
> BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> BIT(POWER_DOMAIN_INIT))
> +#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \
> + BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
> + BIT(POWER_DOMAIN_AUX_A) | \
> + BIT(POWER_DOMAIN_INIT))
> +#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \
> + BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT(POWER_DOMAIN_AUX_B) | \
> + BIT(POWER_DOMAIN_INIT))
> +#define GLK_DPIO_CMN_C_POWER_DOMAINS ( \
> + BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT(POWER_DOMAIN_AUX_C) | \
> + BIT(POWER_DOMAIN_INIT))
> #define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \
> BIT(POWER_DOMAIN_AUX_A) | \
> BIT(POWER_DOMAIN_INIT))
> @@ -926,6 +938,12 @@ static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
> power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC);
> if (power_well->count > 0)
> bxt_ddi_phy_verify_state(dev_priv, power_well->data);
> +
> + if (IS_GEMINILAKE(dev_priv)) {
> + power_well = lookup_power_well(dev_priv, GLK_DPIO_CMN_C);
> + if (power_well->count > 0)
> + bxt_ddi_phy_verify_state(dev_priv, power_well->data);
> + }
> }
>
> static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
> @@ -2219,6 +2237,27 @@ static struct i915_power_well glk_power_wells[] = {
> .id = SKL_DISP_PW_2,
> },
> {
> + .name = "dpio-common-a",
> + .domains = GLK_DPIO_CMN_A_POWER_DOMAINS,
> + .ops = &bxt_dpio_cmn_power_well_ops,
> + .id = BXT_DPIO_CMN_A,
> + .data = DPIO_PHY1,
> + },
> + {
> + .name = "dpio-common-b",
> + .domains = GLK_DPIO_CMN_B_POWER_DOMAINS,
> + .ops = &bxt_dpio_cmn_power_well_ops,
> + .id = BXT_DPIO_CMN_BC,
> + .data = DPIO_PHY0,
> + },
> + {
> + .name = "dpio-common-c",
> + .domains = GLK_DPIO_CMN_C_POWER_DOMAINS,
> + .ops = &bxt_dpio_cmn_power_well_ops,
> + .id = GLK_DPIO_CMN_C,
> + .data = DPIO_PHY2,
> + },
> + {
> .name = "AUX A",
> .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
> .ops = &skl_power_well_ops,
> --
> 2.5.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 10/15] drm/i915/glk: Set DCC delay range 2 in PLL enable sequence
2016-11-10 15:23 [PATCH 00/15] Geminilake enabling Ander Conselvan de Oliveira
` (8 preceding siblings ...)
2016-11-10 15:23 ` [PATCH 09/15] drm/i915/glk: Implement Geminilake DDI init sequence Ander Conselvan de Oliveira
@ 2016-11-10 15:23 ` Ander Conselvan de Oliveira
2016-11-29 15:48 ` [PATCH v2] " Ander Conselvan de Oliveira
2016-11-10 15:23 ` [PATCH 11/15] drm/i915/glk: Update Port PLL enable sequence for Geminilkae Ander Conselvan de Oliveira
` (9 subsequent siblings)
19 siblings, 1 reply; 52+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-11-10 15:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
Follow the PLL enable sequence updated in bspec, which requires the DCC
delay range 2 bit to be set.
v2: Moved from DDI init sequence to PLL enable.
Signed-off-by: Ander Conselvan De Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++++++
drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 ++++++
2 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d78a3e6..88f9f2b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1448,6 +1448,21 @@ enum skl_disp_power_wells {
#define DEEMPH_SHIFT 24
#define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
+#define _PORT_TX_DW5_LN0_A 0x162514
+#define _PORT_TX_DW5_LN0_B 0x6C514
+#define _PORT_TX_DW5_LN0_C 0x6C914
+#define _PORT_TX_DW5_GRP_A 0x162D14
+#define _PORT_TX_DW5_GRP_B 0x6CD14
+#define _PORT_TX_DW5_GRP_C 0x6CF14
+#define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
+ _PORT_TX_DW5_LN0_B, \
+ _PORT_TX_DW5_LN0_C)
+#define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
+ _PORT_TX_DW5_GRP_B, \
+ _PORT_TX_DW5_GRP_C)
+#define DCC_DELAY_RANGE_1 (1 << 9)
+#define DCC_DELAY_RANGE_2 (1 << 8)
+
#define _PORT_TX_DW14_LN0_A 0x162538
#define _PORT_TX_DW14_LN0_B 0x6C538
#define _PORT_TX_DW14_LN0_C 0x6C938
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 0311fd4..24a28b2 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1459,6 +1459,12 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
200))
DRM_ERROR("PLL %d not locked\n", port);
+ if (IS_GEMINILAKE(dev_priv)) {
+ temp = I915_READ(BXT_PORT_TX_DW5_GRP(phy, ch));
+ temp |= DCC_DELAY_RANGE_2;
+ I915_WRITE(BXT_PORT_TX_DW5_GRP(phy, ch), temp);
+ }
+
/*
* While we write to the group register to program all lanes at once we
* can read only lane registers and we pick lanes 0/1 for that.
--
2.5.5
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^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v2] drm/i915/glk: Set DCC delay range 2 in PLL enable sequence
2016-11-10 15:23 ` [PATCH 10/15] drm/i915/glk: Set DCC delay range 2 in PLL enable sequence Ander Conselvan de Oliveira
@ 2016-11-29 15:48 ` Ander Conselvan de Oliveira
2016-11-29 16:58 ` Vivi, Rodrigo
0 siblings, 1 reply; 52+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-11-29 15:48 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira, Rodrigo Vivi
Follow the PLL enable sequence updated in bspec, which requires the DCC
delay range 2 bit to be set.
v2: Moved from DDI init sequence to PLL enable.
v3: Don't read value from GRP register. (Rodrido)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ander Conselvan De Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++++++
drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 ++++++
2 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d1f0720..6cff01d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1784,6 +1784,21 @@ enum skl_disp_power_wells {
#define DEEMPH_SHIFT 24
#define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
+#define _PORT_TX_DW5_LN0_A 0x162514
+#define _PORT_TX_DW5_LN0_B 0x6C514
+#define _PORT_TX_DW5_LN0_C 0x6C914
+#define _PORT_TX_DW5_GRP_A 0x162D14
+#define _PORT_TX_DW5_GRP_B 0x6CD14
+#define _PORT_TX_DW5_GRP_C 0x6CF14
+#define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
+ _PORT_TX_DW5_LN0_B, \
+ _PORT_TX_DW5_LN0_C)
+#define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
+ _PORT_TX_DW5_GRP_B, \
+ _PORT_TX_DW5_GRP_C)
+#define DCC_DELAY_RANGE_1 (1 << 9)
+#define DCC_DELAY_RANGE_2 (1 << 8)
+
#define _PORT_TX_DW14_LN0_A 0x162538
#define _PORT_TX_DW14_LN0_B 0x6C538
#define _PORT_TX_DW14_LN0_C 0x6C938
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 8a82507..63104b7 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1458,6 +1458,12 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
200))
DRM_ERROR("PLL %d not locked\n", port);
+ if (IS_GEMINILAKE(dev_priv)) {
+ temp = I915_READ(BXT_PORT_TX_DW5_LN0(phy, ch));
+ temp |= DCC_DELAY_RANGE_2;
+ I915_WRITE(BXT_PORT_TX_DW5_GRP(phy, ch), temp);
+ }
+
/*
* While we write to the group register to program all lanes at once we
* can read only lane registers and we pick lanes 0/1 for that.
--
2.5.5
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^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH v2] drm/i915/glk: Set DCC delay range 2 in PLL enable sequence
2016-11-29 15:48 ` [PATCH v2] " Ander Conselvan de Oliveira
@ 2016-11-29 16:58 ` Vivi, Rodrigo
0 siblings, 0 replies; 52+ messages in thread
From: Vivi, Rodrigo @ 2016-11-29 16:58 UTC (permalink / raw)
To: Conselvan De Oliveira, Ander; +Cc: intel-gfx
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
On Tue, 2016-11-29 at 17:48 +0200, Ander Conselvan de Oliveira wrote:
> Follow the PLL enable sequence updated in bspec, which requires the DCC
> delay range 2 bit to be set.
>
> v2: Moved from DDI init sequence to PLL enable.
> v3: Don't read value from GRP register. (Rodrido)
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Ander Conselvan De Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++++++
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 ++++++
> 2 files changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d1f0720..6cff01d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1784,6 +1784,21 @@ enum skl_disp_power_wells {
> #define DEEMPH_SHIFT 24
> #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
>
> +#define _PORT_TX_DW5_LN0_A 0x162514
> +#define _PORT_TX_DW5_LN0_B 0x6C514
> +#define _PORT_TX_DW5_LN0_C 0x6C914
> +#define _PORT_TX_DW5_GRP_A 0x162D14
> +#define _PORT_TX_DW5_GRP_B 0x6CD14
> +#define _PORT_TX_DW5_GRP_C 0x6CF14
> +#define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
> + _PORT_TX_DW5_LN0_B, \
> + _PORT_TX_DW5_LN0_C)
> +#define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
> + _PORT_TX_DW5_GRP_B, \
> + _PORT_TX_DW5_GRP_C)
> +#define DCC_DELAY_RANGE_1 (1 << 9)
> +#define DCC_DELAY_RANGE_2 (1 << 8)
> +
> #define _PORT_TX_DW14_LN0_A 0x162538
> #define _PORT_TX_DW14_LN0_B 0x6C538
> #define _PORT_TX_DW14_LN0_C 0x6C938
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 8a82507..63104b7 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1458,6 +1458,12 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
> 200))
> DRM_ERROR("PLL %d not locked\n", port);
>
> + if (IS_GEMINILAKE(dev_priv)) {
> + temp = I915_READ(BXT_PORT_TX_DW5_LN0(phy, ch));
> + temp |= DCC_DELAY_RANGE_2;
> + I915_WRITE(BXT_PORT_TX_DW5_GRP(phy, ch), temp);
> + }
> +
> /*
> * While we write to the group register to program all lanes at once we
> * can read only lane registers and we pick lanes 0/1 for that.
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^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 11/15] drm/i915/glk: Update Port PLL enable sequence for Geminilkae
2016-11-10 15:23 [PATCH 00/15] Geminilake enabling Ander Conselvan de Oliveira
` (9 preceding siblings ...)
2016-11-10 15:23 ` [PATCH 10/15] drm/i915/glk: Set DCC delay range 2 in PLL enable sequence Ander Conselvan de Oliveira
@ 2016-11-10 15:23 ` Ander Conselvan de Oliveira
2016-12-02 0:44 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 12/15] drm/i915/glk: Reuse broxton's cdclk code for GLK Ander Conselvan de Oliveira
` (8 subsequent siblings)
19 siblings, 1 reply; 52+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-11-10 15:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
From: Madhav Chauhan <madhav.chauhan@intel.com>
Add steps for enabling and disabling Port PLL as per bspec.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_dpll_mgr.c | 20 ++++++++++++++++++++
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 88f9f2b..98e24a7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1238,6 +1238,8 @@ enum skl_disp_power_wells {
#define PORT_PLL_ENABLE (1 << 31)
#define PORT_PLL_LOCK (1 << 30)
#define PORT_PLL_REF_SEL (1 << 27)
+#define PORT_PLL_POWER_ENABLE (1 << 26)
+#define PORT_PLL_POWER_STATE (1 << 25)
#define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
#define _PORT_PLL_EBB_0_A 0x162034
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 24a28b2..35f5f1a 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1381,6 +1381,16 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
temp |= PORT_PLL_REF_SEL;
I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
+ if (IS_GEMINILAKE(dev_priv)) {
+ temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
+ temp |= PORT_PLL_POWER_ENABLE;
+ I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
+
+ if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
+ PORT_PLL_POWER_STATE), 200))
+ DRM_ERROR("Power state not set for PLL:%d\n", port);
+ }
+
/* Disable 10 bit clock */
temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
@@ -1486,6 +1496,16 @@ static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
temp &= ~PORT_PLL_ENABLE;
I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
POSTING_READ(BXT_PORT_PLL_ENABLE(port));
+
+ if (IS_GEMINILAKE(dev_priv)) {
+ temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
+ temp &= ~PORT_PLL_POWER_ENABLE;
+ I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
+
+ if (wait_for_us(!(I915_READ(BXT_PORT_PLL_ENABLE(port)) &
+ PORT_PLL_POWER_STATE), 200))
+ DRM_ERROR("Power state not reset for PLL:%d\n", port);
+ }
}
static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 11/15] drm/i915/glk: Update Port PLL enable sequence for Geminilkae
2016-11-10 15:23 ` [PATCH 11/15] drm/i915/glk: Update Port PLL enable sequence for Geminilkae Ander Conselvan de Oliveira
@ 2016-12-02 0:44 ` Rodrigo Vivi
0 siblings, 0 replies; 52+ messages in thread
From: Rodrigo Vivi @ 2016-12-02 0:44 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
On Thu, Nov 10, 2016 at 05:23:16PM +0200, Ander Conselvan de Oliveira wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> Add steps for enabling and disabling Port PLL as per bspec.
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 20 ++++++++++++++++++++
> 2 files changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 88f9f2b..98e24a7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1238,6 +1238,8 @@ enum skl_disp_power_wells {
> #define PORT_PLL_ENABLE (1 << 31)
> #define PORT_PLL_LOCK (1 << 30)
> #define PORT_PLL_REF_SEL (1 << 27)
> +#define PORT_PLL_POWER_ENABLE (1 << 26)
> +#define PORT_PLL_POWER_STATE (1 << 25)
> #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
>
> #define _PORT_PLL_EBB_0_A 0x162034
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 24a28b2..35f5f1a 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1381,6 +1381,16 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
> temp |= PORT_PLL_REF_SEL;
> I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
>
> + if (IS_GEMINILAKE(dev_priv)) {
> + temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
> + temp |= PORT_PLL_POWER_ENABLE;
> + I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
> +
> + if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
> + PORT_PLL_POWER_STATE), 200))
> + DRM_ERROR("Power state not set for PLL:%d\n", port);
> + }
> +
> /* Disable 10 bit clock */
> temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
> temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
> @@ -1486,6 +1496,16 @@ static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
> temp &= ~PORT_PLL_ENABLE;
> I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
> POSTING_READ(BXT_PORT_PLL_ENABLE(port));
> +
> + if (IS_GEMINILAKE(dev_priv)) {
> + temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
> + temp &= ~PORT_PLL_POWER_ENABLE;
> + I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
> +
> + if (wait_for_us(!(I915_READ(BXT_PORT_PLL_ENABLE(port)) &
> + PORT_PLL_POWER_STATE), 200))
> + DRM_ERROR("Power state not reset for PLL:%d\n", port);
> + }
> }
>
> static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
> --
> 2.5.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 12/15] drm/i915/glk: Reuse broxton's cdclk code for GLK
2016-11-10 15:23 [PATCH 00/15] Geminilake enabling Ander Conselvan de Oliveira
` (10 preceding siblings ...)
2016-11-10 15:23 ` [PATCH 11/15] drm/i915/glk: Update Port PLL enable sequence for Geminilkae Ander Conselvan de Oliveira
@ 2016-11-10 15:23 ` Ander Conselvan de Oliveira
2016-12-02 0:43 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 13/15] drm/i915/glk: Allow dotclock up to 2 * cdclk on geminilake Ander Conselvan de Oliveira
` (7 subsequent siblings)
19 siblings, 1 reply; 52+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-11-10 15:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
Geminilake has the same register layout, reference clock and programming
sequence as broxton. The difference is that it doesn't support the 1.5
divider and has different ratios, but a lot of code can be shared
between the two platforms.
v2: Rebase (s/broxton/bxt).
v3: Fix vco calculation in glk_de_pll_vco().
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 73 ++++++++++++++++++++++++++++++++----
1 file changed, 65 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4069a6e..62cc390 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -124,6 +124,7 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc);
static void intel_modeset_setup_hw_state(struct drm_device *dev);
static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
static int ilk_max_pixel_rate(struct drm_atomic_state *state);
+static int glk_calc_cdclk(int max_pixclk);
static int bxt_calc_cdclk(int max_pixclk);
struct intel_limit {
@@ -5866,6 +5867,8 @@ static void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
max_cdclk = 308571;
dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
+ } else if (IS_GEMINILAKE(dev_priv)) {
+ dev_priv->max_cdclk_freq = 316800;
} else if (IS_BROXTON(dev_priv)) {
dev_priv->max_cdclk_freq = 624000;
} else if (IS_BROADWELL(dev_priv)) {
@@ -5953,6 +5956,26 @@ static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
return dev_priv->cdclk_pll.ref * ratio;
}
+static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
+{
+ int ratio;
+
+ if (cdclk == dev_priv->cdclk_pll.ref)
+ return 0;
+
+ switch (cdclk) {
+ default:
+ MISSING_CASE(cdclk);
+ case 79200:
+ case 158400:
+ case 316800:
+ ratio = 33;
+ break;
+ }
+
+ return dev_priv->cdclk_pll.ref * ratio;
+}
+
static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
{
I915_WRITE(BXT_DE_PLL_ENABLE, 0);
@@ -5994,7 +6017,10 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
u32 val, divider;
int vco, ret;
- vco = bxt_de_pll_vco(dev_priv, cdclk);
+ if (IS_GEMINILAKE(dev_priv))
+ vco = glk_de_pll_vco(dev_priv, cdclk);
+ else
+ vco = bxt_de_pll_vco(dev_priv, cdclk);
DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
@@ -6007,6 +6033,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
divider = BXT_CDCLK_CD2X_DIV_SEL_2;
break;
case 3:
+ WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
break;
case 2:
@@ -6116,6 +6143,8 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
void bxt_init_cdclk(struct drm_i915_private *dev_priv)
{
+ int cdclk;
+
bxt_sanitize_cdclk(dev_priv);
if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
@@ -6126,7 +6155,12 @@ void bxt_init_cdclk(struct drm_i915_private *dev_priv)
* - The initial CDCLK needs to be read from VBT.
* Need to make this change after VBT has changes for BXT.
*/
- bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
+ if (IS_GEMINILAKE(dev_priv))
+ cdclk = glk_calc_cdclk(0);
+ else
+ cdclk = bxt_calc_cdclk(0);
+
+ bxt_set_cdclk(dev_priv, cdclk);
}
void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
@@ -6552,6 +6586,16 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
return 200000;
}
+static int glk_calc_cdclk(int max_pixclk)
+{
+ if (max_pixclk > 158400)
+ return 316800;
+ else if (max_pixclk > 79200)
+ return 158400;
+ else
+ return 79200;
+}
+
static int bxt_calc_cdclk(int max_pixclk)
{
if (max_pixclk > 576000)
@@ -6614,15 +6658,27 @@ static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
{
+ struct drm_i915_private *dev_priv = to_i915(state->dev);
int max_pixclk = ilk_max_pixel_rate(state);
struct intel_atomic_state *intel_state =
to_intel_atomic_state(state);
+ int cdclk;
- intel_state->cdclk = intel_state->dev_cdclk =
- bxt_calc_cdclk(max_pixclk);
+ if (IS_GEMINILAKE(dev_priv))
+ cdclk = glk_calc_cdclk(max_pixclk);
+ else
+ cdclk = bxt_calc_cdclk(max_pixclk);
- if (!intel_state->active_crtcs)
- intel_state->dev_cdclk = bxt_calc_cdclk(0);
+ intel_state->cdclk = intel_state->dev_cdclk = cdclk;
+
+ if (!intel_state->active_crtcs) {
+ if (IS_GEMINILAKE(dev_priv))
+ cdclk = glk_calc_cdclk(0);
+ else
+ cdclk = bxt_calc_cdclk(0);
+
+ intel_state->dev_cdclk = cdclk;
+ }
return 0;
}
@@ -7324,6 +7380,7 @@ static int broxton_get_display_clock_speed(struct drm_i915_private *dev_priv)
div = 2;
break;
case BXT_CDCLK_CD2X_DIV_SEL_1_5:
+ WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
div = 3;
break;
case BXT_CDCLK_CD2X_DIV_SEL_2:
@@ -16022,7 +16079,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
dev_priv->display.get_display_clock_speed =
skylake_get_display_clock_speed;
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
dev_priv->display.get_display_clock_speed =
broxton_get_display_clock_speed;
else if (IS_BROADWELL(dev_priv))
@@ -16095,7 +16152,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
valleyview_modeset_commit_cdclk;
dev_priv->display.modeset_calc_cdclk =
valleyview_modeset_calc_cdclk;
- } else if (IS_BROXTON(dev_priv)) {
+ } else if (IS_GEN9_LP(dev_priv)) {
dev_priv->display.modeset_commit_cdclk =
bxt_modeset_commit_cdclk;
dev_priv->display.modeset_calc_cdclk =
--
2.5.5
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^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 12/15] drm/i915/glk: Reuse broxton's cdclk code for GLK
2016-11-10 15:23 ` [PATCH 12/15] drm/i915/glk: Reuse broxton's cdclk code for GLK Ander Conselvan de Oliveira
@ 2016-12-02 0:43 ` Rodrigo Vivi
0 siblings, 0 replies; 52+ messages in thread
From: Rodrigo Vivi @ 2016-12-02 0:43 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
On Thu, Nov 10, 2016 at 05:23:17PM +0200, Ander Conselvan de Oliveira wrote:
> Geminilake has the same register layout, reference clock and programming
> sequence as broxton. The difference is that it doesn't support the 1.5
> divider and has different ratios, but a lot of code can be shared
> between the two platforms.
>
> v2: Rebase (s/broxton/bxt).
>
> v3: Fix vco calculation in glk_de_pll_vco().
>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 73 ++++++++++++++++++++++++++++++++----
> 1 file changed, 65 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4069a6e..62cc390 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -124,6 +124,7 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc);
> static void intel_modeset_setup_hw_state(struct drm_device *dev);
> static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
> static int ilk_max_pixel_rate(struct drm_atomic_state *state);
> +static int glk_calc_cdclk(int max_pixclk);
> static int bxt_calc_cdclk(int max_pixclk);
>
> struct intel_limit {
> @@ -5866,6 +5867,8 @@ static void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
> max_cdclk = 308571;
>
> dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
> + } else if (IS_GEMINILAKE(dev_priv)) {
> + dev_priv->max_cdclk_freq = 316800;
> } else if (IS_BROXTON(dev_priv)) {
> dev_priv->max_cdclk_freq = 624000;
> } else if (IS_BROADWELL(dev_priv)) {
> @@ -5953,6 +5956,26 @@ static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
> return dev_priv->cdclk_pll.ref * ratio;
> }
>
> +static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
> +{
> + int ratio;
> +
> + if (cdclk == dev_priv->cdclk_pll.ref)
> + return 0;
> +
> + switch (cdclk) {
> + default:
> + MISSING_CASE(cdclk);
> + case 79200:
> + case 158400:
> + case 316800:
> + ratio = 33;
> + break;
> + }
> +
> + return dev_priv->cdclk_pll.ref * ratio;
> +}
> +
> static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
> {
> I915_WRITE(BXT_DE_PLL_ENABLE, 0);
> @@ -5994,7 +6017,10 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
> u32 val, divider;
> int vco, ret;
>
> - vco = bxt_de_pll_vco(dev_priv, cdclk);
> + if (IS_GEMINILAKE(dev_priv))
> + vco = glk_de_pll_vco(dev_priv, cdclk);
> + else
> + vco = bxt_de_pll_vco(dev_priv, cdclk);
>
> DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
>
> @@ -6007,6 +6033,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
> divider = BXT_CDCLK_CD2X_DIV_SEL_2;
> break;
> case 3:
> + WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
> divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
> break;
> case 2:
> @@ -6116,6 +6143,8 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
>
> void bxt_init_cdclk(struct drm_i915_private *dev_priv)
> {
> + int cdclk;
> +
> bxt_sanitize_cdclk(dev_priv);
>
> if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
> @@ -6126,7 +6155,12 @@ void bxt_init_cdclk(struct drm_i915_private *dev_priv)
> * - The initial CDCLK needs to be read from VBT.
> * Need to make this change after VBT has changes for BXT.
> */
> - bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
> + if (IS_GEMINILAKE(dev_priv))
> + cdclk = glk_calc_cdclk(0);
> + else
> + cdclk = bxt_calc_cdclk(0);
> +
> + bxt_set_cdclk(dev_priv, cdclk);
> }
>
> void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
> @@ -6552,6 +6586,16 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
> return 200000;
> }
>
> +static int glk_calc_cdclk(int max_pixclk)
> +{
> + if (max_pixclk > 158400)
> + return 316800;
> + else if (max_pixclk > 79200)
> + return 158400;
> + else
> + return 79200;
> +}
> +
> static int bxt_calc_cdclk(int max_pixclk)
> {
> if (max_pixclk > 576000)
> @@ -6614,15 +6658,27 @@ static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
>
> static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
> {
> + struct drm_i915_private *dev_priv = to_i915(state->dev);
> int max_pixclk = ilk_max_pixel_rate(state);
> struct intel_atomic_state *intel_state =
> to_intel_atomic_state(state);
> + int cdclk;
>
> - intel_state->cdclk = intel_state->dev_cdclk =
> - bxt_calc_cdclk(max_pixclk);
> + if (IS_GEMINILAKE(dev_priv))
> + cdclk = glk_calc_cdclk(max_pixclk);
> + else
> + cdclk = bxt_calc_cdclk(max_pixclk);
>
> - if (!intel_state->active_crtcs)
> - intel_state->dev_cdclk = bxt_calc_cdclk(0);
> + intel_state->cdclk = intel_state->dev_cdclk = cdclk;
> +
> + if (!intel_state->active_crtcs) {
> + if (IS_GEMINILAKE(dev_priv))
> + cdclk = glk_calc_cdclk(0);
> + else
> + cdclk = bxt_calc_cdclk(0);
> +
> + intel_state->dev_cdclk = cdclk;
> + }
>
> return 0;
> }
> @@ -7324,6 +7380,7 @@ static int broxton_get_display_clock_speed(struct drm_i915_private *dev_priv)
> div = 2;
> break;
> case BXT_CDCLK_CD2X_DIV_SEL_1_5:
> + WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
> div = 3;
> break;
> case BXT_CDCLK_CD2X_DIV_SEL_2:
> @@ -16022,7 +16079,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> dev_priv->display.get_display_clock_speed =
> skylake_get_display_clock_speed;
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> dev_priv->display.get_display_clock_speed =
> broxton_get_display_clock_speed;
> else if (IS_BROADWELL(dev_priv))
> @@ -16095,7 +16152,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
> valleyview_modeset_commit_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> valleyview_modeset_calc_cdclk;
> - } else if (IS_BROXTON(dev_priv)) {
> + } else if (IS_GEN9_LP(dev_priv)) {
> dev_priv->display.modeset_commit_cdclk =
> bxt_modeset_commit_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> --
> 2.5.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 13/15] drm/i915/glk: Allow dotclock up to 2 * cdclk on geminilake
2016-11-10 15:23 [PATCH 00/15] Geminilake enabling Ander Conselvan de Oliveira
` (11 preceding siblings ...)
2016-11-10 15:23 ` [PATCH 12/15] drm/i915/glk: Reuse broxton's cdclk code for GLK Ander Conselvan de Oliveira
@ 2016-11-10 15:23 ` Ander Conselvan de Oliveira
2016-12-01 23:59 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 14/15] drm/i915/glk: Implement core display init/uninit sequence for geminilake Ander Conselvan de Oliveira
` (6 subsequent siblings)
19 siblings, 1 reply; 52+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-11-10 15:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
Geminilake has double wide pipes so it can output two pixels per CD
clock.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 62cc390..7763c44 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5830,8 +5830,10 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
{
int max_cdclk_freq = dev_priv->max_cdclk_freq;
- if (INTEL_INFO(dev_priv)->gen >= 9 ||
- IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+ if (IS_GEMINILAKE(dev_priv))
+ return 2 * max_cdclk_freq;
+ else if (INTEL_INFO(dev_priv)->gen >= 9 ||
+ IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
return max_cdclk_freq;
else if (IS_CHERRYVIEW(dev_priv))
return max_cdclk_freq*95/100;
@@ -6588,9 +6590,9 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
static int glk_calc_cdclk(int max_pixclk)
{
- if (max_pixclk > 158400)
+ if (max_pixclk > 2 * 158400)
return 316800;
- else if (max_pixclk > 79200)
+ else if (max_pixclk > 2 * 79200)
return 158400;
else
return 79200;
--
2.5.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 13/15] drm/i915/glk: Allow dotclock up to 2 * cdclk on geminilake
2016-11-10 15:23 ` [PATCH 13/15] drm/i915/glk: Allow dotclock up to 2 * cdclk on geminilake Ander Conselvan de Oliveira
@ 2016-12-01 23:59 ` Rodrigo Vivi
0 siblings, 0 replies; 52+ messages in thread
From: Rodrigo Vivi @ 2016-12-01 23:59 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
On Thu, Nov 10, 2016 at 05:23:18PM +0200, Ander Conselvan de Oliveira wrote:
> Geminilake has double wide pipes so it can output two pixels per CD
> clock.
>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 62cc390..7763c44 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5830,8 +5830,10 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> {
> int max_cdclk_freq = dev_priv->max_cdclk_freq;
>
> - if (INTEL_INFO(dev_priv)->gen >= 9 ||
> - IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> + if (IS_GEMINILAKE(dev_priv))
> + return 2 * max_cdclk_freq;
> + else if (INTEL_INFO(dev_priv)->gen >= 9 ||
> + IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> return max_cdclk_freq;
> else if (IS_CHERRYVIEW(dev_priv))
> return max_cdclk_freq*95/100;
> @@ -6588,9 +6590,9 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
>
> static int glk_calc_cdclk(int max_pixclk)
> {
> - if (max_pixclk > 158400)
> + if (max_pixclk > 2 * 158400)
> return 316800;
> - else if (max_pixclk > 79200)
> + else if (max_pixclk > 2 * 79200)
> return 158400;
> else
> return 79200;
> --
> 2.5.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 14/15] drm/i915/glk: Implement core display init/uninit sequence for geminilake
2016-11-10 15:23 [PATCH 00/15] Geminilake enabling Ander Conselvan de Oliveira
` (12 preceding siblings ...)
2016-11-10 15:23 ` [PATCH 13/15] drm/i915/glk: Allow dotclock up to 2 * cdclk on geminilake Ander Conselvan de Oliveira
@ 2016-11-10 15:23 ` Ander Conselvan de Oliveira
2016-12-01 23:58 ` Rodrigo Vivi
2016-11-10 15:23 ` [PATCH 15/15] drm/i915/glk: Configure number of sprite planes properly Ander Conselvan de Oliveira
` (5 subsequent siblings)
19 siblings, 1 reply; 52+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-11-10 15:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
The sequence is pretty much the same as broxton, except that bspec
requires the AUX domains to be enabled. But since those can't be enabled
before the phys are initialized, we just use the same sequence as
broxton.
v2: Don't manually enable AUX domains. (Ander)
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 30d5112..2ee8984 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2721,7 +2721,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
skl_display_core_init(dev_priv, resume);
- } else if (IS_BROXTON(dev_priv)) {
+ } else if (IS_GEN9_LP(dev_priv)) {
bxt_display_core_init(dev_priv, resume);
} else if (IS_CHERRYVIEW(dev_priv)) {
mutex_lock(&power_domains->lock);
@@ -2760,7 +2760,7 @@ void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
skl_display_core_uninit(dev_priv);
- else if (IS_BROXTON(dev_priv))
+ else if (IS_GEN9_LP(dev_priv))
bxt_display_core_uninit(dev_priv);
}
--
2.5.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 14/15] drm/i915/glk: Implement core display init/uninit sequence for geminilake
2016-11-10 15:23 ` [PATCH 14/15] drm/i915/glk: Implement core display init/uninit sequence for geminilake Ander Conselvan de Oliveira
@ 2016-12-01 23:58 ` Rodrigo Vivi
0 siblings, 0 replies; 52+ messages in thread
From: Rodrigo Vivi @ 2016-12-01 23:58 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
On Thu, Nov 10, 2016 at 05:23:19PM +0200, Ander Conselvan de Oliveira wrote:
> The sequence is pretty much the same as broxton, except that bspec
> requires the AUX domains to be enabled. But since those can't be enabled
> before the phys are initialized, we just use the same sequence as
> broxton.
>
> v2: Don't manually enable AUX domains. (Ander)
>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 30d5112..2ee8984 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2721,7 +2721,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
>
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> skl_display_core_init(dev_priv, resume);
> - } else if (IS_BROXTON(dev_priv)) {
> + } else if (IS_GEN9_LP(dev_priv)) {
> bxt_display_core_init(dev_priv, resume);
> } else if (IS_CHERRYVIEW(dev_priv)) {
> mutex_lock(&power_domains->lock);
> @@ -2760,7 +2760,7 @@ void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
>
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> skl_display_core_uninit(dev_priv);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
> bxt_display_core_uninit(dev_priv);
> }
>
> --
> 2.5.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 15/15] drm/i915/glk: Configure number of sprite planes properly
2016-11-10 15:23 [PATCH 00/15] Geminilake enabling Ander Conselvan de Oliveira
` (13 preceding siblings ...)
2016-11-10 15:23 ` [PATCH 14/15] drm/i915/glk: Implement core display init/uninit sequence for geminilake Ander Conselvan de Oliveira
@ 2016-11-10 15:23 ` Ander Conselvan de Oliveira
2016-12-01 23:57 ` Rodrigo Vivi
2016-11-10 16:17 ` ✓ Fi.CI.BAT: success for Geminilake enabling Patchwork
` (4 subsequent siblings)
19 siblings, 1 reply; 52+ messages in thread
From: Ander Conselvan de Oliveira @ 2016-11-10 15:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Ander Conselvan de Oliveira
Geminilake has 4 planes (3 sprites) per pipe.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/intel_device_info.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 185e3bb..602d761 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -278,7 +278,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
* we don't expose the topmost plane at all to prevent ABI breakage
* down the line.
*/
- if (IS_BROXTON(dev_priv)) {
+ if (IS_GEMINILAKE(dev_priv))
+ for_each_pipe(dev_priv, pipe)
+ info->num_sprites[pipe] = 3;
+ else if (IS_BROXTON(dev_priv)) {
info->num_sprites[PIPE_A] = 2;
info->num_sprites[PIPE_B] = 2;
info->num_sprites[PIPE_C] = 1;
--
2.5.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 15/15] drm/i915/glk: Configure number of sprite planes properly
2016-11-10 15:23 ` [PATCH 15/15] drm/i915/glk: Configure number of sprite planes properly Ander Conselvan de Oliveira
@ 2016-12-01 23:57 ` Rodrigo Vivi
0 siblings, 0 replies; 52+ messages in thread
From: Rodrigo Vivi @ 2016-12-01 23:57 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
On Thu, Nov 10, 2016 at 05:23:20PM +0200, Ander Conselvan de Oliveira wrote:
> Geminilake has 4 planes (3 sprites) per pipe.
>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
> drivers/gpu/drm/i915/intel_device_info.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 185e3bb..602d761 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -278,7 +278,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> * we don't expose the topmost plane at all to prevent ABI breakage
> * down the line.
> */
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEMINILAKE(dev_priv))
> + for_each_pipe(dev_priv, pipe)
> + info->num_sprites[pipe] = 3;
> + else if (IS_BROXTON(dev_priv)) {
> info->num_sprites[PIPE_A] = 2;
> info->num_sprites[PIPE_B] = 2;
> info->num_sprites[PIPE_C] = 1;
> --
> 2.5.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* ✓ Fi.CI.BAT: success for Geminilake enabling
2016-11-10 15:23 [PATCH 00/15] Geminilake enabling Ander Conselvan de Oliveira
` (14 preceding siblings ...)
2016-11-10 15:23 ` [PATCH 15/15] drm/i915/glk: Configure number of sprite planes properly Ander Conselvan de Oliveira
@ 2016-11-10 16:17 ` Patchwork
2016-11-11 14:45 ` ✓ Fi.CI.BAT: success for Geminilake enabling (rev2) Patchwork
` (3 subsequent siblings)
19 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2016-11-10 16:17 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
== Series Details ==
Series: Geminilake enabling
URL : https://patchwork.freedesktop.org/series/15118/
State : success
== Summary ==
Series 15118v1 Geminilake enabling
https://patchwork.freedesktop.org/api/1.0/series/15118/revisions/1/mbox/
fi-bdw-5557u total:244 pass:229 dwarn:0 dfail:0 fail:0 skip:15
fi-bsw-n3050 total:244 pass:204 dwarn:0 dfail:0 fail:0 skip:40
fi-bxt-t5700 total:244 pass:216 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-j1900 total:244 pass:216 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-n2820 total:244 pass:212 dwarn:0 dfail:0 fail:0 skip:32
fi-hsw-4770 total:244 pass:224 dwarn:0 dfail:0 fail:0 skip:20
fi-hsw-4770r total:244 pass:224 dwarn:0 dfail:0 fail:0 skip:20
fi-ilk-650 total:244 pass:191 dwarn:0 dfail:0 fail:0 skip:53
fi-ivb-3520m total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-ivb-3770 total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-kbl-7200u total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-skl-6260u total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14
fi-skl-6700hq total:244 pass:223 dwarn:0 dfail:0 fail:0 skip:21
fi-skl-6700k total:244 pass:222 dwarn:1 dfail:0 fail:0 skip:21
fi-skl-6770hq total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14
fi-snb-2520m total:244 pass:212 dwarn:0 dfail:0 fail:0 skip:32
fi-snb-2600 total:244 pass:211 dwarn:0 dfail:0 fail:0 skip:33
eb88955cdc6a1f4dabff6bc27747c1c9e9a3aaef drm-intel-nightly: 2016y-11m-10d-09h-29m-41s UTC integration manifest
e587e04 drm/i915/glk: Configure number of sprite planes properly
cc704fe drm/i915/glk: Implement core display init/uninit sequence for geminilake
ec6b708 drm/i915/glk: Allow dotclock up to 2 * cdclk on geminilake
0f6ce8d drm/i915/glk: Reuse broxton's cdclk code for GLK
57d0559 drm/i915/glk: Update Port PLL enable sequence for Geminilkae
18ca745 drm/i915/glk: Set DCC delay range 2 in PLL enable sequence
44c1b6b drm/i915/glk: Implement Geminilake DDI init sequence
e190020 drm/i915/glk: Add power wells for Geminilake
f03db5e drm/i915/glk: Set DDI PHY lane lane optimization for Geminilake too
c7815d4 drm/i915/glk: Force DDI initialization.
e9db326 drm/i915/glk: Reuse broxton code for geminilake
fbd1fe9 drm/i915/glk: Add a IS_GEN9_LP() macro
fc0ecef drm/i915/glk: Add Geminilake PCI IDs
ba285b3 drm/i915/glk: Introduce Geminilake platform definition
fdb5ee2 drm/i915: Create a common GEN9_LP_FEATURE.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2957/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* ✓ Fi.CI.BAT: success for Geminilake enabling (rev2)
2016-11-10 15:23 [PATCH 00/15] Geminilake enabling Ander Conselvan de Oliveira
` (15 preceding siblings ...)
2016-11-10 16:17 ` ✓ Fi.CI.BAT: success for Geminilake enabling Patchwork
@ 2016-11-11 14:45 ` Patchwork
2016-11-14 14:47 ` ✓ Fi.CI.BAT: success for Geminilake enabling (rev5) Patchwork
` (2 subsequent siblings)
19 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2016-11-11 14:45 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
== Series Details ==
Series: Geminilake enabling (rev2)
URL : https://patchwork.freedesktop.org/series/15118/
State : success
== Summary ==
Series 15118v2 Geminilake enabling
https://patchwork.freedesktop.org/api/1.0/series/15118/revisions/2/mbox/
fi-bdw-5557u total:244 pass:229 dwarn:0 dfail:0 fail:0 skip:15
fi-bsw-n3050 total:244 pass:204 dwarn:0 dfail:0 fail:0 skip:40
fi-bxt-t5700 total:244 pass:216 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-j1900 total:244 pass:216 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-n2820 total:244 pass:212 dwarn:0 dfail:0 fail:0 skip:32
fi-hsw-4770 total:244 pass:224 dwarn:0 dfail:0 fail:0 skip:20
fi-hsw-4770r total:244 pass:224 dwarn:0 dfail:0 fail:0 skip:20
fi-ilk-650 total:244 pass:191 dwarn:0 dfail:0 fail:0 skip:53
fi-ivb-3520m total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-ivb-3770 total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-kbl-7200u total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-skl-6260u total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14
fi-skl-6700hq total:244 pass:223 dwarn:0 dfail:0 fail:0 skip:21
fi-skl-6700k total:244 pass:222 dwarn:1 dfail:0 fail:0 skip:21
fi-skl-6770hq total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14
fi-snb-2520m total:244 pass:212 dwarn:0 dfail:0 fail:0 skip:32
fi-snb-2600 total:244 pass:211 dwarn:0 dfail:0 fail:0 skip:33
7b290828029bfbbb50b1b907b197adc3f30e0d22 drm-intel-nightly: 2016y-11m-11d-13h-18m-42s UTC integration manifest
5e4b76b drm/i915/glk: Configure number of sprite planes properly
ff6061e drm/i915/glk: Implement core display init/uninit sequence for geminilake
ab20ac43 drm/i915/glk: Allow dotclock up to 2 * cdclk on geminilake
3b702ad drm/i915/glk: Reuse broxton's cdclk code for GLK
2845b00 drm/i915/glk: Update Port PLL enable sequence for Geminilkae
a723276 drm/i915/glk: Set DCC delay range 2 in PLL enable sequence
d970945 drm/i915/glk: Implement Geminilake DDI init sequence
f7e6b49 drm/i915/glk: Add power wells for Geminilake
0ad651c1 drm/i915/glk: Set DDI PHY lane lane optimization for Geminilake too
f415efb drm/i915/glk: Force DDI initialization.
78881dd drm/i915/glk: Reuse broxton code for geminilake
171b4ba drm/i915/glk: Add a IS_GEN9_LP() macro
4c69daa drm/i915/glk: Add Geminilake PCI IDs
55ff300 drm/i915/glk: Introduce Geminilake platform definition
668846a drm/i915: Create a common GEN9_LP_FEATURE.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2969/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* ✓ Fi.CI.BAT: success for Geminilake enabling (rev5)
2016-11-10 15:23 [PATCH 00/15] Geminilake enabling Ander Conselvan de Oliveira
` (16 preceding siblings ...)
2016-11-11 14:45 ` ✓ Fi.CI.BAT: success for Geminilake enabling (rev2) Patchwork
@ 2016-11-14 14:47 ` Patchwork
2016-11-14 16:16 ` Patchwork
2016-12-01 11:15 ` ✓ Fi.CI.BAT: success for Geminilake enabling (rev8) Patchwork
19 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2016-11-14 14:47 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
== Series Details ==
Series: Geminilake enabling (rev5)
URL : https://patchwork.freedesktop.org/series/15118/
State : success
== Summary ==
Series 15118v5 Geminilake enabling
https://patchwork.freedesktop.org/api/1.0/series/15118/revisions/5/mbox/
fi-bdw-5557u total:244 pass:229 dwarn:0 dfail:0 fail:0 skip:15
fi-bsw-n3050 total:244 pass:204 dwarn:0 dfail:0 fail:0 skip:40
fi-bxt-t5700 total:244 pass:216 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-j1900 total:244 pass:216 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-n2820 total:244 pass:212 dwarn:0 dfail:0 fail:0 skip:32
fi-hsw-4770 total:244 pass:224 dwarn:0 dfail:0 fail:0 skip:20
fi-hsw-4770r total:244 pass:224 dwarn:0 dfail:0 fail:0 skip:20
fi-ilk-650 total:244 pass:191 dwarn:0 dfail:0 fail:0 skip:53
fi-ivb-3520m total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-ivb-3770 total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-kbl-7200u total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-skl-6260u total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14
fi-skl-6700hq total:244 pass:223 dwarn:0 dfail:0 fail:0 skip:21
fi-skl-6700k total:244 pass:222 dwarn:1 dfail:0 fail:0 skip:21
fi-skl-6770hq total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14
fi-snb-2520m total:244 pass:212 dwarn:0 dfail:0 fail:0 skip:32
fi-snb-2600 total:244 pass:211 dwarn:0 dfail:0 fail:0 skip:33
02b726586a8230ae7630d909a263776fc11c35ad drm-intel-nightly: 2016y-11m-14d-13h-35m-49s UTC integration manifest
08e030e drm/i915/glk: Add Geminilake PCI IDs
bbb3d12 drm/i915/glk: Introduce Geminilake platform definition
a5a27da drm/i915: Create a common GEN9_LP_FEATURE.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2983/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* ✓ Fi.CI.BAT: success for Geminilake enabling (rev5)
2016-11-10 15:23 [PATCH 00/15] Geminilake enabling Ander Conselvan de Oliveira
` (17 preceding siblings ...)
2016-11-14 14:47 ` ✓ Fi.CI.BAT: success for Geminilake enabling (rev5) Patchwork
@ 2016-11-14 16:16 ` Patchwork
2016-12-01 11:15 ` ✓ Fi.CI.BAT: success for Geminilake enabling (rev8) Patchwork
19 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2016-11-14 16:16 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
== Series Details ==
Series: Geminilake enabling (rev5)
URL : https://patchwork.freedesktop.org/series/15118/
State : success
== Summary ==
Series 15118v5 Geminilake enabling
https://patchwork.freedesktop.org/api/1.0/series/15118/revisions/5/mbox/
fi-bdw-5557u total:244 pass:229 dwarn:0 dfail:0 fail:0 skip:15
fi-bsw-n3050 total:244 pass:204 dwarn:0 dfail:0 fail:0 skip:40
fi-bxt-t5700 total:244 pass:216 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-j1900 total:244 pass:216 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-n2820 total:244 pass:212 dwarn:0 dfail:0 fail:0 skip:32
fi-hsw-4770 total:244 pass:224 dwarn:0 dfail:0 fail:0 skip:20
fi-hsw-4770r total:244 pass:224 dwarn:0 dfail:0 fail:0 skip:20
fi-ilk-650 total:244 pass:191 dwarn:0 dfail:0 fail:0 skip:53
fi-ivb-3520m total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-ivb-3770 total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-kbl-7200u total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-skl-6260u total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14
fi-skl-6700hq total:244 pass:223 dwarn:0 dfail:0 fail:0 skip:21
fi-skl-6700k total:244 pass:222 dwarn:1 dfail:0 fail:0 skip:21
fi-skl-6770hq total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14
fi-snb-2520m total:244 pass:212 dwarn:0 dfail:0 fail:0 skip:32
fi-snb-2600 total:244 pass:211 dwarn:0 dfail:0 fail:0 skip:33
522cb36969544bb72e3215644c21fac2a60af418 drm-intel-nightly: 2016y-11m-14d-15h-21m-36s UTC integration manifest
5baa173 drm/i915/glk: Add Geminilake PCI IDs
bdf9462 drm/i915/glk: Introduce Geminilake platform definition
4749323 drm/i915: Create a common GEN9_LP_FEATURE.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2984/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* ✓ Fi.CI.BAT: success for Geminilake enabling (rev8)
2016-11-10 15:23 [PATCH 00/15] Geminilake enabling Ander Conselvan de Oliveira
` (18 preceding siblings ...)
2016-11-14 16:16 ` Patchwork
@ 2016-12-01 11:15 ` Patchwork
2016-12-01 11:43 ` Ander Conselvan De Oliveira
19 siblings, 1 reply; 52+ messages in thread
From: Patchwork @ 2016-12-01 11:15 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
== Series Details ==
Series: Geminilake enabling (rev8)
URL : https://patchwork.freedesktop.org/series/15118/
State : success
== Summary ==
Series 15118v8 Geminilake enabling
https://patchwork.freedesktop.org/api/1.0/series/15118/revisions/8/mbox/
fi-bdw-5557u total:245 pass:230 dwarn:0 dfail:0 fail:0 skip:15
fi-bsw-n3050 total:245 pass:205 dwarn:0 dfail:0 fail:0 skip:40
fi-bxt-t5700 total:245 pass:217 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-j1900 total:245 pass:217 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-n2820 total:245 pass:213 dwarn:0 dfail:0 fail:0 skip:32
fi-hsw-4770 total:245 pass:225 dwarn:0 dfail:0 fail:0 skip:20
fi-hsw-4770r total:245 pass:225 dwarn:0 dfail:0 fail:0 skip:20
fi-ilk-650 total:245 pass:192 dwarn:0 dfail:0 fail:0 skip:53
fi-ivb-3520m total:245 pass:223 dwarn:0 dfail:0 fail:0 skip:22
fi-ivb-3770 total:245 pass:223 dwarn:0 dfail:0 fail:0 skip:22
fi-kbl-7500u total:245 pass:223 dwarn:0 dfail:0 fail:0 skip:22
fi-skl-6260u total:245 pass:231 dwarn:0 dfail:0 fail:0 skip:14
fi-skl-6700hq total:245 pass:224 dwarn:0 dfail:0 fail:0 skip:21
fi-skl-6700k total:245 pass:223 dwarn:1 dfail:0 fail:0 skip:21
fi-skl-6770hq total:245 pass:231 dwarn:0 dfail:0 fail:0 skip:14
fi-snb-2520m total:245 pass:213 dwarn:0 dfail:0 fail:0 skip:32
fi-snb-2600 total:245 pass:212 dwarn:0 dfail:0 fail:0 skip:33
ae97fd2e43ca3693dbd127f51b9bba1c2dd1d37d drm-tip: 2016y-12m-01d-10h-10m-46s UTC integration manifest
69d83f8 drm/i915/glk: Add Geminilake PCI IDs
e30b2e3 drm/i915/glk: Introduce Geminilake platform definition
cd83440 drm/i915: Create a common GEN9_LP_FEATURE.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3159/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: ✓ Fi.CI.BAT: success for Geminilake enabling (rev8)
2016-12-01 11:15 ` ✓ Fi.CI.BAT: success for Geminilake enabling (rev8) Patchwork
@ 2016-12-01 11:43 ` Ander Conselvan De Oliveira
0 siblings, 0 replies; 52+ messages in thread
From: Ander Conselvan De Oliveira @ 2016-12-01 11:43 UTC (permalink / raw)
To: intel-gfx
On Thu, 2016-12-01 at 11:15 +0000, Patchwork wrote:
> == Series Details ==
>
> Series: Geminilake enabling (rev8)
> URL : https://patchwork.freedesktop.org/series/15118/
> State : success
I pushed up to patch 4. Thanks for the reviews so far.
Ander
>
> == Summary ==
>
> Series 15118v8 Geminilake enabling
> https://patchwork.freedesktop.org/api/1.0/series/15118/revisions/8/mbox/
>
>
> fi-bdw-5557u total:245 pass:230 dwarn:0 dfail:0 fail:0 skip:15
> fi-bsw-n3050 total:245 pass:205 dwarn:0 dfail:0 fail:0 skip:40
> fi-bxt-t5700 total:245 pass:217 dwarn:0 dfail:0 fail:0 skip:28
> fi-byt-j1900 total:245 pass:217 dwarn:0 dfail:0 fail:0 skip:28
> fi-byt-n2820 total:245 pass:213 dwarn:0 dfail:0 fail:0 skip:32
> fi-hsw-4770 total:245 pass:225 dwarn:0 dfail:0 fail:0 skip:20
> fi-hsw-4770r total:245 pass:225 dwarn:0 dfail:0 fail:0 skip:20
> fi-ilk-650 total:245 pass:192 dwarn:0 dfail:0 fail:0 skip:53
> fi-ivb-3520m total:245 pass:223 dwarn:0 dfail:0 fail:0 skip:22
> fi-ivb-3770 total:245 pass:223 dwarn:0 dfail:0 fail:0 skip:22
> fi-kbl-7500u total:245 pass:223 dwarn:0 dfail:0 fail:0 skip:22
> fi-skl-6260u total:245 pass:231 dwarn:0 dfail:0 fail:0 skip:14
> fi-skl-6700hq total:245 pass:224 dwarn:0 dfail:0 fail:0 skip:21
> fi-skl-6700k total:245 pass:223 dwarn:1 dfail:0 fail:0 skip:21
> fi-skl-6770hq total:245 pass:231 dwarn:0 dfail:0 fail:0 skip:14
> fi-snb-2520m total:245 pass:213 dwarn:0 dfail:0 fail:0 skip:32
> fi-snb-2600 total:245 pass:212 dwarn:0 dfail:0 fail:0 skip:33
>
> ae97fd2e43ca3693dbd127f51b9bba1c2dd1d37d drm-tip: 2016y-12m-01d-10h-10m-46s
> UTC integration manifest
> 69d83f8 drm/i915/glk: Add Geminilake PCI IDs
> e30b2e3 drm/i915/glk: Introduce Geminilake platform definition
> cd83440 drm/i915: Create a common GEN9_LP_FEATURE.
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3159/
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread