[PATCH 0/7] dal patches for dec 2, 2016

[PATCH 0/7] dal patches for dec 2, 2016

[Harry Wentland]

* couple small bug fixes and cleanups


Harry Wentland (2):
  drm/amd/display: Removing extra newline
  drm/amd/display: Remove obsolete LATEST_ATOM_BIOS_SUPPORT

Joshua Aberback (1):
  drm/amd/display: Block 3D Timings

Roman Li (1):
  drm/amd/display: fix REG_SET_5 macro

Tony Cheng (1):
  drm/amd/display: refactor DCE11 DVVM

Wenjing Liu (1):
  drm/amd/display: Update rgb limited range csc matrix calculation

jimqu (1):
  drm/amd/display: Fix memory corruption issue.

 drivers/gpu/drm/amd/display/dc/bios/Makefile       |   1 -
 .../gpu/drm/amd/display/dc/bios/command_table.c    |  16 --
 drivers/gpu/drm/amd/display/dc/core/dc.c           |   6 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 135 +++++++++-
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h |  59 +++-
 .../drm/amd/display/dc/dce100/dce100_resource.c    |   6 +-
 .../drm/amd/display/dc/dce110/dce110_mem_input.c   | 113 +-------
 .../drm/amd/display/dc/dce110/dce110_mem_input.h   |  11 -
 .../drm/amd/display/dc/dce110/dce110_mem_input_v.c |   8 +-
 .../drm/amd/display/dc/dce110/dce110_resource.c    |   6 +-
 .../display/dc/dce110/dce110_timing_generator.c    |   4 +
 .../drm/amd/display/dc/dce112/dce112_resource.c    |   6 +-
 .../gpu/drm/amd/display/dc/dce80/dce80_resource.c  |   6 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h  |   4 +-
 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h    |   2 +-
 drivers/gpu/drm/amd/display/dc/os_types.h          |   1 -
 drivers/gpu/drm/amd/display/modules/color/color.c  | 300 +++++++++++++++------
 17 files changed, 427 insertions(+), 257 deletions(-)

-- 
2.9.3

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[PATCH 1/7] drm/amd/display: Fix memory corruption issue.

[Harry Wentland]

From: jimqu <Jim.Qu@amd.com>

temp_flip_context is always same as current_context,
and the current_context will be freed in
dc_commit_targets(), but  temp_flip_context will be used in
dc_update_surfaces_for_target().

Change-Id: I86d1f311ce8c2d4989c2f212e4c65f721bcdc0fc
Signed-off-by: JimQu <Jim.Qu@amd.com>
Reviewed-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f7638f84421b..424a7d4b8731 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1096,8 +1096,12 @@ bool dc_commit_targets(
 
 	resource_validate_ctx_destruct(core_dc->current_context);
 
-	dm_free(core_dc->current_context);
+	if (core_dc->temp_flip_context != core_dc->current_context) {
+		dm_free(core_dc->temp_flip_context);
+		core_dc->temp_flip_context = core_dc->current_context;
+	}
 	core_dc->current_context = context;
+	memset(core_dc->temp_flip_context, 0, sizeof(*core_dc->temp_flip_context));
 
 	return (result == DC_OK);
 
-- 
2.9.3

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[PATCH 2/7] drm/amd/display: Block 3D Timings

[Harry Wentland]

From: Joshua Aberback <Joshua.Aberback@amd.com>

- we don't yet support 3D timings in DAL3
- somehow a code path was being executed that resulted in HW programming
for a 3D timing, which caused 3D displays to show half the desktop in one
frame, and the other half of the desktop in the next frame
- blocking all 3D timings in timing generator validation until we
implement proper 3D timing support

Change-Id: Id9e0dfef33a09c2a96c3e69cedf30c47a3553a2b
Signed-off-by: Joshua Aberback <Joshua.Aberback@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index b1c97125f6fb..12a258763ef1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -1113,6 +1113,10 @@ bool dce110_timing_generator_validate_timing(
 	if (!timing)
 		return false;
 
+	/* Currently we don't support 3D, so block all 3D timings */
+	if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE)
+		return false;
+
 	/* Check maximum number of pixels supported by Timing Generator
 	 * (Currently will never fail, in order to fail needs display which
 	 * needs more than 8192 horizontal and
-- 
2.9.3

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[PATCH 3/7] drm/amd/display: Update rgb limited range csc matrix calculation

[Harry Wentland]

From: Wenjing Liu <Wenjing.Liu@amd.com>

[Description]
The issue causes hue adjustment for rgb
limited range color space programmed wrong.
Update calculation formula for rgb limited range

Change-Id: I3c81b04dfcd372638a0ec63dc16bb7b49152e444
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/modules/color/color.c | 300 ++++++++++++++++------
 1 file changed, 216 insertions(+), 84 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/color/color.c b/drivers/gpu/drm/amd/display/modules/color/color.c
index cf030b18f6a9..30d09d358576 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color.c
@@ -854,26 +854,60 @@ static void calculate_rgb_matrix_legacy(struct core_color *core_color,
 	rgb_matrix[11] = grph_bright;
 }
 
-static void calculate_rgb_limited_range_matrix(struct core_color *core_color,
-		unsigned int sink_index, struct fixed31_32 *rgb_matrix)
+static void calculate_rgb_limited_range_matrix_legacy(
+		struct core_color *core_color, unsigned int sink_index,
+		struct fixed31_32 *rgb_matrix)
 {
-	struct fixed31_32 ideal[12];
-
-	static const int32_t matrix_[] = {
-			85546875, 0, 0, 6250000,
-			0, 85546875, 0, 6250000,
-			0, 0, 85546875, 6250000
-		};
-
-	uint32_t i = 0;
+	const struct fixed31_32 k1 =
+		dal_fixed31_32_from_fraction(701000, 1000000);
+	const struct fixed31_32 k2 =
+		dal_fixed31_32_from_fraction(236568, 1000000);
+	const struct fixed31_32 k3 =
+		dal_fixed31_32_from_fraction(-587000, 1000000);
+	const struct fixed31_32 k4 =
+		dal_fixed31_32_from_fraction(464432, 1000000);
+	const struct fixed31_32 k5 =
+		dal_fixed31_32_from_fraction(-114000, 1000000);
+	const struct fixed31_32 k6 =
+		dal_fixed31_32_from_fraction(-701000, 1000000);
+	const struct fixed31_32 k7 =
+		dal_fixed31_32_from_fraction(-299000, 1000000);
+	const struct fixed31_32 k8 =
+		dal_fixed31_32_from_fraction(-292569, 1000000);
+	const struct fixed31_32 k9 =
+		dal_fixed31_32_from_fraction(413000, 1000000);
+	const struct fixed31_32 k10 =
+		dal_fixed31_32_from_fraction(-92482, 1000000);
+	const struct fixed31_32 k11 =
+		dal_fixed31_32_from_fraction(-114000, 1000000);
+	const struct fixed31_32 k12 =
+		dal_fixed31_32_from_fraction(385051, 1000000);
+	const struct fixed31_32 k13 =
+		dal_fixed31_32_from_fraction(-299000, 1000000);
+	const struct fixed31_32 k14 =
+		dal_fixed31_32_from_fraction(886000, 1000000);
+	const struct fixed31_32 k15 =
+		dal_fixed31_32_from_fraction(-587000, 1000000);
+	const struct fixed31_32 k16 =
+		dal_fixed31_32_from_fraction(-741914, 1000000);
+	const struct fixed31_32 k17 =
+		dal_fixed31_32_from_fraction(886000, 1000000);
+	const struct fixed31_32 k18 =
+		dal_fixed31_32_from_fraction(-144086, 1000000);
 
-	do {
-		ideal[i] = dal_fixed31_32_from_fraction(
-			matrix_[i],
-			100000000);
-		++i;
-	} while (i != ARRAY_SIZE(matrix_));
+	const struct fixed31_32 luma_r =
+		dal_fixed31_32_from_fraction(299, 1000);
+	const struct fixed31_32 luma_g =
+		dal_fixed31_32_from_fraction(587, 1000);
+	const struct fixed31_32 luma_b =
+		dal_fixed31_32_from_fraction(114, 1000);
+	const struct fixed31_32 luma_scale =
+		dal_fixed31_32_from_fraction(875855, 1000000);
 
+	const struct fixed31_32 rgb_scale =
+		dal_fixed31_32_from_fraction(85546875, 100000000);
+	const struct fixed31_32 rgb_bias =
+		dal_fixed31_32_from_fraction(625, 10000);
 
 	struct fixed31_32 grph_cont;
 	struct fixed31_32 grph_sat;
@@ -885,84 +919,182 @@ static void calculate_rgb_limited_range_matrix(struct core_color *core_color,
 		core_color, sink_index, &grph_cont, &grph_sat,
 		&grph_bright, &sin_grph_hue, &cos_grph_hue);
 
-	const struct fixed31_32 multiplier =
-		dal_fixed31_32_mul(grph_cont, grph_sat);
-
-	rgb_matrix[8] = dal_fixed31_32_mul(ideal[0], grph_cont);
+	/* COEF_1_1 = GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K1 +*/
+	/* Sin(GrphHue) * K2))*/
+	/* (Cos(GrphHue) * K1 + Sin(GrphHue) * K2)*/
+	rgb_matrix[0] =
+		dal_fixed31_32_add(
+			dal_fixed31_32_mul(cos_grph_hue, k1),
+			dal_fixed31_32_mul(sin_grph_hue, k2));
+	/* GrphSat * (Cos(GrphHue) * K1 + Sin(GrphHue) * K2 */
+	rgb_matrix[0] = dal_fixed31_32_mul(grph_sat, rgb_matrix[0]);
+	/* (LumaR + GrphSat * (Cos(GrphHue) * K1 + Sin(GrphHue) * K2))*/
+	rgb_matrix[0] = dal_fixed31_32_add(luma_r, rgb_matrix[0]);
+	/* GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K1 + Sin(GrphHue)**/
+	/* K2))*/
+	rgb_matrix[0] = dal_fixed31_32_mul(grph_cont, rgb_matrix[0]);
+	/* LumaScale * GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K1 + */
+	/* Sin(GrphHue) * K2))*/
+	rgb_matrix[0] = dal_fixed31_32_mul(luma_scale, rgb_matrix[0]);
 
-	rgb_matrix[9] = dal_fixed31_32_mul(ideal[1], grph_cont);
+	/* COEF_1_2 = GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K3 +*/
+	/* Sin(GrphHue) * K4))*/
+	/* (Cos(GrphHue) * K3 + Sin(GrphHue) * K4)*/
+	rgb_matrix[1] =
+		dal_fixed31_32_add(
+			dal_fixed31_32_mul(cos_grph_hue, k3),
+			dal_fixed31_32_mul(sin_grph_hue, k4));
+	/* GrphSat * (Cos(GrphHue) * K3 + Sin(GrphHue) * K4)*/
+	rgb_matrix[1] = dal_fixed31_32_mul(grph_sat, rgb_matrix[1]);
+	/* (LumaG + GrphSat * (Cos(GrphHue) * K3 + Sin(GrphHue) * K4))*/
+	rgb_matrix[1] = dal_fixed31_32_add(luma_g, rgb_matrix[1]);
+	/* GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K3 + Sin(GrphHue)**/
+	/* K4))*/
+	rgb_matrix[1] = dal_fixed31_32_mul(grph_cont, rgb_matrix[1]);
+	/* LumaScale * GrphCont * (LumaG + GrphSat *(Cos(GrphHue) * K3 + */
+	/* Sin(GrphHue) * K4))*/
+	rgb_matrix[1] = dal_fixed31_32_mul(luma_scale, rgb_matrix[1]);
 
-	rgb_matrix[10] = dal_fixed31_32_mul(ideal[2], grph_cont);
+	/* COEF_1_3 = GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K5 +*/
+	/* Sin(GrphHue) * K6))*/
+	/* (Cos(GrphHue) * K5 + Sin(GrphHue) * K6)*/
+	rgb_matrix[2] =
+		dal_fixed31_32_add(
+			dal_fixed31_32_mul(cos_grph_hue, k5),
+			dal_fixed31_32_mul(sin_grph_hue, k6));
+	/* GrphSat * (Cos(GrphHue) * K5 + Sin(GrphHue) * K6)*/
+	rgb_matrix[2] = dal_fixed31_32_mul(grph_sat, rgb_matrix[2]);
+	/* LumaB + GrphSat * (Cos(GrphHue) * K5 + Sin(GrphHue) * K6)*/
+	rgb_matrix[2] = dal_fixed31_32_add(luma_b, rgb_matrix[2]);
+	/* GrphCont  * (LumaB + GrphSat * (Cos(GrphHue) * K5 + Sin(GrphHue)**/
+	/* K6))*/
+	rgb_matrix[2] = dal_fixed31_32_mul(grph_cont, rgb_matrix[2]);
+	/* LumaScale * GrphCont  * (LumaB + GrphSat *(Cos(GrphHue) * K5 + */
+	/* Sin(GrphHue) * K6))*/
+	rgb_matrix[2] = dal_fixed31_32_mul(luma_scale, rgb_matrix[2]);
 
-	rgb_matrix[11] = dal_fixed31_32_add(
-			ideal[3],
-			dal_fixed31_32_mul(
-				grph_bright,
-				dal_fixed31_32_from_fraction(86, 100)));
+	/* COEF_1_4 = RGBBias + RGBScale * GrphBright*/
+	rgb_matrix[3] = dal_fixed31_32_add(
+			rgb_bias,
+			dal_fixed31_32_mul(rgb_scale, grph_bright));
 
-	rgb_matrix[0] = dal_fixed31_32_mul(
-		multiplier,
+	/* COEF_2_1 = GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K7 +*/
+	/* Sin(GrphHue) * K8))*/
+	/* (Cos(GrphHue) * K7 + Sin(GrphHue) * K8)*/
+	rgb_matrix[4] =
 		dal_fixed31_32_add(
-			dal_fixed31_32_mul(
-				ideal[8],
-				sin_grph_hue),
-			dal_fixed31_32_mul(
-				ideal[4],
-				cos_grph_hue)));
+			dal_fixed31_32_mul(cos_grph_hue, k7),
+			dal_fixed31_32_mul(sin_grph_hue, k8));
+	/* GrphSat * (Cos(GrphHue) * K7 + Sin(GrphHue) * K8)*/
+	rgb_matrix[4] = dal_fixed31_32_mul(grph_sat, rgb_matrix[4]);
+	/* (LumaR + GrphSat * (Cos(GrphHue) * K7 + Sin(GrphHue) * K8))*/
+	rgb_matrix[4] = dal_fixed31_32_add(luma_r, rgb_matrix[4]);
+	/* GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K7 + Sin(GrphHue)**/
+	/* K8))*/
+	rgb_matrix[4] = dal_fixed31_32_mul(grph_cont, rgb_matrix[4]);
+	/* LumaScale * GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K7 + */
+	/* Sin(GrphHue) * K8))*/
+	rgb_matrix[4] = dal_fixed31_32_mul(luma_scale, rgb_matrix[4]);
 
-	rgb_matrix[1] = dal_fixed31_32_mul(
-		multiplier,
+	/* COEF_2_2 = GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K9 +*/
+	/* Sin(GrphHue) * K10))*/
+	/* (Cos(GrphHue) * K9 + Sin(GrphHue) * K10))*/
+	rgb_matrix[5] =
 		dal_fixed31_32_add(
-			dal_fixed31_32_mul(
-				ideal[9],
-				sin_grph_hue),
-			dal_fixed31_32_mul(
-				ideal[5],
-				cos_grph_hue)));
+			dal_fixed31_32_mul(cos_grph_hue, k9),
+			dal_fixed31_32_mul(sin_grph_hue, k10));
+	/* GrphSat * (Cos(GrphHue) * K9 + Sin(GrphHue) * K10))*/
+	rgb_matrix[5] = dal_fixed31_32_mul(grph_sat, rgb_matrix[5]);
+	/* (LumaG + GrphSat * (Cos(GrphHue) * K9 + Sin(GrphHue) * K10))*/
+	rgb_matrix[5] = dal_fixed31_32_add(luma_g, rgb_matrix[5]);
+	/* GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K9 + Sin(GrphHue)**/
+	/* K10))*/
+	rgb_matrix[5] = dal_fixed31_32_mul(grph_cont, rgb_matrix[5]);
+	/* LumaScale * GrphCont * (LumaG + GrphSat *(Cos(GrphHue) * K9 + */
+	/* Sin(GrphHue) * K10))*/
+	rgb_matrix[5] = dal_fixed31_32_mul(luma_scale, rgb_matrix[5]);
 
-	rgb_matrix[2] = dal_fixed31_32_mul(
-		multiplier,
+	/* COEF_2_3 = GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K11 +*/
+	/* Sin(GrphHue) * K12))*/
+	/* (Cos(GrphHue) * K11 + Sin(GrphHue) * K12))*/
+	rgb_matrix[6] =
 		dal_fixed31_32_add(
-			dal_fixed31_32_mul(
-				ideal[10],
-				sin_grph_hue),
-			dal_fixed31_32_mul(
-				ideal[6],
-				cos_grph_hue)));
+			dal_fixed31_32_mul(cos_grph_hue, k11),
+			dal_fixed31_32_mul(sin_grph_hue, k12));
+	/* GrphSat * (Cos(GrphHue) * K11 + Sin(GrphHue) * K12))*/
+	rgb_matrix[6] = dal_fixed31_32_mul(grph_sat, rgb_matrix[6]);
+	/* (LumaB + GrphSat * (Cos(GrphHue) * K11 + Sin(GrphHue) * K12))*/
+	rgb_matrix[6] = dal_fixed31_32_add(luma_b, rgb_matrix[6]);
+	/* GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K11 + Sin(GrphHue)**/
+	/* K12))*/
+	rgb_matrix[6] = dal_fixed31_32_mul(grph_cont, rgb_matrix[6]);
+	/* LumaScale * GrphCont  * (LumaB + GrphSat *(Cos(GrphHue) * K11 +*/
+	/* Sin(GrphHue) * K12)) */
+	rgb_matrix[6] = dal_fixed31_32_mul(luma_scale, rgb_matrix[6]);
 
-	rgb_matrix[3] = ideal[7];
+	/* COEF_2_4 = RGBBias + RGBScale * GrphBright*/
+	rgb_matrix[7] = dal_fixed31_32_add(
+			rgb_bias,
+			dal_fixed31_32_mul(rgb_scale, grph_bright));
 
-	rgb_matrix[4] = dal_fixed31_32_mul(
-		multiplier,
-		dal_fixed31_32_sub(
-			dal_fixed31_32_mul(
-				ideal[8],
-				cos_grph_hue),
-			dal_fixed31_32_mul(
-				ideal[4],
-				sin_grph_hue)));
+	/* COEF_3_1 = GrphCont  * (LumaR + GrphSat * (Cos(GrphHue) * K13 +*/
+	/* Sin(GrphHue) * K14))*/
+	/* (Cos(GrphHue) * K13 + Sin(GrphHue) * K14)) */
+	rgb_matrix[8] =
+		dal_fixed31_32_add(
+			dal_fixed31_32_mul(cos_grph_hue, k13),
+			dal_fixed31_32_mul(sin_grph_hue, k14));
+	/* GrphSat * (Cos(GrphHue) * K13 + Sin(GrphHue) * K14)) */
+	rgb_matrix[8] = dal_fixed31_32_mul(grph_sat, rgb_matrix[8]);
+	/* (LumaR + GrphSat * (Cos(GrphHue) * K13 + Sin(GrphHue) * K14)) */
+	rgb_matrix[8] = dal_fixed31_32_add(luma_r, rgb_matrix[8]);
+	/* GrphCont  * (LumaR + GrphSat * (Cos(GrphHue) * K13 + Sin(GrphHue)**/
+	/* K14)) */
+	rgb_matrix[8] = dal_fixed31_32_mul(grph_cont, rgb_matrix[8]);
+	/* LumaScale * GrphCont * (LumaR + GrphSat * (Cos(GrphHue) * K13 +*/
+	/* Sin(GrphHue) * K14))*/
+	rgb_matrix[8] = dal_fixed31_32_mul(luma_scale, rgb_matrix[8]);
 
-	rgb_matrix[5] = dal_fixed31_32_mul(
-		multiplier,
-		dal_fixed31_32_sub(
-			dal_fixed31_32_mul(
-				ideal[9],
-				cos_grph_hue),
-			dal_fixed31_32_mul(
-				ideal[5],
-				sin_grph_hue)));
+	/* COEF_3_2    = GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K15 +*/
+	/* Sin(GrphHue) * K16)) */
+	/* GrphSat * (Cos(GrphHue) * K15 + Sin(GrphHue) * K16) */
+	rgb_matrix[9] =
+		dal_fixed31_32_add(
+			dal_fixed31_32_mul(cos_grph_hue, k15),
+			dal_fixed31_32_mul(sin_grph_hue, k16));
+	/* (LumaG + GrphSat * (Cos(GrphHue) * K15 + Sin(GrphHue) * K16)) */
+	rgb_matrix[9] = dal_fixed31_32_mul(grph_sat, rgb_matrix[9]);
+	/* (LumaG + GrphSat * (Cos(GrphHue) * K15 + Sin(GrphHue) * K16)) */
+	rgb_matrix[9] = dal_fixed31_32_add(luma_g, rgb_matrix[9]);
+	/* GrphCont * (LumaG + GrphSat * (Cos(GrphHue) * K15 + Sin(GrphHue)**/
+	/* K16)) */
+	rgb_matrix[9] = dal_fixed31_32_mul(grph_cont, rgb_matrix[9]);
+	/* LumaScale * GrphCont * (LumaG + GrphSat *(Cos(GrphHue) * K15 + */
+	/* Sin(GrphHue) * K16))*/
+	rgb_matrix[9] = dal_fixed31_32_mul(luma_scale, rgb_matrix[9]);
 
-	rgb_matrix[6] = dal_fixed31_32_mul(
-		multiplier,
-		dal_fixed31_32_sub(
-			dal_fixed31_32_mul(
-				ideal[10],
-				cos_grph_hue),
-			dal_fixed31_32_mul(
-				ideal[6],
-				sin_grph_hue)));
+	/*  COEF_3_3 = GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K17 +*/
+	/* Sin(GrphHue) * K18)) */
+	/* (Cos(GrphHue) * K17 + Sin(GrphHue) * K18)) */
+	rgb_matrix[10] =
+		dal_fixed31_32_add(
+			dal_fixed31_32_mul(cos_grph_hue, k17),
+			dal_fixed31_32_mul(sin_grph_hue, k18));
+	/*  GrphSat * (Cos(GrphHue) * K17 + Sin(GrphHue) * K18)) */
+	rgb_matrix[10] = dal_fixed31_32_mul(grph_sat, rgb_matrix[10]);
+	/* (LumaB + GrphSat * (Cos(GrphHue) * K17 + Sin(GrphHue) * K18)) */
+	rgb_matrix[10] = dal_fixed31_32_add(luma_b, rgb_matrix[10]);
+	/* GrphCont * (LumaB + GrphSat * (Cos(GrphHue) * K17 + Sin(GrphHue)**/
+	/* K18)) */
+	rgb_matrix[10] = dal_fixed31_32_mul(grph_cont, rgb_matrix[10]);
+	/* LumaScale * GrphCont * (LumaB + GrphSat *(Cos(GrphHue) * */
+	/* K17 + Sin(GrphHue) * K18))*/
+	rgb_matrix[10] = dal_fixed31_32_mul(luma_scale, rgb_matrix[10]);
 
-	rgb_matrix[7] = ideal[11];
+	/* COEF_3_4 = RGBBias + RGBScale * GrphBright */
+	rgb_matrix[11] = dal_fixed31_32_add(
+			rgb_bias,
+			dal_fixed31_32_mul(rgb_scale, grph_bright));
 }
 
 static void calculate_yuv_matrix(struct core_color *core_color,
@@ -1110,9 +1242,9 @@ static void calculate_csc_matrix(struct core_color *core_color,
 			(csc_matrix, fixed_csc_matrix, 12);
 		break;
 	case COLOR_SPACE_SRGB_LIMITED:
-		calculate_rgb_limited_range_matrix(core_color, sink_index,
-				fixed_csc_matrix);
-		convert_float_matrix(csc_matrix, fixed_csc_matrix, 12);
+		calculate_rgb_limited_range_matrix_legacy(
+				core_color, sink_index, fixed_csc_matrix);
+		convert_float_matrix_legacy(csc_matrix, fixed_csc_matrix, 12);
 		break;
 	case COLOR_SPACE_YCBCR601:
 	case COLOR_SPACE_YCBCR709:
-- 
2.9.3

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[PATCH 4/7] drm/amd/display: Removing extra newline

[Harry Wentland]

Change-Id: I2f043d0ac4cb23621dfd74d560994fc08690809c
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/os_types.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h b/drivers/gpu/drm/amd/display/dc/os_types.h
index 459a2741eccb..7f0c282a1466 100644
--- a/drivers/gpu/drm/amd/display/dc/os_types.h
+++ b/drivers/gpu/drm/amd/display/dc/os_types.h
@@ -54,7 +54,6 @@
 
 #define dm_min(x, y) min(x, y)
 #define dm_max(x, y) max(x, y)
-
 #endif
 
 
-- 
2.9.3

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[PATCH 5/7] drm/amd/display: Remove obsolete LATEST_ATOM_BIOS_SUPPORT

[Harry Wentland]

Change-Id: I12e580840fbdcc162303dc4c66d9d8fc12ecbacd
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/bios/Makefile        |  1 -
 drivers/gpu/drm/amd/display/dc/bios/command_table.c | 16 ----------------
 2 files changed, 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/Makefile b/drivers/gpu/drm/amd/display/dc/bios/Makefile
index 20480d6e2a02..1368e4995ed2 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/bios/Makefile
@@ -20,5 +20,4 @@ AMD_DAL_FILES += $(AMDDALPATH)/dc/bios/dce80/command_table_helper_dce80.o
 ###############################################################################
 AMD_DAL_FILES += $(AMDDALPATH)/dc/bios/dce110/command_table_helper_dce110.o
 
-ccflags-y += -DLATEST_ATOM_BIOS_SUPPORT
 AMD_DAL_FILES += $(AMDDALPATH)/dc/bios/dce112/command_table_helper_dce112.o
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
index 51f6052eac96..d0eedb6235fe 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
@@ -115,11 +115,9 @@ static enum bp_result encoder_control_digx_v4(
 	struct bios_parser *bp,
 	struct bp_encoder_control *cntl);
 
-#ifdef LATEST_ATOM_BIOS_SUPPORT
 static enum bp_result encoder_control_digx_v5(
 	struct bios_parser *bp,
 	struct bp_encoder_control *cntl);
-#endif
 
 static void init_encoder_control_dig_v1(struct bios_parser *bp);
 
@@ -136,11 +134,9 @@ static void init_dig_encoder_control(struct bios_parser *bp)
 		bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v4;
 		break;
 
-#ifdef LATEST_ATOM_BIOS_SUPPORT
 	case 5:
 		bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v5;
 		break;
-#endif
 
 	default:
 		init_encoder_control_dig_v1(bp);
@@ -290,7 +286,6 @@ static enum bp_result encoder_control_digx_v4(
 	return result;
 }
 
-#ifdef LATEST_ATOM_BIOS_SUPPORT
 static enum bp_result encoder_control_digx_v5(
 	struct bios_parser *bp,
 	struct bp_encoder_control *cntl)
@@ -348,7 +343,6 @@ static enum bp_result encoder_control_digx_v5(
 
 	return result;
 }
-#endif
 
 /*******************************************************************************
  ********************************************************************************
@@ -829,7 +823,6 @@ static enum bp_result transmitter_control_v1_6(
 	struct bp_transmitter_control *cntl)
 {
 	enum bp_result result = BP_RESULT_FAILURE;
-#ifdef LATEST_ATOM_BIOS_SUPPORT
 	const struct command_table_helper *cmd = bp->cmd_helper;
 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6 params;
 
@@ -883,7 +876,6 @@ static enum bp_result transmitter_control_v1_6(
 
 	if (EXEC_BIOS_CMD_TABLE(UNIPHYTransmitterControl, params))
 		result = BP_RESULT_OK;
-#endif
 	return result;
 }
 
@@ -1141,7 +1133,6 @@ static enum bp_result set_pixel_clock_v7(
 	struct bp_pixel_clock_parameters *bp_params)
 {
 	enum bp_result result = BP_RESULT_FAILURE;
-#ifdef LATEST_ATOM_BIOS_SUPPORT
 	PIXEL_CLOCK_PARAMETERS_V7 clk;
 	uint8_t controller_id;
 	uint32_t pll_id;
@@ -1203,7 +1194,6 @@ static enum bp_result set_pixel_clock_v7(
 		if (EXEC_BIOS_CMD_TABLE(SetPixelClock, clk))
 			result = BP_RESULT_OK;
 	}
-#endif
 	return result;
 }
 
@@ -2539,15 +2529,12 @@ static enum bp_result enable_disp_power_gating_v2_1(
  **
  ********************************************************************************
  *******************************************************************************/
-#ifdef LATEST_ATOM_BIOS_SUPPORT
 static enum bp_result set_dce_clock_v2_1(
 	struct bios_parser *bp,
 	struct bp_set_dce_clock_parameters *bp_params);
-#endif
 
 static void init_set_dce_clock(struct bios_parser *bp)
 {
-#ifdef LATEST_ATOM_BIOS_SUPPORT
 	switch (BIOS_CMD_TABLE_PARA_REVISION(SetDCEClock)) {
 	case 1:
 		bp->cmd_tbl.set_dce_clock = set_dce_clock_v2_1;
@@ -2556,10 +2543,8 @@ static void init_set_dce_clock(struct bios_parser *bp)
 		bp->cmd_tbl.set_dce_clock = NULL;
 		break;
 	}
-#endif
 }
 
-#ifdef LATEST_ATOM_BIOS_SUPPORT
 static enum bp_result set_dce_clock_v2_1(
 	struct bios_parser *bp,
 	struct bp_set_dce_clock_parameters *bp_params)
@@ -2606,4 +2591,3 @@ static enum bp_result set_dce_clock_v2_1(
 
 	return result;
 }
-#endif
-- 
2.9.3

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[PATCH 6/7] drm/amd/display: fix REG_SET_5 macro

[Harry Wentland]

From: Roman Li <Roman.Li@amd.com>

Change-Id: I20ecd7f66d97ec51b65ed96d62279f53a4a37e60
Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
index 159b2c519f2b..dbc8424f7b69 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
@@ -84,7 +84,7 @@
 
 #define REG_SET_5(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4,	\
 		f5, v5)	\
-		REG_SET_N(reg, 6, init_value, \
+		REG_SET_N(reg, 5, init_value, \
 				FN(reg, f1), v1,\
 				FN(reg, f2), v2,\
 				FN(reg, f3), v3,\
-- 
2.9.3

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[PATCH 7/7] drm/amd/display: refactor DCE11 DVVM

[Harry Wentland]

From: Tony Cheng <tony.cheng@amd.com>

- move to new programming style
- clean up table to make it obvious what we are programming

Change-Id: I3eb96038c3fbdeed29d6c96da5832603cc1601c9
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Zeyu Fan <Zeyu.Fan@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 135 ++++++++++++++++++++-
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h |  59 +++++++--
 .../drm/amd/display/dc/dce100/dce100_resource.c    |   6 +-
 .../drm/amd/display/dc/dce110/dce110_mem_input.c   | 113 +----------------
 .../drm/amd/display/dc/dce110/dce110_mem_input.h   |  11 --
 .../drm/amd/display/dc/dce110/dce110_mem_input_v.c |   8 +-
 .../drm/amd/display/dc/dce110/dce110_resource.c    |   6 +-
 .../drm/amd/display/dc/dce112/dce112_resource.c    |   6 +-
 .../gpu/drm/amd/display/dc/dce80/dce80_resource.c  |   6 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h  |   4 +-
 10 files changed, 201 insertions(+), 153 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
index 654731cccdcd..fd8a49afbec6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
@@ -35,6 +35,137 @@
 #define FN(reg_name, field_name) \
 	mi->shifts->field_name, mi->masks->field_name
 
+struct pte_setting {
+	unsigned int bpp;
+	unsigned int page_width;
+	unsigned int page_height;
+	unsigned char min_pte_before_flip_horiz_scan;
+	unsigned char min_pte_before_flip_vert_scan;
+	unsigned char pte_req_per_chunk;
+	unsigned char param_6;
+	unsigned char param_7;
+	unsigned char param_8;
+};
+
+enum mi_bits_per_pixel {
+	mi_bpp_8 = 0,
+	mi_bpp_16,
+	mi_bpp_32,
+	mi_bpp_64,
+	mi_bpp_count,
+};
+
+enum mi_tiling_format {
+	mi_tiling_linear = 0,
+	mi_tiling_1D,
+	mi_tiling_2D,
+	mi_tiling_count,
+};
+
+static const struct pte_setting pte_settings[mi_tiling_count][mi_bpp_count] = {
+	[mi_tiling_linear] = {
+		{  8, 4096, 1, 8, 0, 1, 0, 0, 0},
+		{ 16, 2048, 1, 8, 0, 1, 0, 0, 0},
+		{ 32, 1024, 1, 8, 0, 1, 0, 0, 0},
+		{ 64,  512, 1, 8, 0, 1, 0, 0, 0}, /* new for 64bpp from HW */
+	},
+	[mi_tiling_1D] = {
+		{  8, 512, 8, 1, 0, 1, 0, 0, 0},  /* 0 for invalid */
+		{ 16, 256, 8, 2, 0, 1, 0, 0, 0},
+		{ 32, 128, 8, 4, 0, 1, 0, 0, 0},
+		{ 64,  64, 8, 4, 0, 1, 0, 0, 0}, /* fake */
+	},
+	[mi_tiling_2D] = {
+		{  8, 64, 64,  8,  8, 1, 4, 0, 0},
+		{ 16, 64, 32,  8, 16, 1, 8, 0, 0},
+		{ 32, 32, 32, 16, 16, 1, 8, 0, 0},
+		{ 64,  8, 32, 16, 16, 1, 8, 0, 0}, /* fake */
+	},
+};
+
+static enum mi_bits_per_pixel get_mi_bpp(
+		enum surface_pixel_format format)
+{
+	if (format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616)
+		return mi_bpp_64;
+	else if (format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888)
+		return mi_bpp_32;
+	else if (format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB1555)
+		return mi_bpp_16;
+	else
+		return mi_bpp_8;
+}
+
+static enum mi_tiling_format get_mi_tiling(
+		union dc_tiling_info *tiling_info)
+{
+	switch (tiling_info->gfx8.array_mode) {
+	case DC_ARRAY_1D_TILED_THIN1:
+	case DC_ARRAY_1D_TILED_THICK:
+	case DC_ARRAY_PRT_TILED_THIN1:
+		return mi_tiling_1D;
+	case DC_ARRAY_2D_TILED_THIN1:
+	case DC_ARRAY_2D_TILED_THICK:
+	case DC_ARRAY_2D_TILED_X_THICK:
+	case DC_ARRAY_PRT_2D_TILED_THIN1:
+	case DC_ARRAY_PRT_2D_TILED_THICK:
+		return mi_tiling_2D;
+	case DC_ARRAY_LINEAR_GENERAL:
+	case DC_ARRAY_LINEAR_ALLIGNED:
+		return mi_tiling_linear;
+	default:
+		return mi_tiling_2D;
+	}
+}
+
+static bool is_vert_scan(enum dc_rotation_angle rotation)
+{
+	switch (rotation) {
+	case ROTATION_ANGLE_90:
+	case ROTATION_ANGLE_270:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static unsigned int log_2(unsigned int num)
+{
+	unsigned int result = 0;
+
+	while ((num >>= 1) != 0)
+		result++;
+
+	return result;
+}
+
+void dce_mem_input_program_pte_vm(struct mem_input *mi,
+		enum surface_pixel_format format,
+		union dc_tiling_info *tiling_info,
+		enum dc_rotation_angle rotation)
+{
+	enum mi_bits_per_pixel mi_bpp = get_mi_bpp(format);
+	enum mi_tiling_format mi_tiling = get_mi_tiling(tiling_info);
+	const struct pte_setting *pte = &pte_settings[mi_tiling][mi_bpp];
+
+	unsigned int page_width = log_2(pte->page_width);
+	unsigned int page_height = log_2(pte->page_height);
+	unsigned int min_pte_before_flip = is_vert_scan(rotation) ?
+			pte->min_pte_before_flip_vert_scan :
+			pte->min_pte_before_flip_horiz_scan;
+
+	REG_UPDATE(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT,
+			GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, 0xff);
+
+	REG_UPDATE_3(DVMM_PTE_CONTROL,
+			DVMM_PAGE_WIDTH, page_width,
+			DVMM_PAGE_HEIGHT, page_height,
+			DVMM_MIN_PTE_BEFORE_FLIP, min_pte_before_flip);
+
+	REG_UPDATE_2(DVMM_PTE_ARB_CONTROL,
+			DVMM_PTE_REQ_PER_CHUNK, pte->pte_req_per_chunk,
+			DVMM_MAX_PTE_REQ_OUTSTANDING, 0xff);
+}
 
 static void program_urgency_watermark(struct mem_input *mi,
 	uint32_t wm_select,
@@ -244,7 +375,7 @@ static void program_grph_pixel_format(
 			GRPH_PRESCALE_B_SIGN, sign);
 }
 
-bool dce_mem_input_program_surface_config(struct mem_input *mi,
+void dce_mem_input_program_surface_config(struct mem_input *mi,
 	enum surface_pixel_format format,
 	union dc_tiling_info *tiling_info,
 	union plane_size *plane_size,
@@ -260,8 +391,6 @@ bool dce_mem_input_program_surface_config(struct mem_input *mi,
 	if (format >= SURFACE_PIXEL_FORMAT_GRPH_BEGIN &&
 		format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
 		program_grph_pixel_format(mi, format);
-
-	return true;
 }
 
 static uint32_t get_dmif_switch_time_us(
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
index d5930a925fcb..a366b3a5b79d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
@@ -42,10 +42,22 @@
 	SRI(DPG_PIPE_STUTTER_CONTROL, DMIF_PG, id),\
 	SRI(DMIF_BUFFER_CONTROL, PIPE, id)
 
-#define MI_REG_LIST(id)\
+#define MI_DCE_PTE_REG_LIST(id)\
+	SRI(DVMM_PTE_CONTROL, DCP, id),\
+	SRI(DVMM_PTE_ARB_CONTROL, DCP, id)
+
+#define MI_DCE8_REG_LIST(id)\
 	MI_DCE_BASE_REG_LIST(id),\
 	SRI(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, DMIF_PG, id)
 
+#define MI_DCE11_2_REG_LIST(id)\
+	MI_DCE8_REG_LIST(id),\
+	SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id)
+
+#define MI_DCE11_REG_LIST(id)\
+	MI_DCE11_2_REG_LIST(id),\
+	MI_DCE_PTE_REG_LIST(id)
+
 struct dce_mem_input_registers {
 	/* DCP */
 	uint32_t GRPH_ENABLE;
@@ -58,6 +70,9 @@ struct dce_mem_input_registers {
 	uint32_t HW_ROTATION;
 	uint32_t GRPH_SWAP_CNTL;
 	uint32_t PRESCALE_GRPH_CONTROL;
+	uint32_t GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT;
+	uint32_t DVMM_PTE_CONTROL;
+	uint32_t DVMM_PTE_ARB_CONTROL;
 	/* DMIF_PG */
 	uint32_t DPG_PIPE_ARBITRATION_CONTROL1;
 	uint32_t DPG_WATERMARK_MASK_CONTROL;
@@ -103,6 +118,16 @@ struct dce_mem_input_registers {
 	SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\
 	SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh)
 
+#define MI_DCP_DCE11_MASK_SH_LIST(mask_sh, blk)\
+	SFB(blk, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, mask_sh)
+
+#define MI_DCP_PTE_MASK_SH_LIST(mask_sh, blk)\
+	SFB(blk, DVMM_PTE_CONTROL, DVMM_PAGE_WIDTH, mask_sh),\
+	SFB(blk, DVMM_PTE_CONTROL, DVMM_PAGE_HEIGHT, mask_sh),\
+	SFB(blk, DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP, mask_sh),\
+	SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_PTE_REQ_PER_CHUNK, mask_sh),\
+	SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_MAX_PTE_REQ_OUTSTANDING, mask_sh)
+
 #define MI_DMIF_PG_MASK_SH_LIST(mask_sh, blk)\
 	SFB(blk, DPG_PIPE_ARBITRATION_CONTROL1, PIXEL_DURATION, mask_sh),\
 	SFB(blk, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, mask_sh),\
@@ -122,11 +147,19 @@ struct dce_mem_input_registers {
 	SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\
 	SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK, mask_sh)
 
-#define MI_DCE_MASK_SH_LIST(mask_sh)\
-	MI_DCP_MASK_SH_LIST(mask_sh,),\
-	MI_DMIF_PG_MASK_SH_LIST(mask_sh,),\
-	MI_DMIF_PG_MASK_SH_DCE(mask_sh,),\
-	MI_GFX8_TILE_MASK_SH_LIST(mask_sh,)
+#define MI_DCE8_MASK_SH_LIST(mask_sh)\
+	MI_DCP_MASK_SH_LIST(mask_sh, ),\
+	MI_DMIF_PG_MASK_SH_LIST(mask_sh, ),\
+	MI_DMIF_PG_MASK_SH_DCE(mask_sh, ),\
+	MI_GFX8_TILE_MASK_SH_LIST(mask_sh, )
+
+#define MI_DCE11_2_MASK_SH_LIST(mask_sh)\
+	MI_DCE8_MASK_SH_LIST(mask_sh),\
+	MI_DCP_DCE11_MASK_SH_LIST(mask_sh, )
+
+#define MI_DCE11_MASK_SH_LIST(mask_sh)\
+	MI_DCE11_2_MASK_SH_LIST(mask_sh),\
+	MI_DCP_PTE_MASK_SH_LIST(mask_sh, )
 
 #define MI_REG_FIELD_LIST(type) \
 	type GRPH_ENABLE; \
@@ -142,6 +175,12 @@ struct dce_mem_input_registers {
 	type GRPH_PRESCALE_R_SIGN; \
 	type GRPH_PRESCALE_G_SIGN; \
 	type GRPH_PRESCALE_B_SIGN; \
+	type GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT; \
+	type DVMM_PAGE_WIDTH; \
+	type DVMM_PAGE_HEIGHT; \
+	type DVMM_MIN_PTE_BEFORE_FLIP; \
+	type DVMM_PTE_REQ_PER_CHUNK; \
+	type DVMM_MAX_PTE_REQ_OUTSTANDING; \
 	type GRPH_DEPTH; \
 	type GRPH_FORMAT; \
 	type GRPH_NUM_BANKS; \
@@ -191,7 +230,13 @@ struct dce_mem_input_wa {
 };
 
 struct mem_input;
-bool dce_mem_input_program_surface_config(struct mem_input *mi,
+
+void dce_mem_input_program_pte_vm(struct mem_input *mi,
+	enum surface_pixel_format format,
+	union dc_tiling_info *tiling_info,
+	enum dc_rotation_angle rotation);
+
+void dce_mem_input_program_surface_config(struct mem_input *mi,
 	enum surface_pixel_format format,
 	union dc_tiling_info *tiling_info,
 	union plane_size *plane_size,
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 16595dc875a1..9ace6d1cca79 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -481,7 +481,7 @@ static const struct resource_create_funcs res_create_funcs = {
 };
 
 #define mi_inst_regs(id) { \
-	MI_REG_LIST(id), \
+	MI_DCE8_REG_LIST(id), \
 	.MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
 }
 static const struct dce_mem_input_registers mi_regs[] = {
@@ -494,12 +494,12 @@ static const struct dce_mem_input_registers mi_regs[] = {
 };
 
 static const struct dce_mem_input_shift mi_shifts = {
-		MI_DCE_MASK_SH_LIST(__SHIFT),
+		MI_DCE8_MASK_SH_LIST(__SHIFT),
 		.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
 };
 
 static const struct dce_mem_input_mask mi_masks = {
-		MI_DCE_MASK_SH_LIST(_MASK),
+		MI_DCE8_MASK_SH_LIST(_MASK),
 		.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c
index c0a68c6f585e..af9d682f8943 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c
@@ -150,117 +150,6 @@ bool dce110_mem_input_program_surface_flip_and_addr(
 	return true;
 }
 
-/* Scatter Gather param tables */
-static const unsigned int dvmm_Hw_Setting_2DTiling[4][9] = {
-		{  8, 64, 64,  8,  8, 1, 4, 0, 0},
-		{ 16, 64, 32,  8, 16, 1, 8, 0, 0},
-		{ 32, 32, 32, 16, 16, 1, 8, 0, 0},
-		{ 64,  8, 32, 16, 16, 1, 8, 0, 0}, /* fake */
-};
-
-static const unsigned int dvmm_Hw_Setting_1DTiling[4][9] = {
-		{  8, 512, 8, 1, 0, 1, 0, 0, 0},  /* 0 for invalid */
-		{ 16, 256, 8, 2, 0, 1, 0, 0, 0},
-		{ 32, 128, 8, 4, 0, 1, 0, 0, 0},
-		{ 64,  64, 8, 4, 0, 1, 0, 0, 0}, /* fake */
-};
-
-static const unsigned int dvmm_Hw_Setting_Linear[4][9] = {
-		{  8, 4096, 1, 8, 0, 1, 0, 0, 0},
-		{ 16, 2048, 1, 8, 0, 1, 0, 0, 0},
-		{ 32, 1024, 1, 8, 0, 1, 0, 0, 0},
-		{ 64,  512, 1, 8, 0, 1, 0, 0, 0}, /* new for 64bpp from HW */
-};
-
-/* Helper to get table entry from surface info */
-static const unsigned int *get_dvmm_hw_setting(
-		union dc_tiling_info *tiling_info,
-		enum surface_pixel_format format)
-{
-	enum bits_per_pixel {
-		bpp_8 = 0,
-		bpp_16,
-		bpp_32,
-		bpp_64
-	} bpp;
-
-	if (format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616)
-		bpp = bpp_64;
-	else if (format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888)
-		bpp = bpp_32;
-	else if (format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB1555)
-		bpp = bpp_16;
-	else
-		bpp = bpp_8;
-
-	switch (tiling_info->gfx8.array_mode) {
-	case DC_ARRAY_1D_TILED_THIN1:
-	case DC_ARRAY_1D_TILED_THICK:
-	case DC_ARRAY_PRT_TILED_THIN1:
-		return dvmm_Hw_Setting_1DTiling[bpp];
-	case DC_ARRAY_2D_TILED_THIN1:
-	case DC_ARRAY_2D_TILED_THICK:
-	case DC_ARRAY_2D_TILED_X_THICK:
-	case DC_ARRAY_PRT_2D_TILED_THIN1:
-	case DC_ARRAY_PRT_2D_TILED_THICK:
-		return dvmm_Hw_Setting_2DTiling[bpp];
-	case DC_ARRAY_LINEAR_GENERAL:
-	case DC_ARRAY_LINEAR_ALLIGNED:
-		return dvmm_Hw_Setting_Linear[bpp];
-	default:
-		return dvmm_Hw_Setting_2DTiling[bpp];
-	}
-}
-
-bool dce110_mem_input_program_pte_vm(
-		struct mem_input *mem_input,
-		enum surface_pixel_format format,
-		union dc_tiling_info *tiling_info,
-		enum dc_rotation_angle rotation)
-{
-	struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
-	const unsigned int *pte = get_dvmm_hw_setting(tiling_info, format);
-
-	unsigned int page_width = 0;
-	unsigned int page_height = 0;
-	unsigned int temp_page_width = pte[1];
-	unsigned int temp_page_height = pte[2];
-	unsigned int min_pte_before_flip = 0;
-	uint32_t value = 0;
-
-	while ((temp_page_width >>= 1) != 0)
-		page_width++;
-	while ((temp_page_height >>= 1) != 0)
-		page_height++;
-
-	switch (rotation) {
-	case ROTATION_ANGLE_90:
-	case ROTATION_ANGLE_270:
-		min_pte_before_flip = pte[4];
-		break;
-	default:
-		min_pte_before_flip = pte[3];
-		break;
-	}
-
-	value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT));
-	set_reg_field_value(value, 0xff, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT);
-	dm_write_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT), value);
-
-	value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmDVMM_PTE_CONTROL));
-	set_reg_field_value(value, page_width, DVMM_PTE_CONTROL, DVMM_PAGE_WIDTH);
-	set_reg_field_value(value, page_height, DVMM_PTE_CONTROL, DVMM_PAGE_HEIGHT);
-	set_reg_field_value(value, min_pte_before_flip, DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP);
-	dm_write_reg(mem_input110->base.ctx, DCP_REG(mmDVMM_PTE_CONTROL), value);
-
-	value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmDVMM_PTE_ARB_CONTROL));
-	set_reg_field_value(value, pte[5], DVMM_PTE_ARB_CONTROL, DVMM_PTE_REQ_PER_CHUNK);
-	set_reg_field_value(value, 0xff, DVMM_PTE_ARB_CONTROL, DVMM_MAX_PTE_REQ_OUTSTANDING);
-	dm_write_reg(mem_input110->base.ctx, DCP_REG(mmDVMM_PTE_ARB_CONTROL), value);
-
-	return true;
-}
-
 static void program_urgency_watermark(
 	const struct dc_context *ctx,
 	const uint32_t offset,
@@ -502,7 +391,7 @@ static struct mem_input_funcs dce110_mem_input_funcs = {
 	.mem_input_program_surface_flip_and_addr =
 			dce110_mem_input_program_surface_flip_and_addr,
 	.mem_input_program_pte_vm =
-			dce110_mem_input_program_pte_vm,
+			dce_mem_input_program_pte_vm,
 	.mem_input_program_surface_config =
 			dce_mem_input_program_surface_config,
 	.mem_input_is_flip_pending =
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h
index 83b2df93ce49..a80a20c09da4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.h
@@ -108,17 +108,6 @@ bool  dce110_mem_input_program_surface_config(
 	bool horizontal_mirror);
 
 /*
- * dce110_mem_input_program_pte_vm
- *
- * This function will program pte vm registers.
- */
-bool  dce110_mem_input_program_pte_vm(
-	struct mem_input *mem_input,
-	enum surface_pixel_format format,
-	union dc_tiling_info *tiling_info,
-	enum dc_rotation_angle rotation);
-
-/*
  * dce110_mem_input_is_flip_pending
  *
  * This function will wait until the surface update-pending bit is cleared.
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
index f0310bab4030..757e946d0837 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
@@ -584,7 +584,7 @@ static const unsigned int *get_dvmm_hw_setting(
 	}
 }
 
-bool dce110_mem_input_v_program_pte_vm(
+void dce110_mem_input_v_program_pte_vm(
 		struct mem_input *mem_input,
 		enum surface_pixel_format format,
 		union dc_tiling_info *tiling_info,
@@ -655,11 +655,9 @@ bool dce110_mem_input_v_program_pte_vm(
 	set_reg_field_value(value, pte_chroma[5], UNP_DVMM_PTE_ARB_CONTROL_C, DVMM_PTE_REQ_PER_CHUNK_C);
 	set_reg_field_value(value, 0xff, UNP_DVMM_PTE_ARB_CONTROL_C, DVMM_MAX_PTE_REQ_OUTSTANDING_C);
 	dm_write_reg(mem_input110->base.ctx, DCP_REG(mmUNP_DVMM_PTE_ARB_CONTROL_C), value);
-
-	return true;
 }
 
-bool dce110_mem_input_v_program_surface_config(
+void dce110_mem_input_v_program_surface_config(
 	struct mem_input *mem_input,
 	enum surface_pixel_format format,
 	union dc_tiling_info *tiling_info,
@@ -674,8 +672,6 @@ bool dce110_mem_input_v_program_surface_config(
 	program_tiling(mem_input110, tiling_info, format);
 	program_size_and_rotation(mem_input110, rotation, plane_size);
 	program_pixel_format(mem_input110, format);
-
-	return true;
 }
 
 static void program_urgency_watermark(
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 959467fa421e..cac3dc425039 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -474,7 +474,7 @@ static const struct resource_create_funcs res_create_funcs = {
 };
 
 #define mi_inst_regs(id) { \
-	MI_REG_LIST(id), \
+	MI_DCE11_REG_LIST(id), \
 	.MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
 }
 static const struct dce_mem_input_registers mi_regs[] = {
@@ -484,12 +484,12 @@ static const struct dce_mem_input_registers mi_regs[] = {
 };
 
 static const struct dce_mem_input_shift mi_shifts = {
-		MI_DCE_MASK_SH_LIST(__SHIFT),
+		MI_DCE11_MASK_SH_LIST(__SHIFT),
 		.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
 };
 
 static const struct dce_mem_input_mask mi_masks = {
-		MI_DCE_MASK_SH_LIST(_MASK),
+		MI_DCE11_MASK_SH_LIST(_MASK),
 		.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index bfb2c3fcd2cb..4e3273c0fa91 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -495,7 +495,7 @@ static const struct resource_create_funcs res_create_funcs = {
 	.create_hwseq = dce112_hwseq_create,
 };
 
-#define mi_inst_regs(id) { MI_REG_LIST(id) }
+#define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) }
 static const struct dce_mem_input_registers mi_regs[] = {
 		mi_inst_regs(0),
 		mi_inst_regs(1),
@@ -506,11 +506,11 @@ static const struct dce_mem_input_registers mi_regs[] = {
 };
 
 static const struct dce_mem_input_shift mi_shifts = {
-		MI_DCE_MASK_SH_LIST(__SHIFT)
+		MI_DCE11_2_MASK_SH_LIST(__SHIFT)
 };
 
 static const struct dce_mem_input_mask mi_masks = {
-		MI_DCE_MASK_SH_LIST(_MASK)
+		MI_DCE11_2_MASK_SH_LIST(_MASK)
 };
 
 static struct mem_input *dce112_mem_input_create(
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 06720407b6fc..3b626b7883d4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -462,7 +462,7 @@ static const struct resource_create_funcs res_create_funcs = {
 };
 
 #define mi_inst_regs(id) { \
-	MI_REG_LIST(id), \
+	MI_DCE8_REG_LIST(id), \
 	.MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
 }
 static const struct dce_mem_input_registers mi_regs[] = {
@@ -475,12 +475,12 @@ static const struct dce_mem_input_registers mi_regs[] = {
 };
 
 static const struct dce_mem_input_shift mi_shifts = {
-		MI_DCE_MASK_SH_LIST(__SHIFT),
+		MI_DCE8_MASK_SH_LIST(__SHIFT),
 		.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
 };
 
 static const struct dce_mem_input_mask mi_masks = {
-		MI_DCE_MASK_SH_LIST(_MASK),
+		MI_DCE8_MASK_SH_LIST(_MASK),
 		.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
index 78dab74edc2d..80566c844758 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
@@ -82,13 +82,13 @@ struct mem_input_funcs {
 		const struct dc_plane_address *address,
 		bool flip_immediate);
 
-	bool (*mem_input_program_pte_vm)(
+	void (*mem_input_program_pte_vm)(
 		struct mem_input *mem_input,
 		enum surface_pixel_format format,
 		union dc_tiling_info *tiling_info,
 		enum dc_rotation_angle rotation);
 
-	bool (*mem_input_program_surface_config)(
+	void (*mem_input_program_surface_config)(
 		struct mem_input *mem_input,
 		enum surface_pixel_format format,
 		union dc_tiling_info *tiling_info,
-- 
2.9.3

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