* [PATCH 00/12] DC Patches for Dec 5, 2016
@ 2016-12-06 18:35 Harry Wentland
[not found] ` <20161206183538.11584-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 14+ messages in thread
From: Harry Wentland @ 2016-12-06 18:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
* larger rework of display_clock code to facilitate sharing between
ASIC generations
* some small bug fixes
Dmytro Laktyushkin (10):
drm/amd/display: remove dead display clock code
drm/amd/display: restyle display clock calls part 1
drm/amd/display: restyle display clock calls part 2
drm/amd/display: remove store clock state
drm/amd/display: remove get_min_clocks_state
drm/amd/display: remove clocks_state enum
drm/amd/display: consolidate dce8-11.2 display clock code
drm/amd/display: add newline to generic_reg_wait timeout message
drm/amd/display: fix display clock integrated info read
drm/amd/display: create scratch_val_ctx as temp w/a
Wenjing Liu (1):
drm/amd/display: use rgb full range as default quantization for non
HDMI
Yongqiang Sun (1):
drm/amd/display: Add missing GRPH register definition
drivers/gpu/drm/amd/display/dc/core/dc.c | 9 +-
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 13 +-
drivers/gpu/drm/amd/display/dc/dc_helper.c | 2 +-
drivers/gpu/drm/amd/display/dc/dce/Makefile | 3 +-
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 4 +-
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 519 ++++++++++
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 133 +++
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 1 +
.../drm/amd/display/dc/dce100/dce100_resource.c | 31 +-
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 65 +-
.../drm/amd/display/dc/dce110/dce110_resource.c | 74 +-
.../drm/amd/display/dc/dce110/dce110_resource.h | 3 -
.../drm/amd/display/dc/dce112/dce112_resource.c | 37 +-
.../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 76 +-
drivers/gpu/drm/amd/display/dc/dm_services_types.h | 18 +-
drivers/gpu/drm/amd/display/dc/gpu/Makefile | 17 +-
.../display/dc/gpu/dce110/display_clock_dce110.c | 1035 --------------------
.../display/dc/gpu/dce110/display_clock_dce110.h | 53 -
.../display/dc/gpu/dce112/display_clock_dce112.c | 717 +-------------
.../display/dc/gpu/dce112/display_clock_dce112.h | 39 +-
.../amd/display/dc/gpu/dce80/display_clock_dce80.c | 934 ------------------
.../amd/display/dc/gpu/dce80/display_clock_dce80.h | 57 --
drivers/gpu/drm/amd/display/dc/gpu/display_clock.c | 217 ----
drivers/gpu/drm/amd/display/dc/gpu/display_clock.h | 89 --
drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 1 +
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 -
.../amd/display/include/display_clock_interface.h | 149 +--
drivers/gpu/drm/amd/display/modules/color/color.c | 88 +-
.../gpu/drm/amd/display/modules/inc/mod_color.h | 12 +-
29 files changed, 920 insertions(+), 3478 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
delete mode 100644 drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c
delete mode 100644 drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h
delete mode 100644 drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c
delete mode 100644 drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h
delete mode 100644 drivers/gpu/drm/amd/display/dc/gpu/display_clock.c
delete mode 100644 drivers/gpu/drm/amd/display/dc/gpu/display_clock.h
--
2.9.3
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 01/12] drm/amd/display: Add missing GRPH register definition
[not found] ` <20161206183538.11584-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
@ 2016-12-06 18:35 ` Harry Wentland
2016-12-06 18:35 ` [PATCH 02/12] drm/amd/display: remove dead display clock code Harry Wentland
` (11 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Harry Wentland @ 2016-12-06 18:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Yongqiang Sun
From: Yongqiang Sun <yongqiang.sun@amd.com>
Change-Id: I532294115c6ef0600256f2971d26e7e7668aea47
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
index a366b3a5b79d..022272d30fe4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
@@ -193,6 +193,7 @@ struct dce_mem_input_registers {
type GRPH_ARRAY_MODE;\
type GRPH_COLOR_EXPANSION_MODE;\
type GRPH_SW_MODE; \
+ type GRPH_SE_ENABLE; \
type GRPH_NUM_SHADER_ENGINES; \
type GRPH_NUM_PIPES; \
type PIXEL_DURATION; \
--
2.9.3
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 02/12] drm/amd/display: remove dead display clock code
[not found] ` <20161206183538.11584-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2016-12-06 18:35 ` [PATCH 01/12] drm/amd/display: Add missing GRPH register definition Harry Wentland
@ 2016-12-06 18:35 ` Harry Wentland
2016-12-06 18:35 ` [PATCH 03/12] drm/amd/display: restyle display clock calls part 1 Harry Wentland
` (10 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Harry Wentland @ 2016-12-06 18:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Change-Id: I6484f68e32d4ffef4f17984f956b30b1ef91b874
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
.../display/dc/gpu/dce110/display_clock_dce110.c | 468 +-------------------
.../display/dc/gpu/dce110/display_clock_dce110.h | 1 -
.../display/dc/gpu/dce112/display_clock_dce112.c | 477 +--------------------
.../display/dc/gpu/dce112/display_clock_dce112.h | 18 -
.../amd/display/dc/gpu/dce80/display_clock_dce80.c | 476 +-------------------
.../amd/display/dc/gpu/dce80/display_clock_dce80.h | 1 -
drivers/gpu/drm/amd/display/dc/gpu/display_clock.c | 122 ------
drivers/gpu/drm/amd/display/dc/gpu/display_clock.h | 28 --
.../amd/display/include/display_clock_interface.h | 85 ----
9 files changed, 29 insertions(+), 1647 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c
index 1bc39f12b6a1..cc13afa326ad 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c
@@ -268,404 +268,6 @@ static void destroy(struct display_clock **base)
*base = NULL;
}
-static uint32_t get_validation_clock(struct display_clock *dc)
-{
- uint32_t clk = 0;
- struct display_clock_dce110 *disp_clk = DCLCK110_FROM_BASE(dc);
-
- switch (disp_clk->max_clks_state) {
- case CLOCKS_STATE_ULTRA_LOW:
- /*Currently not supported, it has 0 in table entry*/
- case CLOCKS_STATE_LOW:
- clk = max_clks_by_state[CLOCKS_STATE_LOW].
- display_clk_khz;
- break;
-
- case CLOCKS_STATE_NOMINAL:
- clk = max_clks_by_state[CLOCKS_STATE_NOMINAL].
- display_clk_khz;
- break;
-
- case CLOCKS_STATE_PERFORMANCE:
- clk = max_clks_by_state[CLOCKS_STATE_PERFORMANCE].
- display_clk_khz;
- break;
-
- case CLOCKS_STATE_INVALID:
- default:
- /*Invalid Clocks State*/
- dm_logger_write(dc->ctx->logger, LOG_WARNING,
- "Invalid clock state");
- /* just return the display engine clock for
- * lowest supported state*/
- clk = max_clks_by_state[CLOCKS_STATE_LOW].
- display_clk_khz;
- break;
- }
- return clk;
-}
-
-static struct fixed32_32 get_deep_color_factor(struct min_clock_params *params)
-{
- /* DeepColorFactor = IF (HDMI = True, bpp / 24, 1)*/
- struct fixed32_32 deep_color_factor = dal_fixed32_32_from_int(1);
-
- if (params->signal_type != SIGNAL_TYPE_HDMI_TYPE_A)
- return deep_color_factor;
-
- switch (params->deep_color_depth) {
- case COLOR_DEPTH_101010:
- /*deep color ratio for 30bpp is 30/24 = 1.25*/
- deep_color_factor = dal_fixed32_32_from_fraction(30, 24);
- break;
-
- case COLOR_DEPTH_121212:
- /* deep color ratio for 36bpp is 36/24 = 1.5*/
- deep_color_factor = dal_fixed32_32_from_fraction(36, 24);
- break;
-
- case COLOR_DEPTH_161616:
- /* deep color ratio for 48bpp is 48/24 = 2.0 */
- deep_color_factor = dal_fixed32_32_from_fraction(48, 24);
- break;
- default:
- break;
- }
- return deep_color_factor;
-}
-
-static struct fixed32_32 get_scaler_efficiency(
- struct dc_context *ctx,
- struct min_clock_params *params)
-{
- struct fixed32_32 scaler_efficiency = dal_fixed32_32_from_int(3);
-
- if (params->scaler_efficiency == V_SCALER_EFFICIENCY_LB18BPP) {
- scaler_efficiency =
- dal_fixed32_32_add(
- dal_fixed32_32_from_fraction(35555, 10000),
- dal_fixed32_32_from_fraction(
- 55556,
- 100000 * 10000));
- } else if (params->scaler_efficiency == V_SCALER_EFFICIENCY_LB24BPP) {
- scaler_efficiency =
- dal_fixed32_32_add(
- dal_fixed32_32_from_fraction(34285, 10000),
- dal_fixed32_32_from_fraction(
- 71429,
- 100000 * 10000));
- } else if (params->scaler_efficiency == V_SCALER_EFFICIENCY_LB30BPP)
- scaler_efficiency = dal_fixed32_32_from_fraction(32, 10);
-
- return scaler_efficiency;
-}
-
-static struct fixed32_32 get_lb_lines_in_per_line_out(
- struct min_clock_params *params,
- struct fixed32_32 v_scale_ratio)
-{
- struct fixed32_32 two = dal_fixed32_32_from_int(2);
- struct fixed32_32 four = dal_fixed32_32_from_int(4);
- struct fixed32_32 f4_to_3 = dal_fixed32_32_from_fraction(4, 3);
- struct fixed32_32 f6_to_4 = dal_fixed32_32_from_fraction(6, 4);
-
- if (params->line_buffer_prefetch_enabled)
- return dal_fixed32_32_max(v_scale_ratio, dal_fixed32_32_one);
- else if (dal_fixed32_32_le(v_scale_ratio, dal_fixed32_32_one))
- return dal_fixed32_32_one;
- else if (dal_fixed32_32_le(v_scale_ratio, f4_to_3))
- return f4_to_3;
- else if (dal_fixed32_32_le(v_scale_ratio, f6_to_4))
- return f6_to_4;
- else if (dal_fixed32_32_le(v_scale_ratio, two))
- return two;
- else if (dal_fixed32_32_le(v_scale_ratio, dal_fixed32_32_from_int(3)))
- return four;
- else
- return dal_fixed32_32_zero;
-}
-
-static uint32_t get_actual_required_display_clk(
- struct display_clock_dce110 *disp_clk,
- uint32_t target_clk_khz)
-{
- uint32_t disp_clk_khz = target_clk_khz;
- uint32_t div = INVALID_DIVIDER;
- uint32_t did = INVALID_DID;
- uint32_t scaled_vco =
- disp_clk->dentist_vco_freq_khz * DIVIDER_RANGE_SCALE_FACTOR;
-
- ASSERT_CRITICAL(!!disp_clk_khz);
-
- if (disp_clk_khz)
- div = scaled_vco / disp_clk_khz;
-
- did = dal_divider_range_get_did(divider_ranges, DIVIDER_RANGE_MAX, div);
-
- if (did != INVALID_DID) {
- div = dal_divider_range_get_divider(
- divider_ranges, DIVIDER_RANGE_MAX, did);
-
- if ((div != INVALID_DIVIDER) &&
- (did > DIVIDER_RANGE_01_BASE_DIVIDER_ID))
- if (disp_clk_khz > (scaled_vco / div))
- div = dal_divider_range_get_divider(
- divider_ranges, DIVIDER_RANGE_MAX,
- did - 1);
-
- if (div != INVALID_DIVIDER)
- disp_clk_khz = scaled_vco / div;
-
- }
- /* We need to add 10KHz to this value because the accuracy in VBIOS is
- in 10KHz units. So we need to always round the last digit up in order
- to reach the next div level.*/
- return disp_clk_khz + 10;
-}
-
-static uint32_t calc_single_display_min_clks(
- struct display_clock *base,
- struct min_clock_params *params,
- bool set_clk)
-{
- struct fixed32_32 h_scale_ratio = dal_fixed32_32_one;
- struct fixed32_32 v_scale_ratio = dal_fixed32_32_one;
- uint32_t pix_clk_khz = 0;
- uint32_t lb_source_width = 0;
- struct fixed32_32 deep_color_factor;
- struct fixed32_32 scaler_efficiency;
- struct fixed32_32 v_filter_init;
- uint32_t v_filter_init_trunc;
- uint32_t num_lines_at_frame_start = 3;
- struct fixed32_32 v_filter_init_ceil;
- struct fixed32_32 lines_per_lines_out_at_frame_start;
- struct fixed32_32 lb_lines_in_per_line_out; /* in middle of the frame*/
- uint32_t src_wdth_rnd_to_chunks;
- struct fixed32_32 scaling_coeff;
- struct fixed32_32 h_blank_granularity_factor =
- dal_fixed32_32_one;
- struct fixed32_32 fx_disp_clk_mhz;
- struct fixed32_32 line_time;
- struct fixed32_32 disp_pipe_pix_throughput;
- struct fixed32_32 fx_alt_disp_clk_mhz;
- uint32_t disp_clk_khz;
- uint32_t alt_disp_clk_khz;
- struct display_clock_dce110 *disp_clk_110 = DCLCK110_FROM_BASE(base);
- uint32_t max_clk_khz = get_validation_clock(base);
- bool panning_allowed = false; /* TODO: receive this value from AS */
-
- if (params == NULL) {
- dm_logger_write(base->ctx->logger, LOG_WARNING,
- "Invalid input parameter in %s",
- __func__);
- return 0;
- }
-
- deep_color_factor = get_deep_color_factor(params);
- scaler_efficiency = get_scaler_efficiency(base->ctx, params);
- pix_clk_khz = params->requested_pixel_clock;
- lb_source_width = params->source_view.width;
-
- if (0 != params->dest_view.height && 0 != params->dest_view.width) {
-
- h_scale_ratio = dal_fixed32_32_from_fraction(
- params->source_view.width,
- params->dest_view.width);
- v_scale_ratio = dal_fixed32_32_from_fraction(
- params->source_view.height,
- params->dest_view.height);
- } else {
- dm_logger_write(base->ctx->logger, LOG_WARNING,
- "Destination height or width is 0!\n");
- }
-
- v_filter_init =
- dal_fixed32_32_add(
- v_scale_ratio,
- dal_fixed32_32_add_int(
- dal_fixed32_32_div_int(
- dal_fixed32_32_mul_int(
- v_scale_ratio,
- params->timing_info.INTERLACED),
- 2),
- params->scaling_info.v_taps + 1));
- v_filter_init = dal_fixed32_32_div_int(v_filter_init, 2);
-
- v_filter_init_trunc = dal_fixed32_32_floor(v_filter_init);
-
- v_filter_init_ceil = dal_fixed32_32_from_fraction(
- v_filter_init_trunc, 2);
- v_filter_init_ceil = dal_fixed32_32_from_int(
- dal_fixed32_32_ceil(v_filter_init_ceil));
- v_filter_init_ceil = dal_fixed32_32_mul_int(v_filter_init_ceil, 2);
-
- lines_per_lines_out_at_frame_start =
- dal_fixed32_32_div_int(v_filter_init_ceil,
- num_lines_at_frame_start);
- lb_lines_in_per_line_out =
- get_lb_lines_in_per_line_out(params, v_scale_ratio);
-
- if (panning_allowed)
- src_wdth_rnd_to_chunks =
- ((lb_source_width - 1) / 128) * 128 + 256;
- else
- src_wdth_rnd_to_chunks =
- ((lb_source_width + 127) / 128) * 128;
-
- scaling_coeff =
- dal_fixed32_32_div(
- dal_fixed32_32_from_int(params->scaling_info.v_taps),
- scaler_efficiency);
-
- if (dal_fixed32_32_le(h_scale_ratio, dal_fixed32_32_one))
- scaling_coeff = dal_fixed32_32_max(
- dal_fixed32_32_from_int(
- dal_fixed32_32_ceil(
- dal_fixed32_32_from_fraction(
- params->scaling_info.h_taps,
- 4))),
- dal_fixed32_32_max(
- dal_fixed32_32_mul(
- scaling_coeff,
- h_scale_ratio),
- dal_fixed32_32_one));
-
- if (!params->line_buffer_prefetch_enabled &&
- dal_fixed32_32_floor(lb_lines_in_per_line_out) != 2 &&
- dal_fixed32_32_floor(lb_lines_in_per_line_out) != 4) {
- uint32_t line_total_pixel =
- params->timing_info.h_total + lb_source_width - 256;
- h_blank_granularity_factor = dal_fixed32_32_div(
- dal_fixed32_32_from_int(params->timing_info.h_total),
- dal_fixed32_32_div(
- dal_fixed32_32_from_fraction(
- line_total_pixel, 2),
- h_scale_ratio));
- }
-
- /* Calculate display clock with ramping. Ramping factor is 1.1*/
- fx_disp_clk_mhz =
- dal_fixed32_32_div_int(
- dal_fixed32_32_mul_int(scaling_coeff, 11),
- 10);
- line_time = dal_fixed32_32_from_fraction(
- params->timing_info.h_total * 1000, pix_clk_khz);
-
- disp_pipe_pix_throughput = dal_fixed32_32_mul(
- lb_lines_in_per_line_out, h_blank_granularity_factor);
- disp_pipe_pix_throughput = dal_fixed32_32_max(
- disp_pipe_pix_throughput,
- lines_per_lines_out_at_frame_start);
- disp_pipe_pix_throughput = dal_fixed32_32_div(dal_fixed32_32_mul_int(
- disp_pipe_pix_throughput, src_wdth_rnd_to_chunks),
- line_time);
-
- if (0 != params->timing_info.h_total) {
- fx_disp_clk_mhz =
- dal_fixed32_32_max(
- dal_fixed32_32_div_int(
- dal_fixed32_32_mul_int(
- scaling_coeff, pix_clk_khz),
- 1000),
- disp_pipe_pix_throughput);
- fx_disp_clk_mhz =
- dal_fixed32_32_mul(
- fx_disp_clk_mhz,
- dal_fixed32_32_from_fraction(11, 10));
- }
-
- fx_disp_clk_mhz = dal_fixed32_32_max(fx_disp_clk_mhz,
- dal_fixed32_32_mul(deep_color_factor,
- dal_fixed32_32_from_fraction(11, 10)));
-
- /* Calculate display clock without ramping */
- fx_alt_disp_clk_mhz = scaling_coeff;
-
- if (0 != params->timing_info.h_total) {
- fx_alt_disp_clk_mhz = dal_fixed32_32_max(
- dal_fixed32_32_div_int(dal_fixed32_32_mul_int(
- scaling_coeff, pix_clk_khz),
- 1000),
- dal_fixed32_32_div_int(dal_fixed32_32_mul_int(
- disp_pipe_pix_throughput, 105),
- 100));
- }
-
- if (set_clk && disp_clk_110->ss_on_gpu_pll &&
- disp_clk_110->gpu_pll_ss_divider)
- fx_alt_disp_clk_mhz = dal_fixed32_32_mul(fx_alt_disp_clk_mhz,
- dal_fixed32_32_add_int(
- dal_fixed32_32_div_int(
- dal_fixed32_32_div_int(
- dal_fixed32_32_from_fraction(
- disp_clk_110->gpu_pll_ss_percentage,
- disp_clk_110->gpu_pll_ss_divider), 100),
- 2),
- 1));
-
- /* convert to integer */
- disp_clk_khz = dal_fixed32_32_round(
- dal_fixed32_32_mul_int(fx_disp_clk_mhz, 1000));
- alt_disp_clk_khz = dal_fixed32_32_round(
- dal_fixed32_32_mul_int(fx_alt_disp_clk_mhz, 1000));
-
- if ((disp_clk_khz > max_clk_khz) && (alt_disp_clk_khz <= max_clk_khz))
- disp_clk_khz = alt_disp_clk_khz;
-
- if (set_clk) { /* only compensate clock if we are going to set it.*/
- disp_clk_khz = get_actual_required_display_clk(
- disp_clk_110, disp_clk_khz);
- }
-
- disp_clk_khz = disp_clk_khz > max_clk_khz ? max_clk_khz : disp_clk_khz;
-
- return disp_clk_khz;
-}
-
-static uint32_t calculate_min_clock(
- struct display_clock *base,
- uint32_t path_num,
- struct min_clock_params *params)
-{
- uint32_t i;
- uint32_t validation_clk_khz =
- get_validation_clock(base);
- uint32_t min_clk_khz = validation_clk_khz;
- uint32_t max_clk_khz = 0;
- struct display_clock_dce110 *dc = DCLCK110_FROM_BASE(base);
-
- if (dc->use_max_disp_clk)
- return min_clk_khz;
-
- if (params != NULL) {
- uint32_t disp_clk_khz = 0;
-
- for (i = 0; i < path_num; ++i) {
-
- disp_clk_khz = calc_single_display_min_clks(
- base, params, true);
-
- /* update the max required clock found*/
- if (disp_clk_khz > max_clk_khz)
- max_clk_khz = disp_clk_khz;
-
- params++;
- }
- }
-
- min_clk_khz = max_clk_khz;
-
- if (min_clk_khz > validation_clk_khz)
- min_clk_khz = validation_clk_khz;
- else if (min_clk_khz < base->min_display_clk_threshold_khz)
- min_clk_khz = base->min_display_clk_threshold_khz;
-
- if (dc->use_max_disp_clk)
- min_clk_khz = get_validation_clock(base);
-
- return min_clk_khz;
-}
-
static bool display_clock_integrated_info_construct(
struct display_clock_dce110 *disp_clk)
{
@@ -741,38 +343,6 @@ static bool display_clock_integrated_info_construct(
return true;
}
-static uint32_t get_clock(struct display_clock *dc)
-{
- uint32_t disp_clock = get_validation_clock(dc);
- uint32_t target_div = INVALID_DIVIDER;
- uint32_t addr = mmDENTIST_DISPCLK_CNTL;
- uint32_t value = 0;
- uint32_t field = 0;
- struct display_clock_dce110 *disp_clk = DCLCK110_FROM_BASE(dc);
-
- if (disp_clk->dfs_bypass_enabled && disp_clk->dfs_bypass_disp_clk)
- return disp_clk->dfs_bypass_disp_clk;
-
- /* Read the mmDENTIST_DISPCLK_CNTL to get the currently programmed
- DID DENTIST_DISPCLK_WDIVIDER.*/
- value = dm_read_reg(dc->ctx, addr);
- field = get_reg_field_value(
- value, DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER);
-
- /* Convert DENTIST_DISPCLK_WDIVIDER to actual divider*/
- target_div = dal_divider_range_get_divider(
- divider_ranges,
- DIVIDER_RANGE_MAX,
- field);
-
- if (target_div != INVALID_DIVIDER)
- /* Calculate the current DFS clock in KHz.
- Should be okay up to 42.9 THz before overflowing.*/
- disp_clock = (DIVIDER_RANGE_SCALE_FACTOR
- * disp_clk->dentist_vco_freq_khz) / target_div;
- return disp_clock;
-}
-
static enum clocks_state get_required_clocks_state(
struct display_clock *dc,
struct state_dependent_clocks *req_clocks)
@@ -882,44 +452,15 @@ static void set_clock(
psr_wait_loop(base->ctx, requested_clk_khz);
}
-static void set_clock_state(
- struct display_clock *dc,
- struct display_clock_state clk_state)
-{
- struct display_clock_dce110 *disp_clk = DCLCK110_FROM_BASE(dc);
-
- disp_clk->clock_state = clk_state;
-}
-
-static struct display_clock_state get_clock_state(
- struct display_clock *dc)
-{
- struct display_clock_dce110 *disp_clk = DCLCK110_FROM_BASE(dc);
-
- return disp_clk->clock_state;
-}
-
-static uint32_t get_dfs_bypass_threshold(struct display_clock *dc)
-{
- return DCE110_DFS_BYPASS_THRESHOLD_KHZ;
-}
static const struct display_clock_funcs funcs = {
.destroy = destroy,
- .calculate_min_clock = calculate_min_clock,
- .get_clock = get_clock,
- .get_clock_state = get_clock_state,
- .get_dfs_bypass_threshold = get_dfs_bypass_threshold,
.get_dp_ref_clk_frequency = get_dp_ref_clk_frequency,
.get_min_clocks_state = get_min_clocks_state,
.get_required_clocks_state = get_required_clocks_state,
- .get_validation_clock = get_validation_clock,
.set_clock = set_clock,
- .set_clock_state = set_clock_state,
- .set_dp_ref_clock_source = NULL,
.set_min_clocks_state = set_min_clocks_state,
- .store_max_clocks_state = store_max_clocks_state,
- .validate = NULL,
+ .store_max_clocks_state = store_max_clocks_state
};
static bool dal_display_clock_dce110_construct(
@@ -929,8 +470,11 @@ static bool dal_display_clock_dce110_construct(
struct display_clock *dc_base = &dc110->disp_clk_base;
struct dc_bios *bp = ctx->dc_bios;
- if (!dal_display_clock_construct_base(dc_base, ctx))
- return false;
+ dc_base->ctx = ctx;
+ dc_base->id = CLOCK_SOURCE_ID_DCPLL;
+ dc_base->min_display_clk_threshold_khz = 0;
+
+ dc_base->cur_min_clks_state = CLOCKS_STATE_INVALID;
dc_base->funcs = &funcs;
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h
index 0cdc7b52a09f..88b4bdd75e56 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h
@@ -44,7 +44,6 @@ struct display_clock_dce110 {
/* Cache the display clock returned by VBIOS if DFS-bypass is enabled.
* This is basically "Crystal Frequency In KHz" (XTALIN) frequency */
uint32_t dfs_bypass_disp_clk;
- struct display_clock_state clock_state;
};
#define DCLCK110_FROM_BASE(dc_base) \
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
index 9b7c9755e316..bf044260c0bb 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
@@ -242,406 +242,6 @@ void dispclk_dce112_destroy(struct display_clock **base)
*base = NULL;
}
-uint32_t dispclk_dce112_get_validation_clock(struct display_clock *dc)
-{
- uint32_t clk = 0;
- struct display_clock_dce112 *disp_clk = DCLCK112_FROM_BASE(dc);
-
- switch (disp_clk->max_clks_state) {
- case CLOCKS_STATE_ULTRA_LOW:
- clk = (disp_clk->max_clks_by_state + CLOCKS_STATE_ULTRA_LOW)->
- display_clk_khz;
-
- case CLOCKS_STATE_LOW:
- clk = (disp_clk->max_clks_by_state + CLOCKS_STATE_LOW)->
- display_clk_khz;
- break;
-
- case CLOCKS_STATE_NOMINAL:
- clk = (disp_clk->max_clks_by_state + CLOCKS_STATE_NOMINAL)->
- display_clk_khz;
- break;
-
- case CLOCKS_STATE_PERFORMANCE:
- clk = (disp_clk->max_clks_by_state + CLOCKS_STATE_PERFORMANCE)->
- display_clk_khz;
- break;
-
- case CLOCKS_STATE_INVALID:
- default:
- /*Invalid Clocks State*/
- dm_logger_write(dc->ctx->logger, LOG_WARNING,
- "Invalid clock state");
- /* just return the display engine clock for
- * lowest supported state*/
- clk = (disp_clk->max_clks_by_state + CLOCKS_STATE_LOW)->
- display_clk_khz;
- break;
- }
- return clk;
-}
-
-static struct fixed32_32 get_deep_color_factor(struct min_clock_params *params)
-{
- /* DeepColorFactor = IF (HDMI = True, bpp / 24, 1)*/
- struct fixed32_32 deep_color_factor = dal_fixed32_32_from_int(1);
-
- if (params->signal_type != SIGNAL_TYPE_HDMI_TYPE_A)
- return deep_color_factor;
-
- switch (params->deep_color_depth) {
- case COLOR_DEPTH_101010:
- /*deep color ratio for 30bpp is 30/24 = 1.25*/
- deep_color_factor = dal_fixed32_32_from_fraction(30, 24);
- break;
-
- case COLOR_DEPTH_121212:
- /* deep color ratio for 36bpp is 36/24 = 1.5*/
- deep_color_factor = dal_fixed32_32_from_fraction(36, 24);
- break;
-
- case COLOR_DEPTH_161616:
- /* deep color ratio for 48bpp is 48/24 = 2.0 */
- deep_color_factor = dal_fixed32_32_from_fraction(48, 24);
- break;
- default:
- break;
- }
- return deep_color_factor;
-}
-
-static struct fixed32_32 get_scaler_efficiency(
- struct dc_context *ctx,
- struct min_clock_params *params)
-{
- struct fixed32_32 scaler_efficiency = dal_fixed32_32_from_int(3);
-
- if (params->scaler_efficiency == V_SCALER_EFFICIENCY_LB18BPP) {
- scaler_efficiency =
- dal_fixed32_32_add(
- dal_fixed32_32_from_fraction(35555, 10000),
- dal_fixed32_32_from_fraction(
- 55556,
- 100000 * 10000));
- } else if (params->scaler_efficiency == V_SCALER_EFFICIENCY_LB24BPP) {
- scaler_efficiency =
- dal_fixed32_32_add(
- dal_fixed32_32_from_fraction(34285, 10000),
- dal_fixed32_32_from_fraction(
- 71429,
- 100000 * 10000));
- } else if (params->scaler_efficiency == V_SCALER_EFFICIENCY_LB30BPP)
- scaler_efficiency = dal_fixed32_32_from_fraction(32, 10);
-
- return scaler_efficiency;
-}
-
-static struct fixed32_32 get_lb_lines_in_per_line_out(
- struct min_clock_params *params,
- struct fixed32_32 v_scale_ratio)
-{
- struct fixed32_32 two = dal_fixed32_32_from_int(2);
- struct fixed32_32 four = dal_fixed32_32_from_int(4);
- struct fixed32_32 f4_to_3 = dal_fixed32_32_from_fraction(4, 3);
- struct fixed32_32 f6_to_4 = dal_fixed32_32_from_fraction(6, 4);
-
- if (params->line_buffer_prefetch_enabled)
- return dal_fixed32_32_max(v_scale_ratio, dal_fixed32_32_one);
- else if (dal_fixed32_32_le(v_scale_ratio, dal_fixed32_32_one))
- return dal_fixed32_32_one;
- else if (dal_fixed32_32_le(v_scale_ratio, f4_to_3))
- return f4_to_3;
- else if (dal_fixed32_32_le(v_scale_ratio, f6_to_4))
- return f6_to_4;
- else if (dal_fixed32_32_le(v_scale_ratio, two))
- return two;
- else if (dal_fixed32_32_le(v_scale_ratio, dal_fixed32_32_from_int(3)))
- return four;
- else
- return dal_fixed32_32_zero;
-}
-
-static uint32_t get_actual_required_display_clk(
- struct display_clock_dce112 *disp_clk,
- uint32_t target_clk_khz)
-{
- uint32_t disp_clk_khz = target_clk_khz;
- uint32_t div = INVALID_DIVIDER;
- uint32_t did = INVALID_DID;
- uint32_t scaled_vco =
- disp_clk->dentist_vco_freq_khz * DIVIDER_RANGE_SCALE_FACTOR;
-
- ASSERT_CRITICAL(!!disp_clk_khz);
-
- if (disp_clk_khz)
- div = scaled_vco / disp_clk_khz;
-
- did = dal_divider_range_get_did(divider_ranges, DIVIDER_RANGE_MAX, div);
-
- if (did != INVALID_DID) {
- div = dal_divider_range_get_divider(
- divider_ranges, DIVIDER_RANGE_MAX, did);
-
- if ((div != INVALID_DIVIDER) &&
- (did > DIVIDER_RANGE_01_BASE_DIVIDER_ID))
- if (disp_clk_khz > (scaled_vco / div))
- div = dal_divider_range_get_divider(
- divider_ranges, DIVIDER_RANGE_MAX,
- did - 1);
-
- if (div != INVALID_DIVIDER)
- disp_clk_khz = scaled_vco / div;
-
- }
- /* We need to add 10KHz to this value because the accuracy in VBIOS is
- in 10KHz units. So we need to always round the last digit up in order
- to reach the next div level.*/
- return disp_clk_khz + 10;
-}
-
-static uint32_t calc_single_display_min_clks(
- struct display_clock *base,
- struct min_clock_params *params,
- bool set_clk)
-{
- struct fixed32_32 h_scale_ratio = dal_fixed32_32_one;
- struct fixed32_32 v_scale_ratio = dal_fixed32_32_one;
- uint32_t pix_clk_khz = 0;
- uint32_t lb_source_width = 0;
- struct fixed32_32 deep_color_factor;
- struct fixed32_32 scaler_efficiency;
- struct fixed32_32 v_filter_init;
- uint32_t v_filter_init_trunc;
- uint32_t num_lines_at_frame_start = 3;
- struct fixed32_32 v_filter_init_ceil;
- struct fixed32_32 lines_per_lines_out_at_frame_start;
- struct fixed32_32 lb_lines_in_per_line_out; /* in middle of the frame*/
- uint32_t src_wdth_rnd_to_chunks;
- struct fixed32_32 scaling_coeff;
- struct fixed32_32 h_blank_granularity_factor =
- dal_fixed32_32_one;
- struct fixed32_32 fx_disp_clk_mhz;
- struct fixed32_32 line_time;
- struct fixed32_32 disp_pipe_pix_throughput;
- struct fixed32_32 fx_alt_disp_clk_mhz;
- uint32_t disp_clk_khz;
- uint32_t alt_disp_clk_khz;
- struct display_clock_dce112 *disp_clk_110 = DCLCK112_FROM_BASE(base);
- uint32_t max_clk_khz = dispclk_dce112_get_validation_clock(base);
- bool panning_allowed = false; /* TODO: receive this value from AS */
-
- if (params == NULL) {
- dm_logger_write(base->ctx->logger, LOG_WARNING,
- "Invalid input parameter in %s",
- __func__);
- return 0;
- }
-
- deep_color_factor = get_deep_color_factor(params);
- scaler_efficiency = get_scaler_efficiency(base->ctx, params);
- pix_clk_khz = params->requested_pixel_clock;
- lb_source_width = params->source_view.width;
-
- if (0 != params->dest_view.height && 0 != params->dest_view.width) {
-
- h_scale_ratio = dal_fixed32_32_from_fraction(
- params->source_view.width,
- params->dest_view.width);
- v_scale_ratio = dal_fixed32_32_from_fraction(
- params->source_view.height,
- params->dest_view.height);
- } else {
- dm_logger_write(base->ctx->logger, LOG_WARNING,
- "Destination height or width is 0!\n");
- }
-
- v_filter_init =
- dal_fixed32_32_add(
- v_scale_ratio,
- dal_fixed32_32_add_int(
- dal_fixed32_32_div_int(
- dal_fixed32_32_mul_int(
- v_scale_ratio,
- params->timing_info.INTERLACED),
- 2),
- params->scaling_info.v_taps + 1));
- v_filter_init = dal_fixed32_32_div_int(v_filter_init, 2);
-
- v_filter_init_trunc = dal_fixed32_32_floor(v_filter_init);
-
- v_filter_init_ceil = dal_fixed32_32_from_fraction(
- v_filter_init_trunc, 2);
- v_filter_init_ceil = dal_fixed32_32_from_int(
- dal_fixed32_32_ceil(v_filter_init_ceil));
- v_filter_init_ceil = dal_fixed32_32_mul_int(v_filter_init_ceil, 2);
-
- lines_per_lines_out_at_frame_start =
- dal_fixed32_32_div_int(v_filter_init_ceil,
- num_lines_at_frame_start);
- lb_lines_in_per_line_out =
- get_lb_lines_in_per_line_out(params, v_scale_ratio);
-
- if (panning_allowed)
- src_wdth_rnd_to_chunks =
- ((lb_source_width - 1) / 128) * 128 + 256;
- else
- src_wdth_rnd_to_chunks =
- ((lb_source_width + 127) / 128) * 128;
-
- scaling_coeff =
- dal_fixed32_32_div(
- dal_fixed32_32_from_int(params->scaling_info.v_taps),
- scaler_efficiency);
-
- if (dal_fixed32_32_le(h_scale_ratio, dal_fixed32_32_one))
- scaling_coeff = dal_fixed32_32_max(
- dal_fixed32_32_from_int(
- dal_fixed32_32_ceil(
- dal_fixed32_32_from_fraction(
- params->scaling_info.h_taps,
- 4))),
- dal_fixed32_32_max(
- dal_fixed32_32_mul(
- scaling_coeff,
- h_scale_ratio),
- dal_fixed32_32_one));
-
- if (!params->line_buffer_prefetch_enabled &&
- dal_fixed32_32_floor(lb_lines_in_per_line_out) != 2 &&
- dal_fixed32_32_floor(lb_lines_in_per_line_out) != 4) {
- uint32_t line_total_pixel =
- params->timing_info.h_total + lb_source_width - 256;
- h_blank_granularity_factor = dal_fixed32_32_div(
- dal_fixed32_32_from_int(params->timing_info.h_total),
- dal_fixed32_32_div(
- dal_fixed32_32_from_fraction(
- line_total_pixel, 2),
- h_scale_ratio));
- }
-
- /* Calculate display clock with ramping. Ramping factor is 1.1*/
- fx_disp_clk_mhz =
- dal_fixed32_32_div_int(
- dal_fixed32_32_mul_int(scaling_coeff, 11),
- 10);
- line_time = dal_fixed32_32_from_fraction(
- params->timing_info.h_total * 1000, pix_clk_khz);
-
- disp_pipe_pix_throughput = dal_fixed32_32_mul(
- lb_lines_in_per_line_out, h_blank_granularity_factor);
- disp_pipe_pix_throughput = dal_fixed32_32_max(
- disp_pipe_pix_throughput,
- lines_per_lines_out_at_frame_start);
- disp_pipe_pix_throughput = dal_fixed32_32_div(dal_fixed32_32_mul_int(
- disp_pipe_pix_throughput, src_wdth_rnd_to_chunks),
- line_time);
-
- if (0 != params->timing_info.h_total) {
- fx_disp_clk_mhz =
- dal_fixed32_32_max(
- dal_fixed32_32_div_int(
- dal_fixed32_32_mul_int(
- scaling_coeff, pix_clk_khz),
- 1000),
- disp_pipe_pix_throughput);
- fx_disp_clk_mhz =
- dal_fixed32_32_mul(
- fx_disp_clk_mhz,
- dal_fixed32_32_from_fraction(11, 10));
- }
-
- fx_disp_clk_mhz = dal_fixed32_32_max(fx_disp_clk_mhz,
- dal_fixed32_32_mul(deep_color_factor,
- dal_fixed32_32_from_fraction(11, 10)));
-
- /* Calculate display clock without ramping */
- fx_alt_disp_clk_mhz = scaling_coeff;
-
- if (0 != params->timing_info.h_total) {
- fx_alt_disp_clk_mhz = dal_fixed32_32_max(
- dal_fixed32_32_div_int(dal_fixed32_32_mul_int(
- scaling_coeff, pix_clk_khz),
- 1000),
- dal_fixed32_32_div_int(dal_fixed32_32_mul_int(
- disp_pipe_pix_throughput, 105),
- 100));
- }
-
- if (set_clk && disp_clk_110->ss_on_gpu_pll &&
- disp_clk_110->gpu_pll_ss_divider)
- fx_alt_disp_clk_mhz = dal_fixed32_32_mul(fx_alt_disp_clk_mhz,
- dal_fixed32_32_add_int(
- dal_fixed32_32_div_int(
- dal_fixed32_32_div_int(
- dal_fixed32_32_from_fraction(
- disp_clk_110->gpu_pll_ss_percentage,
- disp_clk_110->gpu_pll_ss_divider), 100),
- 2),
- 1));
-
- /* convert to integer */
- disp_clk_khz = dal_fixed32_32_round(
- dal_fixed32_32_mul_int(fx_disp_clk_mhz, 1000));
- alt_disp_clk_khz = dal_fixed32_32_round(
- dal_fixed32_32_mul_int(fx_alt_disp_clk_mhz, 1000));
-
- if ((disp_clk_khz > max_clk_khz) && (alt_disp_clk_khz <= max_clk_khz))
- disp_clk_khz = alt_disp_clk_khz;
-
- if (set_clk) { /* only compensate clock if we are going to set it.*/
- disp_clk_khz = get_actual_required_display_clk(
- disp_clk_110, disp_clk_khz);
- }
-
- disp_clk_khz = disp_clk_khz > max_clk_khz ? max_clk_khz : disp_clk_khz;
-
- return disp_clk_khz;
-}
-
-uint32_t dispclk_dce112_calculate_min_clock(
- struct display_clock *base,
- uint32_t path_num,
- struct min_clock_params *params)
-{
- uint32_t i;
- uint32_t validation_clk_khz =
- dispclk_dce112_get_validation_clock(base);
- uint32_t min_clk_khz = validation_clk_khz;
- uint32_t max_clk_khz = 0;
- struct display_clock_dce112 *dc = DCLCK112_FROM_BASE(base);
-
- if (dc->use_max_disp_clk)
- return min_clk_khz;
-
- if (params != NULL) {
- uint32_t disp_clk_khz = 0;
-
- for (i = 0; i < path_num; ++i) {
-
- disp_clk_khz = calc_single_display_min_clks(
- base, params, true);
-
- /* update the max required clock found*/
- if (disp_clk_khz > max_clk_khz)
- max_clk_khz = disp_clk_khz;
-
- params++;
- }
- }
-
- min_clk_khz = max_clk_khz;
-
- if (min_clk_khz > validation_clk_khz)
- min_clk_khz = validation_clk_khz;
- else if (min_clk_khz < base->min_display_clk_threshold_khz)
- min_clk_khz = base->min_display_clk_threshold_khz;
-
- if (dc->use_max_disp_clk)
- min_clk_khz = dispclk_dce112_get_validation_clock(base);
-
- return min_clk_khz;
-}
-
static bool display_clock_integrated_info_construct(
struct display_clock_dce112 *disp_clk)
{
@@ -655,8 +255,6 @@ static bool display_clock_integrated_info_construct(
if (disp_clk->dentist_vco_freq_khz == 0)
disp_clk->dentist_vco_freq_khz = 3600000;
- disp_clk->crystal_freq_khz = 100000;
-
base->min_display_clk_threshold_khz =
disp_clk->dentist_vco_freq_khz / 64;
@@ -698,35 +296,6 @@ static bool display_clock_integrated_info_construct(
return true;
}
-static uint32_t get_clock(struct display_clock *dc)
-{
- uint32_t disp_clock = dispclk_dce112_get_validation_clock(dc);
- uint32_t target_div = INVALID_DIVIDER;
- uint32_t addr = mmDENTIST_DISPCLK_CNTL;
- uint32_t value = 0;
- uint32_t field = 0;
- struct display_clock_dce112 *disp_clk = DCLCK112_FROM_BASE(dc);
-
- /* Read the mmDENTIST_DISPCLK_CNTL to get the currently programmed
- DID DENTIST_DISPCLK_WDIVIDER.*/
- value = dm_read_reg(dc->ctx, addr);
- field = get_reg_field_value(
- value, DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER);
-
- /* Convert DENTIST_DISPCLK_WDIVIDER to actual divider*/
- target_div = dal_divider_range_get_divider(
- divider_ranges,
- DIVIDER_RANGE_MAX,
- field);
-
- if (target_div != INVALID_DIVIDER)
- /* Calculate the current DFS clock in KHz.
- Should be okay up to 42.9 THz before overflowing.*/
- disp_clock = (DIVIDER_RANGE_SCALE_FACTOR
- * disp_clk->dentist_vco_freq_khz) / target_div;
- return disp_clock;
-}
-
enum clocks_state dispclk_dce112_get_required_clocks_state(
struct display_clock *dc,
struct state_dependent_clocks *req_clocks)
@@ -797,45 +366,14 @@ void dispclk_dce112_set_clock(
bp->funcs->set_dce_clock(bp, &dce_clk_params);
}
-void dispclk_dce112_set_clock_state(
- struct display_clock *dc,
- struct display_clock_state clk_state)
-{
- struct display_clock_dce112 *disp_clk = DCLCK112_FROM_BASE(dc);
-
- disp_clk->clock_state = clk_state;
-}
-
-struct display_clock_state dispclk_dce112_get_clock_state(
- struct display_clock *dc)
-{
- struct display_clock_dce112 *disp_clk = DCLCK112_FROM_BASE(dc);
-
- return disp_clk->clock_state;
-}
-
-uint32_t dispclk_dce112_get_dfs_bypass_threshold(
- struct display_clock *dc)
-{
- return dce112_DFS_BYPASS_THRESHOLD_KHZ;
-}
-
static const struct display_clock_funcs funcs = {
.destroy = dispclk_dce112_destroy,
- .calculate_min_clock = dispclk_dce112_calculate_min_clock,
- .get_clock = get_clock,
- .get_clock_state = dispclk_dce112_get_clock_state,
- .get_dfs_bypass_threshold = dispclk_dce112_get_dfs_bypass_threshold,
.get_dp_ref_clk_frequency = get_dp_ref_clk_frequency,
.get_min_clocks_state = dispclk_dce112_get_min_clocks_state,
.get_required_clocks_state = dispclk_dce112_get_required_clocks_state,
- .get_validation_clock = dispclk_dce112_get_validation_clock,
.set_clock = dispclk_dce112_set_clock,
- .set_clock_state = dispclk_dce112_set_clock_state,
- .set_dp_ref_clock_source = NULL,
.set_min_clocks_state = dispclk_dce112_set_min_clocks_state,
.store_max_clocks_state = dispclk_dce112_store_max_clocks_state,
- .validate = NULL,
};
bool dal_display_clock_dce112_construct(
@@ -844,11 +382,11 @@ bool dal_display_clock_dce112_construct(
{
struct display_clock *dc_base = &dc112->disp_clk_base;
- /*if (NULL == as)
- return false;*/
+ dc_base->ctx = ctx;
+ dc_base->id = CLOCK_SOURCE_ID_DCPLL;
+ dc_base->min_display_clk_threshold_khz = 0;
- if (!dal_display_clock_construct_base(dc_base, ctx))
- return false;
+ dc_base->cur_min_clks_state = CLOCKS_STATE_INVALID;
dc_base->funcs = &funcs;
@@ -870,12 +408,7 @@ bool dal_display_clock_dce112_construct(
dc112->max_clks_state = CLOCKS_STATE_NOMINAL;
dc112->disp_clk_base.min_display_clk_threshold_khz =
- dc112->crystal_freq_khz;
-
- if (dc112->disp_clk_base.min_display_clk_threshold_khz <
- (dc112->dentist_vco_freq_khz / 62))
- dc112->disp_clk_base.min_display_clk_threshold_khz =
- (dc112->dentist_vco_freq_khz / 62);
+ (dc112->dentist_vco_freq_khz / 62);
dal_divider_range_construct(
÷r_ranges[DIVIDER_RANGE_01],
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
index 937e17929b7c..5ab31185d29d 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
@@ -45,7 +45,6 @@ struct display_clock_dce112 {
/* Cache the display clock returned by VBIOS if DFS-bypass is enabled.
* This is basically "Crystal Frequency In KHz" (XTALIN) frequency */
uint32_t dfs_bypass_disp_clk;
- struct display_clock_state clock_state;
struct state_dependent_clocks *max_clks_by_state;
};
@@ -75,17 +74,6 @@ bool dal_display_clock_dce112_construct(
void dispclk_dce112_destroy(struct display_clock **base);
-uint32_t dispclk_dce112_calculate_min_clock(
- struct display_clock *base,
- uint32_t path_num,
- struct min_clock_params *params);
-
-struct display_clock_state dispclk_dce112_get_clock_state(
- struct display_clock *dc);
-
-uint32_t dispclk_dce112_get_dfs_bypass_threshold(
- struct display_clock *dc);
-
enum clocks_state dispclk_dce112_get_min_clocks_state(
struct display_clock *base);
@@ -93,16 +81,10 @@ enum clocks_state dispclk_dce112_get_required_clocks_state(
struct display_clock *dc,
struct state_dependent_clocks *req_clocks);
-uint32_t dispclk_dce112_get_validation_clock(struct display_clock *dc);
-
void dispclk_dce112_set_clock(
struct display_clock *base,
uint32_t requested_clk_khz);
-void dispclk_dce112_set_clock_state(
- struct display_clock *dc,
- struct display_clock_state clk_state);
-
bool dispclk_dce112_set_min_clocks_state(
struct display_clock *base,
enum clocks_state clocks_state);
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c
index eedcfd6232fc..89ee8bd96979 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c
@@ -90,380 +90,6 @@ static struct divider_range divider_ranges[DIVIDER_RANGE_MAX];
#define FROM_DISPLAY_CLOCK(base) \
container_of(base, struct display_clock_dce80, disp_clk)
-static struct fixed32_32 get_deep_color_factor(struct min_clock_params *params)
-{
- /* DeepColorFactor = IF (HDMI = True, bpp / 24, 1)*/
- struct fixed32_32 deep_color_factor = dal_fixed32_32_from_int(1);
-
- if (params->signal_type != SIGNAL_TYPE_HDMI_TYPE_A)
- return deep_color_factor;
-
- switch (params->deep_color_depth) {
- case COLOR_DEPTH_101010:
- /*deep color ratio for 30bpp is 30/24 = 1.25*/
- deep_color_factor = dal_fixed32_32_from_fraction(30, 24);
- break;
-
- case COLOR_DEPTH_121212:
- /* deep color ratio for 36bpp is 36/24 = 1.5*/
- deep_color_factor = dal_fixed32_32_from_fraction(36, 24);
- break;
-
- case COLOR_DEPTH_161616:
- /* deep color ratio for 48bpp is 48/24 = 2.0 */
- deep_color_factor = dal_fixed32_32_from_fraction(48, 24);
- break;
- default:
- break;
- }
- return deep_color_factor;
-}
-
-static uint32_t get_scaler_efficiency(struct min_clock_params *params)
-{
- uint32_t scaler_efficiency = 3;
-
- switch (params->scaler_efficiency) {
- case V_SCALER_EFFICIENCY_LB18BPP:
- case V_SCALER_EFFICIENCY_LB24BPP:
- scaler_efficiency = 4;
- break;
-
- case V_SCALER_EFFICIENCY_LB30BPP:
- case V_SCALER_EFFICIENCY_LB36BPP:
- scaler_efficiency = 3;
- break;
-
- default:
- break;
- }
-
- return scaler_efficiency;
-}
-
-static uint32_t get_actual_required_display_clk(
- struct display_clock_dce80 *disp_clk,
- uint32_t target_clk_khz)
-{
- uint32_t disp_clk_khz = target_clk_khz;
- uint32_t div = INVALID_DIVIDER;
- uint32_t did = INVALID_DID;
- uint32_t scaled_vco =
- disp_clk->dentist_vco_freq_khz * DIVIDER_RANGE_SCALE_FACTOR;
-
- ASSERT(disp_clk_khz);
-
- if (disp_clk_khz)
- div = scaled_vco / disp_clk_khz;
-
- did = dal_divider_range_get_did(divider_ranges, DIVIDER_RANGE_MAX, div);
-
- if (did != INVALID_DID) {
- div = dal_divider_range_get_divider(
- divider_ranges, DIVIDER_RANGE_MAX, did);
-
- if ((div != INVALID_DIVIDER) &&
- (did > DIVIDER_RANGE_01_BASE_DIVIDER_ID))
- if (disp_clk_khz > (scaled_vco / div))
- div = dal_divider_range_get_divider(
- divider_ranges, DIVIDER_RANGE_MAX,
- did - 1);
-
- if (div != INVALID_DIVIDER)
- disp_clk_khz = scaled_vco / div;
-
- }
- /* We need to add 10KHz to this value because the accuracy in VBIOS is
- in 10KHz units. So we need to always round the last digit up in order
- to reach the next div level.*/
- return disp_clk_khz + 10;
-}
-
-static uint32_t get_validation_clock(struct display_clock *dc)
-{
- uint32_t clk = 0;
- struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-
- switch (disp_clk->max_clks_state) {
- case CLOCKS_STATE_ULTRA_LOW:
- /*Currently not supported, it has 0 in table entry*/
- case CLOCKS_STATE_LOW:
- clk = max_clks_by_state[CLOCKS_STATE_LOW].
- display_clk_khz;
- break;
-
- case CLOCKS_STATE_NOMINAL:
- clk = max_clks_by_state[CLOCKS_STATE_NOMINAL].
- display_clk_khz;
- break;
-
- case CLOCKS_STATE_PERFORMANCE:
- clk = max_clks_by_state[CLOCKS_STATE_PERFORMANCE].
- display_clk_khz;
- break;
-
- case CLOCKS_STATE_INVALID:
- default:
- /*Invalid Clocks State*/
- BREAK_TO_DEBUGGER();
- /* just return the display engine clock for
- * lowest supported state*/
- clk = max_clks_by_state[CLOCKS_STATE_LOW].
- display_clk_khz;
- break;
- }
- return clk;
-}
-
-static uint32_t calc_single_display_min_clks(
- struct display_clock *base,
- struct min_clock_params *params,
- bool set_clk)
-{
- struct fixed32_32 h_scale = dal_fixed32_32_from_int(1);
- struct fixed32_32 v_scale = dal_fixed32_32_from_int(1);
- uint32_t pix_clk_khz = params->requested_pixel_clock;
- uint32_t line_total = params->timing_info.h_total;
- uint32_t max_clk_khz = get_validation_clock(base);
- struct fixed32_32 deep_color_factor = get_deep_color_factor(params);
- uint32_t scaler_efficiency = get_scaler_efficiency(params);
- struct fixed32_32 v_filter_init;
- uint32_t v_filter_init_trunc;
- struct fixed32_32 v_filter_init_ceil;
- struct fixed32_32 src_lines_per_dst_line;
- uint32_t src_wdth_rnd_to_chunks;
- struct fixed32_32 scaling_coeff;
- struct fixed32_32 fx_disp_clk_khz;
- struct fixed32_32 fx_alt_disp_clk_khz;
- uint32_t disp_clk_khz;
- uint32_t alt_disp_clk_khz;
- struct display_clock_dce80 *dc = FROM_DISPLAY_CLOCK(base);
-
- if (0 != params->dest_view.height && 0 != params->dest_view.width) {
-
- h_scale = dal_fixed32_32_from_fraction(
- params->source_view.width,
- params->dest_view.width);
- v_scale = dal_fixed32_32_from_fraction(
- params->source_view.height,
- params->dest_view.height);
- }
-
- v_filter_init = dal_fixed32_32_from_fraction(
- params->scaling_info.v_taps, 2u);
- v_filter_init = dal_fixed32_32_add(v_filter_init,
- dal_fixed32_32_div_int(v_scale, 2));
- v_filter_init = dal_fixed32_32_add(v_filter_init,
- dal_fixed32_32_from_fraction(15, 10));
-
- v_filter_init_trunc = dal_fixed32_32_floor(v_filter_init);
-
- v_filter_init_ceil = dal_fixed32_32_from_fraction(
- v_filter_init_trunc, 2);
- v_filter_init_ceil = dal_fixed32_32_from_int(
- dal_fixed32_32_ceil(v_filter_init_ceil));
- v_filter_init_ceil = dal_fixed32_32_mul_int(v_filter_init_ceil, 2);
- v_filter_init_ceil = dal_fixed32_32_div_int(v_filter_init_ceil, 3);
- v_filter_init_ceil = dal_fixed32_32_from_int(
- dal_fixed32_32_ceil(v_filter_init_ceil));
-
- src_lines_per_dst_line = dal_fixed32_32_max(
- dal_fixed32_32_from_int(dal_fixed32_32_ceil(v_scale)),
- v_filter_init_ceil);
-
- src_wdth_rnd_to_chunks =
- ((params->source_view.width - 1) / 128) * 128 + 256;
-
- scaling_coeff = dal_fixed32_32_max(
- dal_fixed32_32_from_fraction(params->scaling_info.h_taps, 4),
- dal_fixed32_32_mul(
- dal_fixed32_32_from_fraction(
- params->scaling_info.v_taps,
- scaler_efficiency),
- h_scale));
-
- scaling_coeff = dal_fixed32_32_max(scaling_coeff, h_scale);
-
- fx_disp_clk_khz = dal_fixed32_32_mul(
- scaling_coeff, dal_fixed32_32_from_fraction(11, 10));
- if (0 != line_total) {
- struct fixed32_32 d_clk = dal_fixed32_32_mul_int(
- src_lines_per_dst_line, src_wdth_rnd_to_chunks);
- d_clk = dal_fixed32_32_div_int(d_clk, line_total);
- d_clk = dal_fixed32_32_mul(d_clk,
- dal_fixed32_32_from_fraction(11, 10));
- fx_disp_clk_khz = dal_fixed32_32_max(fx_disp_clk_khz, d_clk);
- }
-
- fx_disp_clk_khz = dal_fixed32_32_max(fx_disp_clk_khz,
- dal_fixed32_32_mul(deep_color_factor,
- dal_fixed32_32_from_fraction(11, 10)));
-
- fx_disp_clk_khz = dal_fixed32_32_mul_int(fx_disp_clk_khz, pix_clk_khz);
- fx_disp_clk_khz = dal_fixed32_32_mul(fx_disp_clk_khz,
- dal_fixed32_32_from_fraction(1005, 1000));
-
- fx_alt_disp_clk_khz = scaling_coeff;
-
- if (0 != line_total) {
- struct fixed32_32 d_clk = dal_fixed32_32_mul_int(
- src_lines_per_dst_line, src_wdth_rnd_to_chunks);
- d_clk = dal_fixed32_32_div_int(d_clk, line_total);
- d_clk = dal_fixed32_32_mul(d_clk,
- dal_fixed32_32_from_fraction(105, 100));
- fx_alt_disp_clk_khz = dal_fixed32_32_max(
- fx_alt_disp_clk_khz, d_clk);
- }
- fx_alt_disp_clk_khz = dal_fixed32_32_max(
- fx_alt_disp_clk_khz, fx_alt_disp_clk_khz);
-
- fx_alt_disp_clk_khz = dal_fixed32_32_mul_int(
- fx_alt_disp_clk_khz, pix_clk_khz);
-
- /* convert to integer*/
- disp_clk_khz = dal_fixed32_32_floor(fx_disp_clk_khz);
- alt_disp_clk_khz = dal_fixed32_32_floor(fx_alt_disp_clk_khz);
-
- if (set_clk) { /* only compensate clock if we are going to set it.*/
- disp_clk_khz = get_actual_required_display_clk(
- dc, disp_clk_khz);
- alt_disp_clk_khz = get_actual_required_display_clk(
- dc, alt_disp_clk_khz);
- }
-
- if ((disp_clk_khz > max_clk_khz) && (alt_disp_clk_khz <= max_clk_khz))
- disp_clk_khz = alt_disp_clk_khz;
-
- return disp_clk_khz;
-
-}
-
-static uint32_t calc_cursor_bw_for_min_clks(struct min_clock_params *params)
-{
-
- struct fixed32_32 v_scale = dal_fixed32_32_from_int(1);
- struct fixed32_32 v_filter_ceiling;
- struct fixed32_32 src_lines_per_dst_line;
- struct fixed32_32 cursor_bw;
-
- /* DCE8 Mode Support and Mode Set Architecture Specification Rev 1.3
- 6.3.3 Cursor data Throughput requirement on DISPCLK
- The MCIF to DCP cursor data return throughput is one pixel per DISPCLK
- shared among the display heads.
- If (Total Cursor Bandwidth in pixels for All heads> DISPCLK)
- The mode is not supported
- Cursor Bandwidth in Pixels = Cursor Width *
- (SourceLinesPerDestinationLine / Line Time)
- Assuming that Cursor Width = 128
- */
- /*In the hardware doc they mention an Interlace Factor
- It is not used here because we have already used it when
- calculating destination view*/
- if (0 != params->dest_view.height)
- v_scale = dal_fixed32_32_from_fraction(
- params->source_view.height,
- params->dest_view.height);
-
- {
- /*Do: Vertical Filter Init = 0.5 + VTAPS/2 + VSR/2 * Interlace Factor*/
- /*Interlace Factor is included in verticalScaleRatio*/
- struct fixed32_32 v_filter = dal_fixed32_32_add(
- dal_fixed32_32_from_fraction(params->scaling_info.v_taps, 2),
- dal_fixed32_32_div_int(v_scale, 2));
- /*Do : Ceiling (Vertical Filter Init, 2)/3 )*/
- v_filter_ceiling = dal_fixed32_32_div_int(v_filter, 2);
- v_filter_ceiling = dal_fixed32_32_mul_int(
- dal_fixed32_32_from_int(dal_fixed32_32_ceil(v_filter_ceiling)),
- 2);
- v_filter_ceiling = dal_fixed32_32_div_int(v_filter_ceiling, 3);
- }
- /*Do : MAX( CeilCeiling (VSR), Ceiling (Vertical Filter Init, 2)/3 )*/
- /*Do : SourceLinesPerDestinationLine =
- * MAX( Ceiling (VSR), Ceiling (Vertical Filter Init, 2)/3 )*/
- src_lines_per_dst_line = dal_fixed32_32_max(v_scale, v_filter_ceiling);
-
- if ((params->requested_pixel_clock != 0) &&
- (params->timing_info.h_total != 0)) {
- /* pixelClock is in units of KHz. Calc lineTime in us*/
- struct fixed32_32 inv_line_time = dal_fixed32_32_from_fraction(
- params->requested_pixel_clock,
- params->timing_info.h_total);
- cursor_bw = dal_fixed32_32_mul(
- dal_fixed32_32_mul_int(inv_line_time, 128),
- src_lines_per_dst_line);
- }
-
- /* convert to integer*/
- return dal_fixed32_32_floor(cursor_bw);
-}
-
-static bool validate(
- struct display_clock *dc,
- struct min_clock_params *params)
-{
- uint32_t max_clk_khz = get_validation_clock(dc);
- uint32_t req_clk_khz;
-
- if (params == NULL)
- return false;
-
- req_clk_khz = calc_single_display_min_clks(dc, params, false);
-
- return (req_clk_khz <= max_clk_khz);
-}
-
-static uint32_t calculate_min_clock(
- struct display_clock *dc,
- uint32_t path_num,
- struct min_clock_params *params)
-{
- uint32_t i;
- uint32_t validation_clk_khz = get_validation_clock(dc);
- uint32_t min_clk_khz = validation_clk_khz;
- uint32_t max_clk_khz = 0;
- uint32_t total_cursor_bw = 0;
- struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-
- if (disp_clk->use_max_disp_clk)
- return min_clk_khz;
-
- if (params != NULL) {
- uint32_t disp_clk_khz = 0;
-
- for (i = 0; i < path_num; ++i) {
- disp_clk_khz = calc_single_display_min_clks(
- dc, params, true);
-
- /* update the max required clock found*/
- if (disp_clk_khz > max_clk_khz)
- max_clk_khz = disp_clk_khz;
-
- disp_clk_khz = calc_cursor_bw_for_min_clks(params);
-
- total_cursor_bw += disp_clk_khz;
-
- params++;
-
- }
- }
-
- max_clk_khz = (total_cursor_bw > max_clk_khz) ? total_cursor_bw :
- max_clk_khz;
-
- min_clk_khz = max_clk_khz;
-
- /*"Cursor data Throughput requirement on DISPCLK is now a factor,
- * need to change the code */
- ASSERT(total_cursor_bw < validation_clk_khz);
-
- if (min_clk_khz > validation_clk_khz)
- min_clk_khz = validation_clk_khz;
- else if (min_clk_khz < dc->min_display_clk_threshold_khz)
- min_clk_khz = dc->min_display_clk_threshold_khz;
-
- return min_clk_khz;
-}
-
static void set_clock(
struct display_clock *dc,
uint32_t requested_clk_khz)
@@ -493,54 +119,6 @@ static void set_clock(
disp_clk->cur_min_clks_state = CLOCKS_STATE_NOMINAL;
}
-static uint32_t get_clock(struct display_clock *dc)
-{
- uint32_t disp_clock = get_validation_clock(dc);
- uint32_t target_div = INVALID_DIVIDER;
- uint32_t addr = mmDENTIST_DISPCLK_CNTL;
- uint32_t value = 0;
- uint32_t field = 0;
- struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-
- if (disp_clk->dfs_bypass_enabled && disp_clk->dfs_bypass_disp_clk)
- return disp_clk->dfs_bypass_disp_clk;
-
- /* Read the mmDENTIST_DISPCLK_CNTL to get the currently programmed
- DID DENTIST_DISPCLK_WDIVIDER.*/
- value = dm_read_reg(dc->ctx, addr);
- field = get_reg_field_value(
- value, DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER);
-
- /* Convert DENTIST_DISPCLK_WDIVIDER to actual divider*/
- target_div = dal_divider_range_get_divider(
- divider_ranges,
- DIVIDER_RANGE_MAX,
- field);
-
- if (target_div != INVALID_DIVIDER)
- /* Calculate the current DFS clock in KHz.
- Should be okay up to 42.9 THz before overflowing.*/
- disp_clock = (DIVIDER_RANGE_SCALE_FACTOR
- * disp_clk->dentist_vco_freq_khz) / target_div;
- return disp_clock;
-}
-
-static void set_clock_state(
- struct display_clock *dc,
- struct display_clock_state clk_state)
-{
- struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-
- disp_clk->clock_state = clk_state;
-}
-static struct display_clock_state get_clock_state(
- struct display_clock *dc)
-{
- struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-
- return disp_clk->clock_state;
-}
-
static enum clocks_state get_min_clocks_state(struct display_clock *dc)
{
struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
@@ -818,11 +396,6 @@ static bool display_clock_integrated_info_construct(
return true;
}
-static uint32_t get_dfs_bypass_threshold(struct display_clock *dc)
-{
- return DCE80_DFS_BYPASS_THRESHOLD_KHZ;
-}
-
static void destroy(struct display_clock **dc)
{
struct display_clock_dce80 *disp_clk;
@@ -833,32 +406,34 @@ static void destroy(struct display_clock **dc)
}
static const struct display_clock_funcs funcs = {
- .calculate_min_clock = calculate_min_clock,
.destroy = destroy,
- .get_clock = get_clock,
- .get_clock_state = get_clock_state,
- .get_dfs_bypass_threshold = get_dfs_bypass_threshold,
.get_dp_ref_clk_frequency = get_dp_ref_clk_frequency,
.get_min_clocks_state = get_min_clocks_state,
.get_required_clocks_state = get_required_clocks_state,
- .get_validation_clock = get_validation_clock,
.set_clock = set_clock,
- .set_clock_state = set_clock_state,
- .set_dp_ref_clock_source =
- dal_display_clock_base_set_dp_ref_clock_source,
.set_min_clocks_state = set_min_clocks_state,
- .store_max_clocks_state = store_max_clocks_state,
- .validate = validate,
+ .store_max_clocks_state = store_max_clocks_state
};
-static bool display_clock_construct(
- struct dc_context *ctx,
- struct display_clock_dce80 *disp_clk)
+
+struct display_clock *dal_display_clock_dce80_create(
+ struct dc_context *ctx)
{
- struct display_clock *dc_base = &disp_clk->disp_clk;
+ struct display_clock_dce80 *disp_clk;
+ struct display_clock *dc_base;
- if (!dal_display_clock_construct_base(dc_base, ctx))
- return false;
+ disp_clk = dm_alloc(sizeof(struct display_clock_dce80));
+
+ if (disp_clk == NULL)
+ return NULL;
+
+ dc_base = &disp_clk->disp_clk;
+
+ dc_base->ctx = ctx;
+ dc_base->id = CLOCK_SOURCE_ID_DCPLL;
+ dc_base->min_display_clk_threshold_khz = 0;
+
+ dc_base->cur_min_clks_state = CLOCKS_STATE_INVALID;
dc_base->funcs = &funcs;
/*
@@ -912,21 +487,6 @@ static bool display_clock_construct(
DIVIDER_RANGE_03_STEP_SIZE,
DIVIDER_RANGE_03_BASE_DIVIDER_ID,
DIVIDER_RANGE_MAX_DIVIDER_ID);
- return true;
-}
-
-struct display_clock *dal_display_clock_dce80_create(
- struct dc_context *ctx)
-{
- struct display_clock_dce80 *disp_clk;
-
- disp_clk = dm_alloc(sizeof(struct display_clock_dce80));
-
- if (disp_clk == NULL)
- return NULL;
-
- if (display_clock_construct(ctx, disp_clk))
- return &disp_clk->disp_clk;
dm_free(disp_clk);
return NULL;
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h
index 944dd0380413..c675f1e30870 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h
@@ -48,7 +48,6 @@ struct display_clock_dce80 {
* This is basically "Crystal Frequency In KHz" (XTALIN) frequency */
uint32_t dfs_bypass_disp_clk;
bool use_max_disp_clk;
- struct display_clock_state clock_state;
};
struct display_clock *dal_display_clock_dce80_create(
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/display_clock.c b/drivers/gpu/drm/amd/display/dc/gpu/display_clock.c
index bcc0a5132600..73d982732a67 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/display_clock.c
+++ b/drivers/gpu/drm/amd/display/dc/gpu/display_clock.c
@@ -26,49 +26,6 @@
#include "dm_services.h"
#include "display_clock.h"
-void dal_display_clock_base_set_dp_ref_clock_source(
- struct display_clock *disp_clk,
- enum clock_source_id clk_src)
-{/*must be implemented in derived*/
-
-}
-
-void dal_display_clock_base_set_clock_state(struct display_clock *disp_clk,
- struct display_clock_state clk_state)
-{
- /*Implemented only in DCE81*/
-}
-struct display_clock_state dal_display_clock_base_get_clock_state(
- struct display_clock *disp_clk)
-{
- /*Implemented only in DCE81*/
- struct display_clock_state state = {0};
- return state;
-}
-uint32_t dal_display_clock_base_get_dfs_bypass_threshold(
- struct display_clock *disp_clk)
-{
- /*Implemented only in DCE81*/
- return 0;
-}
-
-bool dal_display_clock_construct_base(
- struct display_clock *base,
- struct dc_context *ctx)
-{
- base->ctx = ctx;
- base->id = CLOCK_SOURCE_ID_DCPLL;
- base->min_display_clk_threshold_khz = 0;
-
-/* Initially set current min clocks state to invalid since we
- * cannot make any assumption about PPLIB's initial state. This will be updated
- * by HWSS via SetMinClocksState() on first mode set prior to programming
- * state dependent clocks.*/
- base->cur_min_clks_state = CLOCKS_STATE_INVALID;
-
- return true;
-}
-
void dal_display_clock_destroy(struct display_clock **disp_clk)
{
if (!disp_clk || !*disp_clk) {
@@ -81,26 +38,6 @@ void dal_display_clock_destroy(struct display_clock **disp_clk)
*disp_clk = NULL;
}
-bool dal_display_clock_validate(
- struct display_clock *disp_clk,
- struct min_clock_params *params)
-{
- return disp_clk->funcs->validate(disp_clk, params);
-}
-
-uint32_t dal_display_clock_calculate_min_clock(
- struct display_clock *disp_clk,
- uint32_t path_num,
- struct min_clock_params *params)
-{
- return disp_clk->funcs->calculate_min_clock(disp_clk, path_num, params);
-}
-
-uint32_t dal_display_clock_get_validation_clock(struct display_clock *disp_clk)
-{
- return disp_clk->funcs->get_validation_clock(disp_clk);
-}
-
void dal_display_clock_set_clock(
struct display_clock *disp_clk,
uint32_t requested_clock_khz)
@@ -108,11 +45,6 @@ void dal_display_clock_set_clock(
disp_clk->funcs->set_clock(disp_clk, requested_clock_khz);
}
-uint32_t dal_display_clock_get_clock(struct display_clock *disp_clk)
-{
- return disp_clk->funcs->get_clock(disp_clk);
-}
-
bool dal_display_clock_get_min_clocks_state(
struct display_clock *disp_clk,
enum clocks_state *clocks_state)
@@ -154,35 +86,6 @@ uint32_t dal_display_clock_get_dp_ref_clk_frequency(
return disp_clk->funcs->get_dp_ref_clk_frequency(disp_clk);
}
-/*the second parameter of "switchreferenceclock" is
- * a dummy argument for all pre dce 6.0 versions*/
-
-void dal_display_clock_switch_reference_clock(
- struct display_clock *disp_clk,
- bool use_external_ref_clk,
- uint32_t requested_clk_khz)
-{
- /* TODO: requires Asic Control*/
- /*
- struct ac_pixel_clk_params params;
- struct asic_control *ac =
- dal_adapter_service_get_asic_control(disp_clk->as);
- dc_service_memset(¶ms, 0, sizeof(struct ac_pixel_clk_params));
-
- params.tgt_pixel_clk_khz = requested_clk_khz;
- params.flags.SET_EXTERNAL_REF_DIV_SRC = use_external_ref_clk;
- params.pll_id = disp_clk->id;
- dal_asic_control_program_display_engine_pll(ac, ¶ms);
- */
-}
-
-void dal_display_clock_set_dp_ref_clock_source(
- struct display_clock *disp_clk,
- enum clock_source_id clk_src)
-{
- disp_clk->funcs->set_dp_ref_clock_source(disp_clk, clk_src);
-}
-
void dal_display_clock_store_max_clocks_state(
struct display_clock *disp_clk,
enum clocks_state max_clocks_state)
@@ -190,28 +93,3 @@ void dal_display_clock_store_max_clocks_state(
disp_clk->funcs->store_max_clocks_state(disp_clk, max_clocks_state);
}
-void dal_display_clock_set_clock_state(
- struct display_clock *disp_clk,
- struct display_clock_state clk_state)
-{
- disp_clk->funcs->set_clock_state(disp_clk, clk_state);
-}
-
-struct display_clock_state dal_display_clock_get_clock_state(
- struct display_clock *disp_clk)
-{
- return disp_clk->funcs->get_clock_state(disp_clk);
-}
-
-uint32_t dal_display_clock_get_dfs_bypass_threshold(
- struct display_clock *disp_clk)
-{
- return disp_clk->funcs->get_dfs_bypass_threshold(disp_clk);
-}
-
-void dal_display_clock_invalid_clock_state(
- struct display_clock *disp_clk)
-{
- disp_clk->cur_min_clks_state = CLOCKS_STATE_INVALID;
-}
-
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/display_clock.h b/drivers/gpu/drm/amd/display/dc/gpu/display_clock.h
index 663580d18a09..4db8442e717a 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/display_clock.h
+++ b/drivers/gpu/drm/amd/display/dc/gpu/display_clock.h
@@ -30,14 +30,8 @@
struct display_clock_funcs {
void (*destroy)(struct display_clock **to_destroy);
- bool (*validate)(struct display_clock *disp_clk,
- struct min_clock_params *params);
- uint32_t (*calculate_min_clock)(struct display_clock *disp_clk,
- uint32_t path_num, struct min_clock_params *params);
- uint32_t (*get_validation_clock)(struct display_clock *disp_clk);
void (*set_clock)(struct display_clock *disp_clk,
uint32_t requested_clock_khz);
- uint32_t (*get_clock)(struct display_clock *disp_clk);
enum clocks_state (*get_min_clocks_state)(
struct display_clock *disp_clk);
enum clocks_state (*get_required_clocks_state)(
@@ -46,15 +40,8 @@ struct display_clock_funcs {
bool (*set_min_clocks_state)(struct display_clock *disp_clk,
enum clocks_state clocks_state);
uint32_t (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk);
- void (*set_dp_ref_clock_source)(struct display_clock *disp_clk,
- enum clock_source_id clk_src);
void (*store_max_clocks_state)(struct display_clock *disp_clk,
enum clocks_state max_clocks_state);
- void (*set_clock_state)(struct display_clock *disp_clk,
- struct display_clock_state clk_state);
- struct display_clock_state (*get_clock_state)(
- struct display_clock *disp_clk);
- uint32_t (*get_dfs_bypass_threshold)(struct display_clock *disp_clk);
};
@@ -66,21 +53,6 @@ struct display_clock {
enum clocks_state cur_min_clks_state;
};
-void dal_display_clock_base_set_dp_ref_clock_source(
- struct display_clock *disp_clk,
- enum clock_source_id clk_src);
-struct display_clock_state dal_display_clock_base_get_clock_state(
- struct display_clock *disp_clk);
-uint32_t dal_display_clock_base_get_dfs_bypass_threshold(
- struct display_clock *disp_clk);
-void dal_display_clock_base_set_clock_state(struct display_clock *disp_clk,
- struct display_clock_state clk_state);
-bool dal_display_clock_construct_base(
- struct display_clock *base,
- struct dc_context *ctx);
-
-uint32_t dal_display_clock_get_validation_clock(struct display_clock *disp_clk);
-
void dal_display_clock_store_max_clocks_state(
struct display_clock *disp_clk,
enum clocks_state max_clocks_state);
diff --git a/drivers/gpu/drm/amd/display/include/display_clock_interface.h b/drivers/gpu/drm/amd/display/include/display_clock_interface.h
index 2006fa21f54c..ef519a284e0f 100644
--- a/drivers/gpu/drm/amd/display/include/display_clock_interface.h
+++ b/drivers/gpu/drm/amd/display/include/display_clock_interface.h
@@ -30,60 +30,6 @@
#include "grph_object_defs.h"
#include "signal_types.h"
-/* Timing related information*/
-struct dc_timing_params {
- uint32_t INTERLACED:1;
- uint32_t HCOUNT_BY_TWO:1;
- uint32_t PIXEL_REPETITION:4; /*< values 1 to 10 supported*/
- uint32_t PREFETCH:1;
-
- uint32_t h_total;
- uint32_t h_addressable;
- uint32_t h_sync_width;
-};
-
-/* Scaling related information*/
-struct dc_scaling_params {
- uint32_t h_overscan_right;
- uint32_t h_overscan_left;
- uint32_t h_taps;
- uint32_t v_taps;
-};
-
-/* VScalerEfficiency */
-enum v_scaler_efficiency {
- V_SCALER_EFFICIENCY_LB36BPP = 0,
- V_SCALER_EFFICIENCY_LB30BPP = 1,
- V_SCALER_EFFICIENCY_LB24BPP = 2,
- V_SCALER_EFFICIENCY_LB18BPP = 3
-};
-
-/* Parameters required for minimum Engine
- * and minimum Display clock calculations*/
-struct min_clock_params {
- uint32_t id;
- uint32_t requested_pixel_clock; /* in KHz */
- uint32_t actual_pixel_clock; /* in KHz */
- struct view source_view;
- struct view dest_view;
- struct dc_timing_params timing_info;
- struct dc_scaling_params scaling_info;
- enum signal_type signal_type;
- enum dc_color_depth deep_color_depth;
- enum v_scaler_efficiency scaler_efficiency;
- bool line_buffer_prefetch_enabled;
-};
-
-/* Result of Minimum System and Display clock calculations.
- * Minimum System clock and Display clock, source and path to be used
- * for Display clock*/
-struct minimum_clocks_calculation_result {
- uint32_t min_sclk_khz;
- uint32_t min_dclk_khz;
- uint32_t min_mclk_khz;
- uint32_t min_deep_sleep_sclk;
-};
-
/* Enumeration of all clocks states */
enum clocks_state {
CLOCKS_STATE_INVALID = 0,
@@ -110,10 +56,6 @@ struct state_dependent_clocks {
uint32_t pixel_clk_khz;
};
-struct display_clock_state {
- uint32_t DFS_BYPASS_ACTIVE:1;
-};
-
struct display_clock;
struct display_clock *dal_display_clock_dce112_create(
@@ -126,18 +68,9 @@ struct display_clock *dal_display_clock_dce80_create(
struct dc_context *ctx);
void dal_display_clock_destroy(struct display_clock **to_destroy);
-bool dal_display_clock_validate(
- struct display_clock *disp_clk,
- struct min_clock_params *params);
-uint32_t dal_display_clock_calculate_min_clock(
- struct display_clock *disp_clk,
- uint32_t path_num,
- struct min_clock_params *params);
-uint32_t dal_display_clock_get_validation_clock(struct display_clock *disp_clk);
void dal_display_clock_set_clock(
struct display_clock *disp_clk,
uint32_t requested_clock_khz);
-uint32_t dal_display_clock_get_clock(struct display_clock *disp_clk);
bool dal_display_clock_get_min_clocks_state(
struct display_clock *disp_clk,
enum clocks_state *clocks_state);
@@ -150,26 +83,8 @@ bool dal_display_clock_set_min_clocks_state(
enum clocks_state clocks_state);
uint32_t dal_display_clock_get_dp_ref_clk_frequency(
struct display_clock *disp_clk);
-/*the second parameter of "switchreferenceclock" is
- * a dummy argument for all pre dce 6.0 versions*/
-void dal_display_clock_switch_reference_clock(
- struct display_clock *disp_clk,
- bool use_external_ref_clk,
- uint32_t requested_clock_khz);
-void dal_display_clock_set_dp_ref_clock_source(
- struct display_clock *disp_clk,
- enum clock_source_id clk_src);
void dal_display_clock_store_max_clocks_state(
struct display_clock *disp_clk,
enum clocks_state max_clocks_state);
-void dal_display_clock_set_clock_state(
- struct display_clock *disp_clk,
- struct display_clock_state clk_state);
-struct display_clock_state dal_display_clock_get_clock_state(
- struct display_clock *disp_clk);
-uint32_t dal_display_clock_get_dfs_bypass_threshold(
- struct display_clock *disp_clk);
-void dal_display_clock_invalid_clock_state(
- struct display_clock *disp_clk);
#endif /* __DISPLAY_CLOCK_INTERFACE_H__ */
--
2.9.3
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 03/12] drm/amd/display: restyle display clock calls part 1
[not found] ` <20161206183538.11584-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2016-12-06 18:35 ` [PATCH 01/12] drm/amd/display: Add missing GRPH register definition Harry Wentland
2016-12-06 18:35 ` [PATCH 02/12] drm/amd/display: remove dead display clock code Harry Wentland
@ 2016-12-06 18:35 ` Harry Wentland
2016-12-06 18:35 ` [PATCH 04/12] drm/amd/display: restyle display clock calls part 2 Harry Wentland
` (9 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Harry Wentland @ 2016-12-06 18:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Change-Id: I3e65c94ea4c59ba7bc802995ad2210eeffc552e3
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +-
.../drm/amd/display/dc/dce100/dce100_resource.c | 2 +-
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 48 ++++------------------
.../drm/amd/display/dc/dce110/dce110_resource.c | 2 +-
.../drm/amd/display/dc/dce112/dce112_resource.c | 2 +-
.../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 2 +-
.../display/dc/gpu/dce112/display_clock_dce112.c | 1 -
.../display/dc/gpu/dce112/display_clock_dce112.h | 1 -
drivers/gpu/drm/amd/display/dc/gpu/display_clock.c | 20 ---------
drivers/gpu/drm/amd/display/dc/gpu/display_clock.h | 30 --------------
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 -
.../amd/display/include/display_clock_interface.h | 35 ++++++++++++----
12 files changed, 42 insertions(+), 107 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 424a7d4b8731..70dc70685471 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1224,7 +1224,9 @@ bool dc_pre_update_surfaces_to_target(
if (prev_disp_clk < context->bw_results.dispclk_khz) {
pplib_apply_display_requirements(core_dc, context,
&context->pp_display_cfg);
- core_dc->hwss.set_display_clock(context);
+ context->res_ctx.pool->display_clock->funcs->set_clock(
+ context->res_ctx.pool->display_clock,
+ context->bw_results.dispclk_khz * 115 / 100);
core_dc->current_context->bw_results.dispclk_khz =
context->bw_results.dispclk_khz;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 9ace6d1cca79..8f18a9403525 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -984,7 +984,7 @@ static bool construct(
dce110_resource_convert_clock_state_pp_to_dc(
static_clk_info.max_clocks_state);
- dal_display_clock_store_max_clocks_state(
+ pool->base.display_clock->funcs->store_max_clocks_state(
pool->base.display_clock, max_clocks_state);
}
{
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 1a682996b531..16ee49dba97b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -497,8 +497,8 @@ static void build_audio_output(
if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
audio_output->pll_info.dp_dto_source_clock_in_khz =
- dal_display_clock_get_dp_ref_clk_frequency(
- pipe_ctx->dis_clk);
+ pipe_ctx->dis_clk->funcs->get_dp_ref_clk_frequency(
+ pipe_ctx->dis_clk);
}
audio_output->pll_info.feed_back_divider =
@@ -788,39 +788,6 @@ void dce110_enable_accelerated_mode(struct core_dc *dc)
bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
}
-/**
- * Call display_engine_clock_dce80 to perform the Dclk programming.
- */
-void dce110_set_display_clock(struct validate_context *context)
-{
- /* Program the display engine clock.
- * Check DFS bypass mode support or not. DFSbypass feature is only when
- * BIOS GPU info table reports support. */
-
- if (/*dal_adapter_service_is_dfs_bypass_enabled()*/ false) {
- /*TODO: set_display_clock_dfs_bypass(
- hws,
- path_set,
- context->res_ctx.pool->display_clock,
- context->res_ctx.min_clocks.min_dclk_khz);*/
- } else {
- /*
- * TODO: need to either port work around from DAL2 function
- * getActualRequiredDisplayClock or program displayclock without
- * calling vbios. Currently temporily work
- * around by increasing the displclk by 15 percent
- */
- dal_display_clock_set_clock(
- context->res_ctx.pool->display_clock,
- context->bw_results.dispclk_khz * 115 / 100);
- }
-
-
- /* TODO: When changing display engine clock, DMCU WaitLoop must be
- * reconfigured in order to maintain the same delays within DMCU
- * programming sequences. */
-}
-
static uint32_t compute_pstate_blackout_duration(
struct bw_fixed blackout_duration,
const struct core_stream *stream)
@@ -1267,8 +1234,10 @@ enum dc_status dce110_apply_ctx_to_hw(
apply_min_clocks(dc, context, &clocks_state, true);
if (context->bw_results.dispclk_khz
- > dc->current_context->bw_results.dispclk_khz)
- dc->hwss.set_display_clock(context);
+ > dc->current_context->bw_results.dispclk_khz)
+ context->res_ctx.pool->display_clock->funcs->set_clock(
+ context->res_ctx.pool->display_clock,
+ context->bw_results.dispclk_khz * 115 / 100);
for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx_old =
@@ -1738,7 +1707,9 @@ static void dce110_set_bandwidth(struct core_dc *dc)
program_wm_for_pipe(dc, pipe_ctx, dc->current_context);
}
- dc->hwss.set_display_clock(dc->current_context);
+ dc->current_context->res_ctx.pool->display_clock->funcs->set_clock(
+ dc->current_context->res_ctx.pool->display_clock,
+ dc->current_context->bw_results.dispclk_khz * 115 / 100);
}
static void dce110_program_front_end_for_pipe(
@@ -1959,7 +1930,6 @@ static const struct hw_sequencer_funcs dce110_funcs = {
.enable_display_power_gating = dce110_enable_display_power_gating,
.power_down_front_end = dce110_power_down_fe,
.pipe_control_lock = dce_pipe_control_lock,
- .set_display_clock = dce110_set_display_clock,
.set_displaymarks = dce110_set_displaymarks,
.increase_watermarks_for_pipe = dce110_increase_watermarks_for_pipe,
.set_bandwidth = dce110_set_bandwidth,
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index cac3dc425039..a63112b2bd36 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -1315,7 +1315,7 @@ static bool construct(
dce110_resource_convert_clock_state_pp_to_dc(
static_clk_info.max_clocks_state);
- dal_display_clock_store_max_clocks_state(
+ pool->base.display_clock->funcs->store_max_clocks_state(
pool->base.display_clock, max_clocks_state);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 4e3273c0fa91..70616019ae47 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -1315,7 +1315,7 @@ static bool construct(
dce110_resource_convert_clock_state_pp_to_dc(
static_clk_info.max_clocks_state);
- dal_display_clock_store_max_clocks_state(
+ pool->base.display_clock->funcs->store_max_clocks_state(
pool->base.display_clock, max_clocks_state);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 3b626b7883d4..dfff2bfff13d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -978,7 +978,7 @@ static bool construct(
dce80_resource_convert_clock_state_pp_to_dc(
static_clk_info.max_clocks_state);
- dal_display_clock_store_max_clocks_state(
+ pool->base.display_clock->funcs->store_max_clocks_state(
pool->base.display_clock, max_clocks_state);
}
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
index bf044260c0bb..665832b0718a 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
@@ -383,7 +383,6 @@ bool dal_display_clock_dce112_construct(
struct display_clock *dc_base = &dc112->disp_clk_base;
dc_base->ctx = ctx;
- dc_base->id = CLOCK_SOURCE_ID_DCPLL;
dc_base->min_display_clk_threshold_khz = 0;
dc_base->cur_min_clks_state = CLOCKS_STATE_INVALID;
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
index 5ab31185d29d..47a149709d91 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
@@ -32,7 +32,6 @@ struct display_clock_dce112 {
/* Max display block clocks state*/
enum clocks_state max_clks_state;
bool use_max_disp_clk;
- uint32_t crystal_freq_khz;
uint32_t dentist_vco_freq_khz;
/* Cache the status of DFS-bypass feature*/
bool dfs_bypass_enabled;
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/display_clock.c b/drivers/gpu/drm/amd/display/dc/gpu/display_clock.c
index 73d982732a67..c70c6b25892e 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/display_clock.c
+++ b/drivers/gpu/drm/amd/display/dc/gpu/display_clock.c
@@ -38,13 +38,6 @@ void dal_display_clock_destroy(struct display_clock **disp_clk)
*disp_clk = NULL;
}
-void dal_display_clock_set_clock(
- struct display_clock *disp_clk,
- uint32_t requested_clock_khz)
-{
- disp_clk->funcs->set_clock(disp_clk, requested_clock_khz);
-}
-
bool dal_display_clock_get_min_clocks_state(
struct display_clock *disp_clk,
enum clocks_state *clocks_state)
@@ -80,16 +73,3 @@ bool dal_display_clock_set_min_clocks_state(
return true;
}
-uint32_t dal_display_clock_get_dp_ref_clk_frequency(
- struct display_clock *disp_clk)
-{
- return disp_clk->funcs->get_dp_ref_clk_frequency(disp_clk);
-}
-
-void dal_display_clock_store_max_clocks_state(
- struct display_clock *disp_clk,
- enum clocks_state max_clocks_state)
-{
- disp_clk->funcs->store_max_clocks_state(disp_clk, max_clocks_state);
-}
-
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/display_clock.h b/drivers/gpu/drm/amd/display/dc/gpu/display_clock.h
index 4db8442e717a..68d2ab0500a6 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/display_clock.h
+++ b/drivers/gpu/drm/amd/display/dc/gpu/display_clock.h
@@ -28,34 +28,4 @@
#include "include/display_clock_interface.h"
-struct display_clock_funcs {
- void (*destroy)(struct display_clock **to_destroy);
- void (*set_clock)(struct display_clock *disp_clk,
- uint32_t requested_clock_khz);
- enum clocks_state (*get_min_clocks_state)(
- struct display_clock *disp_clk);
- enum clocks_state (*get_required_clocks_state)(
- struct display_clock *disp_clk,
- struct state_dependent_clocks *req_clocks);
- bool (*set_min_clocks_state)(struct display_clock *disp_clk,
- enum clocks_state clocks_state);
- uint32_t (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk);
- void (*store_max_clocks_state)(struct display_clock *disp_clk,
- enum clocks_state max_clocks_state);
-
-};
-
-struct display_clock {
- struct dc_context *ctx;
- const struct display_clock_funcs *funcs;
- uint32_t min_display_clk_threshold_khz;
- enum clock_source_id id;
-
- enum clocks_state cur_min_clks_state;
-};
-void dal_display_clock_store_max_clocks_state(
- struct display_clock *disp_clk,
- enum clocks_state max_clocks_state);
-
-
#endif /* __DAL_DISPLAY_CLOCK_H__*/
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 35a556dd9054..50d499cc01a4 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -132,8 +132,6 @@ struct hw_sequencer_funcs {
struct pipe_ctx *pipe_ctx,
struct validate_context *context);
- void (*set_display_clock)(struct validate_context *context);
-
void (*set_bandwidth)(struct core_dc *dc);
void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
diff --git a/drivers/gpu/drm/amd/display/include/display_clock_interface.h b/drivers/gpu/drm/amd/display/include/display_clock_interface.h
index ef519a284e0f..f49253714b1e 100644
--- a/drivers/gpu/drm/amd/display/include/display_clock_interface.h
+++ b/drivers/gpu/drm/amd/display/include/display_clock_interface.h
@@ -56,7 +56,31 @@ struct state_dependent_clocks {
uint32_t pixel_clk_khz;
};
-struct display_clock;
+struct display_clock {
+ struct dc_context *ctx;
+ const struct display_clock_funcs *funcs;
+ uint32_t min_display_clk_threshold_khz;
+ enum clock_source_id id;
+
+ enum clocks_state cur_min_clks_state;
+};
+
+struct display_clock_funcs {
+ void (*destroy)(struct display_clock **to_destroy);
+ void (*set_clock)(struct display_clock *disp_clk,
+ uint32_t requested_clock_khz);
+ enum clocks_state (*get_min_clocks_state)(
+ struct display_clock *disp_clk);
+ enum clocks_state (*get_required_clocks_state)(
+ struct display_clock *disp_clk,
+ struct state_dependent_clocks *req_clocks);
+ bool (*set_min_clocks_state)(struct display_clock *disp_clk,
+ enum clocks_state clocks_state);
+ uint32_t (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk);
+ void (*store_max_clocks_state)(struct display_clock *disp_clk,
+ enum clocks_state max_clocks_state);
+
+};
struct display_clock *dal_display_clock_dce112_create(
struct dc_context *ctx);
@@ -68,9 +92,7 @@ struct display_clock *dal_display_clock_dce80_create(
struct dc_context *ctx);
void dal_display_clock_destroy(struct display_clock **to_destroy);
-void dal_display_clock_set_clock(
- struct display_clock *disp_clk,
- uint32_t requested_clock_khz);
+
bool dal_display_clock_get_min_clocks_state(
struct display_clock *disp_clk,
enum clocks_state *clocks_state);
@@ -81,10 +103,5 @@ bool dal_display_clock_get_required_clocks_state(
bool dal_display_clock_set_min_clocks_state(
struct display_clock *disp_clk,
enum clocks_state clocks_state);
-uint32_t dal_display_clock_get_dp_ref_clk_frequency(
- struct display_clock *disp_clk);
-void dal_display_clock_store_max_clocks_state(
- struct display_clock *disp_clk,
- enum clocks_state max_clocks_state);
#endif /* __DISPLAY_CLOCK_INTERFACE_H__ */
--
2.9.3
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 04/12] drm/amd/display: restyle display clock calls part 2
[not found] ` <20161206183538.11584-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2016-12-06 18:35 ` [PATCH 03/12] drm/amd/display: restyle display clock calls part 1 Harry Wentland
@ 2016-12-06 18:35 ` Harry Wentland
2016-12-06 18:35 ` [PATCH 05/12] drm/amd/display: remove store clock state Harry Wentland
` (8 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Harry Wentland @ 2016-12-06 18:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Change-Id: I04b1cb799d049abea320b50eff14790772a5565d
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 11 ++--
.../drm/amd/display/dc/dce100/dce100_resource.c | 4 +-
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 13 ++--
.../drm/amd/display/dc/dce110/dce110_resource.c | 4 +-
.../drm/amd/display/dc/dce112/dce112_resource.c | 4 +-
.../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 4 +-
drivers/gpu/drm/amd/display/dc/gpu/Makefile | 2 +-
.../display/dc/gpu/dce110/display_clock_dce110.h | 2 +-
.../display/dc/gpu/dce112/display_clock_dce112.h | 2 +-
.../amd/display/dc/gpu/dce80/display_clock_dce80.h | 2 +-
drivers/gpu/drm/amd/display/dc/gpu/display_clock.c | 75 ----------------------
drivers/gpu/drm/amd/display/dc/gpu/display_clock.h | 31 ---------
.../amd/display/include/display_clock_interface.h | 11 ----
13 files changed, 30 insertions(+), 135 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/display/dc/gpu/display_clock.c
delete mode 100644 drivers/gpu/drm/amd/display/dc/gpu/display_clock.h
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 70a25546de1e..ab4efde2d030 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1223,12 +1223,13 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx)
if (link_settings.link_rate == max_link_rate) {
cur_min_clock_state = CLOCKS_STATE_INVALID;
- if (dal_display_clock_get_min_clocks_state(
- pipe_ctx->dis_clk, &cur_min_clock_state)) {
+ if (pipe_ctx->dis_clk->funcs->get_min_clocks_state) {
+ cur_min_clock_state =
+ pipe_ctx->dis_clk->funcs->get_min_clocks_state(
+ pipe_ctx->dis_clk);
if (cur_min_clock_state < CLOCKS_STATE_NOMINAL)
- dal_display_clock_set_min_clocks_state(
- pipe_ctx->dis_clk,
- CLOCKS_STATE_NOMINAL);
+ pipe_ctx->dis_clk->funcs->set_min_clocks_state(
+ pipe_ctx->dis_clk, CLOCKS_STATE_NOMINAL);
} else {
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 8f18a9403525..fa88eb163ab8 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -717,7 +717,9 @@ static void destruct(struct dce110_resource_pool *pool)
}
if (pool->base.display_clock != NULL)
- dal_display_clock_destroy(&pool->base.display_clock);
+ pool->base.display_clock->funcs->destroy(
+ &pool->base.display_clock);
+ pool->base.display_clock = NULL;
if (pool->base.irqs != NULL)
dal_irq_service_destroy(&pool->base.irqs);
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 16ee49dba97b..ca71509af74d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1099,9 +1099,11 @@ static void apply_min_clocks(
if (!pre_mode_set) {
/* set clock_state without verification */
- if (dal_display_clock_set_min_clocks_state(
- pipe_ctx->dis_clk, *clocks_state))
+ if (pipe_ctx->dis_clk->funcs->set_min_clocks_state) {
+ pipe_ctx->dis_clk->funcs->set_min_clocks_state(
+ pipe_ctx->dis_clk, *clocks_state);
return;
+ }
/* TODOFPGA */
}
@@ -1114,9 +1116,10 @@ static void apply_min_clocks(
req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths(
dc, context, true);
- if (dal_display_clock_get_required_clocks_state(
- pipe_ctx->dis_clk, &req_clocks, clocks_state)) {
- dal_display_clock_set_min_clocks_state(
+ if (pipe_ctx->dis_clk->funcs->get_required_clocks_state) {
+ *clocks_state = pipe_ctx->dis_clk->funcs->get_required_clocks_state(
+ pipe_ctx->dis_clk, &req_clocks);
+ pipe_ctx->dis_clk->funcs->set_min_clocks_state(
pipe_ctx->dis_clk, *clocks_state);
} else {
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index a63112b2bd36..6c713396e6ba 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -700,7 +700,9 @@ static void destruct(struct dce110_resource_pool *pool)
}
if (pool->base.display_clock != NULL) {
- dal_display_clock_destroy(&pool->base.display_clock);
+ pool->base.display_clock->funcs->destroy(
+ &pool->base.display_clock);
+ pool->base.display_clock = NULL;
}
if (pool->base.irqs != NULL) {
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 70616019ae47..8792c4ed6e65 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -734,7 +734,9 @@ static void destruct(struct dce110_resource_pool *pool)
}
if (pool->base.display_clock != NULL) {
- dal_display_clock_destroy(&pool->base.display_clock);
+ pool->base.display_clock->funcs->destroy(
+ &pool->base.display_clock);
+ pool->base.display_clock = NULL;
}
if (pool->base.irqs != NULL) {
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index dfff2bfff13d..1e829f805d42 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -657,7 +657,9 @@ static void destruct(struct dce110_resource_pool *pool)
}
if (pool->base.display_clock != NULL) {
- dal_display_clock_destroy(&pool->base.display_clock);
+ pool->base.display_clock->funcs->destroy(
+ &pool->base.display_clock);
+ pool->base.display_clock = NULL;
}
if (pool->base.irqs != NULL) {
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/Makefile b/drivers/gpu/drm/amd/display/dc/gpu/Makefile
index fd17af1ce88e..0b99a7474950 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/gpu/Makefile
@@ -3,7 +3,7 @@
# It provides the control and status of HW adapter resources,
# that are global for the ASIC and sharable between pipes.
-GPU = display_clock.o divider_range.o
+GPU = divider_range.o
AMD_DAL_GPU = $(addprefix $(AMDDALPATH)/dc/gpu/,$(GPU))
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h
index 88b4bdd75e56..703cd656b5b0 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h
@@ -25,7 +25,7 @@
#ifndef __DAL_DISPLAY_CLOCK_DCE110_H__
#define __DAL_DISPLAY_CLOCK_DCE110_H__
-#include "gpu/display_clock.h"
+#include "display_clock_interface.h"
struct display_clock_dce110 {
struct display_clock disp_clk_base;
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
index 47a149709d91..34afff9a00bc 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
@@ -25,7 +25,7 @@
#ifndef __DAL_DISPLAY_CLOCK_DCE112_H__
#define __DAL_DISPLAY_CLOCK_DCE112_H__
-#include "gpu/display_clock.h"
+#include "display_clock_interface.h"
struct display_clock_dce112 {
struct display_clock disp_clk_base;
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h
index c675f1e30870..273a5d902840 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h
@@ -25,7 +25,7 @@
#ifndef __DAL_DISPLAY_CLOCK_DCE80_H__
#define __DAL_DISPLAY_CLOCK_DCE80_H__
-#include "gpu/display_clock.h"
+#include "display_clock_interface.h"
struct display_clock_dce80 {
struct display_clock disp_clk;
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/display_clock.c b/drivers/gpu/drm/amd/display/dc/gpu/display_clock.c
deleted file mode 100644
index c70c6b25892e..000000000000
--- a/drivers/gpu/drm/amd/display/dc/gpu/display_clock.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "display_clock.h"
-
-void dal_display_clock_destroy(struct display_clock **disp_clk)
-{
- if (!disp_clk || !*disp_clk) {
- BREAK_TO_DEBUGGER();
- return;
- }
-
- (*disp_clk)->funcs->destroy(disp_clk);
-
- *disp_clk = NULL;
-}
-
-bool dal_display_clock_get_min_clocks_state(
- struct display_clock *disp_clk,
- enum clocks_state *clocks_state)
-{
- if (!disp_clk->funcs->get_min_clocks_state)
- return false;
-
- *clocks_state = disp_clk->funcs->get_min_clocks_state(disp_clk);
- return true;
-}
-
-bool dal_display_clock_get_required_clocks_state(
- struct display_clock *disp_clk,
- struct state_dependent_clocks *req_clocks,
- enum clocks_state *clocks_state)
-{
- if (!disp_clk->funcs->get_required_clocks_state)
- return false;
-
- *clocks_state = disp_clk->funcs->get_required_clocks_state(
- disp_clk, req_clocks);
- return true;
-}
-
-bool dal_display_clock_set_min_clocks_state(
- struct display_clock *disp_clk,
- enum clocks_state clocks_state)
-{
- if (!disp_clk->funcs->set_min_clocks_state)
- return false;
-
- disp_clk->funcs->set_min_clocks_state(disp_clk, clocks_state);
- return true;
-}
-
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/display_clock.h b/drivers/gpu/drm/amd/display/dc/gpu/display_clock.h
deleted file mode 100644
index 68d2ab0500a6..000000000000
--- a/drivers/gpu/drm/amd/display/dc/gpu/display_clock.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_DISPLAY_CLOCK_H__
-#define __DAL_DISPLAY_CLOCK_H__
-
-#include "include/display_clock_interface.h"
-
-#endif /* __DAL_DISPLAY_CLOCK_H__*/
diff --git a/drivers/gpu/drm/amd/display/include/display_clock_interface.h b/drivers/gpu/drm/amd/display/include/display_clock_interface.h
index f49253714b1e..a46ceebe2452 100644
--- a/drivers/gpu/drm/amd/display/include/display_clock_interface.h
+++ b/drivers/gpu/drm/amd/display/include/display_clock_interface.h
@@ -93,15 +93,4 @@ struct display_clock *dal_display_clock_dce80_create(
void dal_display_clock_destroy(struct display_clock **to_destroy);
-bool dal_display_clock_get_min_clocks_state(
- struct display_clock *disp_clk,
- enum clocks_state *clocks_state);
-bool dal_display_clock_get_required_clocks_state(
- struct display_clock *disp_clk,
- struct state_dependent_clocks *req_clocks,
- enum clocks_state *clocks_state);
-bool dal_display_clock_set_min_clocks_state(
- struct display_clock *disp_clk,
- enum clocks_state clocks_state);
-
#endif /* __DISPLAY_CLOCK_INTERFACE_H__ */
--
2.9.3
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 05/12] drm/amd/display: remove store clock state
[not found] ` <20161206183538.11584-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2016-12-06 18:35 ` [PATCH 04/12] drm/amd/display: restyle display clock calls part 2 Harry Wentland
@ 2016-12-06 18:35 ` Harry Wentland
2016-12-06 18:35 ` [PATCH 06/12] drm/amd/display: remove get_min_clocks_state Harry Wentland
` (7 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Harry Wentland @ 2016-12-06 18:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Change-Id: Id719232abef18c4e410515c0723118f0f198aef9
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
.../drm/amd/display/dc/dce100/dce100_resource.c | 8 +---
.../drm/amd/display/dc/dce110/dce110_resource.c | 8 +---
.../drm/amd/display/dc/dce112/dce112_resource.c | 8 +---
.../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 8 +---
.../display/dc/gpu/dce110/display_clock_dce110.c | 47 +++-----------------
.../display/dc/gpu/dce110/display_clock_dce110.h | 2 -
.../display/dc/gpu/dce112/display_clock_dce112.c | 50 +++-------------------
.../display/dc/gpu/dce112/display_clock_dce112.h | 2 -
.../amd/display/dc/gpu/dce80/display_clock_dce80.c | 50 +++-------------------
.../amd/display/dc/gpu/dce80/display_clock_dce80.h | 2 -
.../amd/display/include/display_clock_interface.h | 5 +--
11 files changed, 29 insertions(+), 161 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index fa88eb163ab8..446f50bb4e0a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -981,14 +981,10 @@ static bool construct(
/* get static clock information for PPLIB or firmware, save
* max_clock_state
*/
- if (dm_pp_get_static_clocks(ctx, &static_clk_info)) {
- enum clocks_state max_clocks_state =
+ if (dm_pp_get_static_clocks(ctx, &static_clk_info))
+ pool->base.display_clock->max_clks_state =
dce110_resource_convert_clock_state_pp_to_dc(
static_clk_info.max_clocks_state);
-
- pool->base.display_clock->funcs->store_max_clocks_state(
- pool->base.display_clock, max_clocks_state);
- }
{
struct irq_service_init_data init_data;
init_data.ctx = dc->ctx;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 6c713396e6ba..d5d888bdf882 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -1312,15 +1312,11 @@ static bool construct(
/* get static clock information for PPLIB or firmware, save
* max_clock_state
*/
- if (dm_pp_get_static_clocks(ctx, &static_clk_info)) {
- enum clocks_state max_clocks_state =
+ if (dm_pp_get_static_clocks(ctx, &static_clk_info))
+ pool->base.display_clock->max_clks_state =
dce110_resource_convert_clock_state_pp_to_dc(
static_clk_info.max_clocks_state);
- pool->base.display_clock->funcs->store_max_clocks_state(
- pool->base.display_clock, max_clocks_state);
- }
-
{
struct irq_service_init_data init_data;
init_data.ctx = dc->ctx;
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 8792c4ed6e65..9903c9a4b8a1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -1312,15 +1312,11 @@ static bool construct(
/* get static clock information for PPLIB or firmware, save
* max_clock_state
*/
- if (dm_pp_get_static_clocks(ctx, &static_clk_info)) {
- enum clocks_state max_clocks_state =
+ if (dm_pp_get_static_clocks(ctx, &static_clk_info))
+ pool->base.display_clock->max_clks_state =
dce110_resource_convert_clock_state_pp_to_dc(
static_clk_info.max_clocks_state);
- pool->base.display_clock->funcs->store_max_clocks_state(
- pool->base.display_clock, max_clocks_state);
- }
-
{
struct irq_service_init_data init_data;
init_data.ctx = dc->ctx;
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 1e829f805d42..51721d10c811 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -975,15 +975,11 @@ static bool construct(
}
- if (dm_pp_get_static_clocks(ctx, &static_clk_info)) {
- enum clocks_state max_clocks_state =
+ if (dm_pp_get_static_clocks(ctx, &static_clk_info))
+ pool->base.display_clock->max_clks_state =
dce80_resource_convert_clock_state_pp_to_dc(
static_clk_info.max_clocks_state);
- pool->base.display_clock->funcs->store_max_clocks_state(
- pool->base.display_clock, max_clocks_state);
- }
-
{
struct irq_service_init_data init_data;
init_data.ctx = dc->ctx;
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c
index cc13afa326ad..ad7ebc1b434c 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c
@@ -103,38 +103,6 @@ static struct divider_range divider_ranges[DIVIDER_RANGE_MAX];
* static functions
*****************************************************************************/
-/*
- * store_max_clocks_state
- *
- * @brief
- * Cache the clock state
- *
- * @param
- * struct display_clock *base - [out] cach the state in this structure
- * enum clocks_state max_clocks_state - [in] state to be stored
- */
-static void store_max_clocks_state(
- struct display_clock *base,
- enum clocks_state max_clocks_state)
-{
- struct display_clock_dce110 *dc = DCLCK110_FROM_BASE(base);
-
- switch (max_clocks_state) {
- case CLOCKS_STATE_LOW:
- case CLOCKS_STATE_NOMINAL:
- case CLOCKS_STATE_PERFORMANCE:
- case CLOCKS_STATE_ULTRA_LOW:
- dc->max_clks_state = max_clocks_state;
- break;
-
- case CLOCKS_STATE_INVALID:
- default:
- /*Invalid Clocks State!*/
- ASSERT_CRITICAL(false);
- break;
- }
-}
-
static enum clocks_state get_min_clocks_state(struct display_clock *base)
{
return base->cur_min_clks_state;
@@ -148,7 +116,7 @@ static bool set_min_clocks_state(
struct dm_pp_power_level_change_request level_change_req = {
DM_PP_POWER_LEVEL_INVALID};
- if (clocks_state > dc->max_clks_state) {
+ if (clocks_state > base->max_clks_state) {
/*Requested state exceeds max supported state.*/
dm_logger_write(base->ctx->logger, LOG_WARNING,
"Requested state exceeds max supported state");
@@ -349,7 +317,7 @@ static enum clocks_state get_required_clocks_state(
{
int32_t i;
struct display_clock_dce110 *disp_clk = DCLCK110_FROM_BASE(dc);
- enum clocks_state low_req_clk = disp_clk->max_clks_state;
+ enum clocks_state low_req_clk = dc->max_clks_state;
if (!req_clocks) {
/* NULL pointer*/
@@ -363,7 +331,7 @@ static enum clocks_state get_required_clocks_state(
* lowest RequiredState with the lowest state that satisfies
* all required clocks
*/
- for (i = disp_clk->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) {
+ for (i = dc->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) {
if ((req_clocks->display_clk_khz <=
max_clks_by_state[i].display_clk_khz) &&
(req_clocks->pixel_clk_khz <=
@@ -433,7 +401,7 @@ static void set_clock(
base->min_display_clk_threshold_khz);
pxl_clk_params.target_pixel_clock = requested_clk_khz;
- pxl_clk_params.pll_id = base->id;
+ pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
bp->funcs->program_display_engine_pll(bp, &pxl_clk_params);
@@ -459,8 +427,7 @@ static const struct display_clock_funcs funcs = {
.get_min_clocks_state = get_min_clocks_state,
.get_required_clocks_state = get_required_clocks_state,
.set_clock = set_clock,
- .set_min_clocks_state = set_min_clocks_state,
- .store_max_clocks_state = store_max_clocks_state
+ .set_min_clocks_state = set_min_clocks_state
};
static bool dal_display_clock_dce110_construct(
@@ -471,7 +438,6 @@ static bool dal_display_clock_dce110_construct(
struct dc_bios *bp = ctx->dc_bios;
dc_base->ctx = ctx;
- dc_base->id = CLOCK_SOURCE_ID_DCPLL;
dc_base->min_display_clk_threshold_khz = 0;
dc_base->cur_min_clks_state = CLOCKS_STATE_INVALID;
@@ -488,12 +454,11 @@ static bool dal_display_clock_dce110_construct(
dc110->gpu_pll_ss_divider = 1000;
dc110->ss_on_gpu_pll = false;
- dc_base->id = CLOCK_SOURCE_ID_DFS;
/* Initially set max clocks state to nominal. This should be updated by
* via a pplib call to DAL IRI eventually calling a
* DisplayEngineClock_Dce110::StoreMaxClocksState(). This call will come in
* on PPLIB init. This is from DCE5x. in case HW wants to use mixed method.*/
- dc110->max_clks_state = CLOCKS_STATE_NOMINAL;
+ dc_base->max_clks_state = CLOCKS_STATE_NOMINAL;
dal_divider_range_construct(
÷r_ranges[DIVIDER_RANGE_01],
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h
index 703cd656b5b0..50b51c41b0d9 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h
@@ -29,8 +29,6 @@
struct display_clock_dce110 {
struct display_clock disp_clk_base;
- /* Max display block clocks state*/
- enum clocks_state max_clks_state;
bool use_max_disp_clk;
uint32_t dentist_vco_freq_khz;
/* Cache the status of DFS-bypass feature*/
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
index 665832b0718a..d8c8d8a1e2b3 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
@@ -72,41 +72,6 @@ enum divider_range_step_size {
static struct divider_range divider_ranges[DIVIDER_RANGE_MAX];
#define dce112_DFS_BYPASS_THRESHOLD_KHZ 400000
-/*****************************************************************************
- * static functions
- *****************************************************************************/
-
-/*
- * store_max_clocks_state
- *
- * @brief
- * Cache the clock state
- *
- * @param
- * struct display_clock *base - [out] cach the state in this structure
- * enum clocks_state max_clocks_state - [in] state to be stored
- */
-void dispclk_dce112_store_max_clocks_state(
- struct display_clock *base,
- enum clocks_state max_clocks_state)
-{
- struct display_clock_dce112 *dc = DCLCK112_FROM_BASE(base);
-
- switch (max_clocks_state) {
- case CLOCKS_STATE_LOW:
- case CLOCKS_STATE_NOMINAL:
- case CLOCKS_STATE_PERFORMANCE:
- case CLOCKS_STATE_ULTRA_LOW:
- dc->max_clks_state = max_clocks_state;
- break;
-
- case CLOCKS_STATE_INVALID:
- default:
- /*Invalid Clocks State!*/
- ASSERT_CRITICAL(false);
- break;
- }
-}
enum clocks_state dispclk_dce112_get_min_clocks_state(
struct display_clock *base)
@@ -122,7 +87,7 @@ bool dispclk_dce112_set_min_clocks_state(
struct dm_pp_power_level_change_request level_change_req = {
DM_PP_POWER_LEVEL_INVALID};
- if (clocks_state > dc->max_clks_state) {
+ if (clocks_state > base->max_clks_state) {
/*Requested state exceeds max supported state.*/
dm_logger_write(base->ctx->logger, LOG_WARNING,
"Requested state exceeds max supported state");
@@ -302,7 +267,7 @@ enum clocks_state dispclk_dce112_get_required_clocks_state(
{
int32_t i;
struct display_clock_dce112 *disp_clk = DCLCK112_FROM_BASE(dc);
- enum clocks_state low_req_clk = disp_clk->max_clks_state;
+ enum clocks_state low_req_clk = dc->max_clks_state;
if (!req_clocks) {
/* NULL pointer*/
@@ -316,7 +281,7 @@ enum clocks_state dispclk_dce112_get_required_clocks_state(
* lowest RequiredState with the lowest state that satisfies
* all required clocks
*/
- for (i = disp_clk->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) {
+ for (i = dc->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) {
if ((req_clocks->display_clk_khz <=
(disp_clk->max_clks_by_state + i)->
display_clk_khz) &&
@@ -333,7 +298,6 @@ void dispclk_dce112_set_clock(
uint32_t requested_clk_khz)
{
struct bp_set_dce_clock_parameters dce_clk_params;
- struct display_clock_dce112 *dc = DCLCK112_FROM_BASE(base);
struct dc_bios *bp = base->ctx->dc_bios;
/* Prepare to program display clock*/
@@ -345,7 +309,7 @@ void dispclk_dce112_set_clock(
base->min_display_clk_threshold_khz);
dce_clk_params.target_clock_frequency = requested_clk_khz;
- dce_clk_params.pll_id = dc->disp_clk_base.id;
+ dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK;
bp->funcs->set_dce_clock(bp, &dce_clk_params);
@@ -372,8 +336,7 @@ static const struct display_clock_funcs funcs = {
.get_min_clocks_state = dispclk_dce112_get_min_clocks_state,
.get_required_clocks_state = dispclk_dce112_get_required_clocks_state,
.set_clock = dispclk_dce112_set_clock,
- .set_min_clocks_state = dispclk_dce112_set_min_clocks_state,
- .store_max_clocks_state = dispclk_dce112_store_max_clocks_state,
+ .set_min_clocks_state = dispclk_dce112_set_min_clocks_state
};
bool dal_display_clock_dce112_construct(
@@ -399,12 +362,11 @@ bool dal_display_clock_dce112_construct(
dc112->gpu_pll_ss_divider = 1000;
dc112->ss_on_gpu_pll = false;
- dc_base->id = CLOCK_SOURCE_ID_DFS;
/* Initially set max clocks state to nominal. This should be updated by
* via a pplib call to DAL IRI eventually calling a
* DisplayEngineClock_dce112::StoreMaxClocksState(). This call will come in
* on PPLIB init. This is from DCE5x. in case HW wants to use mixed method.*/
- dc112->max_clks_state = CLOCKS_STATE_NOMINAL;
+ dc_base->max_clks_state = CLOCKS_STATE_NOMINAL;
dc112->disp_clk_base.min_display_clk_threshold_khz =
(dc112->dentist_vco_freq_khz / 62);
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
index 34afff9a00bc..398af34720f7 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
@@ -29,8 +29,6 @@
struct display_clock_dce112 {
struct display_clock disp_clk_base;
- /* Max display block clocks state*/
- enum clocks_state max_clks_state;
bool use_max_disp_clk;
uint32_t dentist_vco_freq_khz;
/* Cache the status of DFS-bypass feature*/
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c
index 89ee8bd96979..b101f7de2d11 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c
@@ -95,28 +95,20 @@ static void set_clock(
uint32_t requested_clk_khz)
{
struct bp_pixel_clock_parameters pxl_clk_params;
- struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
struct dc_bios *bp = dc->ctx->dc_bios;
/* Prepare to program display clock*/
memset(&pxl_clk_params, 0, sizeof(pxl_clk_params));
pxl_clk_params.target_pixel_clock = requested_clk_khz;
- pxl_clk_params.pll_id = dc->id;
+ pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
bp->funcs->program_display_engine_pll(bp, &pxl_clk_params);
- if (disp_clk->dfs_bypass_enabled) {
-
- /* Cache the fixed display clock*/
- disp_clk->dfs_bypass_disp_clk =
- pxl_clk_params.dfs_bypass_display_clock;
- }
-
/* from power down, we need mark the clock state as ClocksStateNominal
* from HWReset, so when resume we will call pplib voltage regulator.*/
if (requested_clk_khz == 0)
- disp_clk->cur_min_clks_state = CLOCKS_STATE_NOMINAL;
+ dc->cur_min_clks_state = CLOCKS_STATE_NOMINAL;
}
static enum clocks_state get_min_clocks_state(struct display_clock *dc)
@@ -131,8 +123,7 @@ static enum clocks_state get_required_clocks_state
struct state_dependent_clocks *req_clocks)
{
int32_t i;
- struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
- enum clocks_state low_req_clk = disp_clk->max_clks_state;
+ enum clocks_state low_req_clk = dc->max_clks_state;
if (!req_clocks) {
/* NULL pointer*/
@@ -144,7 +135,7 @@ static enum clocks_state get_required_clocks_state
* lowest RequiredState with the lowest state that satisfies
* all required clocks
*/
- for (i = disp_clk->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) {
+ for (i = dc->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) {
if ((req_clocks->display_clk_khz <=
max_clks_by_state[i].display_clk_khz) &&
(req_clocks->pixel_clk_khz <=
@@ -158,12 +149,10 @@ static bool set_min_clocks_state(
struct display_clock *dc,
enum clocks_state clocks_state)
{
- struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-
struct dm_pp_power_level_change_request level_change_req = {
DM_PP_POWER_LEVEL_INVALID};
- if (clocks_state > disp_clk->max_clks_state) {
+ if (clocks_state > dc->max_clks_state) {
/*Requested state exceeds max supported state.*/
dm_logger_write(dc->ctx->logger, LOG_WARNING,
"Requested state exceeds max supported state");
@@ -271,28 +260,6 @@ static uint32_t get_dp_ref_clk_frequency(struct display_clock *dc)
return dp_ref_clk_khz;
}
-static void store_max_clocks_state(
- struct display_clock *dc,
- enum clocks_state max_clocks_state)
-{
- struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-
- switch (max_clocks_state) {
- case CLOCKS_STATE_LOW:
- case CLOCKS_STATE_NOMINAL:
- case CLOCKS_STATE_PERFORMANCE:
- case CLOCKS_STATE_ULTRA_LOW:
- disp_clk->max_clks_state = max_clocks_state;
- break;
-
- case CLOCKS_STATE_INVALID:
- default:
- /*Invalid Clocks State!*/
- BREAK_TO_DEBUGGER();
- break;
- }
-}
-
static void display_clock_ss_construct(
struct display_clock_dce80 *disp_clk)
{
@@ -411,8 +378,7 @@ static const struct display_clock_funcs funcs = {
.get_min_clocks_state = get_min_clocks_state,
.get_required_clocks_state = get_required_clocks_state,
.set_clock = set_clock,
- .set_min_clocks_state = set_min_clocks_state,
- .store_max_clocks_state = store_max_clocks_state
+ .set_min_clocks_state = set_min_clocks_state
};
@@ -430,7 +396,6 @@ struct display_clock *dal_display_clock_dce80_create(
dc_base = &disp_clk->disp_clk;
dc_base->ctx = ctx;
- dc_base->id = CLOCK_SOURCE_ID_DCPLL;
dc_base->min_display_clk_threshold_khz = 0;
dc_base->cur_min_clks_state = CLOCKS_STATE_INVALID;
@@ -450,12 +415,11 @@ struct display_clock *dal_display_clock_dce80_create(
disp_clk->dfs_bypass_disp_clk = 0;
disp_clk->use_max_disp_clk = true;/* false will hang the system! */
- disp_clk->disp_clk.id = CLOCK_SOURCE_ID_DFS;
/* Initially set max clocks state to nominal. This should be updated by
* via a pplib call to DAL IRI eventually calling a
* DisplayEngineClock_Dce50::StoreMaxClocksState(). This call will come in
* on PPLIB init. This is from DCE5x. in case HW wants to use mixed method.*/
- disp_clk->max_clks_state = CLOCKS_STATE_NOMINAL;
+ dc_base->max_clks_state = CLOCKS_STATE_NOMINAL;
/* Initially set current min clocks state to invalid since we
* cannot make any assumption about PPLIB's initial state. This will be updated
* by HWSS via SetMinClocksState() on first mode set prior to programming
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h
index 273a5d902840..1193398b5cea 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h
@@ -37,8 +37,6 @@ struct display_clock_dce80 {
uint32_t gpu_pll_ss_divider;
/* Flag for Enabled SS on GPU PLL*/
bool ss_on_gpu_pll;
- /* Max display block clocks state*/
- enum clocks_state max_clks_state;
/* Current minimum display block clocks state*/
enum clocks_state cur_min_clks_state;
/* DFS-bypass feature variable
diff --git a/drivers/gpu/drm/amd/display/include/display_clock_interface.h b/drivers/gpu/drm/amd/display/include/display_clock_interface.h
index a46ceebe2452..bc678a59a3c1 100644
--- a/drivers/gpu/drm/amd/display/include/display_clock_interface.h
+++ b/drivers/gpu/drm/amd/display/include/display_clock_interface.h
@@ -60,7 +60,8 @@ struct display_clock {
struct dc_context *ctx;
const struct display_clock_funcs *funcs;
uint32_t min_display_clk_threshold_khz;
- enum clock_source_id id;
+ /* Max display block clocks state*/
+ enum clocks_state max_clks_state;
enum clocks_state cur_min_clks_state;
};
@@ -77,8 +78,6 @@ struct display_clock_funcs {
bool (*set_min_clocks_state)(struct display_clock *disp_clk,
enum clocks_state clocks_state);
uint32_t (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk);
- void (*store_max_clocks_state)(struct display_clock *disp_clk,
- enum clocks_state max_clocks_state);
};
--
2.9.3
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 06/12] drm/amd/display: remove get_min_clocks_state
[not found] ` <20161206183538.11584-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (4 preceding siblings ...)
2016-12-06 18:35 ` [PATCH 05/12] drm/amd/display: remove store clock state Harry Wentland
@ 2016-12-06 18:35 ` Harry Wentland
2016-12-06 18:35 ` [PATCH 07/12] drm/amd/display: remove clocks_state enum Harry Wentland
` (6 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Harry Wentland @ 2016-12-06 18:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Change-Id: Ib2d6f7c159812f6300701d4cfc2de355096d5a57
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 10 +----
.../display/dc/gpu/dce110/display_clock_dce110.c | 42 +++++++++++---------
.../display/dc/gpu/dce112/display_clock_dce112.c | 45 ++++++++++++----------
.../display/dc/gpu/dce112/display_clock_dce112.h | 2 +-
.../amd/display/dc/gpu/dce80/display_clock_dce80.c | 30 ++++++++-------
.../amd/display/include/display_clock_interface.h | 2 -
6 files changed, 67 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index ab4efde2d030..558eeefecbff 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1208,7 +1208,6 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx)
struct core_link *link = stream->sink->link;
struct dc_link_settings link_settings = {0};
enum dp_panel_mode panel_mode;
- enum clocks_state cur_min_clock_state;
enum dc_link_rate max_link_rate = LINK_RATE_HIGH2;
/* get link settings for video mode timing */
@@ -1221,13 +1220,8 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx)
max_link_rate = LINK_RATE_HIGH3;
if (link_settings.link_rate == max_link_rate) {
- cur_min_clock_state = CLOCKS_STATE_INVALID;
-
- if (pipe_ctx->dis_clk->funcs->get_min_clocks_state) {
- cur_min_clock_state =
- pipe_ctx->dis_clk->funcs->get_min_clocks_state(
- pipe_ctx->dis_clk);
- if (cur_min_clock_state < CLOCKS_STATE_NOMINAL)
+ if (pipe_ctx->dis_clk->funcs->set_min_clocks_state) {
+ if (pipe_ctx->dis_clk->cur_min_clks_state < CLOCKS_STATE_NOMINAL)
pipe_ctx->dis_clk->funcs->set_min_clocks_state(
pipe_ctx->dis_clk, CLOCKS_STATE_NOMINAL);
} else {
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c
index ad7ebc1b434c..83860208a9c5 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c
@@ -103,25 +103,19 @@ static struct divider_range divider_ranges[DIVIDER_RANGE_MAX];
* static functions
*****************************************************************************/
-static enum clocks_state get_min_clocks_state(struct display_clock *base)
-{
- return base->cur_min_clks_state;
-}
-
-static bool set_min_clocks_state(
- struct display_clock *base,
+static bool dce110_set_min_clocks_state(
+ struct display_clock *dc,
enum clocks_state clocks_state)
{
- struct display_clock_dce110 *dc = DCLCK110_FROM_BASE(base);
struct dm_pp_power_level_change_request level_change_req = {
DM_PP_POWER_LEVEL_INVALID};
- if (clocks_state > base->max_clks_state) {
+ if (clocks_state > dc->max_clks_state) {
/*Requested state exceeds max supported state.*/
- dm_logger_write(base->ctx->logger, LOG_WARNING,
+ dm_logger_write(dc->ctx->logger, LOG_WARNING,
"Requested state exceeds max supported state");
return false;
- } else if (clocks_state == base->cur_min_clks_state) {
+ } else if (clocks_state == dc->cur_min_clks_state) {
/*if we're trying to set the same state, we can just return
* since nothing needs to be done*/
return true;
@@ -140,17 +134,28 @@ static bool set_min_clocks_state(
case CLOCKS_STATE_PERFORMANCE:
level_change_req.power_level = DM_PP_POWER_LEVEL_PERFORMANCE;
break;
+ case CLOCKS_DPM_STATE_LEVEL_4:
+ level_change_req.power_level = DM_PP_POWER_LEVEL_4;
+ break;
+ case CLOCKS_DPM_STATE_LEVEL_5:
+ level_change_req.power_level = DM_PP_POWER_LEVEL_5;
+ break;
+ case CLOCKS_DPM_STATE_LEVEL_6:
+ level_change_req.power_level = DM_PP_POWER_LEVEL_6;
+ break;
+ case CLOCKS_DPM_STATE_LEVEL_7:
+ level_change_req.power_level = DM_PP_POWER_LEVEL_7;
+ break;
case CLOCKS_STATE_INVALID:
default:
- dm_logger_write(base->ctx->logger, LOG_WARNING,
+ dm_logger_write(dc->ctx->logger, LOG_WARNING,
"Requested state invalid state");
return false;
}
/* get max clock state from PPLIB */
- if (dm_pp_apply_power_level_change_request(
- base->ctx, &level_change_req))
- base->cur_min_clks_state = clocks_state;
+ if (dm_pp_apply_power_level_change_request(dc->ctx, &level_change_req))
+ dc->cur_min_clks_state = clocks_state;
return true;
}
@@ -384,7 +389,7 @@ static void psr_wait_loop(struct dc_context *ctx, unsigned int display_clk_khz)
dm_write_reg(ctx, mmMASTER_COMM_CNTL_REG, masterComCntl);
}
-static void set_clock(
+static void dce110_set_clock(
struct display_clock *base,
uint32_t requested_clk_khz)
{
@@ -424,10 +429,9 @@ static void set_clock(
static const struct display_clock_funcs funcs = {
.destroy = destroy,
.get_dp_ref_clk_frequency = get_dp_ref_clk_frequency,
- .get_min_clocks_state = get_min_clocks_state,
.get_required_clocks_state = get_required_clocks_state,
- .set_clock = set_clock,
- .set_min_clocks_state = set_min_clocks_state
+ .set_clock = dce110_set_clock,
+ .set_min_clocks_state = dce110_set_min_clocks_state
};
static bool dal_display_clock_dce110_construct(
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
index d8c8d8a1e2b3..4488497c00fa 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
@@ -73,26 +73,19 @@ static struct divider_range divider_ranges[DIVIDER_RANGE_MAX];
#define dce112_DFS_BYPASS_THRESHOLD_KHZ 400000
-enum clocks_state dispclk_dce112_get_min_clocks_state(
- struct display_clock *base)
-{
- return base->cur_min_clks_state;
-}
-
-bool dispclk_dce112_set_min_clocks_state(
- struct display_clock *base,
+static bool dce112_set_min_clocks_state(
+ struct display_clock *dc,
enum clocks_state clocks_state)
{
- struct display_clock_dce112 *dc = DCLCK112_FROM_BASE(base);
struct dm_pp_power_level_change_request level_change_req = {
- DM_PP_POWER_LEVEL_INVALID};
+ DM_PP_POWER_LEVEL_INVALID };
- if (clocks_state > base->max_clks_state) {
+ if (clocks_state > dc->max_clks_state) {
/*Requested state exceeds max supported state.*/
- dm_logger_write(base->ctx->logger, LOG_WARNING,
+ dm_logger_write(dc->ctx->logger, LOG_WARNING,
"Requested state exceeds max supported state");
return false;
- } else if (clocks_state == base->cur_min_clks_state) {
+ } else if (clocks_state == dc->cur_min_clks_state) {
/*if we're trying to set the same state, we can just return
* since nothing needs to be done*/
return true;
@@ -111,17 +104,28 @@ bool dispclk_dce112_set_min_clocks_state(
case CLOCKS_STATE_PERFORMANCE:
level_change_req.power_level = DM_PP_POWER_LEVEL_PERFORMANCE;
break;
+ case CLOCKS_DPM_STATE_LEVEL_4:
+ level_change_req.power_level = DM_PP_POWER_LEVEL_4;
+ break;
+ case CLOCKS_DPM_STATE_LEVEL_5:
+ level_change_req.power_level = DM_PP_POWER_LEVEL_5;
+ break;
+ case CLOCKS_DPM_STATE_LEVEL_6:
+ level_change_req.power_level = DM_PP_POWER_LEVEL_6;
+ break;
+ case CLOCKS_DPM_STATE_LEVEL_7:
+ level_change_req.power_level = DM_PP_POWER_LEVEL_7;
+ break;
case CLOCKS_STATE_INVALID:
default:
- dm_logger_write(base->ctx->logger, LOG_WARNING,
+ dm_logger_write(dc->ctx->logger, LOG_WARNING,
"Requested state invalid state");
return false;
}
/* get max clock state from PPLIB */
- if (dm_pp_apply_power_level_change_request(
- base->ctx, &level_change_req))
- base->cur_min_clks_state = clocks_state;
+ if (dm_pp_apply_power_level_change_request(dc->ctx, &level_change_req))
+ dc->cur_min_clks_state = clocks_state;
return true;
}
@@ -293,7 +297,7 @@ enum clocks_state dispclk_dce112_get_required_clocks_state(
return low_req_clk;
}
-void dispclk_dce112_set_clock(
+void dce112_set_clock(
struct display_clock *base,
uint32_t requested_clk_khz)
{
@@ -333,10 +337,9 @@ void dispclk_dce112_set_clock(
static const struct display_clock_funcs funcs = {
.destroy = dispclk_dce112_destroy,
.get_dp_ref_clk_frequency = get_dp_ref_clk_frequency,
- .get_min_clocks_state = dispclk_dce112_get_min_clocks_state,
.get_required_clocks_state = dispclk_dce112_get_required_clocks_state,
- .set_clock = dispclk_dce112_set_clock,
- .set_min_clocks_state = dispclk_dce112_set_min_clocks_state
+ .set_clock = dce112_set_clock,
+ .set_min_clocks_state = dce112_set_min_clocks_state
};
bool dal_display_clock_dce112_construct(
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
index 398af34720f7..0246f930ac35 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
@@ -78,7 +78,7 @@ enum clocks_state dispclk_dce112_get_required_clocks_state(
struct display_clock *dc,
struct state_dependent_clocks *req_clocks);
-void dispclk_dce112_set_clock(
+void dce112_set_clock(
struct display_clock *base,
uint32_t requested_clk_khz);
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c
index b101f7de2d11..6057042739bf 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c
@@ -90,7 +90,7 @@ static struct divider_range divider_ranges[DIVIDER_RANGE_MAX];
#define FROM_DISPLAY_CLOCK(base) \
container_of(base, struct display_clock_dce80, disp_clk)
-static void set_clock(
+static void dce80_set_clock(
struct display_clock *dc,
uint32_t requested_clk_khz)
{
@@ -111,13 +111,6 @@ static void set_clock(
dc->cur_min_clks_state = CLOCKS_STATE_NOMINAL;
}
-static enum clocks_state get_min_clocks_state(struct display_clock *dc)
-{
- struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-
- return disp_clk->cur_min_clks_state;
-}
-
static enum clocks_state get_required_clocks_state
(struct display_clock *dc,
struct state_dependent_clocks *req_clocks)
@@ -145,12 +138,12 @@ static enum clocks_state get_required_clocks_state
return low_req_clk;
}
-static bool set_min_clocks_state(
+static bool dce80_set_min_clocks_state(
struct display_clock *dc,
enum clocks_state clocks_state)
{
struct dm_pp_power_level_change_request level_change_req = {
- DM_PP_POWER_LEVEL_INVALID};
+ DM_PP_POWER_LEVEL_INVALID };
if (clocks_state > dc->max_clks_state) {
/*Requested state exceeds max supported state.*/
@@ -176,6 +169,18 @@ static bool set_min_clocks_state(
case CLOCKS_STATE_PERFORMANCE:
level_change_req.power_level = DM_PP_POWER_LEVEL_PERFORMANCE;
break;
+ case CLOCKS_DPM_STATE_LEVEL_4:
+ level_change_req.power_level = DM_PP_POWER_LEVEL_4;
+ break;
+ case CLOCKS_DPM_STATE_LEVEL_5:
+ level_change_req.power_level = DM_PP_POWER_LEVEL_5;
+ break;
+ case CLOCKS_DPM_STATE_LEVEL_6:
+ level_change_req.power_level = DM_PP_POWER_LEVEL_6;
+ break;
+ case CLOCKS_DPM_STATE_LEVEL_7:
+ level_change_req.power_level = DM_PP_POWER_LEVEL_7;
+ break;
case CLOCKS_STATE_INVALID:
default:
dm_logger_write(dc->ctx->logger, LOG_WARNING,
@@ -375,10 +380,9 @@ static void destroy(struct display_clock **dc)
static const struct display_clock_funcs funcs = {
.destroy = destroy,
.get_dp_ref_clk_frequency = get_dp_ref_clk_frequency,
- .get_min_clocks_state = get_min_clocks_state,
.get_required_clocks_state = get_required_clocks_state,
- .set_clock = set_clock,
- .set_min_clocks_state = set_min_clocks_state
+ .set_clock = dce80_set_clock,
+ .set_min_clocks_state = dce80_set_min_clocks_state
};
diff --git a/drivers/gpu/drm/amd/display/include/display_clock_interface.h b/drivers/gpu/drm/amd/display/include/display_clock_interface.h
index bc678a59a3c1..f2deafbd8b12 100644
--- a/drivers/gpu/drm/amd/display/include/display_clock_interface.h
+++ b/drivers/gpu/drm/amd/display/include/display_clock_interface.h
@@ -70,8 +70,6 @@ struct display_clock_funcs {
void (*destroy)(struct display_clock **to_destroy);
void (*set_clock)(struct display_clock *disp_clk,
uint32_t requested_clock_khz);
- enum clocks_state (*get_min_clocks_state)(
- struct display_clock *disp_clk);
enum clocks_state (*get_required_clocks_state)(
struct display_clock *disp_clk,
struct state_dependent_clocks *req_clocks);
--
2.9.3
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 07/12] drm/amd/display: remove clocks_state enum
[not found] ` <20161206183538.11584-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (5 preceding siblings ...)
2016-12-06 18:35 ` [PATCH 06/12] drm/amd/display: remove get_min_clocks_state Harry Wentland
@ 2016-12-06 18:35 ` Harry Wentland
2016-12-06 18:35 ` [PATCH 08/12] drm/amd/display: consolidate dce8-11.2 display clock code Harry Wentland
` (5 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Harry Wentland @ 2016-12-06 18:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Change-Id: I2a653a44ed6001d72ae049409e567ad9a3d882b2
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 +-
.../drm/amd/display/dc/dce100/dce100_resource.c | 3 +-
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 4 +-
.../drm/amd/display/dc/dce110/dce110_resource.c | 44 +--------------
.../drm/amd/display/dc/dce110/dce110_resource.h | 3 -
.../drm/amd/display/dc/dce112/dce112_resource.c | 3 +-
.../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 24 ++++----
.../display/dc/gpu/dce110/display_clock_dce110.c | 62 +++++----------------
.../display/dc/gpu/dce112/display_clock_dce112.c | 62 +++++----------------
.../display/dc/gpu/dce112/display_clock_dce112.h | 8 +--
.../amd/display/dc/gpu/dce80/display_clock_dce80.c | 64 ++++++----------------
.../amd/display/dc/gpu/dce80/display_clock_dce80.h | 2 +-
.../amd/display/include/display_clock_interface.h | 28 ++--------
13 files changed, 75 insertions(+), 236 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 558eeefecbff..47f22d46c0ca 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1221,9 +1221,9 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx)
if (link_settings.link_rate == max_link_rate) {
if (pipe_ctx->dis_clk->funcs->set_min_clocks_state) {
- if (pipe_ctx->dis_clk->cur_min_clks_state < CLOCKS_STATE_NOMINAL)
+ if (pipe_ctx->dis_clk->cur_min_clks_state < DM_PP_CLOCKS_STATE_NOMINAL)
pipe_ctx->dis_clk->funcs->set_min_clocks_state(
- pipe_ctx->dis_clk, CLOCKS_STATE_NOMINAL);
+ pipe_ctx->dis_clk, DM_PP_CLOCKS_STATE_NOMINAL);
} else {
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 446f50bb4e0a..5716ce1e58f4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -983,8 +983,7 @@ static bool construct(
*/
if (dm_pp_get_static_clocks(ctx, &static_clk_info))
pool->base.display_clock->max_clks_state =
- dce110_resource_convert_clock_state_pp_to_dc(
- static_clk_info.max_clocks_state);
+ static_clk_info.max_clocks_state;
{
struct irq_service_init_data init_data;
init_data.ctx = dc->ctx;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index ca71509af74d..6ad23f327631 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1084,7 +1084,7 @@ static uint32_t get_max_pixel_clock_for_all_paths(
static void apply_min_clocks(
struct core_dc *dc,
struct validate_context *context,
- enum clocks_state *clocks_state,
+ enum dm_pp_clocks_state *clocks_state,
bool pre_mode_set)
{
struct state_dependent_clocks req_clocks = {0};
@@ -1193,7 +1193,7 @@ enum dc_status dce110_apply_ctx_to_hw(
enum dc_status status;
int i;
bool programmed_audio_dto = false;
- enum clocks_state clocks_state = CLOCKS_STATE_INVALID;
+ enum dm_pp_clocks_state clocks_state = DM_PP_CLOCKS_STATE_INVALID;
/* Reset old context */
/* look up the targets that have been removed since last commit */
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index d5d888bdf882..8682c8b2a547 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -1188,47 +1188,6 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc)
1000);
}
-enum clocks_state dce110_resource_convert_clock_state_pp_to_dc(
- enum dm_pp_clocks_state pp_clock_state)
-{
- enum clocks_state dc_clocks_state = CLOCKS_STATE_INVALID;
-
- switch (pp_clock_state) {
- case DM_PP_CLOCKS_STATE_INVALID:
- dc_clocks_state = CLOCKS_STATE_INVALID;
- break;
- case DM_PP_CLOCKS_STATE_ULTRA_LOW:
- dc_clocks_state = CLOCKS_STATE_ULTRA_LOW;
- break;
- case DM_PP_CLOCKS_STATE_LOW:
- dc_clocks_state = CLOCKS_STATE_LOW;
- break;
- case DM_PP_CLOCKS_STATE_NOMINAL:
- dc_clocks_state = CLOCKS_STATE_NOMINAL;
- break;
- case DM_PP_CLOCKS_STATE_PERFORMANCE:
- dc_clocks_state = CLOCKS_STATE_PERFORMANCE;
- break;
- case DM_PP_CLOCKS_DPM_STATE_LEVEL_4:
- dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_4;
- break;
- case DM_PP_CLOCKS_DPM_STATE_LEVEL_5:
- dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_5;
- break;
- case DM_PP_CLOCKS_DPM_STATE_LEVEL_6:
- dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_6;
- break;
- case DM_PP_CLOCKS_DPM_STATE_LEVEL_7:
- dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_7;
- break;
- default:
- dc_clocks_state = CLOCKS_STATE_INVALID;
- break;
- }
-
- return dc_clocks_state;
-}
-
const struct resource_caps *dce110_resource_cap(
struct hw_asic_id *asic_id)
{
@@ -1314,8 +1273,7 @@ static bool construct(
*/
if (dm_pp_get_static_clocks(ctx, &static_clk_info))
pool->base.display_clock->max_clks_state =
- dce110_resource_convert_clock_state_pp_to_dc(
- static_clk_info.max_clocks_state);
+ static_clk_info.max_clocks_state;
{
struct irq_service_init_data init_data;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h
index 535623aa0052..0c357fdfa8bc 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h
@@ -40,9 +40,6 @@ struct dce110_resource_pool {
enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx);
-enum clocks_state dce110_resource_convert_clock_state_pp_to_dc(
- enum dm_pp_clocks_state pp_clock_state);
-
void dce110_resource_build_bit_depth_reduction_params(
const struct core_stream *stream,
struct bit_depth_reduction_params *fmt_bit_depth);
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 9903c9a4b8a1..c50a215172b7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -1314,8 +1314,7 @@ static bool construct(
*/
if (dm_pp_get_static_clocks(ctx, &static_clk_info))
pool->base.display_clock->max_clks_state =
- dce110_resource_convert_clock_state_pp_to_dc(
- static_clk_info.max_clocks_state);
+ static_clk_info.max_clocks_state;
{
struct irq_service_init_data init_data;
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 51721d10c811..1d2a31e34617 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -857,41 +857,41 @@ static const struct resource_funcs dce80_res_pool_funcs = {
.validate_bandwidth = dce80_validate_bandwidth
};
-static enum clocks_state dce80_resource_convert_clock_state_pp_to_dc(
+static enum dm_pp_clocks_state dce80_resource_convert_clock_state_pp_to_dc(
enum dm_pp_clocks_state pp_clock_state)
{
- enum clocks_state dc_clocks_state = CLOCKS_STATE_INVALID;
+ enum dm_pp_clocks_state dc_clocks_state = DM_PP_CLOCKS_STATE_INVALID;
switch (pp_clock_state) {
case DM_PP_CLOCKS_STATE_INVALID:
- dc_clocks_state = CLOCKS_STATE_INVALID;
+ dc_clocks_state = DM_PP_CLOCKS_STATE_INVALID;
break;
case DM_PP_CLOCKS_STATE_ULTRA_LOW:
- dc_clocks_state = CLOCKS_STATE_ULTRA_LOW;
+ dc_clocks_state = DM_PP_CLOCKS_STATE_ULTRA_LOW;
break;
case DM_PP_CLOCKS_STATE_LOW:
- dc_clocks_state = CLOCKS_STATE_LOW;
+ dc_clocks_state = DM_PP_CLOCKS_STATE_LOW;
break;
case DM_PP_CLOCKS_STATE_NOMINAL:
- dc_clocks_state = CLOCKS_STATE_NOMINAL;
+ dc_clocks_state = DM_PP_CLOCKS_STATE_NOMINAL;
break;
case DM_PP_CLOCKS_STATE_PERFORMANCE:
- dc_clocks_state = CLOCKS_STATE_PERFORMANCE;
+ dc_clocks_state = DM_PP_CLOCKS_STATE_PERFORMANCE;
break;
case DM_PP_CLOCKS_DPM_STATE_LEVEL_4:
- dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_4;
+ dc_clocks_state = DM_PP_CLOCKS_DPM_STATE_LEVEL_4;
break;
case DM_PP_CLOCKS_DPM_STATE_LEVEL_5:
- dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_5;
+ dc_clocks_state = DM_PP_CLOCKS_DPM_STATE_LEVEL_5;
break;
case DM_PP_CLOCKS_DPM_STATE_LEVEL_6:
- dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_6;
+ dc_clocks_state = DM_PP_CLOCKS_DPM_STATE_LEVEL_6;
break;
case DM_PP_CLOCKS_DPM_STATE_LEVEL_7:
- dc_clocks_state = CLOCKS_DPM_STATE_LEVEL_7;
+ dc_clocks_state = DM_PP_CLOCKS_DPM_STATE_LEVEL_7;
break;
default:
- dc_clocks_state = CLOCKS_STATE_INVALID;
+ dc_clocks_state = DM_PP_CLOCKS_STATE_INVALID;
break;
}
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c
index 83860208a9c5..9dabaac2c550 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c
@@ -105,10 +105,10 @@ static struct divider_range divider_ranges[DIVIDER_RANGE_MAX];
static bool dce110_set_min_clocks_state(
struct display_clock *dc,
- enum clocks_state clocks_state)
+ enum dm_pp_clocks_state clocks_state)
{
struct dm_pp_power_level_change_request level_change_req = {
- DM_PP_POWER_LEVEL_INVALID};
+ clocks_state };
if (clocks_state > dc->max_clks_state) {
/*Requested state exceeds max supported state.*/
@@ -121,38 +121,6 @@ static bool dce110_set_min_clocks_state(
return true;
}
- switch (clocks_state) {
- case CLOCKS_STATE_ULTRA_LOW:
- level_change_req.power_level = DM_PP_POWER_LEVEL_ULTRA_LOW;
- break;
- case CLOCKS_STATE_LOW:
- level_change_req.power_level = DM_PP_POWER_LEVEL_LOW;
- break;
- case CLOCKS_STATE_NOMINAL:
- level_change_req.power_level = DM_PP_POWER_LEVEL_NOMINAL;
- break;
- case CLOCKS_STATE_PERFORMANCE:
- level_change_req.power_level = DM_PP_POWER_LEVEL_PERFORMANCE;
- break;
- case CLOCKS_DPM_STATE_LEVEL_4:
- level_change_req.power_level = DM_PP_POWER_LEVEL_4;
- break;
- case CLOCKS_DPM_STATE_LEVEL_5:
- level_change_req.power_level = DM_PP_POWER_LEVEL_5;
- break;
- case CLOCKS_DPM_STATE_LEVEL_6:
- level_change_req.power_level = DM_PP_POWER_LEVEL_6;
- break;
- case CLOCKS_DPM_STATE_LEVEL_7:
- level_change_req.power_level = DM_PP_POWER_LEVEL_7;
- break;
- case CLOCKS_STATE_INVALID:
- default:
- dm_logger_write(dc->ctx->logger, LOG_WARNING,
- "Requested state invalid state");
- return false;
- }
-
/* get max clock state from PPLIB */
if (dm_pp_apply_power_level_change_request(dc->ctx, &level_change_req))
dc->cur_min_clks_state = clocks_state;
@@ -274,27 +242,27 @@ static bool display_clock_integrated_info_construct(
/*update the maximum display clock for each power state*/
for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
- enum clocks_state clk_state = CLOCKS_STATE_INVALID;
+ enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID;
switch (i) {
case 0:
- clk_state = CLOCKS_STATE_ULTRA_LOW;
+ clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW;
break;
case 1:
- clk_state = CLOCKS_STATE_LOW;
+ clk_state = DM_PP_CLOCKS_STATE_LOW;
break;
case 2:
- clk_state = CLOCKS_STATE_NOMINAL;
+ clk_state = DM_PP_CLOCKS_STATE_NOMINAL;
break;
case 3:
- clk_state = CLOCKS_STATE_PERFORMANCE;
+ clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE;
break;
default:
- clk_state = CLOCKS_STATE_INVALID;
+ clk_state = DM_PP_CLOCKS_STATE_INVALID;
break;
}
@@ -316,27 +284,27 @@ static bool display_clock_integrated_info_construct(
return true;
}
-static enum clocks_state get_required_clocks_state(
+static enum dm_pp_clocks_state get_required_clocks_state(
struct display_clock *dc,
struct state_dependent_clocks *req_clocks)
{
int32_t i;
struct display_clock_dce110 *disp_clk = DCLCK110_FROM_BASE(dc);
- enum clocks_state low_req_clk = dc->max_clks_state;
+ enum dm_pp_clocks_state low_req_clk = dc->max_clks_state;
if (!req_clocks) {
/* NULL pointer*/
dm_logger_write(dc->ctx->logger, LOG_WARNING,
"%s: Invalid parameter",
__func__);
- return CLOCKS_STATE_INVALID;
+ return DM_PP_CLOCKS_STATE_INVALID;
}
/* Iterate from highest supported to lowest valid state, and update
* lowest RequiredState with the lowest state that satisfies
* all required clocks
*/
- for (i = dc->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) {
+ for (i = dc->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; --i) {
if ((req_clocks->display_clk_khz <=
max_clks_by_state[i].display_clk_khz) &&
(req_clocks->pixel_clk_khz <=
@@ -420,7 +388,7 @@ static void dce110_set_clock(
/* from power down, we need mark the clock state as ClocksStateNominal
* from HWReset, so when resume we will call pplib voltage regulator.*/
if (requested_clk_khz == 0)
- base->cur_min_clks_state = CLOCKS_STATE_NOMINAL;
+ base->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
psr_wait_loop(base->ctx, requested_clk_khz);
}
@@ -444,7 +412,7 @@ static bool dal_display_clock_dce110_construct(
dc_base->ctx = ctx;
dc_base->min_display_clk_threshold_khz = 0;
- dc_base->cur_min_clks_state = CLOCKS_STATE_INVALID;
+ dc_base->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
dc_base->funcs = &funcs;
@@ -462,7 +430,7 @@ static bool dal_display_clock_dce110_construct(
* via a pplib call to DAL IRI eventually calling a
* DisplayEngineClock_Dce110::StoreMaxClocksState(). This call will come in
* on PPLIB init. This is from DCE5x. in case HW wants to use mixed method.*/
- dc_base->max_clks_state = CLOCKS_STATE_NOMINAL;
+ dc_base->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
dal_divider_range_construct(
÷r_ranges[DIVIDER_RANGE_01],
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
index 4488497c00fa..930548bdd8b2 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
@@ -75,10 +75,10 @@ static struct divider_range divider_ranges[DIVIDER_RANGE_MAX];
static bool dce112_set_min_clocks_state(
struct display_clock *dc,
- enum clocks_state clocks_state)
+ enum dm_pp_clocks_state clocks_state)
{
struct dm_pp_power_level_change_request level_change_req = {
- DM_PP_POWER_LEVEL_INVALID };
+ clocks_state };
if (clocks_state > dc->max_clks_state) {
/*Requested state exceeds max supported state.*/
@@ -91,38 +91,6 @@ static bool dce112_set_min_clocks_state(
return true;
}
- switch (clocks_state) {
- case CLOCKS_STATE_ULTRA_LOW:
- level_change_req.power_level = DM_PP_POWER_LEVEL_ULTRA_LOW;
- break;
- case CLOCKS_STATE_LOW:
- level_change_req.power_level = DM_PP_POWER_LEVEL_LOW;
- break;
- case CLOCKS_STATE_NOMINAL:
- level_change_req.power_level = DM_PP_POWER_LEVEL_NOMINAL;
- break;
- case CLOCKS_STATE_PERFORMANCE:
- level_change_req.power_level = DM_PP_POWER_LEVEL_PERFORMANCE;
- break;
- case CLOCKS_DPM_STATE_LEVEL_4:
- level_change_req.power_level = DM_PP_POWER_LEVEL_4;
- break;
- case CLOCKS_DPM_STATE_LEVEL_5:
- level_change_req.power_level = DM_PP_POWER_LEVEL_5;
- break;
- case CLOCKS_DPM_STATE_LEVEL_6:
- level_change_req.power_level = DM_PP_POWER_LEVEL_6;
- break;
- case CLOCKS_DPM_STATE_LEVEL_7:
- level_change_req.power_level = DM_PP_POWER_LEVEL_7;
- break;
- case CLOCKS_STATE_INVALID:
- default:
- dm_logger_write(dc->ctx->logger, LOG_WARNING,
- "Requested state invalid state");
- return false;
- }
-
/* get max clock state from PPLIB */
if (dm_pp_apply_power_level_change_request(dc->ctx, &level_change_req))
dc->cur_min_clks_state = clocks_state;
@@ -229,27 +197,27 @@ static bool display_clock_integrated_info_construct(
/*update the maximum display clock for each power state*/
for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
- enum clocks_state clk_state = CLOCKS_STATE_INVALID;
+ enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID;
switch (i) {
case 0:
- clk_state = CLOCKS_STATE_ULTRA_LOW;
+ clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW;
break;
case 1:
- clk_state = CLOCKS_STATE_LOW;
+ clk_state = DM_PP_CLOCKS_STATE_LOW;
break;
case 2:
- clk_state = CLOCKS_STATE_NOMINAL;
+ clk_state = DM_PP_CLOCKS_STATE_NOMINAL;
break;
case 3:
- clk_state = CLOCKS_STATE_PERFORMANCE;
+ clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE;
break;
default:
- clk_state = CLOCKS_STATE_INVALID;
+ clk_state = DM_PP_CLOCKS_STATE_INVALID;
break;
}
@@ -265,27 +233,27 @@ static bool display_clock_integrated_info_construct(
return true;
}
-enum clocks_state dispclk_dce112_get_required_clocks_state(
+enum dm_pp_clocks_state dispclk_dce112_get_required_clocks_state(
struct display_clock *dc,
struct state_dependent_clocks *req_clocks)
{
int32_t i;
struct display_clock_dce112 *disp_clk = DCLCK112_FROM_BASE(dc);
- enum clocks_state low_req_clk = dc->max_clks_state;
+ enum dm_pp_clocks_state low_req_clk = dc->max_clks_state;
if (!req_clocks) {
/* NULL pointer*/
dm_logger_write(dc->ctx->logger, LOG_WARNING,
"%s: Invalid parameter",
__func__);
- return CLOCKS_STATE_INVALID;
+ return DM_PP_CLOCKS_STATE_INVALID;
}
/* Iterate from highest supported to lowest valid state, and update
* lowest RequiredState with the lowest state that satisfies
* all required clocks
*/
- for (i = dc->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) {
+ for (i = dc->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; --i) {
if ((req_clocks->display_clk_khz <=
(disp_clk->max_clks_by_state + i)->
display_clk_khz) &&
@@ -321,7 +289,7 @@ void dce112_set_clock(
/* from power down, we need mark the clock state as ClocksStateNominal
* from HWReset, so when resume we will call pplib voltage regulator.*/
if (requested_clk_khz == 0)
- base->cur_min_clks_state = CLOCKS_STATE_NOMINAL;
+ base->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
/*Program DP ref Clock*/
/*VBIOS will determine DPREFCLK frequency, so we don't set it*/
@@ -351,7 +319,7 @@ bool dal_display_clock_dce112_construct(
dc_base->ctx = ctx;
dc_base->min_display_clk_threshold_khz = 0;
- dc_base->cur_min_clks_state = CLOCKS_STATE_INVALID;
+ dc_base->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
dc_base->funcs = &funcs;
@@ -369,7 +337,7 @@ bool dal_display_clock_dce112_construct(
* via a pplib call to DAL IRI eventually calling a
* DisplayEngineClock_dce112::StoreMaxClocksState(). This call will come in
* on PPLIB init. This is from DCE5x. in case HW wants to use mixed method.*/
- dc_base->max_clks_state = CLOCKS_STATE_NOMINAL;
+ dc_base->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
dc112->disp_clk_base.min_display_clk_threshold_khz =
(dc112->dentist_vco_freq_khz / 62);
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
index 0246f930ac35..b750bb1766bd 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
@@ -71,10 +71,10 @@ bool dal_display_clock_dce112_construct(
void dispclk_dce112_destroy(struct display_clock **base);
-enum clocks_state dispclk_dce112_get_min_clocks_state(
+enum dm_pp_clocks_state dispclk_dce112_get_min_clocks_state(
struct display_clock *base);
-enum clocks_state dispclk_dce112_get_required_clocks_state(
+enum dm_pp_clocks_state dispclk_dce112_get_required_clocks_state(
struct display_clock *dc,
struct state_dependent_clocks *req_clocks);
@@ -84,10 +84,10 @@ void dce112_set_clock(
bool dispclk_dce112_set_min_clocks_state(
struct display_clock *base,
- enum clocks_state clocks_state);
+ enum dm_pp_clocks_state clocks_state);
void dispclk_dce112_store_max_clocks_state(
struct display_clock *base,
- enum clocks_state max_clocks_state);
+ enum dm_pp_clocks_state max_clocks_state);
#endif /* __DAL_DISPLAY_CLOCK_DCE112_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c
index 6057042739bf..9d7cb2cb161c 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c
@@ -108,27 +108,27 @@ static void dce80_set_clock(
/* from power down, we need mark the clock state as ClocksStateNominal
* from HWReset, so when resume we will call pplib voltage regulator.*/
if (requested_clk_khz == 0)
- dc->cur_min_clks_state = CLOCKS_STATE_NOMINAL;
+ dc->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
}
-static enum clocks_state get_required_clocks_state
+static enum dm_pp_clocks_state get_required_clocks_state
(struct display_clock *dc,
struct state_dependent_clocks *req_clocks)
{
int32_t i;
- enum clocks_state low_req_clk = dc->max_clks_state;
+ enum dm_pp_clocks_state low_req_clk = dc->max_clks_state;
if (!req_clocks) {
/* NULL pointer*/
BREAK_TO_DEBUGGER();
- return CLOCKS_STATE_INVALID;
+ return DM_PP_CLOCKS_STATE_INVALID;
}
/* Iterate from highest supported to lowest valid state, and update
* lowest RequiredState with the lowest state that satisfies
* all required clocks
*/
- for (i = dc->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) {
+ for (i = dc->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; --i) {
if ((req_clocks->display_clk_khz <=
max_clks_by_state[i].display_clk_khz) &&
(req_clocks->pixel_clk_khz <=
@@ -140,10 +140,10 @@ static enum clocks_state get_required_clocks_state
static bool dce80_set_min_clocks_state(
struct display_clock *dc,
- enum clocks_state clocks_state)
+ enum dm_pp_clocks_state clocks_state)
{
struct dm_pp_power_level_change_request level_change_req = {
- DM_PP_POWER_LEVEL_INVALID };
+ clocks_state };
if (clocks_state > dc->max_clks_state) {
/*Requested state exceeds max supported state.*/
@@ -156,38 +156,6 @@ static bool dce80_set_min_clocks_state(
return true;
}
- switch (clocks_state) {
- case CLOCKS_STATE_ULTRA_LOW:
- level_change_req.power_level = DM_PP_POWER_LEVEL_ULTRA_LOW;
- break;
- case CLOCKS_STATE_LOW:
- level_change_req.power_level = DM_PP_POWER_LEVEL_LOW;
- break;
- case CLOCKS_STATE_NOMINAL:
- level_change_req.power_level = DM_PP_POWER_LEVEL_NOMINAL;
- break;
- case CLOCKS_STATE_PERFORMANCE:
- level_change_req.power_level = DM_PP_POWER_LEVEL_PERFORMANCE;
- break;
- case CLOCKS_DPM_STATE_LEVEL_4:
- level_change_req.power_level = DM_PP_POWER_LEVEL_4;
- break;
- case CLOCKS_DPM_STATE_LEVEL_5:
- level_change_req.power_level = DM_PP_POWER_LEVEL_5;
- break;
- case CLOCKS_DPM_STATE_LEVEL_6:
- level_change_req.power_level = DM_PP_POWER_LEVEL_6;
- break;
- case CLOCKS_DPM_STATE_LEVEL_7:
- level_change_req.power_level = DM_PP_POWER_LEVEL_7;
- break;
- case CLOCKS_STATE_INVALID:
- default:
- dm_logger_write(dc->ctx->logger, LOG_WARNING,
- "Requested state invalid state");
- return false;
- }
-
/* get max clock state from PPLIB */
if (dm_pp_apply_power_level_change_request(dc->ctx, &level_change_req))
dc->cur_min_clks_state = clocks_state;
@@ -326,27 +294,27 @@ static bool display_clock_integrated_info_construct(
/*update the maximum display clock for each power state*/
for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
- enum clocks_state clk_state = CLOCKS_STATE_INVALID;
+ enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID;
switch (i) {
case 0:
- clk_state = CLOCKS_STATE_ULTRA_LOW;
+ clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW;
break;
case 1:
- clk_state = CLOCKS_STATE_LOW;
+ clk_state = DM_PP_CLOCKS_STATE_LOW;
break;
case 2:
- clk_state = CLOCKS_STATE_NOMINAL;
+ clk_state = DM_PP_CLOCKS_STATE_NOMINAL;
break;
case 3:
- clk_state = CLOCKS_STATE_PERFORMANCE;
+ clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE;
break;
default:
- clk_state = CLOCKS_STATE_INVALID;
+ clk_state = DM_PP_CLOCKS_STATE_INVALID;
break;
}
@@ -402,7 +370,7 @@ struct display_clock *dal_display_clock_dce80_create(
dc_base->ctx = ctx;
dc_base->min_display_clk_threshold_khz = 0;
- dc_base->cur_min_clks_state = CLOCKS_STATE_INVALID;
+ dc_base->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
dc_base->funcs = &funcs;
/*
@@ -423,12 +391,12 @@ struct display_clock *dal_display_clock_dce80_create(
* via a pplib call to DAL IRI eventually calling a
* DisplayEngineClock_Dce50::StoreMaxClocksState(). This call will come in
* on PPLIB init. This is from DCE5x. in case HW wants to use mixed method.*/
- dc_base->max_clks_state = CLOCKS_STATE_NOMINAL;
+ dc_base->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
/* Initially set current min clocks state to invalid since we
* cannot make any assumption about PPLIB's initial state. This will be updated
* by HWSS via SetMinClocksState() on first mode set prior to programming
* state dependent clocks.*/
- disp_clk->cur_min_clks_state = CLOCKS_STATE_INVALID;
+ disp_clk->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
display_clock_ss_construct(disp_clk);
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h
index 1193398b5cea..c155bb6a4321 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h
@@ -38,7 +38,7 @@ struct display_clock_dce80 {
/* Flag for Enabled SS on GPU PLL*/
bool ss_on_gpu_pll;
/* Current minimum display block clocks state*/
- enum clocks_state cur_min_clks_state;
+ enum dm_pp_clocks_state cur_min_clks_state;
/* DFS-bypass feature variable
Cache the status of DFS-bypass feature*/
bool dfs_bypass_enabled;
diff --git a/drivers/gpu/drm/amd/display/include/display_clock_interface.h b/drivers/gpu/drm/amd/display/include/display_clock_interface.h
index f2deafbd8b12..6ba8c093793d 100644
--- a/drivers/gpu/drm/amd/display/include/display_clock_interface.h
+++ b/drivers/gpu/drm/amd/display/include/display_clock_interface.h
@@ -26,29 +26,11 @@
#ifndef __DISPLAY_CLOCK_INTERFACE_H__
#define __DISPLAY_CLOCK_INTERFACE_H__
+#include "dm_services_types.h"
#include "hw_sequencer_types.h"
#include "grph_object_defs.h"
#include "signal_types.h"
-/* Enumeration of all clocks states */
-enum clocks_state {
- CLOCKS_STATE_INVALID = 0,
- CLOCKS_STATE_ULTRA_LOW,
- CLOCKS_STATE_LOW,
- CLOCKS_STATE_NOMINAL,
- CLOCKS_STATE_PERFORMANCE,
- /* Starting from DCE11, Max 8 level DPM state supported */
- CLOCKS_DPM_STATE_LEVEL_INVALID = CLOCKS_STATE_INVALID,
- CLOCKS_DPM_STATE_LEVEL_0 = CLOCKS_STATE_ULTRA_LOW,
- CLOCKS_DPM_STATE_LEVEL_1 = CLOCKS_STATE_LOW,
- CLOCKS_DPM_STATE_LEVEL_2 = CLOCKS_STATE_NOMINAL,
- CLOCKS_DPM_STATE_LEVEL_3 = CLOCKS_STATE_PERFORMANCE,
- CLOCKS_DPM_STATE_LEVEL_4 = CLOCKS_DPM_STATE_LEVEL_3 + 1,
- CLOCKS_DPM_STATE_LEVEL_5 = CLOCKS_DPM_STATE_LEVEL_4 + 1,
- CLOCKS_DPM_STATE_LEVEL_6 = CLOCKS_DPM_STATE_LEVEL_5 + 1,
- CLOCKS_DPM_STATE_LEVEL_7 = CLOCKS_DPM_STATE_LEVEL_6 + 1,
-};
-
/* Structure containing all state-dependent clocks
* (dependent on "enum clocks_state") */
struct state_dependent_clocks {
@@ -61,20 +43,20 @@ struct display_clock {
const struct display_clock_funcs *funcs;
uint32_t min_display_clk_threshold_khz;
/* Max display block clocks state*/
- enum clocks_state max_clks_state;
+ enum dm_pp_clocks_state max_clks_state;
- enum clocks_state cur_min_clks_state;
+ enum dm_pp_clocks_state cur_min_clks_state;
};
struct display_clock_funcs {
void (*destroy)(struct display_clock **to_destroy);
void (*set_clock)(struct display_clock *disp_clk,
uint32_t requested_clock_khz);
- enum clocks_state (*get_required_clocks_state)(
+ enum dm_pp_clocks_state (*get_required_clocks_state)(
struct display_clock *disp_clk,
struct state_dependent_clocks *req_clocks);
bool (*set_min_clocks_state)(struct display_clock *disp_clk,
- enum clocks_state clocks_state);
+ enum dm_pp_clocks_state dm_pp_clocks_state);
uint32_t (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk);
};
--
2.9.3
_______________________________________________
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amd-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 08/12] drm/amd/display: consolidate dce8-11.2 display clock code
[not found] ` <20161206183538.11584-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (6 preceding siblings ...)
2016-12-06 18:35 ` [PATCH 07/12] drm/amd/display: remove clocks_state enum Harry Wentland
@ 2016-12-06 18:35 ` Harry Wentland
2016-12-06 18:35 ` [PATCH 09/12] drm/amd/display: add newline to generic_reg_wait timeout message Harry Wentland
` (4 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Harry Wentland @ 2016-12-06 18:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Change-Id: I4d468ab9ee40809587b0ed84795b0d66343eab13
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/Makefile | 3 +-
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 4 +-
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 519 +++++++++++++++++++++
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 133 ++++++
.../drm/amd/display/dc/dce100/dce100_resource.c | 22 +-
.../drm/amd/display/dc/dce110/dce110_resource.c | 24 +-
.../drm/amd/display/dc/dce112/dce112_resource.c | 28 +-
.../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 70 +--
drivers/gpu/drm/amd/display/dc/dm_services_types.h | 18 +-
drivers/gpu/drm/amd/display/dc/gpu/Makefile | 15 -
.../display/dc/gpu/dce110/display_clock_dce110.c | 516 --------------------
.../display/dc/gpu/dce110/display_clock_dce110.h | 50 --
.../display/dc/gpu/dce112/display_clock_dce112.c | 152 ------
.../display/dc/gpu/dce112/display_clock_dce112.h | 14 -
.../amd/display/dc/gpu/dce80/display_clock_dce80.c | 430 -----------------
.../amd/display/dc/gpu/dce80/display_clock_dce80.h | 54 ---
.../amd/display/include/display_clock_interface.h | 15 +-
17 files changed, 747 insertions(+), 1320 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
delete mode 100644 drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c
delete mode 100644 drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h
delete mode 100644 drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c
delete mode 100644 drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h
diff --git a/drivers/gpu/drm/amd/display/dc/dce/Makefile b/drivers/gpu/drm/amd/display/dc/dce/Makefile
index bfca38170329..6add5977fd39 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dce/Makefile
@@ -6,7 +6,8 @@
# offset/shift/mask stored in dce_hw struct
DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \
-dce_mem_input.o dce_clock_source.o dce_scl_filters.o dce_transform.o
+dce_mem_input.o dce_clock_source.o dce_scl_filters.o dce_transform.o \
+dce_clocks.o
AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
index dc44053e8575..2749c8fa4f1f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
@@ -888,7 +888,9 @@ static const struct audio_funcs funcs = {
void dce_aud_destroy(struct audio **audio)
{
- dm_free(*audio);
+ struct dce_audio *aud = DCE_AUD(*audio);
+
+ dm_free(aud);
*audio = NULL;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
new file mode 100644
index 000000000000..bc1a46b7e373
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -0,0 +1,519 @@
+/*
+ * Copyright 2012-16 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dce_clocks.h"
+#include "dm_services.h"
+#include "reg_helper.h"
+#include "fixed32_32.h"
+#include "bios_parser_interface.h"
+#include "dc.h"
+
+
+#define REG(reg) \
+ (clk_dce->regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+ clk_dce->clk_shift->field_name, clk_dce->clk_mask->field_name
+
+#define CTX \
+ clk_dce->base.ctx
+
+/* Starting point for each divider range.*/
+enum divider_range_start {
+ DIVIDER_RANGE_01_START = 200, /* 2.00*/
+ DIVIDER_RANGE_02_START = 1600, /* 16.00*/
+ DIVIDER_RANGE_03_START = 3200, /* 32.00*/
+ DIVIDER_RANGE_SCALE_FACTOR = 100 /* Results are scaled up by 100.*/
+};
+
+/* Ranges for divider identifiers (Divider ID or DID)
+ mmDENTIST_DISPCLK_CNTL.DENTIST_DISPCLK_WDIVIDER*/
+enum divider_id_register_setting {
+ DIVIDER_RANGE_01_BASE_DIVIDER_ID = 0X08,
+ DIVIDER_RANGE_02_BASE_DIVIDER_ID = 0X40,
+ DIVIDER_RANGE_03_BASE_DIVIDER_ID = 0X60,
+ DIVIDER_RANGE_MAX_DIVIDER_ID = 0X80
+};
+
+/* Step size between each divider within a range.
+ Incrementing the DENTIST_DISPCLK_WDIVIDER by one
+ will increment the divider by this much.*/
+enum divider_range_step_size {
+ DIVIDER_RANGE_01_STEP_SIZE = 25, /* 0.25*/
+ DIVIDER_RANGE_02_STEP_SIZE = 50, /* 0.50*/
+ DIVIDER_RANGE_03_STEP_SIZE = 100 /* 1.00 */
+};
+
+
+static int dce_clocks_get_dp_ref_freq(struct display_clock *clk)
+{
+ struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
+ int dprefclk_wdivider;
+ int dprefclk_src_sel;
+ int dp_ref_clk_khz = 600000;
+ int target_div = INVALID_DIVIDER;
+
+ /* ASSERT DP Reference Clock source is from DFS*/
+ REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel);
+ ASSERT(dprefclk_src_sel == 0);
+
+ /* Read the mmDENTIST_DISPCLK_CNTL to get the currently
+ * programmed DID DENTIST_DPREFCLK_WDIVIDER*/
+ REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider);
+
+ /* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/
+ target_div = dal_divider_range_get_divider(
+ clk_dce->divider_ranges,
+ DIVIDER_RANGE_MAX,
+ dprefclk_wdivider);
+
+ if (target_div != INVALID_DIVIDER) {
+ /* Calculate the current DFS clock, in kHz.*/
+ dp_ref_clk_khz = (DIVIDER_RANGE_SCALE_FACTOR
+ * clk_dce->dentist_vco_freq_khz) / target_div;
+ }
+
+ /* SW will adjust DP REF Clock average value for all purposes
+ * (DP DTO / DP Audio DTO and DP GTC)
+ if clock is spread for all cases:
+ -if SS enabled on DP Ref clock and HW de-spreading enabled with SW
+ calculations for DS_INCR/DS_MODULO (this is planned to be default case)
+ -if SS enabled on DP Ref clock and HW de-spreading enabled with HW
+ calculations (not planned to be used, but average clock should still
+ be valid)
+ -if SS enabled on DP Ref clock and HW de-spreading disabled
+ (should not be case with CIK) then SW should program all rates
+ generated according to average value (case as with previous ASICs)
+ */
+ if (clk_dce->ss_on_gpu_pll && clk_dce->gpu_pll_ss_divider != 0) {
+ struct fixed32_32 ss_percentage = dal_fixed32_32_div_int(
+ dal_fixed32_32_from_fraction(
+ clk_dce->gpu_pll_ss_percentage,
+ clk_dce->gpu_pll_ss_divider), 200);
+ struct fixed32_32 adj_dp_ref_clk_khz;
+
+ ss_percentage = dal_fixed32_32_sub(dal_fixed32_32_one,
+ ss_percentage);
+ adj_dp_ref_clk_khz =
+ dal_fixed32_32_mul_int(
+ ss_percentage,
+ dp_ref_clk_khz);
+ dp_ref_clk_khz = dal_fixed32_32_floor(adj_dp_ref_clk_khz);
+ }
+
+ return dp_ref_clk_khz;
+}
+
+static enum dm_pp_clocks_state dce_get_required_clocks_state(
+ struct display_clock *clk,
+ struct state_dependent_clocks *req_clocks)
+{
+ struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
+ int i;
+ enum dm_pp_clocks_state low_req_clk;
+
+ /* Iterate from highest supported to lowest valid state, and update
+ * lowest RequiredState with the lowest state that satisfies
+ * all required clocks
+ */
+ for (i = clk->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--)
+ if (req_clocks->display_clk_khz >
+ clk_dce->max_clks_by_state[i].display_clk_khz
+ || req_clocks->pixel_clk_khz >
+ clk_dce->max_clks_by_state[i].pixel_clk_khz)
+ break;
+
+ low_req_clk = i + 1;
+ if (low_req_clk > clk->max_clks_state) {
+ dm_logger_write(clk->ctx->logger, LOG_WARNING,
+ "%s: clocks unsupported", __func__);
+ low_req_clk = DM_PP_CLOCKS_STATE_INVALID;
+ }
+
+ return low_req_clk;
+}
+
+static bool dce_clock_set_min_clocks_state(
+ struct display_clock *clk,
+ enum dm_pp_clocks_state clocks_state)
+{
+ struct dm_pp_power_level_change_request level_change_req = {
+ clocks_state };
+
+ if (clocks_state > clk->max_clks_state) {
+ /*Requested state exceeds max supported state.*/
+ dm_logger_write(clk->ctx->logger, LOG_WARNING,
+ "Requested state exceeds max supported state");
+ return false;
+ } else if (clocks_state == clk->cur_min_clks_state) {
+ /*if we're trying to set the same state, we can just return
+ * since nothing needs to be done*/
+ return true;
+ }
+
+ /* get max clock state from PPLIB */
+ if (dm_pp_apply_power_level_change_request(clk->ctx, &level_change_req))
+ clk->cur_min_clks_state = clocks_state;
+
+ return true;
+}
+
+static void dce_set_clock(
+ struct display_clock *clk,
+ uint32_t requested_clk_khz)
+{
+ struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
+ struct bp_pixel_clock_parameters pxl_clk_params = { 0 };
+ struct dc_bios *bp = clk->ctx->dc_bios;
+
+ /* Make sure requested clock isn't lower than minimum threshold*/
+ if (requested_clk_khz > 0)
+ requested_clk_khz = dm_max(requested_clk_khz,
+ clk_dce->dentist_vco_freq_khz / 64);
+
+ /* Prepare to program display clock*/
+ pxl_clk_params.target_pixel_clock = requested_clk_khz;
+ pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
+
+ bp->funcs->program_display_engine_pll(bp, &pxl_clk_params);
+
+ if (clk_dce->dfs_bypass_enabled) {
+
+ /* Cache the fixed display clock*/
+ clk_dce->dfs_bypass_disp_clk =
+ pxl_clk_params.dfs_bypass_display_clock;
+ }
+
+ /* from power down, we need mark the clock state as ClocksStateNominal
+ * from HWReset, so when resume we will call pplib voltage regulator.*/
+ if (requested_clk_khz == 0)
+ clk->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
+}
+
+#define PSR_SET_WAITLOOP 0x31
+
+union dce110_dmcu_psr_config_data_wait_loop_reg1 {
+ struct {
+ unsigned int wait_loop:16; /* [15:0] */
+ unsigned int reserved:16; /* [31:16] */
+ } bits;
+ unsigned int u32;
+};
+
+static void dce_psr_wait_loop(
+ struct dce_disp_clk *clk_dce, unsigned int display_clk_khz)
+{
+ struct dc_context *ctx = clk_dce->base.ctx;
+ union dce110_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
+
+ /* waitDMCUReadyForCmd */
+ REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 100);
+
+ masterCmdData1.u32 = 0;
+ masterCmdData1.bits.wait_loop = display_clk_khz / 1000 / 7;
+ dm_write_reg(ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
+
+ /* setDMCUParam_Cmd */
+ REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
+
+ /* notifyDMCUMsg */
+ REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
+}
+
+static void dce_psr_set_clock(
+ struct display_clock *clk,
+ uint32_t requested_clk_khz)
+{
+ struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
+
+ dce_set_clock(clk, requested_clk_khz);
+ dce_psr_wait_loop(clk_dce, requested_clk_khz);
+}
+
+static void polaris_set_clock(
+ struct display_clock *clk,
+ uint32_t requested_clk_khz)
+{
+ struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
+ struct bp_set_dce_clock_parameters dce_clk_params;
+ struct dc_bios *bp = clk->ctx->dc_bios;
+
+ /* Prepare to program display clock*/
+ memset(&dce_clk_params, 0, sizeof(dce_clk_params));
+
+ /* Make sure requested clock isn't lower than minimum threshold*/
+ if (requested_clk_khz > 0)
+ requested_clk_khz = dm_max(requested_clk_khz,
+ clk_dce->dentist_vco_freq_khz / 64);
+
+ dce_clk_params.target_clock_frequency = requested_clk_khz;
+ dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
+ dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK;
+
+ bp->funcs->set_dce_clock(bp, &dce_clk_params);
+
+ /* from power down, we need mark the clock state as ClocksStateNominal
+ * from HWReset, so when resume we will call pplib voltage regulator.*/
+ if (requested_clk_khz == 0)
+ clk->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
+
+ /*Program DP ref Clock*/
+ /*VBIOS will determine DPREFCLK frequency, so we don't set it*/
+ dce_clk_params.target_clock_frequency = 0;
+ dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK;
+ dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = 0;
+
+ bp->funcs->set_dce_clock(bp, &dce_clk_params);
+}
+
+static void dce_clock_read_integrated_info(struct dce_disp_clk *clk_dce)
+{
+ struct dc_debug *debug = &clk_dce->base.ctx->dc->debug;
+ struct dc_bios *bp = clk_dce->base.ctx->dc_bios;
+ struct integrated_info info = { 0 };
+ struct firmware_info fw_info = { 0 };
+ int i;
+
+ if (bp->integrated_info)
+ info = *bp->integrated_info;
+
+ clk_dce->dentist_vco_freq_khz = info.dentist_vco_freq;
+ if (clk_dce->dentist_vco_freq_khz == 0) {
+ bp->funcs->get_firmware_info(bp, &fw_info);
+ clk_dce->dentist_vco_freq_khz =
+ fw_info.smu_gpu_pll_output_freq;
+ if (clk_dce->dentist_vco_freq_khz == 0)
+ clk_dce->dentist_vco_freq_khz = 3600000;
+ }
+
+ /*update the maximum display clock for each power state*/
+ for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
+ enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID;
+
+ switch (i) {
+ case 0:
+ clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW;
+ break;
+
+ case 1:
+ clk_state = DM_PP_CLOCKS_STATE_LOW;
+ break;
+
+ case 2:
+ clk_state = DM_PP_CLOCKS_STATE_NOMINAL;
+ break;
+
+ case 3:
+ clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE;
+ break;
+
+ default:
+ clk_state = DM_PP_CLOCKS_STATE_INVALID;
+ break;
+ }
+
+ /*Do not allow bad VBIOS/SBIOS to override with invalid values,
+ * check for > 100MHz*/
+ if (info.disp_clk_voltage[i].max_supported_clk >= 100000)
+ clk_dce->max_clks_by_state[clk_state].display_clk_khz =
+ info.disp_clk_voltage[i].max_supported_clk;
+ }
+
+ if (!debug->disable_dfs_bypass)
+ if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
+ clk_dce->dfs_bypass_enabled = true;
+
+ clk_dce->use_max_disp_clk = debug->max_disp_clk;
+}
+
+static void dce_clock_read_ss_info(struct dce_disp_clk *clk_dce)
+{
+ struct dc_bios *bp = clk_dce->base.ctx->dc_bios;
+ int ss_info_num = bp->funcs->get_ss_entry_number(
+ bp, AS_SIGNAL_TYPE_GPU_PLL);
+
+ if (ss_info_num) {
+ struct spread_spectrum_info info = { 0 };
+ enum bp_result result = bp->funcs->get_spread_spectrum_info(
+ bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);
+
+ /* Based on VBIOS, VBIOS will keep entry for GPU PLL SS
+ * even if SS not enabled and in that case
+ * SSInfo.spreadSpectrumPercentage !=0 would be sign
+ * that SS is enabled
+ */
+ if (result == BP_RESULT_OK &&
+ info.spread_spectrum_percentage != 0) {
+ clk_dce->ss_on_gpu_pll = true;
+ clk_dce->gpu_pll_ss_divider = info.spread_percentage_divider;
+
+ if (info.type.CENTER_MODE == 0) {
+ /* Currently for DP Reference clock we
+ * need only SS percentage for
+ * downspread */
+ clk_dce->gpu_pll_ss_percentage =
+ info.spread_spectrum_percentage;
+ }
+ }
+
+ }
+}
+
+static const struct display_clock_funcs dce112_funcs = {
+ .get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq,
+ .get_required_clocks_state = dce_get_required_clocks_state,
+ .set_min_clocks_state = dce_clock_set_min_clocks_state,
+ .set_clock = polaris_set_clock
+};
+
+static const struct display_clock_funcs dce110_funcs = {
+ .get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq,
+ .get_required_clocks_state = dce_get_required_clocks_state,
+ .set_min_clocks_state = dce_clock_set_min_clocks_state,
+ .set_clock = dce_psr_set_clock
+};
+
+static const struct display_clock_funcs dce_funcs = {
+ .get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq,
+ .get_required_clocks_state = dce_get_required_clocks_state,
+ .set_min_clocks_state = dce_clock_set_min_clocks_state,
+ .set_clock = dce_set_clock
+};
+
+static void dce_disp_clk_construct(
+ struct dce_disp_clk *clk_dce,
+ struct dc_context *ctx,
+ const struct dce_disp_clk_registers *regs,
+ const struct dce_disp_clk_shift *clk_shift,
+ const struct dce_disp_clk_mask *clk_mask)
+{
+ struct display_clock *base = &clk_dce->base;
+
+ base->ctx = ctx;
+ base->funcs = &dce_funcs;
+
+ clk_dce->regs = regs;
+ clk_dce->clk_shift = clk_shift;
+ clk_dce->clk_mask = clk_mask;
+
+ clk_dce->dfs_bypass_disp_clk = 0;
+ clk_dce->gpu_pll_ss_percentage = 0;
+ clk_dce->gpu_pll_ss_divider = 1000;
+ clk_dce->ss_on_gpu_pll = false;
+ base->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
+ base->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
+
+ dce_clock_read_integrated_info(clk_dce);
+ dce_clock_read_ss_info(clk_dce);
+
+ dal_divider_range_construct(
+ &clk_dce->divider_ranges[DIVIDER_RANGE_01],
+ DIVIDER_RANGE_01_START,
+ DIVIDER_RANGE_01_STEP_SIZE,
+ DIVIDER_RANGE_01_BASE_DIVIDER_ID,
+ DIVIDER_RANGE_02_BASE_DIVIDER_ID);
+ dal_divider_range_construct(
+ &clk_dce->divider_ranges[DIVIDER_RANGE_02],
+ DIVIDER_RANGE_02_START,
+ DIVIDER_RANGE_02_STEP_SIZE,
+ DIVIDER_RANGE_02_BASE_DIVIDER_ID,
+ DIVIDER_RANGE_03_BASE_DIVIDER_ID);
+ dal_divider_range_construct(
+ &clk_dce->divider_ranges[DIVIDER_RANGE_03],
+ DIVIDER_RANGE_03_START,
+ DIVIDER_RANGE_03_STEP_SIZE,
+ DIVIDER_RANGE_03_BASE_DIVIDER_ID,
+ DIVIDER_RANGE_MAX_DIVIDER_ID);
+}
+
+struct display_clock *dce_disp_clk_create(
+ struct dc_context *ctx,
+ const struct dce_disp_clk_registers *regs,
+ const struct dce_disp_clk_shift *clk_shift,
+ const struct dce_disp_clk_mask *clk_mask)
+{
+ struct dce_disp_clk *clk_dce = dm_alloc(sizeof(*clk_dce));
+
+ if (clk_dce == NULL) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
+
+ dce_disp_clk_construct(
+ clk_dce, ctx, regs, clk_shift, clk_mask);
+
+ return &clk_dce->base;
+}
+
+struct display_clock *dce110_disp_clk_create(
+ struct dc_context *ctx,
+ const struct dce_disp_clk_registers *regs,
+ const struct dce_disp_clk_shift *clk_shift,
+ const struct dce_disp_clk_mask *clk_mask)
+{
+ struct dce_disp_clk *clk_dce = dm_alloc(sizeof(*clk_dce));
+
+ if (clk_dce == NULL) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
+
+ dce_disp_clk_construct(
+ clk_dce, ctx, regs, clk_shift, clk_mask);
+
+ clk_dce->base.funcs = &dce110_funcs;
+
+ return &clk_dce->base;
+}
+
+struct display_clock *dce112_disp_clk_create(
+ struct dc_context *ctx,
+ const struct dce_disp_clk_registers *regs,
+ const struct dce_disp_clk_shift *clk_shift,
+ const struct dce_disp_clk_mask *clk_mask)
+{
+ struct dce_disp_clk *clk_dce = dm_alloc(sizeof(*clk_dce));
+
+ if (clk_dce == NULL) {
+ BREAK_TO_DEBUGGER();
+ return NULL;
+ }
+
+ dce_disp_clk_construct(
+ clk_dce, ctx, regs, clk_shift, clk_mask);
+
+ clk_dce->base.funcs = &dce112_funcs;
+
+ return &clk_dce->base;
+}
+
+void dce_disp_clk_destroy(struct display_clock **disp_clk)
+{
+ struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(*disp_clk);
+
+ dm_free(clk_dce);
+ *disp_clk = NULL;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
new file mode 100644
index 000000000000..e3b23749f0a2
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright 2012-16 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#ifndef _DCE_CLOCKS_H_
+#define _DCE_CLOCKS_H_
+
+#include "display_clock_interface.h"
+#include "../gpu/divider_range.h"
+
+
+#define TO_DCE_CLOCKS(clocks)\
+ container_of(clocks, struct dce_disp_clk, base)
+
+#define CLK_COMMON_REG_LIST_DCE_BASE() \
+ .DPREFCLK_CNTL = mmDPREFCLK_CNTL, \
+ .DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL, \
+ .MASTER_COMM_DATA_REG1 = mmMASTER_COMM_DATA_REG1, \
+ .MASTER_COMM_CMD_REG = mmMASTER_COMM_CMD_REG, \
+ .MASTER_COMM_CNTL_REG = mmMASTER_COMM_CNTL_REG
+
+#define CLK_SF(reg_name, field_name, post_fix)\
+ .field_name = reg_name ## __ ## field_name ## post_fix
+
+#define CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
+ CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \
+ CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh), \
+ CLK_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
+ CLK_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh)
+
+
+#define CLK_REG_FIELD_LIST(type) \
+ type DPREFCLK_SRC_SEL; \
+ type DENTIST_DPREFCLK_WDIVIDER; \
+ type MASTER_COMM_CMD_REG_BYTE0; \
+ type MASTER_COMM_INTERRUPT
+
+struct dce_disp_clk_shift {
+ CLK_REG_FIELD_LIST(uint8_t);
+};
+
+struct dce_disp_clk_mask {
+ CLK_REG_FIELD_LIST(uint32_t);
+};
+
+struct dce_disp_clk_registers {
+ uint32_t DPREFCLK_CNTL;
+ uint32_t DENTIST_DISPCLK_CNTL;
+ uint32_t MASTER_COMM_DATA_REG1;
+ uint32_t MASTER_COMM_CMD_REG;
+ uint32_t MASTER_COMM_CNTL_REG;
+};
+
+/* Array identifiers and count for the divider ranges.*/
+enum divider_range_count {
+ DIVIDER_RANGE_01 = 0,
+ DIVIDER_RANGE_02,
+ DIVIDER_RANGE_03,
+ DIVIDER_RANGE_MAX /* == 3*/
+};
+
+struct dce_disp_clk {
+ struct display_clock base;
+ const struct dce_disp_clk_registers *regs;
+ const struct dce_disp_clk_shift *clk_shift;
+ const struct dce_disp_clk_mask *clk_mask;
+
+ struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES];
+ struct divider_range divider_ranges[DIVIDER_RANGE_MAX];
+
+ bool use_max_disp_clk;
+ uint32_t dentist_vco_freq_khz;
+
+ /* Cache the status of DFS-bypass feature*/
+ bool dfs_bypass_enabled;
+ /* Cache the display clock returned by VBIOS if DFS-bypass is enabled.
+ * This is basically "Crystal Frequency In KHz" (XTALIN) frequency */
+ uint32_t dfs_bypass_disp_clk;
+
+ /* Flag for Enabled SS on GPU PLL */
+ bool ss_on_gpu_pll;
+ /* GPU PLL SS percentage (if down-spread enabled) */
+ uint32_t gpu_pll_ss_percentage;
+ /* GPU PLL SS percentage Divider (100 or 1000) */
+ uint32_t gpu_pll_ss_divider;
+
+
+};
+
+
+struct display_clock *dce_disp_clk_create(
+ struct dc_context *ctx,
+ const struct dce_disp_clk_registers *regs,
+ const struct dce_disp_clk_shift *clk_shift,
+ const struct dce_disp_clk_mask *clk_mask);
+
+struct display_clock *dce110_disp_clk_create(
+ struct dc_context *ctx,
+ const struct dce_disp_clk_registers *regs,
+ const struct dce_disp_clk_shift *clk_shift,
+ const struct dce_disp_clk_mask *clk_mask);
+
+struct display_clock *dce112_disp_clk_create(
+ struct dc_context *ctx,
+ const struct dce_disp_clk_registers *regs,
+ const struct dce_disp_clk_shift *clk_shift,
+ const struct dce_disp_clk_mask *clk_mask);
+
+void dce_disp_clk_destroy(struct display_clock **disp_clk);
+
+#endif /* _DCE_CLOCKS_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 5716ce1e58f4..c97416f7bc93 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -40,6 +40,7 @@
#include "dce110/dce110_ipp.h"
#include "dce/dce_transform.h"
#include "dce110/dce110_opp.h"
+#include "dce/dce_clocks.h"
#include "dce/dce_clock_source.h"
#include "dce/dce_audio.h"
#include "dce/dce_hwseq.h"
@@ -200,6 +201,18 @@ static const struct dce110_ipp_reg_offsets dce100_ipp_reg_offsets[] = {
.reg_name = mm ## block ## id ## _ ## reg_name
+static const struct dce_disp_clk_registers disp_clk_regs = {
+ CLK_COMMON_REG_LIST_DCE_BASE()
+};
+
+static const struct dce_disp_clk_shift disp_clk_shift = {
+ CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
+};
+
+static const struct dce_disp_clk_mask disp_clk_mask = {
+ CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
+};
+
#define transform_regs(id)\
[id] = {\
XFM_COMMON_REG_LIST_DCE100(id)\
@@ -717,9 +730,7 @@ static void destruct(struct dce110_resource_pool *pool)
}
if (pool->base.display_clock != NULL)
- pool->base.display_clock->funcs->destroy(
- &pool->base.display_clock);
- pool->base.display_clock = NULL;
+ dce_disp_clk_destroy(&pool->base.display_clock);
if (pool->base.irqs != NULL)
dal_irq_service_destroy(&pool->base.irqs);
@@ -970,7 +981,10 @@ static bool construct(
}
}
- pool->base.display_clock = dal_display_clock_dce110_create(ctx);
+ pool->base.display_clock = dce_disp_clk_create(ctx,
+ &disp_clk_regs,
+ &disp_clk_shift,
+ &disp_clk_mask);
if (pool->base.display_clock == NULL) {
dm_error("DC: failed to create display clock!\n");
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 8682c8b2a547..fa601f7f0b5a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -45,6 +45,7 @@
#include "dce110/dce110_transform_v.h"
#include "dce110/dce110_opp.h"
#include "dce110/dce110_opp_v.h"
+#include "dce/dce_clocks.h"
#include "dce/dce_clock_source.h"
#include "dce/dce_hwseq.h"
#include "dce110/dce110_hw_sequencer.h"
@@ -187,6 +188,17 @@ static const struct dce110_ipp_reg_offsets dce110_ipp_reg_offsets[] = {
#define SRI(reg_name, block, id)\
.reg_name = mm ## block ## id ## _ ## reg_name
+static const struct dce_disp_clk_registers disp_clk_regs = {
+ CLK_COMMON_REG_LIST_DCE_BASE()
+};
+
+static const struct dce_disp_clk_shift disp_clk_shift = {
+ CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
+};
+
+static const struct dce_disp_clk_mask disp_clk_mask = {
+ CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
+};
#define transform_regs(id)\
[id] = {\
@@ -699,11 +711,8 @@ static void destruct(struct dce110_resource_pool *pool)
}
}
- if (pool->base.display_clock != NULL) {
- pool->base.display_clock->funcs->destroy(
- &pool->base.display_clock);
- pool->base.display_clock = NULL;
- }
+ if (pool->base.display_clock != NULL)
+ dce_disp_clk_destroy(&pool->base.display_clock);
if (pool->base.irqs != NULL) {
dal_irq_service_destroy(&pool->base.irqs);
@@ -1261,7 +1270,10 @@ static bool construct(
}
}
- pool->base.display_clock = dal_display_clock_dce110_create(ctx);
+ pool->base.display_clock = dce110_disp_clk_create(ctx,
+ &disp_clk_regs,
+ &disp_clk_shift,
+ &disp_clk_mask);
if (pool->base.display_clock == NULL) {
dm_error("DC: failed to create display clock!\n");
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index c50a215172b7..3a478300b848 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -41,6 +41,7 @@
#include "dce/dce_audio.h"
#include "dce112/dce112_opp.h"
#include "dce110/dce110_ipp.h"
+#include "dce/dce_clocks.h"
#include "dce/dce_clock_source.h"
#include "dce/dce_hwseq.h"
@@ -204,6 +205,19 @@ static const struct dce110_ipp_reg_offsets ipp_reg_offsets[] = {
#define SRI(reg_name, block, id)\
.reg_name = mm ## block ## id ## _ ## reg_name
+
+static const struct dce_disp_clk_registers disp_clk_regs = {
+ CLK_COMMON_REG_LIST_DCE_BASE()
+};
+
+static const struct dce_disp_clk_shift disp_clk_shift = {
+ CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
+};
+
+static const struct dce_disp_clk_mask disp_clk_mask = {
+ CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
+};
+
#define transform_regs(id)\
[id] = {\
XFM_COMMON_REG_LIST_DCE110(id)\
@@ -733,11 +747,8 @@ static void destruct(struct dce110_resource_pool *pool)
}
}
- if (pool->base.display_clock != NULL) {
- pool->base.display_clock->funcs->destroy(
- &pool->base.display_clock);
- pool->base.display_clock = NULL;
- }
+ if (pool->base.display_clock != NULL)
+ dce_disp_clk_destroy(&pool->base.display_clock);
if (pool->base.irqs != NULL) {
dal_irq_service_destroy(&pool->base.irqs);
@@ -1299,9 +1310,10 @@ static bool construct(
}
}
- pool->base.display_clock = dal_display_clock_dce112_create(
- ctx);
-
+ pool->base.display_clock = dce112_disp_clk_create(ctx,
+ &disp_clk_regs,
+ &disp_clk_shift,
+ &disp_clk_mask);
if (pool->base.display_clock == NULL) {
dm_error("DC: failed to create display clock!\n");
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 1d2a31e34617..517d42dfff0c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -45,6 +45,7 @@
#include "dce/dce_transform.h"
#include "dce80/dce80_opp.h"
#include "dce110/dce110_ipp.h"
+#include "dce/dce_clocks.h"
#include "dce/dce_clock_source.h"
#include "dce/dce_audio.h"
#include "dce/dce_hwseq.h"
@@ -215,6 +216,19 @@ static const struct dce110_ipp_reg_offsets ipp_reg_offsets[] = {
#define SRI(reg_name, block, id)\
.reg_name = mm ## block ## id ## _ ## reg_name
+
+static const struct dce_disp_clk_registers disp_clk_regs = {
+ CLK_COMMON_REG_LIST_DCE_BASE()
+};
+
+static const struct dce_disp_clk_shift disp_clk_shift = {
+ CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
+};
+
+static const struct dce_disp_clk_mask disp_clk_mask = {
+ CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
+};
+
#define transform_regs(id)\
[id] = {\
XFM_COMMON_REG_LIST_DCE_BASE(id)\
@@ -656,11 +670,8 @@ static void destruct(struct dce110_resource_pool *pool)
}
}
- if (pool->base.display_clock != NULL) {
- pool->base.display_clock->funcs->destroy(
- &pool->base.display_clock);
- pool->base.display_clock = NULL;
- }
+ if (pool->base.display_clock != NULL)
+ dce_disp_clk_destroy(&pool->base.display_clock);
if (pool->base.irqs != NULL) {
dal_irq_service_destroy(&pool->base.irqs);
@@ -857,47 +868,6 @@ static const struct resource_funcs dce80_res_pool_funcs = {
.validate_bandwidth = dce80_validate_bandwidth
};
-static enum dm_pp_clocks_state dce80_resource_convert_clock_state_pp_to_dc(
- enum dm_pp_clocks_state pp_clock_state)
-{
- enum dm_pp_clocks_state dc_clocks_state = DM_PP_CLOCKS_STATE_INVALID;
-
- switch (pp_clock_state) {
- case DM_PP_CLOCKS_STATE_INVALID:
- dc_clocks_state = DM_PP_CLOCKS_STATE_INVALID;
- break;
- case DM_PP_CLOCKS_STATE_ULTRA_LOW:
- dc_clocks_state = DM_PP_CLOCKS_STATE_ULTRA_LOW;
- break;
- case DM_PP_CLOCKS_STATE_LOW:
- dc_clocks_state = DM_PP_CLOCKS_STATE_LOW;
- break;
- case DM_PP_CLOCKS_STATE_NOMINAL:
- dc_clocks_state = DM_PP_CLOCKS_STATE_NOMINAL;
- break;
- case DM_PP_CLOCKS_STATE_PERFORMANCE:
- dc_clocks_state = DM_PP_CLOCKS_STATE_PERFORMANCE;
- break;
- case DM_PP_CLOCKS_DPM_STATE_LEVEL_4:
- dc_clocks_state = DM_PP_CLOCKS_DPM_STATE_LEVEL_4;
- break;
- case DM_PP_CLOCKS_DPM_STATE_LEVEL_5:
- dc_clocks_state = DM_PP_CLOCKS_DPM_STATE_LEVEL_5;
- break;
- case DM_PP_CLOCKS_DPM_STATE_LEVEL_6:
- dc_clocks_state = DM_PP_CLOCKS_DPM_STATE_LEVEL_6;
- break;
- case DM_PP_CLOCKS_DPM_STATE_LEVEL_7:
- dc_clocks_state = DM_PP_CLOCKS_DPM_STATE_LEVEL_7;
- break;
- default:
- dc_clocks_state = DM_PP_CLOCKS_STATE_INVALID;
- break;
- }
-
- return dc_clocks_state;
-}
-
static bool construct(
uint8_t num_virtual_links,
struct core_dc *dc,
@@ -967,7 +937,10 @@ static bool construct(
}
}
- pool->base.display_clock = dal_display_clock_dce80_create(ctx);
+ pool->base.display_clock = dce_disp_clk_create(ctx,
+ &disp_clk_regs,
+ &disp_clk_shift,
+ &disp_clk_mask);
if (pool->base.display_clock == NULL) {
dm_error("DC: failed to create display clock!\n");
BREAK_TO_DEBUGGER();
@@ -977,8 +950,7 @@ static bool construct(
if (dm_pp_get_static_clocks(ctx, &static_clk_info))
pool->base.display_clock->max_clks_state =
- dce80_resource_convert_clock_state_pp_to_dc(
- static_clk_info.max_clocks_state);
+ static_clk_info.max_clocks_state;
{
struct irq_service_init_data init_data;
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
index 44bad17fa318..460971dc3a70 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
@@ -43,15 +43,17 @@ enum dm_pp_clocks_state {
/* Starting from DCE11, Max 8 levels of DPM state supported. */
DM_PP_CLOCKS_DPM_STATE_LEVEL_INVALID = DM_PP_CLOCKS_STATE_INVALID,
- DM_PP_CLOCKS_DPM_STATE_LEVEL_0 = DM_PP_CLOCKS_STATE_ULTRA_LOW,
- DM_PP_CLOCKS_DPM_STATE_LEVEL_1 = DM_PP_CLOCKS_STATE_LOW,
- DM_PP_CLOCKS_DPM_STATE_LEVEL_2 = DM_PP_CLOCKS_STATE_NOMINAL,
+ DM_PP_CLOCKS_DPM_STATE_LEVEL_0,
+ DM_PP_CLOCKS_DPM_STATE_LEVEL_1,
+ DM_PP_CLOCKS_DPM_STATE_LEVEL_2,
/* to be backward compatible */
- DM_PP_CLOCKS_DPM_STATE_LEVEL_3 = DM_PP_CLOCKS_STATE_PERFORMANCE,
- DM_PP_CLOCKS_DPM_STATE_LEVEL_4 = DM_PP_CLOCKS_DPM_STATE_LEVEL_3 + 1,
- DM_PP_CLOCKS_DPM_STATE_LEVEL_5 = DM_PP_CLOCKS_DPM_STATE_LEVEL_4 + 1,
- DM_PP_CLOCKS_DPM_STATE_LEVEL_6 = DM_PP_CLOCKS_DPM_STATE_LEVEL_5 + 1,
- DM_PP_CLOCKS_DPM_STATE_LEVEL_7 = DM_PP_CLOCKS_DPM_STATE_LEVEL_6 + 1,
+ DM_PP_CLOCKS_DPM_STATE_LEVEL_3,
+ DM_PP_CLOCKS_DPM_STATE_LEVEL_4,
+ DM_PP_CLOCKS_DPM_STATE_LEVEL_5,
+ DM_PP_CLOCKS_DPM_STATE_LEVEL_6,
+ DM_PP_CLOCKS_DPM_STATE_LEVEL_7,
+
+ DM_PP_CLOCKS_MAX_STATES
};
struct dm_pp_gpu_clock_range {
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/Makefile b/drivers/gpu/drm/amd/display/dc/gpu/Makefile
index 0b99a7474950..6ab4078405f2 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/gpu/Makefile
@@ -10,23 +10,8 @@ AMD_DAL_GPU = $(addprefix $(AMDDALPATH)/dc/gpu/,$(GPU))
AMD_DISPLAY_FILES += $(AMD_DAL_GPU)
###############################################################################
-# DCE 80 family
-###############################################################################
-GPU_DCE80 = display_clock_dce80.o
-
-AMD_DAL_GPU_DCE80 = $(addprefix $(AMDDALPATH)/dc/gpu/dce80/,$(GPU_DCE80))
-
-AMD_DISPLAY_FILES += $(AMD_DAL_GPU_DCE80)
-
-
-###############################################################################
# DCE 110 family
###############################################################################
-GPU_DCE110 = display_clock_dce110.o
-
-AMD_DAL_GPU_DCE110 = $(addprefix $(AMDDALPATH)/dc/gpu/dce110/,$(GPU_DCE110))
-
-AMD_DISPLAY_FILES += $(AMD_DAL_GPU_DCE110)
GPU_DCE112 = display_clock_dce112.o
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c
deleted file mode 100644
index 9dabaac2c550..000000000000
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c
+++ /dev/null
@@ -1,516 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-#include "dce/dce_11_0_d.h"
-#include "dce/dce_11_0_sh_mask.h"
-
-#include "include/bios_parser_interface.h"
-#include "include/fixed32_32.h"
-#include "include/logger_interface.h"
-
-#include "../divider_range.h"
-
-#include "display_clock_dce110.h"
-#include "dc.h"
-
-#define FROM_DISPLAY_CLOCK(base) \
- container_of(base, struct display_clock_dce110, disp_clk_base)
-
-#define PSR_SET_WAITLOOP 0x31
-
-static struct state_dependent_clocks max_clks_by_state[] = {
-/*ClocksStateInvalid - should not be used*/
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
-{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
-/*ClocksStateLow*/
-{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
-/*ClocksStateNominal*/
-{ .display_clk_khz = 467000, .pixel_clk_khz = 400000 },
-/*ClocksStatePerformance*/
-{ .display_clk_khz = 643000, .pixel_clk_khz = 400000 } };
-
-/* Starting point for each divider range.*/
-enum divider_range_start {
- DIVIDER_RANGE_01_START = 200, /* 2.00*/
- DIVIDER_RANGE_02_START = 1600, /* 16.00*/
- DIVIDER_RANGE_03_START = 3200, /* 32.00*/
- DIVIDER_RANGE_SCALE_FACTOR = 100 /* Results are scaled up by 100.*/
-};
-
-/* Array identifiers and count for the divider ranges.*/
-enum divider_range_count {
- DIVIDER_RANGE_01 = 0,
- DIVIDER_RANGE_02,
- DIVIDER_RANGE_03,
- DIVIDER_RANGE_MAX /* == 3*/
-};
-
-/* Ranges for divider identifiers (Divider ID or DID)
- mmDENTIST_DISPCLK_CNTL.DENTIST_DISPCLK_WDIVIDER*/
-enum divider_id_register_setting {
- DIVIDER_RANGE_01_BASE_DIVIDER_ID = 0X08,
- DIVIDER_RANGE_02_BASE_DIVIDER_ID = 0X40,
- DIVIDER_RANGE_03_BASE_DIVIDER_ID = 0X60,
- DIVIDER_RANGE_MAX_DIVIDER_ID = 0X80
-};
-
-/* Step size between each divider within a range.
- Incrementing the DENTIST_DISPCLK_WDIVIDER by one
- will increment the divider by this much.*/
-enum divider_range_step_size {
- DIVIDER_RANGE_01_STEP_SIZE = 25, /* 0.25*/
- DIVIDER_RANGE_02_STEP_SIZE = 50, /* 0.50*/
- DIVIDER_RANGE_03_STEP_SIZE = 100 /* 1.00 */
-};
-
-union dce110_dmcu_psr_config_data_wait_loop_reg1 {
- struct {
- unsigned int waitLoop:16; /* [15:0] */
- unsigned int reserved:16; /* [31:16] */
- } bits;
- unsigned int u32All;
-};
-
-static struct divider_range divider_ranges[DIVIDER_RANGE_MAX];
-
-#define DCE110_DFS_BYPASS_THRESHOLD_KHZ 400000
-/*****************************************************************************
- * static functions
- *****************************************************************************/
-
-static bool dce110_set_min_clocks_state(
- struct display_clock *dc,
- enum dm_pp_clocks_state clocks_state)
-{
- struct dm_pp_power_level_change_request level_change_req = {
- clocks_state };
-
- if (clocks_state > dc->max_clks_state) {
- /*Requested state exceeds max supported state.*/
- dm_logger_write(dc->ctx->logger, LOG_WARNING,
- "Requested state exceeds max supported state");
- return false;
- } else if (clocks_state == dc->cur_min_clks_state) {
- /*if we're trying to set the same state, we can just return
- * since nothing needs to be done*/
- return true;
- }
-
- /* get max clock state from PPLIB */
- if (dm_pp_apply_power_level_change_request(dc->ctx, &level_change_req))
- dc->cur_min_clks_state = clocks_state;
-
- return true;
-}
-
-static uint32_t get_dp_ref_clk_frequency(struct display_clock *dc)
-{
- uint32_t dispclk_cntl_value;
- uint32_t dp_ref_clk_cntl_value;
- uint32_t dp_ref_clk_cntl_src_sel_value;
- uint32_t dp_ref_clk_khz = 600000;
- uint32_t target_div = INVALID_DIVIDER;
- struct display_clock_dce110 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-
- /* ASSERT DP Reference Clock source is from DFS*/
- dp_ref_clk_cntl_value = dm_read_reg(dc->ctx,
- mmDPREFCLK_CNTL);
-
- dp_ref_clk_cntl_src_sel_value =
- get_reg_field_value(
- dp_ref_clk_cntl_value,
- DPREFCLK_CNTL, DPREFCLK_SRC_SEL);
-
- ASSERT(dp_ref_clk_cntl_src_sel_value == 0);
-
- /* Read the mmDENTIST_DISPCLK_CNTL to get the currently
- * programmed DID DENTIST_DPREFCLK_WDIVIDER*/
- dispclk_cntl_value = dm_read_reg(dc->ctx,
- mmDENTIST_DISPCLK_CNTL);
-
- /* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/
- target_div = dal_divider_range_get_divider(
- divider_ranges,
- DIVIDER_RANGE_MAX,
- get_reg_field_value(dispclk_cntl_value,
- DENTIST_DISPCLK_CNTL,
- DENTIST_DPREFCLK_WDIVIDER));
-
- if (target_div != INVALID_DIVIDER) {
- /* Calculate the current DFS clock, in kHz.*/
- dp_ref_clk_khz = (DIVIDER_RANGE_SCALE_FACTOR
- * disp_clk->dentist_vco_freq_khz) / target_div;
- }
-
- /* SW will adjust DP REF Clock average value for all purposes
- * (DP DTO / DP Audio DTO and DP GTC)
- if clock is spread for all cases:
- -if SS enabled on DP Ref clock and HW de-spreading enabled with SW
- calculations for DS_INCR/DS_MODULO (this is planned to be default case)
- -if SS enabled on DP Ref clock and HW de-spreading enabled with HW
- calculations (not planned to be used, but average clock should still
- be valid)
- -if SS enabled on DP Ref clock and HW de-spreading disabled
- (should not be case with CIK) then SW should program all rates
- generated according to average value (case as with previous ASICs)
- */
- if ((disp_clk->ss_on_gpu_pll) && (disp_clk->gpu_pll_ss_divider != 0)) {
- struct fixed32_32 ss_percentage = dal_fixed32_32_div_int(
- dal_fixed32_32_from_fraction(
- disp_clk->gpu_pll_ss_percentage,
- disp_clk->gpu_pll_ss_divider), 200);
- struct fixed32_32 adj_dp_ref_clk_khz;
-
- ss_percentage = dal_fixed32_32_sub(dal_fixed32_32_one,
- ss_percentage);
- adj_dp_ref_clk_khz =
- dal_fixed32_32_mul_int(
- ss_percentage,
- dp_ref_clk_khz);
- dp_ref_clk_khz = dal_fixed32_32_floor(adj_dp_ref_clk_khz);
- }
-
- return dp_ref_clk_khz;
-}
-
-static void destroy(struct display_clock **base)
-{
- struct display_clock_dce110 *dc110;
-
- dc110 = DCLCK110_FROM_BASE(*base);
-
- dm_free(dc110);
-
- *base = NULL;
-}
-
-static bool display_clock_integrated_info_construct(
- struct display_clock_dce110 *disp_clk)
-{
- struct dc_debug *debug = &disp_clk->disp_clk_base.ctx->dc->debug;
- struct dc_bios *bp = disp_clk->disp_clk_base.ctx->dc_bios;
- struct integrated_info info;
- struct firmware_info fw_info;
- uint32_t i;
- struct display_clock *base = &disp_clk->disp_clk_base;
-
- memset(&info, 0, sizeof(struct integrated_info));
- memset(&fw_info, 0, sizeof(struct firmware_info));
-
- if (bp->integrated_info)
- info = *bp->integrated_info;
-
- disp_clk->dentist_vco_freq_khz = info.dentist_vco_freq;
- if (disp_clk->dentist_vco_freq_khz == 0) {
- bp->funcs->get_firmware_info(bp, &fw_info);
- disp_clk->dentist_vco_freq_khz =
- fw_info.smu_gpu_pll_output_freq;
- if (disp_clk->dentist_vco_freq_khz == 0)
- disp_clk->dentist_vco_freq_khz = 3600000;
- }
-
- base->min_display_clk_threshold_khz =
- disp_clk->dentist_vco_freq_khz / 64;
-
- if (bp->integrated_info == NULL)
- return false;
-
- /*update the maximum display clock for each power state*/
- for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
- enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID;
-
- switch (i) {
- case 0:
- clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW;
- break;
-
- case 1:
- clk_state = DM_PP_CLOCKS_STATE_LOW;
- break;
-
- case 2:
- clk_state = DM_PP_CLOCKS_STATE_NOMINAL;
- break;
-
- case 3:
- clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE;
- break;
-
- default:
- clk_state = DM_PP_CLOCKS_STATE_INVALID;
- break;
- }
-
- /*Do not allow bad VBIOS/SBIOS to override with invalid values,
- * check for > 100MHz*/
- if (info.disp_clk_voltage[i].max_supported_clk >= 100000) {
- max_clks_by_state[clk_state].display_clk_khz =
- info.disp_clk_voltage[i].max_supported_clk;
- }
- }
-
- disp_clk->dfs_bypass_enabled = false;
- if (!debug->disable_dfs_bypass)
- if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
- disp_clk->dfs_bypass_enabled = true;
-
- disp_clk->use_max_disp_clk = debug->max_disp_clk;
-
- return true;
-}
-
-static enum dm_pp_clocks_state get_required_clocks_state(
- struct display_clock *dc,
- struct state_dependent_clocks *req_clocks)
-{
- int32_t i;
- struct display_clock_dce110 *disp_clk = DCLCK110_FROM_BASE(dc);
- enum dm_pp_clocks_state low_req_clk = dc->max_clks_state;
-
- if (!req_clocks) {
- /* NULL pointer*/
- dm_logger_write(dc->ctx->logger, LOG_WARNING,
- "%s: Invalid parameter",
- __func__);
- return DM_PP_CLOCKS_STATE_INVALID;
- }
-
- /* Iterate from highest supported to lowest valid state, and update
- * lowest RequiredState with the lowest state that satisfies
- * all required clocks
- */
- for (i = dc->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; --i) {
- if ((req_clocks->display_clk_khz <=
- max_clks_by_state[i].display_clk_khz) &&
- (req_clocks->pixel_clk_khz <=
- max_clks_by_state[i].pixel_clk_khz))
- low_req_clk = i;
- }
- return low_req_clk;
-}
-
-static void psr_wait_loop(struct dc_context *ctx, unsigned int display_clk_khz)
-{
- unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
- unsigned int dmcu_wait_reg_ready_interval = 100;
- unsigned int regValue;
- uint32_t masterCmd;
- uint32_t masterComCntl;
- union dce110_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
-
- /* waitDMCUReadyForCmd */
- do {
- dm_delay_in_microseconds(ctx, dmcu_wait_reg_ready_interval);
- regValue = dm_read_reg(ctx, mmMASTER_COMM_CNTL_REG);
- dmcu_max_retry_on_wait_reg_ready--;
- } while
- /* expected value is 0, loop while not 0*/
- ((MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK & regValue) &&
- dmcu_max_retry_on_wait_reg_ready > 0);
-
- masterCmdData1.u32All = 0;
- masterCmdData1.bits.waitLoop = display_clk_khz / 1000 / 7;
- dm_write_reg(ctx, mmMASTER_COMM_DATA_REG1, masterCmdData1.u32All);
-
- /* setDMCUParam_Cmd */
- masterCmd = dm_read_reg(ctx, mmMASTER_COMM_CMD_REG);
- set_reg_field_value(
- masterCmd,
- PSR_SET_WAITLOOP,
- MASTER_COMM_CMD_REG,
- MASTER_COMM_CMD_REG_BYTE0);
-
- dm_write_reg(ctx, mmMASTER_COMM_CMD_REG, masterCmd);
-
- /* notifyDMCUMsg */
- masterComCntl = dm_read_reg(ctx, mmMASTER_COMM_CNTL_REG);
- set_reg_field_value(
- masterComCntl,
- 1,
- MASTER_COMM_CNTL_REG,
- MASTER_COMM_INTERRUPT);
- dm_write_reg(ctx, mmMASTER_COMM_CNTL_REG, masterComCntl);
-}
-
-static void dce110_set_clock(
- struct display_clock *base,
- uint32_t requested_clk_khz)
-{
- struct bp_pixel_clock_parameters pxl_clk_params;
- struct display_clock_dce110 *dc = DCLCK110_FROM_BASE(base);
- struct dc_bios *bp = base->ctx->dc_bios;
-
- /* Prepare to program display clock*/
- memset(&pxl_clk_params, 0, sizeof(pxl_clk_params));
-
- /* Make sure requested clock isn't lower than minimum threshold*/
- if (requested_clk_khz > 0)
- requested_clk_khz = dm_max(requested_clk_khz,
- base->min_display_clk_threshold_khz);
-
- pxl_clk_params.target_pixel_clock = requested_clk_khz;
- pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
-
- bp->funcs->program_display_engine_pll(bp, &pxl_clk_params);
-
- if (dc->dfs_bypass_enabled) {
-
- /* Cache the fixed display clock*/
- dc->dfs_bypass_disp_clk =
- pxl_clk_params.dfs_bypass_display_clock;
- }
-
- /* from power down, we need mark the clock state as ClocksStateNominal
- * from HWReset, so when resume we will call pplib voltage regulator.*/
- if (requested_clk_khz == 0)
- base->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
-
- psr_wait_loop(base->ctx, requested_clk_khz);
-}
-
-
-static const struct display_clock_funcs funcs = {
- .destroy = destroy,
- .get_dp_ref_clk_frequency = get_dp_ref_clk_frequency,
- .get_required_clocks_state = get_required_clocks_state,
- .set_clock = dce110_set_clock,
- .set_min_clocks_state = dce110_set_min_clocks_state
-};
-
-static bool dal_display_clock_dce110_construct(
- struct display_clock_dce110 *dc110,
- struct dc_context *ctx)
-{
- struct display_clock *dc_base = &dc110->disp_clk_base;
- struct dc_bios *bp = ctx->dc_bios;
-
- dc_base->ctx = ctx;
- dc_base->min_display_clk_threshold_khz = 0;
-
- dc_base->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
-
- dc_base->funcs = &funcs;
-
- dc110->dfs_bypass_disp_clk = 0;
-
- if (!display_clock_integrated_info_construct(dc110))
- dm_logger_write(dc_base->ctx->logger, LOG_WARNING,
- "Cannot obtain VBIOS integrated info\n");
-
- dc110->gpu_pll_ss_percentage = 0;
- dc110->gpu_pll_ss_divider = 1000;
- dc110->ss_on_gpu_pll = false;
-
-/* Initially set max clocks state to nominal. This should be updated by
- * via a pplib call to DAL IRI eventually calling a
- * DisplayEngineClock_Dce110::StoreMaxClocksState(). This call will come in
- * on PPLIB init. This is from DCE5x. in case HW wants to use mixed method.*/
- dc_base->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
-
- dal_divider_range_construct(
- ÷r_ranges[DIVIDER_RANGE_01],
- DIVIDER_RANGE_01_START,
- DIVIDER_RANGE_01_STEP_SIZE,
- DIVIDER_RANGE_01_BASE_DIVIDER_ID,
- DIVIDER_RANGE_02_BASE_DIVIDER_ID);
- dal_divider_range_construct(
- ÷r_ranges[DIVIDER_RANGE_02],
- DIVIDER_RANGE_02_START,
- DIVIDER_RANGE_02_STEP_SIZE,
- DIVIDER_RANGE_02_BASE_DIVIDER_ID,
- DIVIDER_RANGE_03_BASE_DIVIDER_ID);
- dal_divider_range_construct(
- ÷r_ranges[DIVIDER_RANGE_03],
- DIVIDER_RANGE_03_START,
- DIVIDER_RANGE_03_STEP_SIZE,
- DIVIDER_RANGE_03_BASE_DIVIDER_ID,
- DIVIDER_RANGE_MAX_DIVIDER_ID);
-
- {
- uint32_t ss_info_num =
- bp->funcs->get_ss_entry_number(bp,
- AS_SIGNAL_TYPE_GPU_PLL);
-
- if (ss_info_num) {
- struct spread_spectrum_info info;
- enum bp_result result;
-
- memset(&info, 0, sizeof(info));
-
- result = bp->funcs->get_spread_spectrum_info(bp,
- AS_SIGNAL_TYPE_GPU_PLL,
- 0,
- &info);
-
- /* Based on VBIOS, VBIOS will keep entry for GPU PLL SS
- * even if SS not enabled and in that case
- * SSInfo.spreadSpectrumPercentage !=0 would be sign
- * that SS is enabled
- */
- if (result == BP_RESULT_OK &&
- info.spread_spectrum_percentage != 0) {
- dc110->ss_on_gpu_pll = true;
- dc110->gpu_pll_ss_divider =
- info.spread_percentage_divider;
-
- if (info.type.CENTER_MODE == 0) {
- /* Currently for DP Reference clock we
- * need only SS percentage for
- * downspread */
- dc110->gpu_pll_ss_percentage =
- info.spread_spectrum_percentage;
- }
- }
-
- }
- }
-
- return true;
-}
-
-/*****************************************************************************
- * public functions
- *****************************************************************************/
-
-struct display_clock *dal_display_clock_dce110_create(
- struct dc_context *ctx)
-{
- struct display_clock_dce110 *dc110;
-
- dc110 = dm_alloc(sizeof(struct display_clock_dce110));
-
- if (dc110 == NULL)
- return NULL;
-
- if (dal_display_clock_dce110_construct(dc110, ctx))
- return &dc110->disp_clk_base;
-
- dm_free(dc110);
-
- return NULL;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h
deleted file mode 100644
index 50b51c41b0d9..000000000000
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-#ifndef __DAL_DISPLAY_CLOCK_DCE110_H__
-#define __DAL_DISPLAY_CLOCK_DCE110_H__
-
-#include "display_clock_interface.h"
-
-struct display_clock_dce110 {
- struct display_clock disp_clk_base;
- bool use_max_disp_clk;
- uint32_t dentist_vco_freq_khz;
- /* Cache the status of DFS-bypass feature*/
- bool dfs_bypass_enabled;
- /* GPU PLL SS percentage (if down-spread enabled) */
- uint32_t gpu_pll_ss_percentage;
- /* GPU PLL SS percentage Divider (100 or 1000) */
- uint32_t gpu_pll_ss_divider;
- /* Flag for Enabled SS on GPU PLL */
- bool ss_on_gpu_pll;
- /* Cache the display clock returned by VBIOS if DFS-bypass is enabled.
- * This is basically "Crystal Frequency In KHz" (XTALIN) frequency */
- uint32_t dfs_bypass_disp_clk;
-};
-
-#define DCLCK110_FROM_BASE(dc_base) \
- container_of(dc_base, struct display_clock_dce110, disp_clk_base)
-
-#endif /* __DAL_DISPLAY_CLOCK_DCE110_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
index 930548bdd8b2..e0d67fb6c633 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
@@ -71,102 +71,6 @@ enum divider_range_step_size {
static struct divider_range divider_ranges[DIVIDER_RANGE_MAX];
-#define dce112_DFS_BYPASS_THRESHOLD_KHZ 400000
-
-static bool dce112_set_min_clocks_state(
- struct display_clock *dc,
- enum dm_pp_clocks_state clocks_state)
-{
- struct dm_pp_power_level_change_request level_change_req = {
- clocks_state };
-
- if (clocks_state > dc->max_clks_state) {
- /*Requested state exceeds max supported state.*/
- dm_logger_write(dc->ctx->logger, LOG_WARNING,
- "Requested state exceeds max supported state");
- return false;
- } else if (clocks_state == dc->cur_min_clks_state) {
- /*if we're trying to set the same state, we can just return
- * since nothing needs to be done*/
- return true;
- }
-
- /* get max clock state from PPLIB */
- if (dm_pp_apply_power_level_change_request(dc->ctx, &level_change_req))
- dc->cur_min_clks_state = clocks_state;
-
- return true;
-}
-
-static uint32_t get_dp_ref_clk_frequency(struct display_clock *dc)
-{
- uint32_t dispclk_cntl_value;
- uint32_t dp_ref_clk_cntl_value;
- uint32_t dp_ref_clk_cntl_src_sel_value;
- uint32_t dp_ref_clk_khz = 600000;
- uint32_t target_div = INVALID_DIVIDER;
- struct display_clock_dce112 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-
- /* ASSERT DP Reference Clock source is from DFS*/
- dp_ref_clk_cntl_value = dm_read_reg(dc->ctx,
- mmDPREFCLK_CNTL);
-
- dp_ref_clk_cntl_src_sel_value =
- get_reg_field_value(
- dp_ref_clk_cntl_value,
- DPREFCLK_CNTL, DPREFCLK_SRC_SEL);
-
- ASSERT(dp_ref_clk_cntl_src_sel_value == 0);
-
- /* Read the mmDENTIST_DISPCLK_CNTL to get the currently
- * programmed DID DENTIST_DPREFCLK_WDIVIDER*/
- dispclk_cntl_value = dm_read_reg(dc->ctx,
- mmDENTIST_DISPCLK_CNTL);
-
- /* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/
- target_div = dal_divider_range_get_divider(
- divider_ranges,
- DIVIDER_RANGE_MAX,
- get_reg_field_value(dispclk_cntl_value,
- DENTIST_DISPCLK_CNTL,
- DENTIST_DPREFCLK_WDIVIDER));
-
- if (target_div != INVALID_DIVIDER) {
- /* Calculate the current DFS clock, in kHz.*/
- dp_ref_clk_khz = (DIVIDER_RANGE_SCALE_FACTOR
- * disp_clk->dentist_vco_freq_khz) / target_div;
- }
-
- /* SW will adjust DP REF Clock average value for all purposes
- * (DP DTO / DP Audio DTO and DP GTC)
- if clock is spread for all cases:
- -if SS enabled on DP Ref clock and HW de-spreading enabled with SW
- calculations for DS_INCR/DS_MODULO (this is planned to be default case)
- -if SS enabled on DP Ref clock and HW de-spreading enabled with HW
- calculations (not planned to be used, but average clock should still
- be valid)
- -if SS enabled on DP Ref clock and HW de-spreading disabled
- (should not be case with CIK) then SW should program all rates
- generated according to average value (case as with previous ASICs)
- */
- if ((disp_clk->ss_on_gpu_pll) && (disp_clk->gpu_pll_ss_divider != 0)) {
- struct fixed32_32 ss_percentage = dal_fixed32_32_div_int(
- dal_fixed32_32_from_fraction(
- disp_clk->gpu_pll_ss_percentage,
- disp_clk->gpu_pll_ss_divider), 200);
- struct fixed32_32 adj_dp_ref_clk_khz;
-
- ss_percentage = dal_fixed32_32_sub(dal_fixed32_32_one,
- ss_percentage);
- adj_dp_ref_clk_khz =
- dal_fixed32_32_mul_int(
- ss_percentage,
- dp_ref_clk_khz);
- dp_ref_clk_khz = dal_fixed32_32_floor(adj_dp_ref_clk_khz);
- }
-
- return dp_ref_clk_khz;
-}
void dispclk_dce112_destroy(struct display_clock **base)
{
@@ -233,38 +137,6 @@ static bool display_clock_integrated_info_construct(
return true;
}
-enum dm_pp_clocks_state dispclk_dce112_get_required_clocks_state(
- struct display_clock *dc,
- struct state_dependent_clocks *req_clocks)
-{
- int32_t i;
- struct display_clock_dce112 *disp_clk = DCLCK112_FROM_BASE(dc);
- enum dm_pp_clocks_state low_req_clk = dc->max_clks_state;
-
- if (!req_clocks) {
- /* NULL pointer*/
- dm_logger_write(dc->ctx->logger, LOG_WARNING,
- "%s: Invalid parameter",
- __func__);
- return DM_PP_CLOCKS_STATE_INVALID;
- }
-
- /* Iterate from highest supported to lowest valid state, and update
- * lowest RequiredState with the lowest state that satisfies
- * all required clocks
- */
- for (i = dc->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; --i) {
- if ((req_clocks->display_clk_khz <=
- (disp_clk->max_clks_by_state + i)->
- display_clk_khz) &&
- (req_clocks->pixel_clk_khz <=
- (disp_clk->max_clks_by_state + i)->
- pixel_clk_khz))
- low_req_clk = i;
- }
- return low_req_clk;
-}
-
void dce112_set_clock(
struct display_clock *base,
uint32_t requested_clk_khz)
@@ -304,10 +176,7 @@ void dce112_set_clock(
static const struct display_clock_funcs funcs = {
.destroy = dispclk_dce112_destroy,
- .get_dp_ref_clk_frequency = get_dp_ref_clk_frequency,
- .get_required_clocks_state = dispclk_dce112_get_required_clocks_state,
.set_clock = dce112_set_clock,
- .set_min_clocks_state = dce112_set_min_clocks_state
};
bool dal_display_clock_dce112_construct(
@@ -406,24 +275,3 @@ bool dal_display_clock_dce112_construct(
return true;
}
-/*****************************************************************************
- * public functions
- *****************************************************************************/
-
-struct display_clock *dal_display_clock_dce112_create(
- struct dc_context *ctx)
-{
- struct display_clock_dce112 *dc112;
-
- dc112 = dm_alloc(sizeof(struct display_clock_dce112));
-
- if (dc112 == NULL)
- return NULL;
-
- if (dal_display_clock_dce112_construct(dc112, ctx))
- return &dc112->disp_clk_base;
-
- dm_free(dc112);
-
- return NULL;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
index b750bb1766bd..0743c514a60f 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
@@ -71,23 +71,9 @@ bool dal_display_clock_dce112_construct(
void dispclk_dce112_destroy(struct display_clock **base);
-enum dm_pp_clocks_state dispclk_dce112_get_min_clocks_state(
- struct display_clock *base);
-
-enum dm_pp_clocks_state dispclk_dce112_get_required_clocks_state(
- struct display_clock *dc,
- struct state_dependent_clocks *req_clocks);
-
void dce112_set_clock(
struct display_clock *base,
uint32_t requested_clk_khz);
-bool dispclk_dce112_set_min_clocks_state(
- struct display_clock *base,
- enum dm_pp_clocks_state clocks_state);
-
-void dispclk_dce112_store_max_clocks_state(
- struct display_clock *base,
- enum dm_pp_clocks_state max_clocks_state);
#endif /* __DAL_DISPLAY_CLOCK_DCE112_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c
deleted file mode 100644
index 9d7cb2cb161c..000000000000
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c
+++ /dev/null
@@ -1,430 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-#include "dce/dce_8_0_d.h"
-#include "dce/dce_8_0_sh_mask.h"
-
-#include "include/bios_parser_interface.h"
-#include "include/fixed32_32.h"
-#include "include/logger_interface.h"
-
-#include "../divider_range.h"
-#include "display_clock_dce80.h"
-#include "dc.h"
-
-#define DCE80_DFS_BYPASS_THRESHOLD_KHZ 100000
-
-/* Max clock values for each state indexed by "enum clocks_state": */
-static struct state_dependent_clocks max_clks_by_state[] = {
-/* ClocksStateInvalid - should not be used */
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/* ClocksStateLow */
-{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
-/* ClocksStateNominal */
-{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
-/* ClocksStatePerformance */
-{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
-
-/* Starting point for each divider range.*/
-enum divider_range_start {
- DIVIDER_RANGE_01_START = 200, /* 2.00*/
- DIVIDER_RANGE_02_START = 1600, /* 16.00*/
- DIVIDER_RANGE_03_START = 3200, /* 32.00*/
- DIVIDER_RANGE_SCALE_FACTOR = 100 /* Results are scaled up by 100.*/
-};
-
-/* Ranges for divider identifiers (Divider ID or DID)
- mmDENTIST_DISPCLK_CNTL.DENTIST_DISPCLK_WDIVIDER*/
-enum divider_id_register_setting {
- DIVIDER_RANGE_01_BASE_DIVIDER_ID = 0X08,
- DIVIDER_RANGE_02_BASE_DIVIDER_ID = 0X40,
- DIVIDER_RANGE_03_BASE_DIVIDER_ID = 0X60,
- DIVIDER_RANGE_MAX_DIVIDER_ID = 0X80
-};
-
-/* Step size between each divider within a range.
- Incrementing the DENTIST_DISPCLK_WDIVIDER by one
- will increment the divider by this much.*/
-enum divider_range_step_size {
- DIVIDER_RANGE_01_STEP_SIZE = 25, /* 0.25*/
- DIVIDER_RANGE_02_STEP_SIZE = 50, /* 0.50*/
- DIVIDER_RANGE_03_STEP_SIZE = 100 /* 1.00 */
-};
-
-/* Array identifiers and count for the divider ranges.*/
-enum divider_range_count {
- DIVIDER_RANGE_01 = 0,
- DIVIDER_RANGE_02,
- DIVIDER_RANGE_03,
- DIVIDER_RANGE_MAX /* == 3*/
-};
-
-static struct divider_range divider_ranges[DIVIDER_RANGE_MAX];
-
-#define FROM_DISPLAY_CLOCK(base) \
- container_of(base, struct display_clock_dce80, disp_clk)
-
-static void dce80_set_clock(
- struct display_clock *dc,
- uint32_t requested_clk_khz)
-{
- struct bp_pixel_clock_parameters pxl_clk_params;
- struct dc_bios *bp = dc->ctx->dc_bios;
-
- /* Prepare to program display clock*/
- memset(&pxl_clk_params, 0, sizeof(pxl_clk_params));
-
- pxl_clk_params.target_pixel_clock = requested_clk_khz;
- pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
-
- bp->funcs->program_display_engine_pll(bp, &pxl_clk_params);
-
- /* from power down, we need mark the clock state as ClocksStateNominal
- * from HWReset, so when resume we will call pplib voltage regulator.*/
- if (requested_clk_khz == 0)
- dc->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
-}
-
-static enum dm_pp_clocks_state get_required_clocks_state
- (struct display_clock *dc,
- struct state_dependent_clocks *req_clocks)
-{
- int32_t i;
- enum dm_pp_clocks_state low_req_clk = dc->max_clks_state;
-
- if (!req_clocks) {
- /* NULL pointer*/
- BREAK_TO_DEBUGGER();
- return DM_PP_CLOCKS_STATE_INVALID;
- }
-
- /* Iterate from highest supported to lowest valid state, and update
- * lowest RequiredState with the lowest state that satisfies
- * all required clocks
- */
- for (i = dc->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; --i) {
- if ((req_clocks->display_clk_khz <=
- max_clks_by_state[i].display_clk_khz) &&
- (req_clocks->pixel_clk_khz <=
- max_clks_by_state[i].pixel_clk_khz))
- low_req_clk = i;
- }
- return low_req_clk;
-}
-
-static bool dce80_set_min_clocks_state(
- struct display_clock *dc,
- enum dm_pp_clocks_state clocks_state)
-{
- struct dm_pp_power_level_change_request level_change_req = {
- clocks_state };
-
- if (clocks_state > dc->max_clks_state) {
- /*Requested state exceeds max supported state.*/
- dm_logger_write(dc->ctx->logger, LOG_WARNING,
- "Requested state exceeds max supported state");
- return false;
- } else if (clocks_state == dc->cur_min_clks_state) {
- /*if we're trying to set the same state, we can just return
- * since nothing needs to be done*/
- return true;
- }
-
- /* get max clock state from PPLIB */
- if (dm_pp_apply_power_level_change_request(dc->ctx, &level_change_req))
- dc->cur_min_clks_state = clocks_state;
-
- return true;
-}
-
-static uint32_t get_dp_ref_clk_frequency(struct display_clock *dc)
-{
- uint32_t dispclk_cntl_value;
- uint32_t dp_ref_clk_cntl_value;
- uint32_t dp_ref_clk_cntl_src_sel_value;
- uint32_t dp_ref_clk_khz = 600000;
- uint32_t target_div = INVALID_DIVIDER;
- struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-
- /* ASSERT DP Reference Clock source is from DFS*/
- dp_ref_clk_cntl_value = dm_read_reg(dc->ctx,
- mmDPREFCLK_CNTL);
-
- dp_ref_clk_cntl_src_sel_value =
- get_reg_field_value(
- dp_ref_clk_cntl_value,
- DPREFCLK_CNTL, DPREFCLK_SRC_SEL);
-
- ASSERT(dp_ref_clk_cntl_src_sel_value == 0);
-
- /* Read the mmDENTIST_DISPCLK_CNTL to get the currently
- * programmed DID DENTIST_DPREFCLK_WDIVIDER*/
- dispclk_cntl_value = dm_read_reg(dc->ctx,
- mmDENTIST_DISPCLK_CNTL);
-
- /* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/
- target_div = dal_divider_range_get_divider(
- divider_ranges,
- DIVIDER_RANGE_MAX,
- get_reg_field_value(dispclk_cntl_value,
- DENTIST_DISPCLK_CNTL,
- DENTIST_DPREFCLK_WDIVIDER));
-
- if (target_div != INVALID_DIVIDER) {
- /* Calculate the current DFS clock, in kHz.*/
- dp_ref_clk_khz = (DIVIDER_RANGE_SCALE_FACTOR
- * disp_clk->dentist_vco_freq_khz) / target_div;
- }
-
- /* SW will adjust DP REF Clock average value for all purposes
- * (DP DTO / DP Audio DTO and DP GTC)
- if clock is spread for all cases:
- -if SS enabled on DP Ref clock and HW de-spreading enabled with SW
- calculations for DS_INCR/DS_MODULO (this is planned to be default case)
- -if SS enabled on DP Ref clock and HW de-spreading enabled with HW
- calculations (not planned to be used, but average clock should still
- be valid)
- -if SS enabled on DP Ref clock and HW de-spreading disabled
- (should not be case with CIK) then SW should program all rates
- generated according to average value (case as with previous ASICs)
- */
- if ((disp_clk->ss_on_gpu_pll) && (disp_clk->gpu_pll_ss_divider != 0)) {
- struct fixed32_32 ss_percentage = dal_fixed32_32_div_int(
- dal_fixed32_32_from_fraction(
- disp_clk->gpu_pll_ss_percentage,
- disp_clk->gpu_pll_ss_divider), 200);
- struct fixed32_32 adj_dp_ref_clk_khz;
-
- ss_percentage = dal_fixed32_32_sub(dal_fixed32_32_one,
- ss_percentage);
- adj_dp_ref_clk_khz =
- dal_fixed32_32_mul_int(
- ss_percentage,
- dp_ref_clk_khz);
- dp_ref_clk_khz = dal_fixed32_32_floor(adj_dp_ref_clk_khz);
- }
-
- return dp_ref_clk_khz;
-}
-
-static void display_clock_ss_construct(
- struct display_clock_dce80 *disp_clk)
-{
- struct dc_bios *bp = disp_clk->disp_clk.ctx->dc_bios;
- uint32_t ss_entry_num = bp->funcs->get_ss_entry_number(bp,
- AS_SIGNAL_TYPE_GPU_PLL);
-
- /*Read SS Info from VBIOS SS Info table for DP Reference Clock spread.*/
- if (ss_entry_num > 0) {/* Should be only one entry */
- struct spread_spectrum_info ss_info;
- enum bp_result res;
-
- memset(&ss_info, 0, sizeof(struct spread_spectrum_info));
-
- res = bp->funcs->get_spread_spectrum_info(bp,
- AS_SIGNAL_TYPE_GPU_PLL, 0, &ss_info);
-
- /* Based on VBIOS, VBIOS will keep entry for GPU PLL SS even if
- * SS not enabled and in that case
- * SSInfo.spreadSpectrumPercentage !=0 would be
- * sign that SS is enabled*/
- if (res == BP_RESULT_OK && ss_info.spread_spectrum_percentage != 0) {
- disp_clk->ss_on_gpu_pll = true;
- disp_clk->gpu_pll_ss_divider =
- ss_info.spread_percentage_divider;
- if (ss_info.type.CENTER_MODE == 0)
- /* Currently we need only SS
- * percentage for down-spread*/
- disp_clk->gpu_pll_ss_percentage =
- ss_info.spread_spectrum_percentage;
- }
- }
-}
-
-static bool display_clock_integrated_info_construct(
- struct display_clock_dce80 *disp_clk)
-{
- struct dc_debug *debug = &disp_clk->disp_clk.ctx->dc->debug;
- struct dc_bios *bp = disp_clk->disp_clk.ctx->dc_bios;
- struct integrated_info info = { { { 0 } } };
- struct firmware_info fw_info = { { 0 } };
- uint32_t i;
-
- if (bp->integrated_info)
- info = *bp->integrated_info;
-
- disp_clk->dentist_vco_freq_khz = info.dentist_vco_freq;
- if (disp_clk->dentist_vco_freq_khz == 0) {
- bp->funcs->get_firmware_info(bp, &fw_info);
- disp_clk->dentist_vco_freq_khz =
- fw_info.smu_gpu_pll_output_freq;
- if (disp_clk->dentist_vco_freq_khz == 0)
- disp_clk->dentist_vco_freq_khz = 3600000;
- }
- disp_clk->disp_clk.min_display_clk_threshold_khz =
- disp_clk->dentist_vco_freq_khz / 64;
-
- /* TODO: initialise disp_clk->dfs_bypass_disp_clk */
-
- /*update the maximum display clock for each power state*/
- for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
- enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID;
-
- switch (i) {
- case 0:
- clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW;
- break;
-
- case 1:
- clk_state = DM_PP_CLOCKS_STATE_LOW;
- break;
-
- case 2:
- clk_state = DM_PP_CLOCKS_STATE_NOMINAL;
- break;
-
- case 3:
- clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE;
- break;
-
- default:
- clk_state = DM_PP_CLOCKS_STATE_INVALID;
- break;
- }
-
- /*Do not allow bad VBIOS/SBIOS to override with invalid values,
- * check for > 100MHz*/
- if (info.disp_clk_voltage[i].max_supported_clk >= 100000) {
- max_clks_by_state[clk_state].display_clk_khz =
- info.disp_clk_voltage[i].max_supported_clk;
- }
- }
-
- disp_clk->dfs_bypass_enabled = false;
- if (!debug->disable_dfs_bypass)
- if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
- disp_clk->dfs_bypass_enabled = true;
-
- disp_clk->use_max_disp_clk = debug->max_disp_clk;
-
- return true;
-}
-
-static void destroy(struct display_clock **dc)
-{
- struct display_clock_dce80 *disp_clk;
-
- disp_clk = FROM_DISPLAY_CLOCK(*dc);
- dm_free(disp_clk);
- *dc = NULL;
-}
-
-static const struct display_clock_funcs funcs = {
- .destroy = destroy,
- .get_dp_ref_clk_frequency = get_dp_ref_clk_frequency,
- .get_required_clocks_state = get_required_clocks_state,
- .set_clock = dce80_set_clock,
- .set_min_clocks_state = dce80_set_min_clocks_state
-};
-
-
-struct display_clock *dal_display_clock_dce80_create(
- struct dc_context *ctx)
-{
- struct display_clock_dce80 *disp_clk;
- struct display_clock *dc_base;
-
- disp_clk = dm_alloc(sizeof(struct display_clock_dce80));
-
- if (disp_clk == NULL)
- return NULL;
-
- dc_base = &disp_clk->disp_clk;
-
- dc_base->ctx = ctx;
- dc_base->min_display_clk_threshold_khz = 0;
-
- dc_base->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
-
- dc_base->funcs = &funcs;
- /*
- * set_dp_ref_clock_source
- * set_clock_state
- * get_clock_state
- * get_dfs_bypass_threshold
- */
-
- disp_clk->gpu_pll_ss_percentage = 0;
- disp_clk->gpu_pll_ss_divider = 1000;
- disp_clk->ss_on_gpu_pll = false;
- disp_clk->dfs_bypass_enabled = false;
- disp_clk->dfs_bypass_disp_clk = 0;
- disp_clk->use_max_disp_clk = true;/* false will hang the system! */
-
-/* Initially set max clocks state to nominal. This should be updated by
- * via a pplib call to DAL IRI eventually calling a
- * DisplayEngineClock_Dce50::StoreMaxClocksState(). This call will come in
- * on PPLIB init. This is from DCE5x. in case HW wants to use mixed method.*/
- dc_base->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
-/* Initially set current min clocks state to invalid since we
- * cannot make any assumption about PPLIB's initial state. This will be updated
- * by HWSS via SetMinClocksState() on first mode set prior to programming
- * state dependent clocks.*/
- disp_clk->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
-
- display_clock_ss_construct(disp_clk);
-
- if (!display_clock_integrated_info_construct(disp_clk)) {
- dm_logger_write(dc_base->ctx->logger, LOG_WARNING,
- "Cannot obtain VBIOS integrated info");
- }
-
- dal_divider_range_construct(
- ÷r_ranges[DIVIDER_RANGE_01],
- DIVIDER_RANGE_01_START,
- DIVIDER_RANGE_01_STEP_SIZE,
- DIVIDER_RANGE_01_BASE_DIVIDER_ID,
- DIVIDER_RANGE_02_BASE_DIVIDER_ID);
- dal_divider_range_construct(
- ÷r_ranges[DIVIDER_RANGE_02],
- DIVIDER_RANGE_02_START,
- DIVIDER_RANGE_02_STEP_SIZE,
- DIVIDER_RANGE_02_BASE_DIVIDER_ID,
- DIVIDER_RANGE_03_BASE_DIVIDER_ID);
- dal_divider_range_construct(
- ÷r_ranges[DIVIDER_RANGE_03],
- DIVIDER_RANGE_03_START,
- DIVIDER_RANGE_03_STEP_SIZE,
- DIVIDER_RANGE_03_BASE_DIVIDER_ID,
- DIVIDER_RANGE_MAX_DIVIDER_ID);
-
- dm_free(disp_clk);
- return NULL;
-}
-
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h
deleted file mode 100644
index c155bb6a4321..000000000000
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-#ifndef __DAL_DISPLAY_CLOCK_DCE80_H__
-#define __DAL_DISPLAY_CLOCK_DCE80_H__
-
-#include "display_clock_interface.h"
-
-struct display_clock_dce80 {
- struct display_clock disp_clk;
- /* DFS input - GPUPLL VCO frequency - from VBIOS Firmware info. */
- uint32_t dentist_vco_freq_khz;
- /* GPU PLL SS percentage (if down-spread enabled)*/
- uint32_t gpu_pll_ss_percentage;
- /* GPU PLL SS percentage Divider (100 or 1000)*/
- uint32_t gpu_pll_ss_divider;
- /* Flag for Enabled SS on GPU PLL*/
- bool ss_on_gpu_pll;
- /* Current minimum display block clocks state*/
- enum dm_pp_clocks_state cur_min_clks_state;
- /* DFS-bypass feature variable
- Cache the status of DFS-bypass feature*/
- bool dfs_bypass_enabled;
- /* Cache the display clock returned by VBIOS if DFS-bypass is enabled.
- * This is basically "Crystal Frequency In KHz" (XTALIN) frequency */
- uint32_t dfs_bypass_disp_clk;
- bool use_max_disp_clk;
-};
-
-struct display_clock *dal_display_clock_dce80_create(
- struct dc_context *ctx);
-
-#endif /* __DAL_DISPLAY_CLOCK_DCE80_H__ */
diff --git a/drivers/gpu/drm/amd/display/include/display_clock_interface.h b/drivers/gpu/drm/amd/display/include/display_clock_interface.h
index 6ba8c093793d..53a01381c638 100644
--- a/drivers/gpu/drm/amd/display/include/display_clock_interface.h
+++ b/drivers/gpu/drm/amd/display/include/display_clock_interface.h
@@ -41,10 +41,9 @@ struct state_dependent_clocks {
struct display_clock {
struct dc_context *ctx;
const struct display_clock_funcs *funcs;
- uint32_t min_display_clk_threshold_khz;
- /* Max display block clocks state*/
- enum dm_pp_clocks_state max_clks_state;
+ int min_display_clk_threshold_khz;
+ enum dm_pp_clocks_state max_clks_state;
enum dm_pp_clocks_state cur_min_clks_state;
};
@@ -61,15 +60,7 @@ struct display_clock_funcs {
};
-struct display_clock *dal_display_clock_dce112_create(
- struct dc_context *ctx);
-
-struct display_clock *dal_display_clock_dce110_create(
- struct dc_context *ctx);
-
-struct display_clock *dal_display_clock_dce80_create(
- struct dc_context *ctx);
-
void dal_display_clock_destroy(struct display_clock **to_destroy);
+
#endif /* __DISPLAY_CLOCK_INTERFACE_H__ */
--
2.9.3
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 09/12] drm/amd/display: add newline to generic_reg_wait timeout message
[not found] ` <20161206183538.11584-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (7 preceding siblings ...)
2016-12-06 18:35 ` [PATCH 08/12] drm/amd/display: consolidate dce8-11.2 display clock code Harry Wentland
@ 2016-12-06 18:35 ` Harry Wentland
2016-12-06 18:35 ` [PATCH 10/12] drm/amd/display: fix display clock integrated info read Harry Wentland
` (3 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Harry Wentland @ 2016-12-06 18:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Change-Id: I56acc2a2bf92318835699693bacea2234ed6ba5e
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c
index 3a80b0c08ae4..c5ff7b6d733d 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
@@ -138,7 +138,7 @@ uint32_t generic_reg_wait(const struct dc_context *ctx,
return reg_val;
}
- DC_ERR("REG_WAIT timeout %dus * %d tries - %s",
+ DC_ERR("REG_WAIT timeout %dus * %d tries - %s\n",
delay_between_poll_us, time_out_num_tries, func_name);
return reg_val;
}
--
2.9.3
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 10/12] drm/amd/display: fix display clock integrated info read
[not found] ` <20161206183538.11584-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (8 preceding siblings ...)
2016-12-06 18:35 ` [PATCH 09/12] drm/amd/display: add newline to generic_reg_wait timeout message Harry Wentland
@ 2016-12-06 18:35 ` Harry Wentland
2016-12-06 18:35 ` [PATCH 11/12] drm/amd/display: use rgb full range as default quantization for non HDMI Harry Wentland
` (2 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Harry Wentland @ 2016-12-06 18:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Change-Id: Ib4776ad5e62f9ab528033b3a493269ad52bd6afd
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
index bc1a46b7e373..524aacead8a2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -342,7 +342,7 @@ static void dce_clock_read_integrated_info(struct dce_disp_clk *clk_dce)
info.disp_clk_voltage[i].max_supported_clk;
}
- if (!debug->disable_dfs_bypass)
+ if (!debug->disable_dfs_bypass && bp->integrated_info)
if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
clk_dce->dfs_bypass_enabled = true;
--
2.9.3
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 11/12] drm/amd/display: use rgb full range as default quantization for non HDMI
[not found] ` <20161206183538.11584-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (9 preceding siblings ...)
2016-12-06 18:35 ` [PATCH 10/12] drm/amd/display: fix display clock integrated info read Harry Wentland
@ 2016-12-06 18:35 ` Harry Wentland
2016-12-06 18:35 ` [PATCH 12/12] drm/amd/display: create scratch_val_ctx as temp w/a Harry Wentland
2016-12-06 18:47 ` [PATCH 00/12] DC Patches for Dec 5, 2016 Deucher, Alexander
12 siblings, 0 replies; 14+ messages in thread
From: Harry Wentland @ 2016-12-06 18:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Wenjing Liu
From: Wenjing Liu <Wenjing.Liu@amd.com>
[Description]
Refactor the quantization decision to color module.
Add the check if non HDMI, default quantization should be rgb full range.
Change-Id: Icf2d690ed71e16f0af8128b8a405f530974d48ce
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/modules/color/color.c | 88 ++++++++++++++++++++--
.../gpu/drm/amd/display/modules/inc/mod_color.h | 12 ++-
2 files changed, 94 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/modules/color/color.c b/drivers/gpu/drm/amd/display/modules/color/color.c
index 30d09d358576..0610b82b6d84 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color.c
@@ -2184,7 +2184,8 @@ bool mod_color_set_saturation(struct mod_color *mod_color,
return true;
}
-bool mod_color_set_preferred_quantization_range(struct mod_color *mod_color,
+bool mod_color_persist_user_preferred_quantization_range(
+ struct mod_color *mod_color,
const struct dc_sink *sink,
enum dc_quantization_range quantization_range)
{
@@ -2214,13 +2215,90 @@ bool mod_color_set_preferred_quantization_range(struct mod_color *mod_color,
bool mod_color_get_preferred_quantization_range(struct mod_color *mod_color,
const struct dc_sink *sink,
+ const struct dc_crtc_timing *timing,
enum dc_quantization_range *quantization_range)
{
struct core_color *core_color = MOD_COLOR_TO_CORE(mod_color);
- unsigned int sink_index;
+ unsigned int sink_index = sink_index_from_sink(core_color, sink);
+ enum dc_quantization_range user_preferred_quantization_range =
+ core_color->state[sink_index].
+ preferred_quantization_range;
+ bool rgb_full_range_supported =
+ mod_color_is_rgb_full_range_supported_for_timing(
+ sink, timing);
+ bool rgb_limited_range_supported =
+ mod_color_is_rgb_limited_range_supported_for_timing(
+ sink, timing);
+
+ if (rgb_full_range_supported && rgb_limited_range_supported)
+ *quantization_range = user_preferred_quantization_range;
+ else if (rgb_full_range_supported && !rgb_limited_range_supported)
+ *quantization_range = QUANTIZATION_RANGE_FULL;
+ else if (!rgb_full_range_supported && rgb_limited_range_supported)
+ *quantization_range = QUANTIZATION_RANGE_LIMITED;
+ else
+ *quantization_range = QUANTIZATION_RANGE_UNKNOWN;
- sink_index = sink_index_from_sink(core_color, sink);
- *quantization_range = core_color->state[sink_index].
- preferred_quantization_range;
return true;
}
+
+bool mod_color_is_rgb_full_range_supported_for_timing(
+ const struct dc_sink *sink,
+ const struct dc_crtc_timing *timing)
+{
+ bool result = false;
+
+ if (!sink || !timing)
+ return result;
+
+ if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
+ if (timing->vic || timing->hdmi_vic)
+ if (timing->h_addressable == 640 &&
+ timing->v_addressable == 480 &&
+ (timing->pix_clk_khz == 25200 ||
+ timing->pix_clk_khz == 25170 ||
+ timing->pix_clk_khz == 25175))
+ result = true;
+ else
+ /* don't support full range rgb */
+ /* for HDMI CEA861 timings except VGA mode */
+ result = false;
+ else
+ result = true;
+ else
+ result = true;
+
+ return result;
+}
+
+bool mod_color_is_rgb_limited_range_supported_for_timing(
+ const struct dc_sink *sink,
+ const struct dc_crtc_timing *timing)
+{
+ bool result = false;
+
+ if (!sink || !timing)
+ return result;
+
+ if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
+ if (timing->vic || timing->hdmi_vic)
+ if (timing->h_addressable == 640 &&
+ timing->v_addressable == 480 &&
+ (timing->pix_clk_khz == 25200 ||
+ timing->pix_clk_khz == 25170 ||
+ timing->pix_clk_khz == 25175))
+ /* don't support rgb limited for */
+ /* HDMI CEA VGA mode */
+ result = false;
+ else
+ /* support rgb limited for non VGA CEA timing */
+ result = true;
+ else
+ /* support rgb limited for non CEA HDMI timing */
+ result = true;
+ else
+ /* don't support rgb limited for non HDMI signal */
+ result = false;
+
+ return result;
+}
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_color.h b/drivers/gpu/drm/amd/display/modules/inc/mod_color.h
index e54fe2cb8611..91abc173444a 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_color.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_color.h
@@ -168,12 +168,22 @@ bool mod_color_set_saturation(struct mod_color *mod_color,
const struct dc_stream **streams, int num_streams,
int saturation_value);
-bool mod_color_set_preferred_quantization_range(struct mod_color *mod_color,
+bool mod_color_persist_user_preferred_quantization_range(
+ struct mod_color *mod_color,
const struct dc_sink *sink,
enum dc_quantization_range quantization_range);
bool mod_color_get_preferred_quantization_range(struct mod_color *mod_color,
const struct dc_sink *sink,
+ const struct dc_crtc_timing *timing,
enum dc_quantization_range *quantization_range);
+bool mod_color_is_rgb_full_range_supported_for_timing(
+ const struct dc_sink *sink,
+ const struct dc_crtc_timing *timing);
+
+bool mod_color_is_rgb_limited_range_supported_for_timing(
+ const struct dc_sink *sink,
+ const struct dc_crtc_timing *timing);
+
#endif /* MOD_COLOR_H_ */
--
2.9.3
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 12/12] drm/amd/display: create scratch_val_ctx as temp w/a
[not found] ` <20161206183538.11584-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (10 preceding siblings ...)
2016-12-06 18:35 ` [PATCH 11/12] drm/amd/display: use rgb full range as default quantization for non HDMI Harry Wentland
@ 2016-12-06 18:35 ` Harry Wentland
2016-12-06 18:47 ` [PATCH 00/12] DC Patches for Dec 5, 2016 Deucher, Alexander
12 siblings, 0 replies; 14+ messages in thread
From: Harry Wentland @ 2016-12-06 18:35 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Change-Id: I361779eff9f07723308793fcf31e9ddcc528298d
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 5 ++++-
drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 70dc70685471..a3c5def507a9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -452,6 +452,8 @@ static void destruct(struct core_dc *dc)
dm_free(dc->temp_flip_context);
dc->temp_flip_context = NULL;
+ dm_free(dc->scratch_val_ctx);
+ dc->scratch_val_ctx = NULL;
destroy_links(dc);
@@ -490,6 +492,7 @@ static bool construct(struct core_dc *dc,
dc->current_context = dm_alloc(sizeof(*dc->current_context));
dc->temp_flip_context = dm_alloc(sizeof(*dc->temp_flip_context));
+ dc->scratch_val_ctx = dm_alloc(sizeof(*dc->temp_flip_context));
if (!dc->current_context || !dc->temp_flip_context) {
dm_error("%s: failed to create validate ctx\n", __func__);
@@ -1217,7 +1220,7 @@ bool dc_pre_update_surfaces_to_target(
goto unexpected_fail;
}
resource_validate_ctx_destruct(context);
- dm_free(context);
+ core_dc->scratch_val_ctx = context;
context = temp_context;
}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h
index 7d6dc8ea75ab..b5a5207a4df0 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h
@@ -24,6 +24,7 @@ struct core_dc {
/* TODO: determine max number of targets*/
struct validate_context *current_context;
struct validate_context *temp_flip_context;
+ struct validate_context *scratch_val_ctx;
struct resource_pool *res_pool;
/*Power State*/
--
2.9.3
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* RE: [PATCH 00/12] DC Patches for Dec 5, 2016
[not found] ` <20161206183538.11584-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (11 preceding siblings ...)
2016-12-06 18:35 ` [PATCH 12/12] drm/amd/display: create scratch_val_ctx as temp w/a Harry Wentland
@ 2016-12-06 18:47 ` Deucher, Alexander
12 siblings, 0 replies; 14+ messages in thread
From: Deucher, Alexander @ 2016-12-06 18:47 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Wentland, Harry
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Harry Wentland
> Sent: Tuesday, December 06, 2016 1:35 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Wentland, Harry
> Subject: [PATCH 00/12] DC Patches for Dec 5, 2016
>
> * larger rework of display_clock code to facilitate sharing between
> ASIC generations
> * some small bug fixes
Nice cleanup. Patches are:
Acked-by: Alex Deucher <alexander.deucher@amd.com>
>
> Dmytro Laktyushkin (10):
> drm/amd/display: remove dead display clock code
> drm/amd/display: restyle display clock calls part 1
> drm/amd/display: restyle display clock calls part 2
> drm/amd/display: remove store clock state
> drm/amd/display: remove get_min_clocks_state
> drm/amd/display: remove clocks_state enum
> drm/amd/display: consolidate dce8-11.2 display clock code
> drm/amd/display: add newline to generic_reg_wait timeout message
> drm/amd/display: fix display clock integrated info read
> drm/amd/display: create scratch_val_ctx as temp w/a
>
> Wenjing Liu (1):
> drm/amd/display: use rgb full range as default quantization for non
> HDMI
>
> Yongqiang Sun (1):
> drm/amd/display: Add missing GRPH register definition
>
> drivers/gpu/drm/amd/display/dc/core/dc.c | 9 +-
> drivers/gpu/drm/amd/display/dc/core/dc_link.c | 13 +-
> drivers/gpu/drm/amd/display/dc/dc_helper.c | 2 +-
> drivers/gpu/drm/amd/display/dc/dce/Makefile | 3 +-
> drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 4 +-
> drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 519 ++++++++++
> drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 133 +++
> drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 1 +
> .../drm/amd/display/dc/dce100/dce100_resource.c | 31 +-
> .../amd/display/dc/dce110/dce110_hw_sequencer.c | 65 +-
> .../drm/amd/display/dc/dce110/dce110_resource.c | 74 +-
> .../drm/amd/display/dc/dce110/dce110_resource.h | 3 -
> .../drm/amd/display/dc/dce112/dce112_resource.c | 37 +-
> .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 76 +-
> drivers/gpu/drm/amd/display/dc/dm_services_types.h | 18 +-
> drivers/gpu/drm/amd/display/dc/gpu/Makefile | 17 +-
> .../display/dc/gpu/dce110/display_clock_dce110.c | 1035 --------------------
> .../display/dc/gpu/dce110/display_clock_dce110.h | 53 -
> .../display/dc/gpu/dce112/display_clock_dce112.c | 717 +-------------
> .../display/dc/gpu/dce112/display_clock_dce112.h | 39 +-
> .../amd/display/dc/gpu/dce80/display_clock_dce80.c | 934 ------------------
> .../amd/display/dc/gpu/dce80/display_clock_dce80.h | 57 --
> drivers/gpu/drm/amd/display/dc/gpu/display_clock.c | 217 ----
> drivers/gpu/drm/amd/display/dc/gpu/display_clock.h | 89 --
> drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 1 +
> drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 -
> .../amd/display/include/display_clock_interface.h | 149 +--
> drivers/gpu/drm/amd/display/modules/color/color.c | 88 +-
> .../gpu/drm/amd/display/modules/inc/mod_color.h | 12 +-
> 29 files changed, 920 insertions(+), 3478 deletions(-)
> create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
> delete mode 100644
> drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c
> delete mode 100644
> drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h
> delete mode 100644
> drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c
> delete mode 100644
> drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h
> delete mode 100644 drivers/gpu/drm/amd/display/dc/gpu/display_clock.c
> delete mode 100644 drivers/gpu/drm/amd/display/dc/gpu/display_clock.h
>
> --
> 2.9.3
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2016-12-06 18:47 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-12-06 18:35 [PATCH 00/12] DC Patches for Dec 5, 2016 Harry Wentland
[not found] ` <20161206183538.11584-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2016-12-06 18:35 ` [PATCH 01/12] drm/amd/display: Add missing GRPH register definition Harry Wentland
2016-12-06 18:35 ` [PATCH 02/12] drm/amd/display: remove dead display clock code Harry Wentland
2016-12-06 18:35 ` [PATCH 03/12] drm/amd/display: restyle display clock calls part 1 Harry Wentland
2016-12-06 18:35 ` [PATCH 04/12] drm/amd/display: restyle display clock calls part 2 Harry Wentland
2016-12-06 18:35 ` [PATCH 05/12] drm/amd/display: remove store clock state Harry Wentland
2016-12-06 18:35 ` [PATCH 06/12] drm/amd/display: remove get_min_clocks_state Harry Wentland
2016-12-06 18:35 ` [PATCH 07/12] drm/amd/display: remove clocks_state enum Harry Wentland
2016-12-06 18:35 ` [PATCH 08/12] drm/amd/display: consolidate dce8-11.2 display clock code Harry Wentland
2016-12-06 18:35 ` [PATCH 09/12] drm/amd/display: add newline to generic_reg_wait timeout message Harry Wentland
2016-12-06 18:35 ` [PATCH 10/12] drm/amd/display: fix display clock integrated info read Harry Wentland
2016-12-06 18:35 ` [PATCH 11/12] drm/amd/display: use rgb full range as default quantization for non HDMI Harry Wentland
2016-12-06 18:35 ` [PATCH 12/12] drm/amd/display: create scratch_val_ctx as temp w/a Harry Wentland
2016-12-06 18:47 ` [PATCH 00/12] DC Patches for Dec 5, 2016 Deucher, Alexander
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