Re: [PATCH] drm/amdgpu: show gfx clock gating status to user

[Huang Rui <ray.huang-5C7GfCeVMHo@public.gmane.org>]

On Wed, Jan 04, 2017 at 10:21:44AM +0800, Huang Rui wrote:
> On Tue, Jan 03, 2017 at 11:02:09PM +0800, Deucher, Alexander wrote:
> > > -----Original Message-----
> > > From: Huang Rui [mailto:ray.huang@amd.com]
> > > Sent: Tuesday, January 03, 2017 5:47 AM
> > > To: Deucher, Alexander; amd-gfx@lists.freedesktop.org
> > > Cc: Zhu, Rex; Mao, David; Fu, Ping; Huang, Ray
> > > Subject: [PATCH] drm/amdgpu: show gfx clock gating status to user
> > > 
> > > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > > ---
> > >  drivers/gpu/drm/amd/amdgpu/amdgpu.h    | 1 +
> > >  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 5 +++++
> > >  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c  | 2 ++
> > >  drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c  | 2 ++
> > >  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 3 +++
> > >  5 files changed, 13 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > > index 96eeea7..989d311 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > > @@ -1033,6 +1033,7 @@ struct amdgpu_gfx {
> > >  	struct amdgpu_irq_src		priv_inst_irq;
> > >  	/* gfx status */
> > >  	uint32_t			gfx_current_status;
> > > +	bool				cg_enabled;
> > >  	/* ce ram size*/
> > >  	unsigned			ce_ram_size;
> > >  	struct amdgpu_cu_info		cu_info;
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > > index a7c7657..10f2eab 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > > @@ -1543,6 +1543,11 @@ static int amdgpu_debugfs_pm_info(struct
> > > seq_file *m, void *data)
> > >  	struct amdgpu_device *adev = dev->dev_private;
> > >  	struct drm_device *ddev = adev->ddev;
> > > 
> > > +	if (adev->gfx.cg_enabled)
> > > +		seq_printf(m, "GFX Clock Gating: Enabled\n");
> > > +	else
> > > +		seq_printf(m, "GFX Clock Gating: Disabled\n");
> > > +
> > 
> > 
> > I think it would be better to print the cg_flags and pg_flags (both as a mask and in human readable form) so we know exactly cg and pg features are enabled.
> > 
> 
> It's probable better. Let me revise this patch and send it later.
> 

Hi Alex,

There is one issue on tonga, polaris10, and polaris11, they use smu to
control clock gating. And flags are below, not use adev->cg_flags. It
cannot indicate clock gating status from adev->cg_flags and the
cg_flags/pg_flags is marked supported state by HW, not runtime enablement state:

#define PP_STATE_CG             0x01
#define PP_STATE_LS             0x02
#define PP_STATE_DS             0x04
#define PP_STATE_SD             0x08
#define PP_STATE_SUPPORT_CG     0x10
#define PP_STATE_SUPPORT_LS     0x20
#define PP_STATE_SUPPORT_DS     0x40
#define PP_STATE_SUPPORT_SD     0x80

I think shall we combine them with AMD_CG_SUPPORT_GFX_MGCG and etc.?
Try to find unified flags to control clock gating and power gating...

Thanks,
Rui
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