[PATCH 0/6] DC Patches Jan 4, 2017

[PATCH 0/6] DC Patches Jan 4, 2017

[Harry Wentland]

* bunch of small patches to enable DP PHY compliance
* gamma fix
* minor link_encoder cleanup

Hersen Wu (2):
  drm/amd/display: Fix link retraining hw sequence for auto test
  drm/amd/display: Fix DP PHY test pre-emphasis not set properly

Roman Li (1):
  drm/amd/display: fix gamma for dpms usecase

Tony Cheng (2):
  drm/amd/display: simplify link_encoder
  drm/amd/display: limit HBR3 support to Polaris and up

Zeyu Fan (1):
  drm/amd/display: Fix link retraining hw sequence

 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c    | 22 ++---
 drivers/gpu/drm/amd/display/dc/core/dc.c           | 28 ++++---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c      |  8 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c   |  4 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 51 +++++++++---
 drivers/gpu/drm/amd/display/dc/dc.h                |  6 +-
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c  | 97 +++-------------------
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h  |  1 +
 .../drm/amd/display/dc/dce100/dce100_resource.c    | 11 ++-
 .../drm/amd/display/dc/dce110/dce110_resource.c    | 11 ++-
 .../drm/amd/display/dc/dce112/dce112_resource.c    | 15 +++-
 .../gpu/drm/amd/display/dc/dce80/dce80_resource.c  | 11 ++-
 .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h   | 20 +----
 drivers/gpu/drm/amd/display/dc/inc/link_hwss.h     |  4 +-
 .../amd/display/dc/virtual/virtual_link_encoder.c  |  4 -
 15 files changed, 131 insertions(+), 162 deletions(-)

-- 
2.9.3

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[PATCH 1/6] drm/amd/display: Fix link retraining hw sequence

[Harry Wentland]

From: Zeyu Fan <Zeyu.Fan@amd.com>

Change-Id: I1caba702ffa75745bdf3c90c90f9c34faad68016
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c           | 15 +++----
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 49 +++++++++++++++++++++-
 drivers/gpu/drm/amd/display/dc/dc.h                |  3 +-
 drivers/gpu/drm/amd/display/dc/inc/link_hwss.h     |  4 ++
 4 files changed, 62 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 69819d834543..ad1ce600a165 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -357,17 +357,18 @@ static void perform_link_training(struct dc *dc,
 }
 
 static void set_preferred_link_settings(struct dc *dc,
-		struct dc_link_settings *link_setting)
+		struct dc_link_settings *link_setting,
+		const struct dc_link *link)
 {
-	struct core_dc *core_dc = DC_TO_CORE(dc);
-	int i;
+	struct core_link *core_link = DC_LINK_TO_CORE(link);
 
-	for (i = 0; i < core_dc->link_count; i++) {
-		core_dc->links[i]->public.verified_link_cap.lane_count =
+	core_link->public.verified_link_cap.lane_count =
 				link_setting->lane_count;
-		core_dc->links[i]->public.verified_link_cap.link_rate =
+	core_link->public.verified_link_cap.link_rate =
 				link_setting->link_rate;
-	}
+	dp_retrain_link_physi(core_link,
+			link_setting,
+			false);
 }
 
 static void enable_hpd(const struct dc_link *link)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 4febc8d2a96d..f870a0e72074 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -200,7 +200,6 @@ void dp_set_hw_test_pattern(
 	encoder->funcs->dp_set_phy_pattern(encoder, &pattern_param);
 }
 
-
 void dp_retrain_link(struct core_link *link)
 {
 	struct pipe_ctx *pipes = link->dc->current_context->res_ctx.pipe_ctx;
@@ -221,3 +220,51 @@ void dp_retrain_link(struct core_link *link)
 		}
 	}
 }
+
+void dp_retrain_link_physi(struct core_link *link,
+			struct dc_link_settings *link_setting,
+			bool skip_video_pattern)
+{
+	struct pipe_ctx *pipes =
+			&link->dc->current_context->res_ctx.pipe_ctx[0];
+	unsigned int i;
+
+	for (i = 0; i < MAX_PIPES; i++) {
+		if (pipes[i].stream != NULL &&
+			pipes[i].stream->sink != NULL &&
+			pipes[i].stream->sink->link != NULL &&
+			pipes[i].stream_enc != NULL &&
+			pipes[i].stream->sink->link == link) {
+			dm_delay_in_microseconds(link->ctx, 100);
+
+			pipes[i].stream_enc->funcs->dp_blank(
+					pipes[i].stream_enc);
+
+			dp_receiver_power_ctrl(link, false);
+
+			link->link_enc->funcs->disable_output(
+					link->link_enc,
+					SIGNAL_TYPE_DISPLAY_PORT);
+
+			/* Clear current link setting.
+			 * memset(&link->public.cur_link_settings, 0,
+			 * 	sizeof(link->public.cur_link_settings));
+			 */
+
+			link->link_enc->funcs->enable_dp_output(
+						link->link_enc,
+						link_setting,
+						pipes[i].clock_source->id);
+
+			dp_receiver_power_ctrl(link, true);
+
+			dc_link_dp_perform_link_training(
+					&link->public,
+					link_setting,
+					skip_video_pattern);
+
+			link->dc->hwss.unblank_stream(&pipes[i],
+					link_setting);
+		}
+	}
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 599f8b0894c2..83d78c2dc24d 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -117,7 +117,8 @@ struct dc_link_funcs {
 			struct dc_link_settings *link_setting,
 			bool skip_video_pattern);
 	void (*set_preferred_link_settings)(struct dc *dc,
-			struct dc_link_settings *link_setting);
+			struct dc_link_settings *link_setting,
+			const struct dc_link *link);
 	void (*enable_hpd)(const struct dc_link *link);
 	void (*disable_hpd)(const struct dc_link *link);
 	void (*set_test_pattern)(
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
index 662fa30d45f7..30831c54878b 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
@@ -70,4 +70,8 @@ enum dp_panel_mode dp_get_panel_mode(struct core_link *link);
 
 void dp_retrain_link(struct core_link *link);
 
+void dp_retrain_link_physi(struct core_link *link,
+		struct dc_link_settings *link_setting,
+		bool skip_video_pattern);
+
 #endif /* __DC_LINK_HWSS_H__ */
-- 
2.9.3

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[PATCH 2/6] drm/amd/display: Fix link retraining hw sequence for auto test

[Harry Wentland]

From: Hersen Wu <hersenxs.wu@amd.com>

Change-Id: Ia0e5ede4f3790c32c292ac381d6d373f507640b0
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c           |  4 +---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c   |  4 ++--
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 27 ++++------------------
 drivers/gpu/drm/amd/display/dc/inc/link_hwss.h     |  4 +---
 4 files changed, 9 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index ad1ce600a165..a7c6c980927e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -366,9 +366,7 @@ static void set_preferred_link_settings(struct dc *dc,
 				link_setting->lane_count;
 	core_link->public.verified_link_cap.link_rate =
 				link_setting->link_rate;
-	dp_retrain_link_physi(core_link,
-			link_setting,
-			false);
+	dp_retrain_link_dp_test(core_link, link_setting, false);
 }
 
 static void enable_hpd(const struct dc_link *link)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index a4b6a6a571df..3d5871dfc8e6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1532,7 +1532,7 @@ static bool handle_hpd_irq_psr_sink(const struct core_link *link)
 
 static void dp_test_send_link_training(struct core_link *link)
 {
-	struct dc_link_settings link_settings;
+	struct dc_link_settings link_settings = {0};
 
 	core_link_read_dpcd(
 			link,
@@ -1549,7 +1549,7 @@ static void dp_test_send_link_training(struct core_link *link)
 	link->public.verified_link_cap.lane_count = link_settings.lane_count;
 	link->public.verified_link_cap.link_rate = link_settings.link_rate;
 
-	dp_retrain_link(link);
+	dp_retrain_link_dp_test(link, &link_settings, false);
 }
 
 static void dp_test_send_phy_test_pattern(struct core_link *link)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index f870a0e72074..e287584ade29 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -200,28 +200,7 @@ void dp_set_hw_test_pattern(
 	encoder->funcs->dp_set_phy_pattern(encoder, &pattern_param);
 }
 
-void dp_retrain_link(struct core_link *link)
-{
-	struct pipe_ctx *pipes = link->dc->current_context->res_ctx.pipe_ctx;
-	unsigned int i;
-
-	for (i = 0; i < MAX_PIPES; i++) {
-		if (pipes[i].stream_enc != NULL) {
-			dm_delay_in_microseconds(link->ctx, 100);
-			pipes->stream_enc->funcs->dp_blank(pipes[i].stream_enc);
-			link->dc->hwss.disable_stream(&pipes[i]);
-			dc_link_dp_perform_link_training(
-					&link->public,
-					&link->public.verified_link_cap,
-					true);
-			link->dc->hwss.enable_stream(&pipes[i]);
-			link->dc->hwss.unblank_stream(&pipes[i],
-					&link->public.verified_link_cap);
-		}
-	}
-}
-
-void dp_retrain_link_physi(struct core_link *link,
+void dp_retrain_link_dp_test(struct core_link *link,
 			struct dc_link_settings *link_setting,
 			bool skip_video_pattern)
 {
@@ -240,6 +219,10 @@ void dp_retrain_link_physi(struct core_link *link,
 			pipes[i].stream_enc->funcs->dp_blank(
 					pipes[i].stream_enc);
 
+			/* disable any test pattern that might be active */
+			dp_set_hw_test_pattern(link,
+					DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
+
 			dp_receiver_power_ctrl(link, false);
 
 			link->link_enc->funcs->disable_output(
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
index 30831c54878b..75d10e93b002 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
@@ -68,9 +68,7 @@ void dp_set_hw_test_pattern(
 
 enum dp_panel_mode dp_get_panel_mode(struct core_link *link);
 
-void dp_retrain_link(struct core_link *link);
-
-void dp_retrain_link_physi(struct core_link *link,
+void dp_retrain_link_dp_test(struct core_link *link,
 		struct dc_link_settings *link_setting,
 		bool skip_video_pattern);
 
-- 
2.9.3

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[PATCH 3/6] drm/amd/display: simplify link_encoder

[Harry Wentland]

From: Tony Cheng <tony.cheng@amd.com>

- remove unnecessary feature flags
- remove wireless and VGA validation

Change-Id: Ia7b5939276667cd1be35f7f3dcc3b756545089f3
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c      |  8 +--
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c  | 64 ++--------------------
 .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h   | 20 +------
 .../amd/display/dc/virtual/virtual_link_encoder.c  |  4 --
 4 files changed, 6 insertions(+), 90 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index b2fc290b5385..b0f316344e86 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -317,7 +317,6 @@ static bool is_dp_sink_present(struct core_link *link)
 {
 	enum gpio_result gpio_result;
 	uint32_t clock_pin = 0;
-	uint32_t data_pin = 0;
 
 	struct ddc *ddc;
 
@@ -353,12 +352,7 @@ static bool is_dp_sink_present(struct core_link *link)
 	gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 	ASSERT(gpio_result == GPIO_RESULT_OK);
 
-	if (gpio_result == GPIO_RESULT_OK)
-		if (link->link_enc->features.flags.bits.
-						DP_SINK_DETECT_POLL_DATA_PIN)
-			gpio_result = dal_gpio_get_value(ddc->pin_data, &data_pin);
-
-	present = (gpio_result == GPIO_RESULT_OK) && !(clock_pin || data_pin);
+	present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 
 	dal_ddc_close(ddc);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index ea4778b6e6d8..aa6b3449913c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -67,11 +67,6 @@
 #define HPD_REG(reg)\
 	(enc110->hpd_regs->reg)
 
-/* For current ASICs pixel clock - 600MHz */
-#define MAX_ENCODER_CLK 600000
-
-#define DCE11_UNIPHY_MAX_PIXEL_CLK_IN_KHZ 594000
-
 #define DEFAULT_AUX_MAX_DATA_SIZE 16
 #define AUX_MAX_DEFER_WRITE_RETRY 20
 /*
@@ -845,18 +840,15 @@ bool dce110_link_encoder_validate_dvi_output(
 {
 	uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK;
 
-	if (enc110->base.features.max_pixel_clock < TMDS_MAX_PIXEL_CLOCK)
-		max_pixel_clock = enc110->base.features.max_pixel_clock;
-
 	if (signal == SIGNAL_TYPE_DVI_DUAL_LINK)
-		max_pixel_clock <<= 1;
+		max_pixel_clock *= 2;
 
 	/* This handles the case of HDMI downgrade to DVI we don't want to
 	 * we don't want to cap the pixel clock if the DDI is not DVI.
 	 */
 	if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK &&
 			connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
-		max_pixel_clock = enc110->base.features.max_pixel_clock;
+		max_pixel_clock = enc110->base.features.max_hdmi_pixel_clock;
 
 	/* DVI only support RGB pixel encoding */
 	if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
@@ -893,9 +885,6 @@ static bool dce110_link_encoder_validate_hdmi_output(
 	enum dc_color_depth max_deep_color =
 			enc110->base.features.max_hdmi_deep_color;
 
-	if (max_deep_color > enc110->base.features.max_deep_color)
-		max_deep_color = enc110->base.features.max_deep_color;
-
 	if (max_deep_color < crtc_timing->display_color_depth)
 		return false;
 
@@ -903,8 +892,7 @@ static bool dce110_link_encoder_validate_hdmi_output(
 		return false;
 
 	if ((adjusted_pix_clk_khz == 0) ||
-		(adjusted_pix_clk_khz > enc110->base.features.max_hdmi_pixel_clock) ||
-		(adjusted_pix_clk_khz > enc110->base.features.max_pixel_clock))
+		(adjusted_pix_clk_khz > enc110->base.features.max_hdmi_pixel_clock))
 		return false;
 
 	/* DCE11 HW does not support 420 */
@@ -915,19 +903,6 @@ static bool dce110_link_encoder_validate_hdmi_output(
 	return true;
 }
 
-bool dce110_link_encoder_validate_rgb_output(
-	const struct dce110_link_encoder *enc110,
-	const struct dc_crtc_timing *crtc_timing)
-{
-	if (crtc_timing->pix_clk_khz > enc110->base.features.max_pixel_clock)
-		return false;
-
-	if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
-		return false;
-
-	return true;
-}
-
 bool dce110_link_encoder_validate_dp_output(
 	const struct dce110_link_encoder *enc110,
 	const struct dc_crtc_timing *crtc_timing)
@@ -949,21 +924,6 @@ bool dce110_link_encoder_validate_dp_output(
 	return false;
 }
 
-bool dce110_link_encoder_validate_wireless_output(
-	const struct dce110_link_encoder *enc110,
-	const struct dc_crtc_timing *crtc_timing)
-{
-	if (crtc_timing->pix_clk_khz > enc110->base.features.max_pixel_clock)
-		return false;
-
-	/* Wireless only supports YCbCr444 */
-	if (crtc_timing->pixel_encoding ==
-			PIXEL_ENCODING_YCBCR444)
-		return true;
-
-	return false;
-}
-
 bool dce110_link_encoder_construct(
 	struct dce110_link_encoder *enc110,
 	const struct encoder_init_data *init_data,
@@ -985,12 +945,6 @@ bool dce110_link_encoder_construct(
 
 	enc110->base.transmitter = init_data->transmitter;
 
-	enc110->base.features.flags.bits.IS_AUDIO_CAPABLE = true;
-
-	enc110->base.features.max_pixel_clock =
-			MAX_ENCODER_CLK;
-
-	enc110->base.features.max_deep_color = COLOR_DEPTH_121212;
 	enc110->base.features.max_hdmi_deep_color = COLOR_DEPTH_121212;
 
 	if (enc110->base.ctx->dc->debug.disable_hdmi_deep_color)
@@ -1070,7 +1024,6 @@ bool dce110_link_encoder_construct(
 				bp_cap_info.DP_HBR2_CAP;
 		enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
 				bp_cap_info.DP_HBR3_EN;
-
 	}
 
 	/* TODO: check PPLIB maxPhyClockInKHz <= 540000, if yes,
@@ -1082,7 +1035,6 @@ bool dce110_link_encoder_construct(
 	/* test pattern 4 support */
 	enc110->base.features.flags.bits.IS_TPS4_CAPABLE = true;
 
-	enc110->base.features.flags.bits.IS_Y_ONLY_CAPABLE = false;
 	/*
 		dal_adapter_service_is_feature_supported(as,
 			FEATURE_SUPPORT_DP_Y_ONLY);
@@ -1118,22 +1070,14 @@ bool dce110_link_encoder_validate_output_with_stream(
 				&stream->public.timing,
 				stream->phy_pix_clk);
 	break;
-	case SIGNAL_TYPE_RGB:
-		is_valid = dce110_link_encoder_validate_rgb_output(
-			enc110, &stream->public.timing);
-	break;
 	case SIGNAL_TYPE_DISPLAY_PORT:
 	case SIGNAL_TYPE_DISPLAY_PORT_MST:
 	case SIGNAL_TYPE_EDP:
 		is_valid = dce110_link_encoder_validate_dp_output(
 			enc110, &stream->public.timing);
 	break;
-	case SIGNAL_TYPE_WIRELESS:
-		is_valid = dce110_link_encoder_validate_wireless_output(
-			enc110, &stream->public.timing);
-	break;
 	default:
-		is_valid = true;
+		is_valid = false;
 	break;
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index 77f8aa410898..49c4b6587456 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -33,34 +33,16 @@ struct encoder_init_data {
 struct encoder_feature_support {
 	union {
 		struct {
-			/* 1 - external encoder; 0 - internal encoder */
-			uint32_t EXTERNAL_ENCODER:1;
-			uint32_t ANALOG_ENCODER:1;
-			uint32_t STEREO_SYNC:1;
-			/* check the DDC data pin
-			 * when performing DP Sink detection */
-			uint32_t DP_SINK_DETECT_POLL_DATA_PIN:1;
-			/* CPLIB authentication
-			 * for external DP chip supported */
-			uint32_t CPLIB_DP_AUTHENTICATION:1;
 			uint32_t IS_HBR2_CAPABLE:1;
 			uint32_t IS_HBR3_CAPABLE:1;
-			uint32_t IS_HBR2_VALIDATED:1;
 			uint32_t IS_TPS3_CAPABLE:1;
 			uint32_t IS_TPS4_CAPABLE:1;
-			uint32_t IS_AUDIO_CAPABLE:1;
-			uint32_t IS_VCE_SUPPORTED:1;
-			uint32_t IS_CONVERTER:1;
-			uint32_t IS_Y_ONLY_CAPABLE:1;
 			uint32_t IS_YCBCR_CAPABLE:1;
 		} bits;
 		uint32_t raw;
 	} flags;
-	/* maximum supported deep color depth */
-	enum dc_color_depth max_deep_color;
+
 	enum dc_color_depth max_hdmi_deep_color;
-	/* maximum supported clock */
-	unsigned int max_pixel_clock;
 	unsigned int max_hdmi_pixel_clock;
 	bool ycbcr420_supported;
 };
diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c
index bb4433ff3b6e..869dedca0b17 100644
--- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c
@@ -28,8 +28,6 @@
 
 #include "virtual_link_encoder.h"
 
-#define VIRTUAL_MAX_PIXEL_CLK_IN_KHZ 600000
-
 static bool virtual_link_encoder_validate_output_with_stream(
 	struct link_encoder *enc,
 	struct pipe_ctx *pipe_ctx) { return true; }
@@ -138,8 +136,6 @@ bool virtual_link_encoder_construct(
 
 	enc->transmitter = init_data->transmitter;
 
-	enc->features.max_pixel_clock = VIRTUAL_MAX_PIXEL_CLK_IN_KHZ;
-
 	enc->output_signals = SIGNAL_TYPE_VIRTUAL;
 
 	enc->preferred_engine = ENGINE_ID_VIRTUAL;
-- 
2.9.3

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[PATCH 4/6] drm/amd/display: limit HBR3 support to Polaris and up

[Harry Wentland]

From: Tony Cheng <tony.cheng@amd.com>

- also fix YCbCr420 supported on Polaris and up

Change-Id: I96c8ea9544ba6aa50841a2b4ca3d03b927916ca2
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c  | 31 ++++------------------
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h  |  1 +
 .../drm/amd/display/dc/dce100/dce100_resource.c    | 11 ++++++--
 .../drm/amd/display/dc/dce110/dce110_resource.c    | 11 ++++++--
 .../drm/amd/display/dc/dce112/dce112_resource.c    | 15 +++++++++--
 .../gpu/drm/amd/display/dc/dce80/dce80_resource.c  | 11 ++++++--
 6 files changed, 46 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index aa6b3449913c..323493b9e129 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -927,10 +927,14 @@ bool dce110_link_encoder_validate_dp_output(
 bool dce110_link_encoder_construct(
 	struct dce110_link_encoder *enc110,
 	const struct encoder_init_data *init_data,
+	const struct encoder_feature_support *enc_features,
 	const struct dce110_link_enc_registers *link_regs,
 	const struct dce110_link_enc_aux_registers *aux_regs,
 	const struct dce110_link_enc_hpd_registers *hpd_regs)
 {
+	struct bp_encoder_cap_info bp_cap_info = {0};
+	const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
+
 	enc110->base.funcs = &dce110_lnk_enc_funcs;
 	enc110->base.ctx = init_data->ctx;
 	enc110->base.id = init_data->encoder;
@@ -941,12 +945,10 @@ bool dce110_link_encoder_construct(
 
 	enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
 
-	enc110->base.features.flags.raw = 0;
+	enc110->base.features = *enc_features;
 
 	enc110->base.transmitter = init_data->transmitter;
 
-	enc110->base.features.max_hdmi_deep_color = COLOR_DEPTH_121212;
-
 	if (enc110->base.ctx->dc->debug.disable_hdmi_deep_color)
 		enc110->base.features.max_hdmi_deep_color = COLOR_DEPTH_888;
 
@@ -1013,10 +1015,6 @@ bool dce110_link_encoder_construct(
 			init_data->channel);
 
 	/* Override features with DCE-specific values */
-	{
-	struct bp_encoder_cap_info bp_cap_info = {0};
-	const struct dc_vbios_funcs *bp_funcs = enc110->base.ctx->dc_bios->funcs;
-
 	if (BP_RESULT_OK == bp_funcs->get_encoder_cap_info(
 			enc110->base.ctx->dc_bios, enc110->base.id,
 			&bp_cap_info))
@@ -1024,26 +1022,7 @@ bool dce110_link_encoder_construct(
 				bp_cap_info.DP_HBR2_CAP;
 		enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
 				bp_cap_info.DP_HBR3_EN;
-	}
-
-	/* TODO: check PPLIB maxPhyClockInKHz <= 540000, if yes,
-	 * IS_HBR3_CAPABLE = 0.
-	 */
 
-	/* test pattern 3 support */
-	enc110->base.features.flags.bits.IS_TPS3_CAPABLE = true;
-	/* test pattern 4 support */
-	enc110->base.features.flags.bits.IS_TPS4_CAPABLE = true;
-
-	/*
-		dal_adapter_service_is_feature_supported(as,
-			FEATURE_SUPPORT_DP_Y_ONLY);
-*/
-	enc110->base.features.flags.bits.IS_YCBCR_CAPABLE = true;
-	/*
-		dal_adapter_service_is_feature_supported(as,
-			FEATURE_SUPPORT_DP_YUV);
-			*/
 	return true;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
index 1635b239402f..b3667df5250b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
@@ -236,6 +236,7 @@ struct dce110_abm_backlight_registers {
 bool dce110_link_encoder_construct(
 	struct dce110_link_encoder *enc110,
 	const struct encoder_init_data *init_data,
+	const struct encoder_feature_support *enc_features,
 	const struct dce110_link_enc_registers *link_regs,
 	const struct dce110_link_enc_aux_registers *aux_regs,
 	const struct dce110_link_enc_hpd_registers *hpd_regs);
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 161d4eee4423..082f1f053a3a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -581,6 +581,14 @@ static struct input_pixel_processor *dce100_ipp_create(
 	return NULL;
 }
 
+static const struct encoder_feature_support link_enc_feature = {
+		.max_hdmi_deep_color = COLOR_DEPTH_121212,
+		.max_hdmi_pixel_clock = 300000,
+		.flags.bits.IS_HBR2_CAPABLE = true,
+		.flags.bits.IS_TPS3_CAPABLE = true,
+		.flags.bits.IS_YCBCR_CAPABLE = true
+};
+
 struct link_encoder *dce100_link_encoder_create(
 	const struct encoder_init_data *enc_init_data)
 {
@@ -593,12 +601,11 @@ struct link_encoder *dce100_link_encoder_create(
 	if (dce110_link_encoder_construct(
 			enc110,
 			enc_init_data,
+			&link_enc_feature,
 			&link_enc_regs[enc_init_data->transmitter],
 			&link_enc_aux_regs[enc_init_data->channel - 1],
 			&link_enc_hpd_regs[enc_init_data->hpd_source])) {
 
-		enc110->base.features.ycbcr420_supported = false;
-		enc110->base.features.max_hdmi_pixel_clock = 300000;
 		return &enc110->base;
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index d4e1ca933b40..ae90da8c1b8c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -570,6 +570,14 @@ static struct input_pixel_processor *dce110_ipp_create(
 	return NULL;
 }
 
+static const struct encoder_feature_support link_enc_feature = {
+		.max_hdmi_deep_color = COLOR_DEPTH_121212,
+		.max_hdmi_pixel_clock = 594000,
+		.flags.bits.IS_HBR2_CAPABLE = true,
+		.flags.bits.IS_TPS3_CAPABLE = true,
+		.flags.bits.IS_YCBCR_CAPABLE = true
+};
+
 struct link_encoder *dce110_link_encoder_create(
 	const struct encoder_init_data *enc_init_data)
 {
@@ -582,12 +590,11 @@ struct link_encoder *dce110_link_encoder_create(
 	if (dce110_link_encoder_construct(
 			enc110,
 			enc_init_data,
+			&link_enc_feature,
 			&link_enc_regs[enc_init_data->transmitter],
 			&link_enc_aux_regs[enc_init_data->channel - 1],
 			&link_enc_hpd_regs[enc_init_data->hpd_source])) {
 
-		enc110->base.features.ycbcr420_supported = false;
-		enc110->base.features.max_hdmi_pixel_clock = 594000;
 		return &enc110->base;
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 2711893b71e5..c63030e9f515 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -564,6 +564,18 @@ static struct transform *dce112_transform_create(
 	dm_free(transform);
 	return NULL;
 }
+
+static const struct encoder_feature_support link_enc_feature = {
+		.max_hdmi_deep_color = COLOR_DEPTH_121212,
+		.max_hdmi_pixel_clock = 600000,
+		.ycbcr420_supported = true,
+		.flags.bits.IS_HBR2_CAPABLE = true,
+		.flags.bits.IS_HBR3_CAPABLE = true,
+		.flags.bits.IS_TPS3_CAPABLE = true,
+		.flags.bits.IS_TPS4_CAPABLE = true,
+		.flags.bits.IS_YCBCR_CAPABLE = true
+};
+
 struct link_encoder *dce112_link_encoder_create(
 	const struct encoder_init_data *enc_init_data)
 {
@@ -576,12 +588,11 @@ struct link_encoder *dce112_link_encoder_create(
 	if (dce110_link_encoder_construct(
 			enc110,
 			enc_init_data,
+			&link_enc_feature,
 			&link_enc_regs[enc_init_data->transmitter],
 			&link_enc_aux_regs[enc_init_data->channel - 1],
 			&link_enc_hpd_regs[enc_init_data->hpd_source])) {
 
-		enc110->base.features.ycbcr420_supported = false;
-		enc110->base.features.max_hdmi_pixel_clock = 600000;
 		return &enc110->base;
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 56a63d985440..e2bfa7efce1c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -611,6 +611,14 @@ static struct input_pixel_processor *dce80_ipp_create(
 	return NULL;
 }
 
+static const struct encoder_feature_support link_enc_feature = {
+		.max_hdmi_deep_color = COLOR_DEPTH_121212,
+		.max_hdmi_pixel_clock = 297000,
+		.flags.bits.IS_HBR2_CAPABLE = true,
+		.flags.bits.IS_TPS3_CAPABLE = true,
+		.flags.bits.IS_YCBCR_CAPABLE = true
+};
+
 struct link_encoder *dce80_link_encoder_create(
 	const struct encoder_init_data *enc_init_data)
 {
@@ -623,12 +631,11 @@ struct link_encoder *dce80_link_encoder_create(
 	if (dce110_link_encoder_construct(
 			enc110,
 			enc_init_data,
+			&link_enc_feature,
 			&link_enc_regs[enc_init_data->transmitter],
 			&link_enc_aux_regs[enc_init_data->channel - 1],
 			&link_enc_hpd_regs[enc_init_data->hpd_source])) {
 
-		enc110->base.features.ycbcr420_supported = false;
-		enc110->base.features.max_hdmi_pixel_clock = 297000;
 		return &enc110->base;
 	}
 
-- 
2.9.3

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[PATCH 5/6] drm/amd/display: fix gamma for dpms usecase

[Harry Wentland]

From: Roman Li <Roman.Li@amd.com>

For dpms usecase we need to set surface transfer function
regardless of gamma set flag.

Change-Id: Ic9bade55ef72e16222569d4e3a18bab610a4b011
Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c    | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index fd03e4f7231b..439dde24e792 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -513,7 +513,6 @@ static void fill_gamma_from_crtc(
 {
 	int i;
 	struct dc_gamma *gamma;
-	struct dc_transfer_func *input_tf;
 	uint16_t *red, *green, *blue;
 	int end = (crtc->gamma_size > NUM_OF_RAW_GAMMA_RAMP_RGB_256) ?
 			NUM_OF_RAW_GAMMA_RAMP_RGB_256 : crtc->gamma_size;
@@ -534,16 +533,6 @@ static void fill_gamma_from_crtc(
 	}
 
 	dc_surface->gamma_correction = gamma;
-
-	input_tf = dc_create_transfer_func();
-
-	if (input_tf == NULL)
-		return;
-
-	input_tf->type = TF_TYPE_PREDEFINED;
-	input_tf->tf = TRANSFER_FUNCTION_SRGB;
-
-	dc_surface->in_transfer_func = input_tf;
 }
 
 static void fill_plane_attributes(
@@ -554,6 +543,7 @@ static void fill_plane_attributes(
 	const struct amdgpu_framebuffer *amdgpu_fb =
 		to_amdgpu_framebuffer(state->fb);
 	const struct drm_crtc *crtc = state->crtc;
+	struct dc_transfer_func *input_tf;
 
 	fill_rects_from_plane_state(state, surface);
 	fill_plane_attributes_from_fb(
@@ -562,6 +552,16 @@ static void fill_plane_attributes(
 		amdgpu_fb,
 		addrReq);
 
+	input_tf = dc_create_transfer_func();
+
+	if (input_tf == NULL)
+		return;
+
+	input_tf->type = TF_TYPE_PREDEFINED;
+	input_tf->tf = TRANSFER_FUNCTION_SRGB;
+
+	surface->in_transfer_func = input_tf;
+
 	/* In case of gamma set, update gamma value */
 	if (crtc->mode.private_flags &
 		AMDGPU_CRTC_MODE_PRIVATE_FLAGS_GAMMASET) {
-- 
2.9.3

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[PATCH 6/6] drm/amd/display: Fix DP PHY test pre-emphasis not set properly

[Harry Wentland]

From: Hersen Wu <hersenxs.wu@amd.com>

Change-Id: I7d910d09c8af042218aa0853abe041c2726856bc
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c              | 15 +++++++++++----
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c    |  9 +++++----
 drivers/gpu/drm/amd/display/dc/dc.h                   |  3 ++-
 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c |  2 +-
 4 files changed, 19 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index a7c6c980927e..25e7d7bc282b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -332,14 +332,21 @@ static bool setup_psr(struct dc *dc, const struct dc_stream *stream)
 }
 
 static void set_drive_settings(struct dc *dc,
-		struct link_training_settings *lt_settings)
+		struct link_training_settings *lt_settings,
+		const struct dc_link *link)
 {
 	struct core_dc *core_dc = DC_TO_CORE(dc);
 	int i;
 
-	for (i = 0; i < core_dc->link_count; i++)
-		dc_link_dp_set_drive_settings(&core_dc->links[i]->public,
-				lt_settings);
+	for (i = 0; i < core_dc->link_count; i++) {
+		if (&core_dc->links[i]->public == link)
+			break;
+	}
+
+	if (i >= core_dc->link_count)
+		ASSERT_CRITICAL(false);
+
+	dc_link_dp_set_drive_settings(&core_dc->links[i]->public, lt_settings);
 }
 
 static void perform_link_training(struct dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index e287584ade29..da49be0672d7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -229,10 +229,9 @@ void dp_retrain_link_dp_test(struct core_link *link,
 					link->link_enc,
 					SIGNAL_TYPE_DISPLAY_PORT);
 
-			/* Clear current link setting.
-			 * memset(&link->public.cur_link_settings, 0,
-			 * 	sizeof(link->public.cur_link_settings));
-			 */
+			/* Clear current link setting. */
+			memset(&link->public.cur_link_settings, 0,
+				sizeof(link->public.cur_link_settings));
 
 			link->link_enc->funcs->enable_dp_output(
 						link->link_enc,
@@ -246,6 +245,8 @@ void dp_retrain_link_dp_test(struct core_link *link,
 					link_setting,
 					skip_video_pattern);
 
+			link->public.cur_link_settings = *link_setting;
+
 			link->dc->hwss.unblank_stream(&pipes[i],
 					link_setting);
 		}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 83d78c2dc24d..64002268818a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -112,7 +112,8 @@ struct link_training_settings;
 
 struct dc_link_funcs {
 	void (*set_drive_settings)(struct dc *dc,
-			struct link_training_settings *lt_settings);
+			struct link_training_settings *lt_settings,
+			const struct dc_link *link);
 	void (*perform_link_training)(struct dc *dc,
 			struct dc_link_settings *link_setting,
 			bool skip_video_pattern);
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index 323493b9e129..cb5e5953b7ab 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -1363,7 +1363,7 @@ void dce110_link_encoder_dp_set_lane_settings(
 	cntl.pixel_clock = link_settings->link_settings.link_rate *
 						LINK_RATE_REF_FREQ_IN_KHZ;
 
-	for (lane = 0; lane < link_settings->link_settings.lane_count; ++lane) {
+	for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
 		/* translate lane settings */
 
 		training_lane_set.bits.VOLTAGE_SWING_SET =
-- 
2.9.3

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