* [CI 1/5] drm/i915: Assert all timeline requests are gone before fini
@ 2017-01-05 15:30 Chris Wilson
2017-01-05 15:30 ` [CI 2/5] drm/i915: Assert that we do create the deferred context Chris Wilson
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Chris Wilson @ 2017-01-05 15:30 UTC (permalink / raw)
To: intel-gfx
During i915_gem_timeline_fini(), assert that all the timeline's request
are completed and removed from the timeline.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_gem_timeline.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_timeline.c b/drivers/gpu/drm/i915/i915_gem_timeline.c
index bf8a471b61e6..b596ca7ee058 100644
--- a/drivers/gpu/drm/i915/i915_gem_timeline.c
+++ b/drivers/gpu/drm/i915/i915_gem_timeline.c
@@ -81,10 +81,18 @@ int i915_gem_timeline_init__global(struct drm_i915_private *i915)
&class, "&global_timeline->lock");
}
-void i915_gem_timeline_fini(struct i915_gem_timeline *tl)
+void i915_gem_timeline_fini(struct i915_gem_timeline *timeline)
{
- lockdep_assert_held(&tl->i915->drm.struct_mutex);
+ int i;
- list_del(&tl->link);
- kfree(tl->name);
+ lockdep_assert_held(&timeline->i915->drm.struct_mutex);
+
+ for (i = 0; i < ARRAY_SIZE(timeline->engine); i++) {
+ struct intel_timeline *tl = &timeline->engine[i];
+
+ GEM_BUG_ON(!list_empty(&tl->requests));
+ }
+
+ list_del(&timeline->link);
+ kfree(timeline->name);
}
--
2.11.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [CI 2/5] drm/i915: Assert that we do create the deferred context
2017-01-05 15:30 [CI 1/5] drm/i915: Assert all timeline requests are gone before fini Chris Wilson
@ 2017-01-05 15:30 ` Chris Wilson
2017-01-05 15:30 ` [CI 3/5] drm/i915/execlists: Reorder execlists register enabling Chris Wilson
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2017-01-05 15:30 UTC (permalink / raw)
To: intel-gfx
In order to convince static analyzers that the allocation function
returns an error or sets ce->state, assert that it is set afterwards.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 227978820320..51ecb395551b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -781,6 +781,7 @@ static int execlists_context_pin(struct intel_engine_cs *engine,
if (ret)
goto err;
}
+ GEM_BUG_ON(!ce->state);
flags = PIN_GLOBAL;
if (ctx->ggtt_offset_bias)
--
2.11.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [CI 3/5] drm/i915/execlists: Reorder execlists register enabling
2017-01-05 15:30 [CI 1/5] drm/i915: Assert all timeline requests are gone before fini Chris Wilson
2017-01-05 15:30 ` [CI 2/5] drm/i915: Assert that we do create the deferred context Chris Wilson
@ 2017-01-05 15:30 ` Chris Wilson
2017-01-05 15:30 ` [CI 4/5] drm/i915: Move a few utility macros into a separate header Chris Wilson
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2017-01-05 15:30 UTC (permalink / raw)
To: intel-gfx
Empirically we restart following a GPU reset more successfully if we call
lrc_init_hws() (which contains a posting read) last. (The failure mode
that was observed was that breadcrumb writes into the HWS from the
recovered requests went astray leading to the context-switch maintaining
forward progress, but the requests not being retired/completed.)
For clarity, lrc_init_hws() is inlined (and the unused function then
removed).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 18 ++++--------------
1 file changed, 4 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 51ecb395551b..a9eefb171170 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1335,15 +1335,6 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
return ret;
}
-static void lrc_init_hws(struct intel_engine_cs *engine)
-{
- struct drm_i915_private *dev_priv = engine->i915;
-
- I915_WRITE(RING_HWS_PGA(engine->mmio_base),
- engine->status_page.ggtt_offset);
- POSTING_READ(RING_HWS_PGA(engine->mmio_base));
-}
-
static int gen8_init_common_ring(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
@@ -1353,20 +1344,19 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
if (ret)
return ret;
- lrc_init_hws(engine);
-
intel_engine_reset_breadcrumbs(engine);
+ intel_engine_init_hangcheck(engine);
I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
-
I915_WRITE(RING_MODE_GEN7(engine),
_MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
_MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
+ I915_WRITE(RING_HWS_PGA(engine->mmio_base),
+ engine->status_page.ggtt_offset);
+ POSTING_READ(RING_HWS_PGA(engine->mmio_base));
DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
- intel_engine_init_hangcheck(engine);
-
/* After a GPU reset, we may have requests to replay */
if (!execlists_elsp_idle(engine)) {
engine->execlist_port[0].count = 0;
--
2.11.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [CI 4/5] drm/i915: Move a few utility macros into a separate header
2017-01-05 15:30 [CI 1/5] drm/i915: Assert all timeline requests are gone before fini Chris Wilson
2017-01-05 15:30 ` [CI 2/5] drm/i915: Assert that we do create the deferred context Chris Wilson
2017-01-05 15:30 ` [CI 3/5] drm/i915/execlists: Reorder execlists register enabling Chris Wilson
@ 2017-01-05 15:30 ` Chris Wilson
2017-01-05 15:30 ` [CI 5/5] drm/i915/guc: Exclude the upper end of the Global GTT for the GuC Chris Wilson
2017-01-05 16:23 ` ✓ Fi.CI.BAT: success for series starting with [CI,1/5] drm/i915: Assert all timeline requests are gone before fini Patchwork
4 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2017-01-05 15:30 UTC (permalink / raw)
To: intel-gfx
In order to defeat some circular dependencies between headers to allow use
of e.g. range_overflows() in a header, move the simple independent macros
into their own header.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 13 +-----------
drivers/gpu/drm/i915/i915_gem.c | 4 ----
drivers/gpu/drm/i915/i915_utils.h | 44 +++++++++++++++++++++++++++++++++++++++
3 files changed, 45 insertions(+), 16 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_utils.h
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7b436621d038..abc8d737cd68 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -52,6 +52,7 @@
#include "i915_params.h"
#include "i915_reg.h"
+#include "i915_utils.h"
#include "intel_bios.h"
#include "intel_dpll_mgr.h"
@@ -219,18 +220,6 @@ static inline const char *enableddisabled(bool v)
return v ? "enabled" : "disabled";
}
-#define range_overflows(start, size, max) ({ \
- typeof(start) start__ = (start); \
- typeof(size) size__ = (size); \
- typeof(max) max__ = (max); \
- (void)(&start__ == &size__); \
- (void)(&start__ == &max__); \
- start__ > max__ || size__ > max__ - start__; \
-})
-
-#define range_overflows_t(type, start, size, max) \
- range_overflows((type)(start), (type)(size), (type)(max))
-
enum pipe {
INVALID_PIPE = -1,
PIPE_A = 0,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 37107448a42b..70ddff3570bb 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4004,10 +4004,6 @@ static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
.put_pages = i915_gem_object_put_pages_gtt,
};
-/* Note we don't consider signbits :| */
-#define overflows_type(x, T) \
- (sizeof(x) > sizeof(T) && (x) >> (sizeof(T) * BITS_PER_BYTE))
-
struct drm_i915_gem_object *
i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size)
{
diff --git a/drivers/gpu/drm/i915/i915_utils.h b/drivers/gpu/drm/i915/i915_utils.h
new file mode 100644
index 000000000000..9983ef30bac8
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __I915_UTILS_H
+#define __I915_UTILS_H
+
+#define range_overflows(start, size, max) ({ \
+ typeof(start) start__ = (start); \
+ typeof(size) size__ = (size); \
+ typeof(max) max__ = (max); \
+ (void)(&start__ == &size__); \
+ (void)(&start__ == &max__); \
+ start__ > max__ || size__ > max__ - start__; \
+})
+
+#define range_overflows_t(type, start, size, max) \
+ range_overflows((type)(start), (type)(size), (type)(max))
+
+/* Note we don't consider signbits :| */
+#define overflows_type(x, T) \
+ (sizeof(x) > sizeof(T) && (x) >> (sizeof(T) * BITS_PER_BYTE))
+
+#endif /* !__I915_UTILS_H */
--
2.11.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [CI 5/5] drm/i915/guc: Exclude the upper end of the Global GTT for the GuC
2017-01-05 15:30 [CI 1/5] drm/i915: Assert all timeline requests are gone before fini Chris Wilson
` (2 preceding siblings ...)
2017-01-05 15:30 ` [CI 4/5] drm/i915: Move a few utility macros into a separate header Chris Wilson
@ 2017-01-05 15:30 ` Chris Wilson
2017-01-05 16:23 ` ✓ Fi.CI.BAT: success for series starting with [CI,1/5] drm/i915: Assert all timeline requests are gone before fini Patchwork
4 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2017-01-05 15:30 UTC (permalink / raw)
To: intel-gfx
The GuC uses a special mapping for the upper end of the Global GTT,
similar to the way it uses a special mapping for the lower end, so
exclude it from our drm_mm to prevent us using it.
v2: Rename to reflect that it is unmappable similar to the region at the
bottom of the GGTT, and couple it into the assertion that we don't feed
unmappable addresses to the GuC.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 10 ++++++++++
drivers/gpu/drm/i915/i915_guc_reg.h | 3 +++
drivers/gpu/drm/i915/intel_uc.h | 1 +
3 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 6af9311f72f5..bc2b4421cbd6 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3176,6 +3176,16 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
if (ret)
return ret;
+ /* Trim the GGTT to fit the GuC mappable upper range (when enabled).
+ * This is easier than doing range restriction on the fly, as we
+ * currently don't have any bits spare to pass in this upper
+ * restriction!
+ */
+ if (HAS_GUC(dev_priv) && i915.enable_guc_loading) {
+ ggtt->base.total = min_t(u64, ggtt->base.total, GUC_GGTT_TOP);
+ ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total);
+ }
+
if ((ggtt->base.total - 1) >> 32) {
DRM_ERROR("We never expected a Global GTT with more than 32bits"
" of address space! Found %lldM!\n",
diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
index 5e638fc37208..6a0adafe0523 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -73,6 +73,9 @@
#define GUC_WOPCM_TOP (0x80 << 12) /* 512KB */
#define BXT_GUC_WOPCM_RC6_RESERVED (0x10 << 12) /* 64KB */
+/* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
+#define GUC_GGTT_TOP 0xFEE00000
+
#define GEN8_GT_PM_CONFIG _MMIO(0x138140)
#define GEN9LP_GT_PM_CONFIG _MMIO(0x138140)
#define GEN9_GT_PM_CONFIG _MMIO(0x13816c)
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 3b1e39b0f3ab..9490a8e049c3 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -203,6 +203,7 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma)
{
u32 offset = i915_ggtt_offset(vma);
GEM_BUG_ON(offset < GUC_WOPCM_TOP);
+ GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
return offset;
}
--
2.11.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [CI,1/5] drm/i915: Assert all timeline requests are gone before fini
2017-01-05 15:30 [CI 1/5] drm/i915: Assert all timeline requests are gone before fini Chris Wilson
` (3 preceding siblings ...)
2017-01-05 15:30 ` [CI 5/5] drm/i915/guc: Exclude the upper end of the Global GTT for the GuC Chris Wilson
@ 2017-01-05 16:23 ` Patchwork
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2017-01-05 16:23 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,1/5] drm/i915: Assert all timeline requests are gone before fini
URL : https://patchwork.freedesktop.org/series/17556/
State : success
== Summary ==
Series 17556v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/17556/revisions/1/mbox/
Test kms_force_connector_basic:
Subgroup prune-stale-modes:
dmesg-warn -> PASS (fi-snb-2520m)
fi-bdw-5557u total:246 pass:231 dwarn:0 dfail:0 fail:1 skip:14
fi-bsw-n3050 total:246 pass:206 dwarn:0 dfail:0 fail:1 skip:39
fi-bxt-j4205 total:246 pass:223 dwarn:0 dfail:0 fail:1 skip:22
fi-bxt-t5700 total:82 pass:69 dwarn:0 dfail:0 fail:0 skip:12
fi-byt-j1900 total:246 pass:218 dwarn:0 dfail:0 fail:1 skip:27
fi-byt-n2820 total:246 pass:214 dwarn:0 dfail:0 fail:1 skip:31
fi-hsw-4770 total:246 pass:226 dwarn:0 dfail:0 fail:1 skip:19
fi-hsw-4770r total:246 pass:226 dwarn:0 dfail:0 fail:1 skip:19
fi-ivb-3520m total:246 pass:224 dwarn:0 dfail:0 fail:1 skip:21
fi-ivb-3770 total:246 pass:224 dwarn:0 dfail:0 fail:1 skip:21
fi-kbl-7500u total:246 pass:224 dwarn:0 dfail:0 fail:1 skip:21
fi-skl-6260u total:246 pass:232 dwarn:0 dfail:0 fail:1 skip:13
fi-skl-6700hq total:246 pass:226 dwarn:0 dfail:0 fail:0 skip:20
fi-skl-6700k total:246 pass:221 dwarn:3 dfail:0 fail:1 skip:21
fi-skl-6770hq total:246 pass:232 dwarn:0 dfail:0 fail:1 skip:13
fi-snb-2520m total:246 pass:214 dwarn:0 dfail:0 fail:1 skip:31
fi-snb-2600 total:246 pass:213 dwarn:0 dfail:0 fail:1 skip:32
6a304f1f2e7446fe71bf7845c34dcdc73436c547 drm-tip: 2017y-01m-05d-11h-52m-09s UTC integration manifest
27795ba drm/i915/guc: Exclude the upper end of the Global GTT for the GuC
a6cc0d9 drm/i915: Move a few utility macros into a separate header
254e24a drm/i915/execlists: Reorder execlists register enabling
ce0843f drm/i915: Assert that we do create the deferred context
18d68ad drm/i915: Assert all timeline requests are gone before fini
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3439/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-01-05 16:23 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-01-05 15:30 [CI 1/5] drm/i915: Assert all timeline requests are gone before fini Chris Wilson
2017-01-05 15:30 ` [CI 2/5] drm/i915: Assert that we do create the deferred context Chris Wilson
2017-01-05 15:30 ` [CI 3/5] drm/i915/execlists: Reorder execlists register enabling Chris Wilson
2017-01-05 15:30 ` [CI 4/5] drm/i915: Move a few utility macros into a separate header Chris Wilson
2017-01-05 15:30 ` [CI 5/5] drm/i915/guc: Exclude the upper end of the Global GTT for the GuC Chris Wilson
2017-01-05 16:23 ` ✓ Fi.CI.BAT: success for series starting with [CI,1/5] drm/i915: Assert all timeline requests are gone before fini Patchwork
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