From: Wenyou Yang <wenyou.yang@atmel.com>
To: Alexandre Belloni <alexandre.belloni@free-electrons.com>,
Russell King <linux@arm.linux.org.uk>,
Nicolas Ferre <nicolas.ferre@atmel.com>,
"Rob Herring" <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>
Cc: <linux-kernel@vger.kernel.org>,
Wenyou Yang <wenyou.yang@microchip.com>,
<devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Wenyou Yang <wenyou.yang@atmel.com>
Subject: [PATCH 0/3] ARM: at91: fix cpuidle crash on SAMA5D4 Xplained board
Date: Fri, 6 Jan 2017 14:59:44 +0800 [thread overview]
Message-ID: <20170106065947.30631-1-wenyou.yang@atmel.com> (raw)
Fix cpuidle crash on SAMA5D4 Xplained board when enable
CONFIG_ARM_AT91_CPUIDLE. Because some SoCs have the L2 cache,
we should flush the L2 cache before entering the cpu idle.
Wenyou Yang (3):
ARM: at91: flush the L2 cache before entering cpu idle
doc: binding: add new compatible for SDRAM/DDR Controller
ARM: dts: at91: use "atmel,sama5d4-ddramc" for ramc
Documentation/devicetree/bindings/arm/atmel-at91.txt | 1 +
arch/arm/boot/dts/sama5d2.dtsi | 2 +-
arch/arm/boot/dts/sama5d4.dtsi | 2 +-
arch/arm/mach-at91/pm.c | 19 +++++++++++++++++++
drivers/memory/atmel-sdramc.c | 1 +
5 files changed, 23 insertions(+), 2 deletions(-)
--
2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: Wenyou Yang <wenyou.yang@atmel.com>
To: Alexandre Belloni <alexandre.belloni@free-electrons.com>,
Russell King <linux@arm.linux.org.uk>,
Nicolas Ferre <nicolas.ferre@atmel.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Wenyou Yang <wenyou.yang@microchip.com>,
Wenyou Yang <wenyou.yang@atmel.com>
Subject: [PATCH 0/3] ARM: at91: fix cpuidle crash on SAMA5D4 Xplained board
Date: Fri, 6 Jan 2017 14:59:44 +0800 [thread overview]
Message-ID: <20170106065947.30631-1-wenyou.yang@atmel.com> (raw)
Fix cpuidle crash on SAMA5D4 Xplained board when enable
CONFIG_ARM_AT91_CPUIDLE. Because some SoCs have the L2 cache,
we should flush the L2 cache before entering the cpu idle.
Wenyou Yang (3):
ARM: at91: flush the L2 cache before entering cpu idle
doc: binding: add new compatible for SDRAM/DDR Controller
ARM: dts: at91: use "atmel,sama5d4-ddramc" for ramc
Documentation/devicetree/bindings/arm/atmel-at91.txt | 1 +
arch/arm/boot/dts/sama5d2.dtsi | 2 +-
arch/arm/boot/dts/sama5d4.dtsi | 2 +-
arch/arm/mach-at91/pm.c | 19 +++++++++++++++++++
drivers/memory/atmel-sdramc.c | 1 +
5 files changed, 23 insertions(+), 2 deletions(-)
--
2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: wenyou.yang@atmel.com (Wenyou Yang)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 0/3] ARM: at91: fix cpuidle crash on SAMA5D4 Xplained board
Date: Fri, 6 Jan 2017 14:59:44 +0800 [thread overview]
Message-ID: <20170106065947.30631-1-wenyou.yang@atmel.com> (raw)
Fix cpuidle crash on SAMA5D4 Xplained board when enable
CONFIG_ARM_AT91_CPUIDLE. Because some SoCs have the L2 cache,
we should flush the L2 cache before entering the cpu idle.
Wenyou Yang (3):
ARM: at91: flush the L2 cache before entering cpu idle
doc: binding: add new compatible for SDRAM/DDR Controller
ARM: dts: at91: use "atmel,sama5d4-ddramc" for ramc
Documentation/devicetree/bindings/arm/atmel-at91.txt | 1 +
arch/arm/boot/dts/sama5d2.dtsi | 2 +-
arch/arm/boot/dts/sama5d4.dtsi | 2 +-
arch/arm/mach-at91/pm.c | 19 +++++++++++++++++++
drivers/memory/atmel-sdramc.c | 1 +
5 files changed, 23 insertions(+), 2 deletions(-)
--
2.11.0
next reply other threads:[~2017-01-06 7:09 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-06 6:59 Wenyou Yang [this message]
2017-01-06 6:59 ` [PATCH 0/3] ARM: at91: fix cpuidle crash on SAMA5D4 Xplained board Wenyou Yang
2017-01-06 6:59 ` Wenyou Yang
2017-01-06 6:59 ` [PATCH 1/3] ARM: at91: flush the L2 cache before entering cpu idle Wenyou Yang
2017-01-06 6:59 ` Wenyou Yang
2017-01-06 6:59 ` Wenyou Yang
2017-01-06 9:05 ` Alexandre Belloni
2017-01-06 9:05 ` Alexandre Belloni
2017-01-06 9:05 ` Alexandre Belloni
2017-01-09 1:47 ` Wenyou.Yang
2017-01-09 1:47 ` Wenyou.Yang at microchip.com
2017-01-09 1:47 ` Wenyou.Yang-UWL1GkI3JZL3oGB3hsPCZA
2017-01-10 16:18 ` Alexandre Belloni
2017-01-10 16:18 ` Alexandre Belloni
2017-01-10 16:18 ` Alexandre Belloni
2017-01-10 16:30 ` Alexandre Belloni
2017-01-10 16:30 ` Alexandre Belloni
2017-01-10 16:30 ` Alexandre Belloni
2017-01-10 16:50 ` Jean-Jacques Hiblot
2017-01-10 16:50 ` Jean-Jacques Hiblot
2017-01-10 16:50 ` Jean-Jacques Hiblot
2017-01-10 17:22 ` Alexandre Belloni
2017-01-10 17:22 ` Alexandre Belloni
2017-01-10 17:22 ` Alexandre Belloni
2017-01-11 8:15 ` Wenyou.Yang
2017-01-11 8:15 ` Wenyou.Yang at microchip.com
2017-01-11 8:15 ` Wenyou.Yang
2017-01-11 11:05 ` Jean-Jacques Hiblot
2017-01-11 11:05 ` Jean-Jacques Hiblot
2017-01-11 11:05 ` Jean-Jacques Hiblot
2017-01-11 11:18 ` Russell King - ARM Linux
2017-01-11 11:18 ` Russell King - ARM Linux
2017-01-11 11:18 ` Russell King - ARM Linux
2017-01-11 13:18 ` Jean-Jacques Hiblot
2017-01-11 13:18 ` Jean-Jacques Hiblot
2017-01-11 13:18 ` Jean-Jacques Hiblot
2017-01-12 1:25 ` Wenyou.Yang
2017-01-12 1:25 ` Wenyou.Yang at microchip.com
2017-01-12 1:25 ` Wenyou.Yang-UWL1GkI3JZL3oGB3hsPCZA
2017-01-06 6:59 ` [PATCH 2/3] doc: binding: add new compatible for SDRAM/DDR Controller Wenyou Yang
2017-01-06 6:59 ` Wenyou Yang
2017-01-06 6:59 ` Wenyou Yang
2017-01-09 18:45 ` Rob Herring
2017-01-09 18:45 ` Rob Herring
2017-01-06 6:59 ` [PATCH 3/3] ARM: dts: at91: use "atmel,sama5d4-ddramc" for ramc Wenyou Yang
2017-01-06 6:59 ` Wenyou Yang
2017-01-06 6:59 ` Wenyou Yang
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