[PATCH 1/2] ASoC: nau8825: correct the function name of register

[PATCH 1/2] ASoC: nau8825: correct the function name of register

[John Hsu]

Change to correct name of the register function.

Signed-off-by: John Hsu <KCHSU0@nuvoton.com>
---
 sound/soc/codecs/nau8825.c | 6 +++---
 sound/soc/codecs/nau8825.h | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/sound/soc/codecs/nau8825.c b/sound/soc/codecs/nau8825.c
index e4fb017..9c98d35 100644
--- a/sound/soc/codecs/nau8825.c
+++ b/sound/soc/codecs/nau8825.c
@@ -561,9 +561,9 @@ static void nau8825_xtalk_prepare(struct nau8825 *nau8825)
 	nau8825_xtalk_backup(nau8825);
 	/* Config IIS as master to output signal by codec */
 	regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
-		NAU8825_I2S_MS_MASK | NAU8825_I2S_DRV_MASK |
+		NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK |
 		NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_MASTER |
-		(0x2 << NAU8825_I2S_DRV_SFT) | 0x1);
+		(0x2 << NAU8825_I2S_LRC_DIV_SFT) | 0x1);
 	/* Ramp up headphone volume to 0dB to get better performance and
 	 * avoid pop noise in headphone.
 	 */
@@ -657,7 +657,7 @@ static void nau8825_xtalk_clean(struct nau8825 *nau8825)
 		NAU8825_IRQ_RMS_EN, NAU8825_IRQ_RMS_EN);
 	/* Recover default value for IIS */
 	regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
-		NAU8825_I2S_MS_MASK | NAU8825_I2S_DRV_MASK |
+		NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK |
 		NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_SLAVE);
 	/* Restore value of specific register for cross talk */
 	nau8825_xtalk_restore(nau8825);
diff --git a/sound/soc/codecs/nau8825.h b/sound/soc/codecs/nau8825.h
index 5732ce1..4b390c4 100644
--- a/sound/soc/codecs/nau8825.h
+++ b/sound/soc/codecs/nau8825.h
@@ -248,8 +248,8 @@
 
 /* I2S_PCM_CTRL2 (0x1d) */
 #define NAU8825_I2S_TRISTATE	(1 << 15) /* 0 - normal mode, 1 - Hi-Z output */
-#define NAU8825_I2S_DRV_SFT	12
-#define NAU8825_I2S_DRV_MASK	(0x3 << NAU8825_I2S_DRV_SFT)
+#define NAU8825_I2S_LRC_DIV_SFT	12
+#define NAU8825_I2S_LRC_DIV_MASK	(0x3 << NAU8825_I2S_LRC_DIV_SFT)
 #define NAU8825_I2S_MS_SFT	3
 #define NAU8825_I2S_MS_MASK	(1 << NAU8825_I2S_MS_SFT)
 #define NAU8825_I2S_MS_MASTER	(1 << NAU8825_I2S_MS_SFT)
-- 
2.6.4

[PATCH 2/2] ASoC: nau8825: provide clock divide for codec mater mode

[John Hsu]

Provide the LRC and BCLK divide. The clock divide needs configuration
properly when codec in master mode.

Signed-off-by: John Hsu <KCHSU0@nuvoton.com>
---
 sound/soc/codecs/nau8825.c | 26 ++++++++++++++++++++++++++
 sound/soc/codecs/nau8825.h |  6 ++++++
 2 files changed, 32 insertions(+)

diff --git a/sound/soc/codecs/nau8825.c b/sound/soc/codecs/nau8825.c
index 9c98d35..3c7a801 100644
--- a/sound/soc/codecs/nau8825.c
+++ b/sound/soc/codecs/nau8825.c
@@ -1421,9 +1421,35 @@ static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 	return 0;
 }
 
+static int nau8825_set_clkdiv(struct snd_soc_dai *codec_dai,
+	int div_id, int div)
+{
+	struct snd_soc_codec *codec = codec_dai->codec;
+	struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
+
+	switch (div_id) {
+	case NAU8825_BCLKDIV:
+		regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
+			NAU8825_I2S_BLK_DIV_MASK, div);
+		break;
+
+	case NAU8825_FSDIV:
+		regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
+			NAU8825_I2S_LRC_DIV_MASK,
+			div << NAU8825_I2S_LRC_DIV_SFT);
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 static const struct snd_soc_dai_ops nau8825_dai_ops = {
 	.hw_params	= nau8825_hw_params,
 	.set_fmt	= nau8825_set_dai_fmt,
+	.set_clkdiv	= nau8825_set_clkdiv,
 };
 
 #define NAU8825_RATES	SNDRV_PCM_RATE_8000_192000
diff --git a/sound/soc/codecs/nau8825.h b/sound/soc/codecs/nau8825.h
index 4b390c4..58b8554 100644
--- a/sound/soc/codecs/nau8825.h
+++ b/sound/soc/codecs/nau8825.h
@@ -425,6 +425,12 @@
 #define NAU8825_CHANRGE_PUMP_EN	(1 << 5)
 
 
+/* Programmable divide */
+enum {
+	NAU8825_BCLKDIV,
+	NAU8825_FSDIV,
+};
+
 /* System Clock Source */
 enum {
 	NAU8825_CLK_DIS = 0,
-- 
2.6.4

Re: [PATCH 2/2] ASoC: nau8825: provide clock divide for codec mater mode

[Mark Brown]

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On Tue, Dec 20, 2016 at 04:47:07PM +0800, John Hsu wrote:
> Provide the LRC and BCLK divide. The clock divide needs configuration
> properly when codec in master mode.

Why is the driver not able to configure these automatically, most
devices manage to do that OK?  Typically systems are fine with the
obvious divisions down from the root clock, the driver should at least
offer that as a default rather than requiring all machine drivers to
duplicate the divisor selection code.

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Applied "ASoC: nau8825: correct the function name of register" to the asoc tree

[Mark Brown]

The patch

   ASoC: nau8825: correct the function name of register

has been applied to the asoc tree at

   git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From a33b56a6a824fa5cd89c74f85cbeb9af1dcef87e Mon Sep 17 00:00:00 2001
From: John Hsu <KCHSU0@nuvoton.com>
Date: Tue, 20 Dec 2016 16:47:06 +0800
Subject: [PATCH] ASoC: nau8825: correct the function name of register

Change to correct name of the register function.

Signed-off-by: John Hsu <KCHSU0@nuvoton.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/codecs/nau8825.c | 6 +++---
 sound/soc/codecs/nau8825.h | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/sound/soc/codecs/nau8825.c b/sound/soc/codecs/nau8825.c
index efe3a44658d5..abf77dd422f4 100644
--- a/sound/soc/codecs/nau8825.c
+++ b/sound/soc/codecs/nau8825.c
@@ -561,9 +561,9 @@ static void nau8825_xtalk_prepare(struct nau8825 *nau8825)
 	nau8825_xtalk_backup(nau8825);
 	/* Config IIS as master to output signal by codec */
 	regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
-		NAU8825_I2S_MS_MASK | NAU8825_I2S_DRV_MASK |
+		NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK |
 		NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_MASTER |
-		(0x2 << NAU8825_I2S_DRV_SFT) | 0x1);
+		(0x2 << NAU8825_I2S_LRC_DIV_SFT) | 0x1);
 	/* Ramp up headphone volume to 0dB to get better performance and
 	 * avoid pop noise in headphone.
 	 */
@@ -657,7 +657,7 @@ static void nau8825_xtalk_clean(struct nau8825 *nau8825)
 		NAU8825_IRQ_RMS_EN, NAU8825_IRQ_RMS_EN);
 	/* Recover default value for IIS */
 	regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
-		NAU8825_I2S_MS_MASK | NAU8825_I2S_DRV_MASK |
+		NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK |
 		NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_SLAVE);
 	/* Restore value of specific register for cross talk */
 	nau8825_xtalk_restore(nau8825);
diff --git a/sound/soc/codecs/nau8825.h b/sound/soc/codecs/nau8825.h
index 5d1704e73241..b6b21b312854 100644
--- a/sound/soc/codecs/nau8825.h
+++ b/sound/soc/codecs/nau8825.h
@@ -247,8 +247,8 @@
 
 /* I2S_PCM_CTRL2 (0x1d) */
 #define NAU8825_I2S_TRISTATE	(1 << 15) /* 0 - normal mode, 1 - Hi-Z output */
-#define NAU8825_I2S_DRV_SFT	12
-#define NAU8825_I2S_DRV_MASK	(0x3 << NAU8825_I2S_DRV_SFT)
+#define NAU8825_I2S_LRC_DIV_SFT	12
+#define NAU8825_I2S_LRC_DIV_MASK	(0x3 << NAU8825_I2S_LRC_DIV_SFT)
 #define NAU8825_I2S_MS_SFT	3
 #define NAU8825_I2S_MS_MASK	(1 << NAU8825_I2S_MS_SFT)
 #define NAU8825_I2S_MS_MASTER	(1 << NAU8825_I2S_MS_SFT)
-- 
2.11.0

Re: [PATCH 2/2] ASoC: nau8825: provide clock divide for codec mater mode

[John Hsu]

On 1/1/2017 2:57 AM, Mark Brown wrote:
> On Tue, Dec 20, 2016 at 04:47:07PM +0800, John Hsu wrote:
>
>> Provide the LRC and BCLK divide. The clock divide needs configuration
>> properly when codec in master mode.
>>
>
> Why is the driver not able to configure these automatically, most
> devices manage to do that OK?  Typically systems are fine with the
> obvious divisions down from the root clock, the driver should at least
> offer that as a default rather than requiring all machine drivers to
> duplicate the divisor selection code.
>

The system clock of codec is always 256FS. Therefore, the driver can
make it automatically. If the codec is as master, the driver needs to
divide the system clock to output the BCLK and FS. But there are too
many combinations between BCLK and FS. The BCLK maybe is 32FS, 64FS,
128FS, etc. The driver needs machine information to do the division.
Thus, I think the best way is to make decision by machine driver.



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Re: [PATCH 2/2] ASoC: nau8825: provide clock divide for codec mater mode

[Mark Brown]

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On Tue, Jan 03, 2017 at 11:04:50AM +0800, John Hsu wrote:
> On 1/1/2017 2:57 AM, Mark Brown wrote:

> > Why is the driver not able to configure these automatically, most
> > devices manage to do that OK?  Typically systems are fine with the
> > obvious divisions down from the root clock, the driver should at least
> > offer that as a default rather than requiring all machine drivers to
> > duplicate the divisor selection code.

> The system clock of codec is always 256FS. Therefore, the driver can
> make it automatically. If the codec is as master, the driver needs to
> divide the system clock to output the BCLK and FS. But there are too
> many combinations between BCLK and FS. The BCLK maybe is 32FS, 64FS,
> 128FS, etc. The driver needs machine information to do the division.
> Thus, I think the best way is to make decision by machine driver.

This all sounds totally standard - other drivers manage to provide a
default easily enough here.  You can determine a default BCLK by looking
at the number of channels and number of bits per sample to work out how
many BCLKs are going to be needed to clock that data out.

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Re: [PATCH 2/2] ASoC: nau8825: provide clock divide for codec mater mode

[John Hsu]

Hi,

On 1/9/2017 7:42 PM, Mark Brown wrote:
> On Tue, Jan 03, 2017 at 11:04:50AM +0800, John Hsu wrote:
>
>> On 1/1/2017 2:57 AM, Mark Brown wrote:
>>
>
>
>>> Why is the driver not able to configure these automatically, most
>>> devices manage to do that OK?  Typically systems are fine with the
>>> obvious divisions down from the root clock, the driver should at least
>>> offer that as a default rather than requiring all machine drivers to
>>> duplicate the divisor selection code.
>>>
>
>
>> The system clock of codec is always 256FS. Therefore, the driver can
>> make it automatically. If the codec is as master, the driver needs to
>> divide the system clock to output the BCLK and FS. But there are too
>> many combinations between BCLK and FS. The BCLK maybe is 32FS, 64FS,
>> 128FS, etc. The driver needs machine information to do the division.
>> Thus, I think the best way is to make decision by machine driver.
>>
>
> This all sounds totally standard - other drivers manage to provide a
> default easily enough here.  You can determine a default BCLK by looking
> at the number of channels and number of bits per sample to work out how
> many BCLKs are going to be needed to clock that data out.
>

I see. The driver should be able to handle it. I'll make another
patch to support the clock divide automatically.



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