* [PATCH 2/6] drm/i915: Align GGTT sizes to a fence tile row
2017-01-09 16:16 [PATCH 1/6] drm/i915: Extract tile_row_size for fencing Chris Wilson
@ 2017-01-09 16:16 ` Chris Wilson
2017-01-09 16:16 ` [PATCH 3/6] drm/i915: Replace WARNs in fence register writes with extensive asserts Chris Wilson
` (5 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Chris Wilson @ 2017-01-09 16:16 UTC (permalink / raw)
To: intel-gfx
Ensure the view occupies the full tile row so that reads/writes into the
VMA do not escape (via fenced detiling) into neighbouring objects - we
will pad the object with scratch pages to satisfy the fence. This
applies the lazy-tiling we employed on gen2/3 to gen4+.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 5 +++--
drivers/gpu/drm/i915/i915_gem.c | 27 +++++++++++++++++++--------
drivers/gpu/drm/i915/i915_gem_tiling.c | 18 +++++++++---------
drivers/gpu/drm/i915/i915_vma.c | 10 ++++++++--
4 files changed, 39 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 52d01be956cc..8185229f370f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3361,9 +3361,10 @@ int i915_gem_open(struct drm_device *dev, struct drm_file *file);
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u64 size,
- int tiling_mode);
+ int tiling_mode, unsigned int stride);
u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
- int tiling_mode, bool fenced);
+ int tiling_mode, unsigned int stride,
+ bool fenced);
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
enum i915_cache_level cache_level);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index df4acbefc4a1..d6fee91a5fa9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2021,21 +2021,29 @@ void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv)
* @dev_priv: i915 device
* @size: object size
* @tiling_mode: tiling mode
+ * @stride: tiling stride
*
* Return the required global GTT size for an object, taking into account
* potential fence register mapping.
*/
u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv,
- u64 size, int tiling_mode)
+ u64 size, int tiling_mode, unsigned int stride)
{
u64 ggtt_size;
- GEM_BUG_ON(size == 0);
+ GEM_BUG_ON(!size);
- if (INTEL_GEN(dev_priv) >= 4 ||
- tiling_mode == I915_TILING_NONE)
+ if (tiling_mode == I915_TILING_NONE)
return size;
+ GEM_BUG_ON(!stride);
+
+ if (INTEL_GEN(dev_priv) >= 4) {
+ stride *= i915_gem_tile_height(tiling_mode);
+ GEM_BUG_ON(stride & 4095);
+ return roundup(size, stride);
+ }
+
/* Previous chips need a power-of-two fence region when tiling */
if (IS_GEN3(dev_priv))
ggtt_size = 1024*1024;
@@ -2053,15 +2061,17 @@ u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv,
* @dev_priv: i915 device
* @size: object size
* @tiling_mode: tiling mode
+ * @stride: tiling stride
* @fenced: is fenced alignment required or not
*
* Return the required global GTT alignment for an object, taking into account
* potential fence register mapping.
*/
u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
- int tiling_mode, bool fenced)
+ int tiling_mode, unsigned int stride,
+ bool fenced)
{
- GEM_BUG_ON(size == 0);
+ GEM_BUG_ON(!size);
/*
* Minimum alignment is 4k (GTT page size), but might be greater
@@ -2076,7 +2086,7 @@ u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
* Previous chips need to be aligned to the size of the smallest
* fence register that can contain the object.
*/
- return i915_gem_get_ggtt_size(dev_priv, size, tiling_mode);
+ return i915_gem_get_ggtt_size(dev_priv, size, tiling_mode, stride);
}
static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
@@ -3687,7 +3697,8 @@ i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
u32 fence_size;
fence_size = i915_gem_get_ggtt_size(dev_priv, vma->size,
- i915_gem_object_get_tiling(obj));
+ i915_gem_object_get_tiling(obj),
+ i915_gem_object_get_stride(obj));
/* If the required space is larger than the available
* aperture, we will not able to find a slot for the
* object and unbinding the object now will be in
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 62ad375de6ca..51b8d71876b7 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -117,7 +117,8 @@ i915_tiling_ok(struct drm_i915_private *dev_priv,
return true;
}
-static bool i915_vma_fence_prepare(struct i915_vma *vma, int tiling_mode)
+static bool i915_vma_fence_prepare(struct i915_vma *vma,
+ int tiling_mode, unsigned int stride)
{
struct drm_i915_private *dev_priv = vma->vm->i915;
u32 size;
@@ -133,7 +134,7 @@ static bool i915_vma_fence_prepare(struct i915_vma *vma, int tiling_mode)
return false;
}
- size = i915_gem_get_ggtt_size(dev_priv, vma->size, tiling_mode);
+ size = i915_gem_get_ggtt_size(dev_priv, vma->size, tiling_mode, stride);
if (vma->node.size < size)
return false;
@@ -145,20 +146,17 @@ static bool i915_vma_fence_prepare(struct i915_vma *vma, int tiling_mode)
/* Make the current GTT allocation valid for the change in tiling. */
static int
-i915_gem_object_fence_prepare(struct drm_i915_gem_object *obj, int tiling_mode)
+i915_gem_object_fence_prepare(struct drm_i915_gem_object *obj,
+ int tiling_mode, unsigned int stride)
{
- struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
struct i915_vma *vma;
int ret;
if (tiling_mode == I915_TILING_NONE)
return 0;
- if (INTEL_GEN(dev_priv) >= 4)
- return 0;
-
list_for_each_entry(vma, &obj->vma_list, obj_link) {
- if (i915_vma_fence_prepare(vma, tiling_mode))
+ if (i915_vma_fence_prepare(vma, tiling_mode, stride))
continue;
ret = i915_vma_unbind(vma);
@@ -255,7 +253,9 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
* whilst executing a fenced command for an untiled object.
*/
- err = i915_gem_object_fence_prepare(obj, args->tiling_mode);
+ err = i915_gem_object_fence_prepare(obj,
+ args->tiling_mode,
+ args->stride);
if (!err) {
struct i915_vma *vma;
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 58f2483362ad..734f77b7697f 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -284,11 +284,14 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
fence_size = i915_gem_get_ggtt_size(dev_priv,
vma->size,
- i915_gem_object_get_tiling(obj));
+ i915_gem_object_get_tiling(obj),
+ i915_gem_object_get_stride(obj));
fence_alignment = i915_gem_get_ggtt_alignment(dev_priv,
vma->size,
i915_gem_object_get_tiling(obj),
+ i915_gem_object_get_stride(obj),
true);
+ GEM_BUG_ON(!is_power_of_2(fence_alignment));
fenceable = (vma->node.size == fence_size &&
(vma->node.start & (fence_alignment - 1)) == 0);
@@ -370,12 +373,15 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
size = max(size, vma->size);
if (flags & PIN_MAPPABLE)
size = i915_gem_get_ggtt_size(dev_priv, size,
- i915_gem_object_get_tiling(obj));
+ i915_gem_object_get_tiling(obj),
+ i915_gem_object_get_stride(obj));
alignment = max(max(alignment, vma->display_alignment),
i915_gem_get_ggtt_alignment(dev_priv, size,
i915_gem_object_get_tiling(obj),
+ i915_gem_object_get_stride(obj),
flags & PIN_MAPPABLE));
+ GEM_BUG_ON(!is_power_of_2(alignment));
start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
--
2.11.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/6] drm/i915: Replace WARNs in fence register writes with extensive asserts
2017-01-09 16:16 [PATCH 1/6] drm/i915: Extract tile_row_size for fencing Chris Wilson
2017-01-09 16:16 ` [PATCH 2/6] drm/i915: Align GGTT sizes to a fence tile row Chris Wilson
@ 2017-01-09 16:16 ` Chris Wilson
2017-01-09 16:16 ` [PATCH 4/6] drm/i915: Store required fence size/alignment for GGTT vma Chris Wilson
` (4 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Chris Wilson @ 2017-01-09 16:16 UTC (permalink / raw)
To: intel-gfx
All of these conditions are prechecked by i915_tiling_ok() before we
allow setting the tiling/stride on the object and so we should never
fail asserting those conditions before writing the register.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 50 ++++++++++++++-----------------
1 file changed, 22 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index 399ae7f73184..26f242359fbd 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -81,8 +81,13 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *fence,
u32 row_size = i915_gem_object_get_tile_row_size(vma->obj);
u32 size = rounddown((u32)vma->node.size, row_size);
- val = ((vma->node.start + size - 4096) & 0xfffff000) << 32;
- val |= vma->node.start & 0xfffff000;
+ GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma));
+ GEM_BUG_ON(vma->node.start & 4095);
+ GEM_BUG_ON(vma->node.size & 4095);
+ GEM_BUG_ON(stride & 127);
+
+ val = (vma->node.start + size - 4096) << 32;
+ val |= vma->node.start;
val |= (u64)((stride / 128) - 1) << fence_pitch_shift;
if (i915_gem_object_get_tiling(vma->obj) == I915_TILING_Y)
val |= BIT(I965_FENCE_TILING_Y_SHIFT);
@@ -120,31 +125,24 @@ static void i915_write_fence_reg(struct drm_i915_fence_reg *fence,
unsigned int tiling = i915_gem_object_get_tiling(vma->obj);
bool is_y_tiled = tiling == I915_TILING_Y;
unsigned int stride = i915_gem_object_get_stride(vma->obj);
- int pitch_val;
- int tile_width;
- WARN((vma->node.start & ~I915_FENCE_START_MASK) ||
- !is_power_of_2(vma->node.size) ||
- (vma->node.start & (vma->node.size - 1)),
- "object 0x%08llx [fenceable? %d] not 1M or pot-size (0x%08llx) aligned\n",
- vma->node.start,
- i915_vma_is_map_and_fenceable(vma),
- vma->node.size);
+ GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma));
+ GEM_BUG_ON(vma->node.start & ~I915_FENCE_START_MASK);
+ GEM_BUG_ON(!is_power_of_2(vma->node.size));
+ GEM_BUG_ON(vma->node.start & (vma->node.size - 1));
if (is_y_tiled && HAS_128_BYTE_Y_TILING(fence->i915))
- tile_width = 128;
+ stride /= 128;
else
- tile_width = 512;
-
- /* Note: pitch better be a power of two tile widths */
- pitch_val = stride / tile_width;
- pitch_val = ffs(pitch_val) - 1;
+ stride /= 512;
+ GEM_BUG_ON(!is_power_of_2(stride));
val = vma->node.start;
if (is_y_tiled)
val |= BIT(I830_FENCE_TILING_Y_SHIFT);
val |= I915_FENCE_SIZE_BITS(vma->node.size);
- val |= pitch_val << I830_FENCE_PITCH_SHIFT;
+ val |= ilog2(stride) << I830_FENCE_PITCH_SHIFT;
+
val |= I830_FENCE_REG_VALID;
}
@@ -167,22 +165,18 @@ static void i830_write_fence_reg(struct drm_i915_fence_reg *fence,
unsigned int tiling = i915_gem_object_get_tiling(vma->obj);
bool is_y_tiled = tiling == I915_TILING_Y;
unsigned int stride = i915_gem_object_get_stride(vma->obj);
- u32 pitch_val;
-
- WARN((vma->node.start & ~I830_FENCE_START_MASK) ||
- !is_power_of_2(vma->node.size) ||
- (vma->node.start & (vma->node.size - 1)),
- "object 0x%08llx not 512K or pot-size 0x%08llx aligned\n",
- vma->node.start, vma->node.size);
- pitch_val = stride / 128;
- pitch_val = ffs(pitch_val) - 1;
+ GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma));
+ GEM_BUG_ON(vma->node.start & ~I830_FENCE_START_MASK);
+ GEM_BUG_ON(!is_power_of_2(vma->node.size));
+ GEM_BUG_ON(!is_power_of_2(stride / 128));
+ GEM_BUG_ON(vma->node.start & (vma->node.size - 1));
val = vma->node.start;
if (is_y_tiled)
val |= BIT(I830_FENCE_TILING_Y_SHIFT);
val |= I830_FENCE_SIZE_BITS(vma->node.size);
- val |= pitch_val << I830_FENCE_PITCH_SHIFT;
+ val |= ilog2(stride / 128) << I830_FENCE_PITCH_SHIFT;
val |= I830_FENCE_REG_VALID;
}
--
2.11.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 4/6] drm/i915: Store required fence size/alignment for GGTT vma
2017-01-09 16:16 [PATCH 1/6] drm/i915: Extract tile_row_size for fencing Chris Wilson
2017-01-09 16:16 ` [PATCH 2/6] drm/i915: Align GGTT sizes to a fence tile row Chris Wilson
2017-01-09 16:16 ` [PATCH 3/6] drm/i915: Replace WARNs in fence register writes with extensive asserts Chris Wilson
@ 2017-01-09 16:16 ` Chris Wilson
2017-01-09 16:16 ` [PATCH 5/6] drm/i915: Remove the rounding down of the gen4+ fence region Chris Wilson
` (3 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Chris Wilson @ 2017-01-09 16:16 UTC (permalink / raw)
To: intel-gfx
The fence size/alignment is a combination of the vma size plus object
tiling parameters. Those parameters are rarely changed, making the fence
size/alignemnt roughly constant for the lifetime of the VMA. We can
simplify subsequent calculations by precalculating the size/alignment
required for GGTT vma taking fencing into account (with an update if we
do change the tiling or stride).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 7 ++--
drivers/gpu/drm/i915/i915_gem.c | 27 +++++---------
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 20 +++++-----
drivers/gpu/drm/i915/i915_gem_tiling.c | 36 ++++++++++--------
drivers/gpu/drm/i915/i915_vma.c | 61 +++++++++++++++----------------
drivers/gpu/drm/i915/i915_vma.h | 3 ++
6 files changed, 73 insertions(+), 81 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8185229f370f..5ee76628be98 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3360,11 +3360,10 @@ int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
int i915_gem_open(struct drm_device *dev, struct drm_file *file);
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
-u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u64 size,
+u32 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u32 size,
int tiling_mode, unsigned int stride);
-u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
- int tiling_mode, unsigned int stride,
- bool fenced);
+u32 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u32 size,
+ int tiling_mode, unsigned int stride);
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
enum i915_cache_level cache_level);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d6fee91a5fa9..056a5f165e39 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2026,10 +2026,10 @@ void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv)
* Return the required global GTT size for an object, taking into account
* potential fence register mapping.
*/
-u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv,
- u64 size, int tiling_mode, unsigned int stride)
+u32 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv,
+ u32 size, int tiling_mode, unsigned int stride)
{
- u64 ggtt_size;
+ u32 ggtt_size;
GEM_BUG_ON(!size);
@@ -2062,14 +2062,12 @@ u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv,
* @size: object size
* @tiling_mode: tiling mode
* @stride: tiling stride
- * @fenced: is fenced alignment required or not
*
* Return the required global GTT alignment for an object, taking into account
* potential fence register mapping.
*/
-u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
- int tiling_mode, unsigned int stride,
- bool fenced)
+u32 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u32 size,
+ int tiling_mode, unsigned int stride)
{
GEM_BUG_ON(!size);
@@ -2077,9 +2075,7 @@ u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
* Minimum alignment is 4k (GTT page size), but might be greater
* if a fence register is needed for the object.
*/
- if (INTEL_GEN(dev_priv) >= 4 ||
- (!fenced && (IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))) ||
- tiling_mode == I915_TILING_NONE)
+ if (INTEL_GEN(dev_priv) >= 4 || tiling_mode == I915_TILING_NONE)
return 4096;
/*
@@ -3549,7 +3545,7 @@ i915_gem_object_unpin_from_display_plane(struct i915_vma *vma)
return;
if (--vma->obj->pin_display == 0)
- vma->display_alignment = 0;
+ vma->display_alignment = 4096;
/* Bump the LRU to try and avoid premature eviction whilst flipping */
if (!i915_vma_is_active(vma))
@@ -3694,11 +3690,6 @@ i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
return ERR_PTR(-ENOSPC);
if (flags & PIN_MAPPABLE) {
- u32 fence_size;
-
- fence_size = i915_gem_get_ggtt_size(dev_priv, vma->size,
- i915_gem_object_get_tiling(obj),
- i915_gem_object_get_stride(obj));
/* If the required space is larger than the available
* aperture, we will not able to find a slot for the
* object and unbinding the object now will be in
@@ -3706,7 +3697,7 @@ i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
* the object in and out of the Global GTT and
* waste a lot of cycles under the mutex.
*/
- if (fence_size > dev_priv->ggtt.mappable_end)
+ if (vma->fence_size > dev_priv->ggtt.mappable_end)
return ERR_PTR(-E2BIG);
/* If NONBLOCK is set the caller is optimistically
@@ -3725,7 +3716,7 @@ i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
* we could try to minimise harm to others.
*/
if (flags & PIN_NONBLOCK &&
- fence_size > dev_priv->ggtt.mappable_end / 2)
+ vma->fence_size > dev_priv->ggtt.mappable_end / 2)
return ERR_PTR(-ENOSPC);
}
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index 26f242359fbd..8b37c4cb311a 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -79,11 +79,11 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *fence,
if (vma) {
unsigned int stride = i915_gem_object_get_stride(vma->obj);
u32 row_size = i915_gem_object_get_tile_row_size(vma->obj);
- u32 size = rounddown((u32)vma->node.size, row_size);
+ u32 size = rounddown((u32)vma->fence_size, row_size);
GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma));
GEM_BUG_ON(vma->node.start & 4095);
- GEM_BUG_ON(vma->node.size & 4095);
+ GEM_BUG_ON(vma->fence_size & 4095);
GEM_BUG_ON(stride & 127);
val = (vma->node.start + size - 4096) << 32;
@@ -128,8 +128,8 @@ static void i915_write_fence_reg(struct drm_i915_fence_reg *fence,
GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma));
GEM_BUG_ON(vma->node.start & ~I915_FENCE_START_MASK);
- GEM_BUG_ON(!is_power_of_2(vma->node.size));
- GEM_BUG_ON(vma->node.start & (vma->node.size - 1));
+ GEM_BUG_ON(!is_power_of_2(vma->fence_size));
+ GEM_BUG_ON(vma->node.start & (vma->fence_size - 1));
if (is_y_tiled && HAS_128_BYTE_Y_TILING(fence->i915))
stride /= 128;
@@ -140,7 +140,7 @@ static void i915_write_fence_reg(struct drm_i915_fence_reg *fence,
val = vma->node.start;
if (is_y_tiled)
val |= BIT(I830_FENCE_TILING_Y_SHIFT);
- val |= I915_FENCE_SIZE_BITS(vma->node.size);
+ val |= I915_FENCE_SIZE_BITS(vma->fence_size);
val |= ilog2(stride) << I830_FENCE_PITCH_SHIFT;
val |= I830_FENCE_REG_VALID;
@@ -162,20 +162,18 @@ static void i830_write_fence_reg(struct drm_i915_fence_reg *fence,
val = 0;
if (vma) {
- unsigned int tiling = i915_gem_object_get_tiling(vma->obj);
- bool is_y_tiled = tiling == I915_TILING_Y;
unsigned int stride = i915_gem_object_get_stride(vma->obj);
GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma));
GEM_BUG_ON(vma->node.start & ~I830_FENCE_START_MASK);
- GEM_BUG_ON(!is_power_of_2(vma->node.size));
+ GEM_BUG_ON(!is_power_of_2(vma->fence_size));
GEM_BUG_ON(!is_power_of_2(stride / 128));
- GEM_BUG_ON(vma->node.start & (vma->node.size - 1));
+ GEM_BUG_ON(vma->node.start & (vma->fence_size - 1));
val = vma->node.start;
- if (is_y_tiled)
+ if (i915_gem_object_get_tiling(vma->obj) == I915_TILING_Y)
val |= BIT(I830_FENCE_TILING_Y_SHIFT);
- val |= I830_FENCE_SIZE_BITS(vma->node.size);
+ val |= I830_FENCE_SIZE_BITS(vma->fence_size);
val |= ilog2(stride / 128) << I830_FENCE_PITCH_SHIFT;
val |= I830_FENCE_REG_VALID;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 51b8d71876b7..23a896cd934f 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -120,25 +120,18 @@ i915_tiling_ok(struct drm_i915_private *dev_priv,
static bool i915_vma_fence_prepare(struct i915_vma *vma,
int tiling_mode, unsigned int stride)
{
- struct drm_i915_private *dev_priv = vma->vm->i915;
- u32 size;
+ struct drm_i915_private *i915 = vma->vm->i915;
+ u32 size, alignment;
if (!i915_vma_is_map_and_fenceable(vma))
return true;
- if (INTEL_GEN(dev_priv) == 3) {
- if (vma->node.start & ~I915_FENCE_START_MASK)
- return false;
- } else {
- if (vma->node.start & ~I830_FENCE_START_MASK)
- return false;
- }
-
- size = i915_gem_get_ggtt_size(dev_priv, vma->size, tiling_mode, stride);
+ size = i915_gem_get_ggtt_size(i915, vma->size, tiling_mode, stride);
if (vma->node.size < size)
return false;
- if (vma->node.start & (size - 1))
+ alignment = i915_gem_get_ggtt_alignment(i915, vma->size, tiling_mode, stride);
+ if (vma->node.start & (alignment - 1))
return false;
return true;
@@ -156,6 +149,9 @@ i915_gem_object_fence_prepare(struct drm_i915_gem_object *obj,
return 0;
list_for_each_entry(vma, &obj->vma_list, obj_link) {
+ if (!i915_vma_is_ggtt(vma))
+ break;
+
if (i915_vma_fence_prepare(vma, tiling_mode, stride))
continue;
@@ -277,10 +273,18 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
mutex_unlock(&obj->mm.lock);
list_for_each_entry(vma, &obj->vma_list, obj_link) {
- if (!vma->fence)
- continue;
-
- vma->fence->dirty = true;
+ if (!i915_vma_is_ggtt(vma))
+ break;
+
+ vma->fence_size = i915_gem_get_ggtt_size(dev_priv, vma->size,
+ args->tiling_mode,
+ args->stride);
+ vma->fence_alignment = i915_gem_get_ggtt_alignment(dev_priv, vma->size,
+ args->tiling_mode,
+ args->stride);
+
+ if (vma->fence)
+ vma->fence->dirty = true;
}
obj->tiling_and_stride =
args->stride | args->tiling_mode;
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 734f77b7697f..a605d735662c 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -91,6 +91,7 @@ __i915_vma_create(struct drm_i915_gem_object *obj,
vma->vm = vm;
vma->obj = obj;
vma->size = obj->base.size;
+ vma->display_alignment = 4096;
if (view) {
vma->ggtt_view = *view;
@@ -110,6 +111,17 @@ __i915_vma_create(struct drm_i915_gem_object *obj,
}
if (i915_is_ggtt(vm)) {
+ GEM_BUG_ON(overflows_type(vma->size, u32));
+ vma->fence_size = i915_gem_get_ggtt_size(vm->i915, vma->size,
+ i915_gem_object_get_tiling(obj),
+ i915_gem_object_get_stride(obj));
+ GEM_BUG_ON(vma->fence_size & 4095);
+
+ vma->fence_alignment = i915_gem_get_ggtt_alignment(vm->i915, vma->size,
+ i915_gem_object_get_tiling(obj),
+ i915_gem_object_get_stride(obj));
+ GEM_BUG_ON(!is_power_of_2(vma->fence_alignment));
+
vma->flags |= I915_VMA_GGTT;
list_add(&vma->obj_link, &obj->vma_list);
} else {
@@ -277,34 +289,24 @@ i915_vma_misplaced(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
{
- struct drm_i915_gem_object *obj = vma->obj;
- struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
bool mappable, fenceable;
- u32 fence_size, fence_alignment;
- fence_size = i915_gem_get_ggtt_size(dev_priv,
- vma->size,
- i915_gem_object_get_tiling(obj),
- i915_gem_object_get_stride(obj));
- fence_alignment = i915_gem_get_ggtt_alignment(dev_priv,
- vma->size,
- i915_gem_object_get_tiling(obj),
- i915_gem_object_get_stride(obj),
- true);
- GEM_BUG_ON(!is_power_of_2(fence_alignment));
-
- fenceable = (vma->node.size == fence_size &&
- (vma->node.start & (fence_alignment - 1)) == 0);
-
- mappable = (vma->node.start + fence_size <=
- dev_priv->ggtt.mappable_end);
+ GEM_BUG_ON(!i915_vma_is_ggtt(vma));
+ GEM_BUG_ON(!vma->fence_size);
/*
* Explicitly disable for rotated VMA since the display does not
* need the fence and the VMA is not accessible to other users.
*/
- if (mappable && fenceable &&
- vma->ggtt_view.type != I915_GGTT_VIEW_ROTATED)
+ if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
+ return;
+
+ fenceable = (vma->node.size >= vma->fence_size &&
+ (vma->node.start & (vma->fence_alignment - 1)) == 0);
+
+ mappable = vma->node.start + vma->fence_size <= i915_vm_to_ggtt(vma->vm)->mappable_end;
+
+ if (mappable && fenceable)
vma->flags |= I915_VMA_CAN_FENCE;
else
vma->flags &= ~I915_VMA_CAN_FENCE;
@@ -371,17 +373,12 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
GEM_BUG_ON(drm_mm_node_allocated(&vma->node));
size = max(size, vma->size);
- if (flags & PIN_MAPPABLE)
- size = i915_gem_get_ggtt_size(dev_priv, size,
- i915_gem_object_get_tiling(obj),
- i915_gem_object_get_stride(obj));
-
- alignment = max(max(alignment, vma->display_alignment),
- i915_gem_get_ggtt_alignment(dev_priv, size,
- i915_gem_object_get_tiling(obj),
- i915_gem_object_get_stride(obj),
- flags & PIN_MAPPABLE));
- GEM_BUG_ON(!is_power_of_2(alignment));
+ alignment = max(alignment, vma->display_alignment);
+ if (flags & PIN_MAPPABLE) {
+ size = max_t(typeof(size), size, vma->fence_size);
+ alignment = max_t(typeof(alignment),
+ alignment, vma->fence_alignment);
+ }
start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index e3b2b3b1e056..a969bbb65871 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -55,6 +55,9 @@ struct i915_vma {
u64 size;
u64 display_alignment;
+ u32 fence_size;
+ u32 fence_alignment;
+
unsigned int flags;
/**
* How many users have pinned this object in GTT space. The following
--
2.11.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 5/6] drm/i915: Remove the rounding down of the gen4+ fence region
2017-01-09 16:16 [PATCH 1/6] drm/i915: Extract tile_row_size for fencing Chris Wilson
` (2 preceding siblings ...)
2017-01-09 16:16 ` [PATCH 4/6] drm/i915: Store required fence size/alignment for GGTT vma Chris Wilson
@ 2017-01-09 16:16 ` Chris Wilson
2017-01-09 16:16 ` [PATCH 6/6] drm/i915: Move ggtt fence/alignment to i915_gem_tiling.c Chris Wilson
` (2 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Chris Wilson @ 2017-01-09 16:16 UTC (permalink / raw)
To: intel-gfx
Restricting the fence to the end of the previous tile-row breaks access
to the final portion of the object. On gen2/3 we employed lazy fencing
to pad out the fence with scratch page to provide access to the tail,
and now we also pad out the object on gen4+ we can apply the same fix.
Fixes: af1a7301c7cf ("drm/i915: Only fence tiled region of object.")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index 8b37c4cb311a..9e65696a960c 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -78,15 +78,13 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *fence,
val = 0;
if (vma) {
unsigned int stride = i915_gem_object_get_stride(vma->obj);
- u32 row_size = i915_gem_object_get_tile_row_size(vma->obj);
- u32 size = rounddown((u32)vma->fence_size, row_size);
GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma));
GEM_BUG_ON(vma->node.start & 4095);
GEM_BUG_ON(vma->fence_size & 4095);
GEM_BUG_ON(stride & 127);
- val = (vma->node.start + size - 4096) << 32;
+ val = (vma->node.start + vma->fence_size - 4096) << 32;
val |= vma->node.start;
val |= (u64)((stride / 128) - 1) << fence_pitch_shift;
if (i915_gem_object_get_tiling(vma->obj) == I915_TILING_Y)
--
2.11.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 6/6] drm/i915: Move ggtt fence/alignment to i915_gem_tiling.c
2017-01-09 16:16 [PATCH 1/6] drm/i915: Extract tile_row_size for fencing Chris Wilson
` (3 preceding siblings ...)
2017-01-09 16:16 ` [PATCH 5/6] drm/i915: Remove the rounding down of the gen4+ fence region Chris Wilson
@ 2017-01-09 16:16 ` Chris Wilson
2017-01-10 7:17 ` Joonas Lahtinen
2017-01-09 17:23 ` ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Extract tile_row_size for fencing Patchwork
2017-01-10 7:12 ` [PATCH 1/6] " Joonas Lahtinen
6 siblings, 1 reply; 13+ messages in thread
From: Chris Wilson @ 2017-01-09 16:16 UTC (permalink / raw)
To: intel-gfx
Rename i915_gem_get_ggtt_size() and i915_gem_get_ggtt_alignment() to
i915_gem_fence_size() and i915_gem_fence_alignment() respectively to
better match usage. Similarly move the pair of functions into
i915_gem_tiling.c next to the fence restrictions.
Suggested-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 10 ++--
drivers/gpu/drm/i915/i915_gem.c | 69 ---------------------------
drivers/gpu/drm/i915/i915_gem_tiling.c | 85 ++++++++++++++++++++++++++++++----
drivers/gpu/drm/i915/i915_vma.c | 12 ++---
4 files changed, 88 insertions(+), 88 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5ee76628be98..2b325032fedc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3360,11 +3360,6 @@ int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
int i915_gem_open(struct drm_device *dev, struct drm_file *file);
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
-u32 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u32 size,
- int tiling_mode, unsigned int stride);
-u32 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u32 size,
- int tiling_mode, unsigned int stride);
-
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
enum i915_cache_level cache_level);
@@ -3531,6 +3526,11 @@ static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_objec
i915_gem_object_is_tiled(obj);
}
+u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
+ unsigned int tiling, unsigned int stride);
+u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
+ unsigned int tiling, unsigned int stride);
+
/* i915_debugfs.c */
#ifdef CONFIG_DEBUG_FS
int i915_debugfs_register(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 056a5f165e39..13c02015709c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2016,75 +2016,6 @@ void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv)
}
}
-/**
- * i915_gem_get_ggtt_size - return required global GTT size for an object
- * @dev_priv: i915 device
- * @size: object size
- * @tiling_mode: tiling mode
- * @stride: tiling stride
- *
- * Return the required global GTT size for an object, taking into account
- * potential fence register mapping.
- */
-u32 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv,
- u32 size, int tiling_mode, unsigned int stride)
-{
- u32 ggtt_size;
-
- GEM_BUG_ON(!size);
-
- if (tiling_mode == I915_TILING_NONE)
- return size;
-
- GEM_BUG_ON(!stride);
-
- if (INTEL_GEN(dev_priv) >= 4) {
- stride *= i915_gem_tile_height(tiling_mode);
- GEM_BUG_ON(stride & 4095);
- return roundup(size, stride);
- }
-
- /* Previous chips need a power-of-two fence region when tiling */
- if (IS_GEN3(dev_priv))
- ggtt_size = 1024*1024;
- else
- ggtt_size = 512*1024;
-
- while (ggtt_size < size)
- ggtt_size <<= 1;
-
- return ggtt_size;
-}
-
-/**
- * i915_gem_get_ggtt_alignment - return required global GTT alignment
- * @dev_priv: i915 device
- * @size: object size
- * @tiling_mode: tiling mode
- * @stride: tiling stride
- *
- * Return the required global GTT alignment for an object, taking into account
- * potential fence register mapping.
- */
-u32 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u32 size,
- int tiling_mode, unsigned int stride)
-{
- GEM_BUG_ON(!size);
-
- /*
- * Minimum alignment is 4k (GTT page size), but might be greater
- * if a fence register is needed for the object.
- */
- if (INTEL_GEN(dev_priv) >= 4 || tiling_mode == I915_TILING_NONE)
- return 4096;
-
- /*
- * Previous chips need to be aligned to the size of the smallest
- * fence register that can contain the object.
- */
- return i915_gem_get_ggtt_size(dev_priv, size, tiling_mode, stride);
-}
-
static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
{
struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 23a896cd934f..30cb869759fb 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -58,6 +58,75 @@
* invovlement.
*/
+/**
+ * i915_gem_fence_size - required global GTT size for a fence
+ * @i915: i915 device
+ * @size: object size
+ * @tiling: tiling mode
+ * @stride: tiling stride
+ *
+ * Return the required global GTT size for a fence (view of a tiled object),
+ * taking into account potential fence register mapping.
+ */
+u32 i915_gem_fence_size(struct drm_i915_private *i915,
+ u32 size, unsigned int tiling, unsigned int stride)
+{
+ u32 ggtt_size;
+
+ GEM_BUG_ON(!size);
+
+ if (tiling == I915_TILING_NONE)
+ return size;
+
+ GEM_BUG_ON(!stride);
+
+ if (INTEL_GEN(i915) >= 4) {
+ stride *= i915_gem_tile_height(tiling);
+ GEM_BUG_ON(stride & 4095);
+ return roundup(size, stride);
+ }
+
+ /* Previous chips need a power-of-two fence region when tiling */
+ if (IS_GEN3(i915))
+ ggtt_size = 1024*1024;
+ else
+ ggtt_size = 512*1024;
+
+ while (ggtt_size < size)
+ ggtt_size <<= 1;
+
+ return ggtt_size;
+}
+
+/**
+ * i915_gem_fence_alignment - required global GTT alignment for a fence
+ * @i915: i915 device
+ * @size: object size
+ * @tiling: tiling mode
+ * @stride: tiling stride
+ *
+ * Return the required global GTT alignment for a fence (a view of a tiled
+ * object), taking into account potential fence register mapping.
+ */
+u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size,
+ unsigned int tiling, unsigned int stride)
+{
+ GEM_BUG_ON(!size);
+
+ /*
+ * Minimum alignment is 4k (GTT page size), but might be greater
+ * if a fence register is needed for the object.
+ */
+ if (INTEL_GEN(i915) >= 4 || tiling == I915_TILING_NONE)
+ return 4096;
+
+ /*
+ * Previous chips need to be aligned to the size of the smallest
+ * fence register that can contain the object.
+ */
+ return i915_gem_fence_size(i915, size, tiling, stride);
+}
+
/* Check pitch constriants for all chips & tiling formats */
static bool
i915_tiling_ok(struct drm_i915_private *dev_priv,
@@ -126,11 +195,11 @@ static bool i915_vma_fence_prepare(struct i915_vma *vma,
if (!i915_vma_is_map_and_fenceable(vma))
return true;
- size = i915_gem_get_ggtt_size(i915, vma->size, tiling_mode, stride);
+ size = i915_gem_fence_size(i915, vma->size, tiling_mode, stride);
if (vma->node.size < size)
return false;
- alignment = i915_gem_get_ggtt_alignment(i915, vma->size, tiling_mode, stride);
+ alignment = i915_gem_fence_alignment(i915, vma->size, tiling_mode, stride);
if (vma->node.start & (alignment - 1))
return false;
@@ -276,12 +345,12 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
if (!i915_vma_is_ggtt(vma))
break;
- vma->fence_size = i915_gem_get_ggtt_size(dev_priv, vma->size,
- args->tiling_mode,
- args->stride);
- vma->fence_alignment = i915_gem_get_ggtt_alignment(dev_priv, vma->size,
- args->tiling_mode,
- args->stride);
+ vma->fence_size = i915_gem_fence_size(dev_priv, vma->size,
+ args->tiling_mode,
+ args->stride);
+ vma->fence_alignment = i915_gem_fence_alignment(dev_priv, vma->size,
+ args->tiling_mode,
+ args->stride);
if (vma->fence)
vma->fence->dirty = true;
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index a605d735662c..f137475fab51 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -112,14 +112,14 @@ __i915_vma_create(struct drm_i915_gem_object *obj,
if (i915_is_ggtt(vm)) {
GEM_BUG_ON(overflows_type(vma->size, u32));
- vma->fence_size = i915_gem_get_ggtt_size(vm->i915, vma->size,
- i915_gem_object_get_tiling(obj),
- i915_gem_object_get_stride(obj));
+ vma->fence_size = i915_gem_fence_size(vm->i915, vma->size,
+ i915_gem_object_get_tiling(obj),
+ i915_gem_object_get_stride(obj));
GEM_BUG_ON(vma->fence_size & 4095);
- vma->fence_alignment = i915_gem_get_ggtt_alignment(vm->i915, vma->size,
- i915_gem_object_get_tiling(obj),
- i915_gem_object_get_stride(obj));
+ vma->fence_alignment = i915_gem_fence_alignment(vm->i915, vma->size,
+ i915_gem_object_get_tiling(obj),
+ i915_gem_object_get_stride(obj));
GEM_BUG_ON(!is_power_of_2(vma->fence_alignment));
vma->flags |= I915_VMA_GGTT;
--
2.11.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 6/6] drm/i915: Move ggtt fence/alignment to i915_gem_tiling.c
2017-01-09 16:16 ` [PATCH 6/6] drm/i915: Move ggtt fence/alignment to i915_gem_tiling.c Chris Wilson
@ 2017-01-10 7:17 ` Joonas Lahtinen
2017-01-10 8:10 ` Chris Wilson
0 siblings, 1 reply; 13+ messages in thread
From: Joonas Lahtinen @ 2017-01-10 7:17 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2017-01-09 at 16:16 +0000, Chris Wilson wrote:
> Rename i915_gem_get_ggtt_size() and i915_gem_get_ggtt_alignment() to
> i915_gem_fence_size() and i915_gem_fence_alignment() respectively to
Extra space here ------^
> better match usage. Similarly move the pair of functions into
> i915_gem_tiling.c next to the fence restrictions.
>
> Suggested-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Usually S-o-b is the last line.
Looking forward to i915_gem_tiling.h in the future, so without the
extra space this is;
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 6/6] drm/i915: Move ggtt fence/alignment to i915_gem_tiling.c
2017-01-10 7:17 ` Joonas Lahtinen
@ 2017-01-10 8:10 ` Chris Wilson
0 siblings, 0 replies; 13+ messages in thread
From: Chris Wilson @ 2017-01-10 8:10 UTC (permalink / raw)
To: Joonas Lahtinen; +Cc: intel-gfx
On Tue, Jan 10, 2017 at 09:17:00AM +0200, Joonas Lahtinen wrote:
> On ma, 2017-01-09 at 16:16 +0000, Chris Wilson wrote:
> > Rename i915_gem_get_ggtt_size() and i915_gem_get_ggtt_alignment() to
> > i915_gem_fence_size() and i915_gem_fence_alignment() respectively to
>
> Extra space here ------^
>
> > better match usage. Similarly move the pair of functions into
> > i915_gem_tiling.c next to the fence restrictions.
> >
> > Suggested-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>
> Usually S-o-b is the last line.
No, typically cc come after. It's the s-o-b by maintainers that come after
since the list is in rough chronological order (though I like to keep
fixes/reported/tested first as high importance).
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Extract tile_row_size for fencing
2017-01-09 16:16 [PATCH 1/6] drm/i915: Extract tile_row_size for fencing Chris Wilson
` (4 preceding siblings ...)
2017-01-09 16:16 ` [PATCH 6/6] drm/i915: Move ggtt fence/alignment to i915_gem_tiling.c Chris Wilson
@ 2017-01-09 17:23 ` Patchwork
2017-01-10 9:35 ` Chris Wilson
2017-01-10 7:12 ` [PATCH 1/6] " Joonas Lahtinen
6 siblings, 1 reply; 13+ messages in thread
From: Patchwork @ 2017-01-09 17:23 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/6] drm/i915: Extract tile_row_size for fencing
URL : https://patchwork.freedesktop.org/series/17709/
State : success
== Summary ==
Series 17709v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/17709/revisions/1/mbox/
Test kms_force_connector_basic:
Subgroup force-connector-state:
dmesg-warn -> PASS (fi-snb-2520m)
Subgroup prune-stale-modes:
skip -> PASS (fi-ivb-3520m)
fi-bdw-5557u total:246 pass:232 dwarn:0 dfail:0 fail:0 skip:14
fi-bsw-n3050 total:246 pass:207 dwarn:0 dfail:0 fail:0 skip:39
fi-bxt-j4205 total:246 pass:224 dwarn:0 dfail:0 fail:0 skip:22
fi-bxt-t5700 total:82 pass:69 dwarn:0 dfail:0 fail:0 skip:12
fi-byt-j1900 total:246 pass:219 dwarn:0 dfail:0 fail:0 skip:27
fi-byt-n2820 total:246 pass:215 dwarn:0 dfail:0 fail:0 skip:31
fi-hsw-4770 total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19
fi-hsw-4770r total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19
fi-ivb-3520m total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21
fi-ivb-3770 total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21
fi-kbl-7500u total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21
fi-skl-6260u total:246 pass:233 dwarn:0 dfail:0 fail:0 skip:13
fi-skl-6700hq total:246 pass:226 dwarn:0 dfail:0 fail:0 skip:20
fi-skl-6700k total:246 pass:222 dwarn:3 dfail:0 fail:0 skip:21
fi-skl-6770hq total:246 pass:233 dwarn:0 dfail:0 fail:0 skip:13
fi-snb-2520m total:246 pass:215 dwarn:0 dfail:0 fail:0 skip:31
fi-snb-2600 total:246 pass:214 dwarn:0 dfail:0 fail:0 skip:32
9ea6a075c23ea914695d57944c0e74cff0c6bff4 drm-tip: 2017y-01m-09d-16h-11m-21s UTC integration manifest
b533a17 drm/i915: Move ggtt fence/alignment to i915_gem_tiling.c
c63f59d drm/i915: Remove the rounding down of the gen4+ fence region
a7511fe drm/i915: Store required fence size/alignment for GGTT vma
9e8a955 drm/i915: Replace WARNs in fence register writes with extensive asserts
624b8da drm/i915: Align GGTT sizes to a fence tile row
3ecfb17 drm/i915: Extract tile_row_size for fencing
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3455/
_______________________________________________
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Extract tile_row_size for fencing
2017-01-09 17:23 ` ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Extract tile_row_size for fencing Patchwork
@ 2017-01-10 9:35 ` Chris Wilson
2017-01-10 10:12 ` Tvrtko Ursulin
0 siblings, 1 reply; 13+ messages in thread
From: Chris Wilson @ 2017-01-10 9:35 UTC (permalink / raw)
To: intel-gfx
On Mon, Jan 09, 2017 at 05:23:45PM -0000, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/6] drm/i915: Extract tile_row_size for fencing
> URL : https://patchwork.freedesktop.org/series/17709/
> State : success
>
> == Summary ==
>
> Series 17709v1 Series without cover letter
> https://patchwork.freedesktop.org/api/1.0/series/17709/revisions/1/mbox/
>
> Test kms_force_connector_basic:
> Subgroup force-connector-state:
> dmesg-warn -> PASS (fi-snb-2520m)
> Subgroup prune-stale-modes:
> skip -> PASS (fi-ivb-3520m)
>
> fi-bdw-5557u total:246 pass:232 dwarn:0 dfail:0 fail:0 skip:14
> fi-bsw-n3050 total:246 pass:207 dwarn:0 dfail:0 fail:0 skip:39
> fi-bxt-j4205 total:246 pass:224 dwarn:0 dfail:0 fail:0 skip:22
> fi-bxt-t5700 total:82 pass:69 dwarn:0 dfail:0 fail:0 skip:12
> fi-byt-j1900 total:246 pass:219 dwarn:0 dfail:0 fail:0 skip:27
> fi-byt-n2820 total:246 pass:215 dwarn:0 dfail:0 fail:0 skip:31
> fi-hsw-4770 total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19
> fi-hsw-4770r total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19
> fi-ivb-3520m total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21
> fi-ivb-3770 total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21
> fi-kbl-7500u total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21
> fi-skl-6260u total:246 pass:233 dwarn:0 dfail:0 fail:0 skip:13
> fi-skl-6700hq total:246 pass:226 dwarn:0 dfail:0 fail:0 skip:20
> fi-skl-6700k total:246 pass:222 dwarn:3 dfail:0 fail:0 skip:21
> fi-skl-6770hq total:246 pass:233 dwarn:0 dfail:0 fail:0 skip:13
> fi-snb-2520m total:246 pass:215 dwarn:0 dfail:0 fail:0 skip:31
> fi-snb-2600 total:246 pass:214 dwarn:0 dfail:0 fail:0 skip:32
One small series done. Now for the more contentious parts from the parent.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Extract tile_row_size for fencing
2017-01-10 9:35 ` Chris Wilson
@ 2017-01-10 10:12 ` Tvrtko Ursulin
2017-01-10 10:22 ` Chris Wilson
0 siblings, 1 reply; 13+ messages in thread
From: Tvrtko Ursulin @ 2017-01-10 10:12 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 10/01/2017 09:35, Chris Wilson wrote:
> On Mon, Jan 09, 2017 at 05:23:45PM -0000, Patchwork wrote:
>> == Series Details ==
>>
>> Series: series starting with [1/6] drm/i915: Extract tile_row_size for fencing
>> URL : https://patchwork.freedesktop.org/series/17709/
>> State : success
>>
>> == Summary ==
>>
>> Series 17709v1 Series without cover letter
>> https://patchwork.freedesktop.org/api/1.0/series/17709/revisions/1/mbox/
>>
>> Test kms_force_connector_basic:
>> Subgroup force-connector-state:
>> dmesg-warn -> PASS (fi-snb-2520m)
>> Subgroup prune-stale-modes:
>> skip -> PASS (fi-ivb-3520m)
>>
>> fi-bdw-5557u total:246 pass:232 dwarn:0 dfail:0 fail:0 skip:14
>> fi-bsw-n3050 total:246 pass:207 dwarn:0 dfail:0 fail:0 skip:39
>> fi-bxt-j4205 total:246 pass:224 dwarn:0 dfail:0 fail:0 skip:22
>> fi-bxt-t5700 total:82 pass:69 dwarn:0 dfail:0 fail:0 skip:12
>> fi-byt-j1900 total:246 pass:219 dwarn:0 dfail:0 fail:0 skip:27
>> fi-byt-n2820 total:246 pass:215 dwarn:0 dfail:0 fail:0 skip:31
>> fi-hsw-4770 total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19
>> fi-hsw-4770r total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19
>> fi-ivb-3520m total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21
>> fi-ivb-3770 total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21
>> fi-kbl-7500u total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21
>> fi-skl-6260u total:246 pass:233 dwarn:0 dfail:0 fail:0 skip:13
>> fi-skl-6700hq total:246 pass:226 dwarn:0 dfail:0 fail:0 skip:20
>> fi-skl-6700k total:246 pass:222 dwarn:3 dfail:0 fail:0 skip:21
>> fi-skl-6770hq total:246 pass:233 dwarn:0 dfail:0 fail:0 skip:13
>> fi-snb-2520m total:246 pass:215 dwarn:0 dfail:0 fail:0 skip:31
>> fi-snb-2600 total:246 pass:214 dwarn:0 dfail:0 fail:0 skip:32
>
> One small series done. Now for the more contentious parts from the parent.
"drm/i915: Consolidate reset_request()" and "drm/i915: Set guilty-flag
on fence after detecting a hang" could also be extracted since I think
I've seen the back merge happened.
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Extract tile_row_size for fencing
2017-01-10 10:12 ` Tvrtko Ursulin
@ 2017-01-10 10:22 ` Chris Wilson
0 siblings, 0 replies; 13+ messages in thread
From: Chris Wilson @ 2017-01-10 10:22 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
On Tue, Jan 10, 2017 at 10:12:35AM +0000, Tvrtko Ursulin wrote:
>
> On 10/01/2017 09:35, Chris Wilson wrote:
> >On Mon, Jan 09, 2017 at 05:23:45PM -0000, Patchwork wrote:
> >>== Series Details ==
> >>
> >>Series: series starting with [1/6] drm/i915: Extract tile_row_size for fencing
> >>URL : https://patchwork.freedesktop.org/series/17709/
> >>State : success
> >>
> >>== Summary ==
> >>
> >>Series 17709v1 Series without cover letter
> >>https://patchwork.freedesktop.org/api/1.0/series/17709/revisions/1/mbox/
> >>
> >>Test kms_force_connector_basic:
> >> Subgroup force-connector-state:
> >> dmesg-warn -> PASS (fi-snb-2520m)
> >> Subgroup prune-stale-modes:
> >> skip -> PASS (fi-ivb-3520m)
> >>
> >>fi-bdw-5557u total:246 pass:232 dwarn:0 dfail:0 fail:0 skip:14
> >>fi-bsw-n3050 total:246 pass:207 dwarn:0 dfail:0 fail:0 skip:39
> >>fi-bxt-j4205 total:246 pass:224 dwarn:0 dfail:0 fail:0 skip:22
> >>fi-bxt-t5700 total:82 pass:69 dwarn:0 dfail:0 fail:0 skip:12
> >>fi-byt-j1900 total:246 pass:219 dwarn:0 dfail:0 fail:0 skip:27
> >>fi-byt-n2820 total:246 pass:215 dwarn:0 dfail:0 fail:0 skip:31
> >>fi-hsw-4770 total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19
> >>fi-hsw-4770r total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19
> >>fi-ivb-3520m total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21
> >>fi-ivb-3770 total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21
> >>fi-kbl-7500u total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21
> >>fi-skl-6260u total:246 pass:233 dwarn:0 dfail:0 fail:0 skip:13
> >>fi-skl-6700hq total:246 pass:226 dwarn:0 dfail:0 fail:0 skip:20
> >>fi-skl-6700k total:246 pass:222 dwarn:3 dfail:0 fail:0 skip:21
> >>fi-skl-6770hq total:246 pass:233 dwarn:0 dfail:0 fail:0 skip:13
> >>fi-snb-2520m total:246 pass:215 dwarn:0 dfail:0 fail:0 skip:31
> >>fi-snb-2600 total:246 pass:214 dwarn:0 dfail:0 fail:0 skip:32
> >
> >One small series done. Now for the more contentious parts from the parent.
>
> "drm/i915: Consolidate reset_request()" and "drm/i915: Set
> guilty-flag on fence after detecting a hang" could also be extracted
> since I think I've seen the back merge happened.
Ok, they were waiting upon a backmerge, but now I have a couple more
patches in that series for feedback...
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/6] drm/i915: Extract tile_row_size for fencing
2017-01-09 16:16 [PATCH 1/6] drm/i915: Extract tile_row_size for fencing Chris Wilson
` (5 preceding siblings ...)
2017-01-09 17:23 ` ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Extract tile_row_size for fencing Patchwork
@ 2017-01-10 7:12 ` Joonas Lahtinen
6 siblings, 0 replies; 13+ messages in thread
From: Joonas Lahtinen @ 2017-01-10 7:12 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On ma, 2017-01-09 at 16:16 +0000, Chris Wilson wrote:
> Computing the tile row size of a tiled object (for use with fence
> registers) is repeated, so extract it to a common helper.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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^ permalink raw reply [flat|nested] 13+ messages in thread