[PATCH 1/6] drm/i915: Remove disable_lite_restore_wa

[PATCH 1/6] drm/i915: Remove disable_lite_restore_wa

[Chris Wilson]

This w/a was only used for preproduction hw, which is no longer in use.
Remove the workaround to simplify the code.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c        | 11 +----------
 drivers/gpu/drm/i915/intel_ringbuffer.h |  1 -
 2 files changed, 1 insertion(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index eceffe25c022..8ffa4961aa40 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -272,10 +272,6 @@ logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
 
-	engine->disable_lite_restore_wa =
-		IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) &&
-		(engine->id == VCS || engine->id == VCS2);
-
 	engine->ctx_desc_template = GEN8_CTX_VALID;
 	if (IS_GEN8(dev_priv))
 		engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;
@@ -284,11 +280,6 @@ logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
 	/* TODO: WaDisableLiteRestore when we start using semaphore
 	 * signalling between Command Streamers */
 	/* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */
-
-	/* WaEnableForceRestoreInCtxtDescForVCS:skl */
-	/* WaEnableForceRestoreInCtxtDescForVCS:bxt */
-	if (engine->disable_lite_restore_wa)
-		engine->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
 }
 
 /**
@@ -558,7 +549,7 @@ static bool execlists_elsp_ready(struct intel_engine_cs *engine)
 	int port;
 
 	port = 1; /* wait for a free slot */
-	if (engine->disable_lite_restore_wa || engine->preempt_wa)
+	if (engine->preempt_wa)
 		port = 0; /* wait for GPU to be idle before continuing */
 
 	return !engine->execlist_port[port].request;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 79c2b8d72322..9183d148b36a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -380,7 +380,6 @@ struct intel_engine_cs {
 	struct rb_root execlist_queue;
 	struct rb_node *execlist_first;
 	unsigned int fw_domains;
-	bool disable_lite_restore_wa;
 	bool preempt_wa;
 	u32 ctx_desc_template;
 
-- 
2.11.0

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[PATCH 2/6] drm/i915: Remove BXT incoherent seqno write workaround

[Chris Wilson]

This w/a was only used for preproduction hw, which is no longer in use.
Remove the workaround to simplify the code.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 17 -----------------
 1 file changed, 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 8ffa4961aa40..202ce1e6e499 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1638,21 +1638,6 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
 	return 0;
 }
 
-static void bxt_a_seqno_barrier(struct intel_engine_cs *engine)
-{
-	/*
-	 * On BXT A steppings there is a HW coherency issue whereby the
-	 * MI_STORE_DATA_IMM storing the completed request's seqno
-	 * occasionally doesn't invalidate the CPU cache. Work around this by
-	 * clflushing the corresponding cacheline whenever the caller wants
-	 * the coherency to be guaranteed. Note that this cacheline is known
-	 * to be clean at this point, since we only write it in
-	 * bxt_a_set_seqno(), where we also do a clflush after the write. So
-	 * this clflush in practice becomes an invalidate operation.
-	 */
-	intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
-}
-
 /*
  * Reserve space for 2 NOOPs at the end of each request to be
  * used as a workaround for not being allowed to do lite
@@ -1800,8 +1785,6 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
 	engine->irq_enable = gen8_logical_ring_enable_irq;
 	engine->irq_disable = gen8_logical_ring_disable_irq;
 	engine->emit_bb_start = gen8_emit_bb_start;
-	if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
-		engine->irq_seqno_barrier = bxt_a_seqno_barrier;
 }
 
 static inline void
-- 
2.11.0

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[PATCH 3/6] drm/i915: Remove BXT restore arbitration around ctx switch

[Chris Wilson]

This w/a (WaDisableCtxRestoreArbitration) was only used for preproduction
hw, which is no longer in use. Remove the workaround to simplify the code.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 202ce1e6e499..b3d1a9520616 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1102,10 +1102,6 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
 	struct drm_i915_private *dev_priv = engine->i915;
 	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
 
-	/* WaDisableCtxRestoreArbitration:bxt */
-	if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
-		wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
-
 	/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
 	ret = gen8_emit_flush_coherentl3_wa(engine, batch, index);
 	if (ret < 0)
@@ -1202,10 +1198,6 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
 		wa_ctx_emit(batch, index, MI_NOOP);
 	}
 
-	/* WaDisableCtxRestoreArbitration:bxt */
-	if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
-		wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
-
 	wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
 
 	return wa_ctx_end(wa_ctx, *offset = index, 1);
-- 
2.11.0

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[PATCH 4/6] drm/i915: Remove BXT disable pixel mask clamping w/a

[Chris Wilson]

This w/a (WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken) was only
used for preproduction hw, which is no longer in use. Remove the
workaround to simplify the code.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index b3d1a9520616..029a60e8683d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1170,15 +1170,6 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
 {
 	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
 
-	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
-	if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
-		wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
-		wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
-		wa_ctx_emit(batch, index,
-			    _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
-		wa_ctx_emit(batch, index, MI_NOOP);
-	}
-
 	/* WaClearTdlStateAckDirtyBits:bxt */
 	if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_B0)) {
 		wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4));
-- 
2.11.0

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[PATCH 5/6] drm/i915: Remove BXT TDL state w/a

[Chris Wilson]

This w/a (WaClearTdlStateAckDirtyBits) was only used for preproduction hw,
which is no longer in use. Remove the workaround to simplify the code.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 19 -------------------
 1 file changed, 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 029a60e8683d..32096d141d57 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1170,25 +1170,6 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
 {
 	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
 
-	/* WaClearTdlStateAckDirtyBits:bxt */
-	if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_B0)) {
-		wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4));
-
-		wa_ctx_emit_reg(batch, index, GEN8_STATE_ACK);
-		wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
-
-		wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE1);
-		wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
-
-		wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE2);
-		wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
-
-		wa_ctx_emit_reg(batch, index, GEN7_ROW_CHICKEN2);
-		/* dummy write to CS, mask bits are 0 to ensure the register is not modified */
-		wa_ctx_emit(batch, index, 0x0);
-		wa_ctx_emit(batch, index, MI_NOOP);
-	}
-
 	wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
 
 	return wa_ctx_end(wa_ctx, *offset = index, 1);
-- 
2.11.0

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[PATCH 6/6] drm/i915: Remove unused per-bb wa_ctx for gen9

[Chris Wilson]

Stop creating and emitting the wa_ctx per-bb as it is no longer used.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/intel_lrc.c | 37 +++++++++++++------------------------
 1 file changed, 13 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 32096d141d57..2a15829027ad 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1163,18 +1163,6 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
 	return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
 }
 
-static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
-			       struct i915_wa_ctx_bb *wa_ctx,
-			       uint32_t *batch,
-			       uint32_t *offset)
-{
-	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
-
-	wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
-
-	return wa_ctx_end(wa_ctx, *offset = index, 1);
-}
-
 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size)
 {
 	struct drm_i915_gem_object *obj;
@@ -1239,7 +1227,9 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
 
 	page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0);
 	batch = kmap_atomic(page);
-	offset = 0;
+
+	/* skip first cacheline to use offset 0 as no wa_ctx */
+	offset = CACHELINE_DWORDS;
 
 	if (IS_GEN8(engine->i915)) {
 		ret = gen8_init_indirectctx_bb(engine,
@@ -1262,13 +1252,6 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
 					       &offset);
 		if (ret)
 			goto out;
-
-		ret = gen9_init_perctx_bb(engine,
-					  &wa_ctx->per_ctx,
-					  batch,
-					  &offset);
-		if (ret)
-			goto out;
 	}
 
 out:
@@ -1993,19 +1976,25 @@ static void execlists_init_reg_state(u32 *reg_state,
 			       RING_INDIRECT_CTX(engine->mmio_base), 0);
 		ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET,
 			       RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0);
-		if (engine->wa_ctx.vma) {
+
+		if (engine->wa_ctx.indirect_ctx.offset) {
 			struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
-			u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
 
 			reg_state[CTX_RCS_INDIRECT_CTX+1] =
-				(ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
+				(i915_ggtt_offset(wa_ctx->vma) +
+				 wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
 				(wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);
+		}
+
+		if (engine->wa_ctx.per_ctx.offset) {
+			struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
 
 			reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
 				intel_lr_indirect_ctx_offset(engine) << 6;
 
 			reg_state[CTX_BB_PER_CTX_PTR+1] =
-				(ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
+				(i915_ggtt_offset(wa_ctx->vma) +
+				 wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
 				0x01;
 		}
 	}
-- 
2.11.0

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Re: [PATCH 1/6] drm/i915: Remove disable_lite_restore_wa

[Joonas Lahtinen]

On ma, 2017-01-23 at 13:05 +0000, Chris Wilson wrote:
> This w/a was only used for preproduction hw, which is no longer in use.
> Remove the workaround to simplify the code.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

This is on par with the current trend.

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Re: [PATCH 3/6] drm/i915: Remove BXT restore arbitration around ctx switch

[Joonas Lahtinen]

On ma, 2017-01-23 at 13:05 +0000, Chris Wilson wrote:
> This w/a (WaDisableCtxRestoreArbitration) was only used for preproduction
> hw, which is no longer in use. Remove the workaround to simplify the code.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Ditto.

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Regards, Joonas
-- 
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Open Source Technology Center
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Re: [PATCH 1/6] drm/i915: Remove disable_lite_restore_wa

[Chris Wilson]

On Mon, Jan 23, 2017 at 01:05:56PM +0000, Chris Wilson wrote:
> This w/a was only used for preproduction hw, which is no longer in use.
> Remove the workaround to simplify the code.

Note to self, remember to include WaEnableForceRestoreInCtxtDescForVCS
-Chris

-- 
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Re: [PATCH 5/6] drm/i915: Remove BXT TDL state w/a

[Joonas Lahtinen]

On ma, 2017-01-23 at 13:06 +0000, Chris Wilson wrote:
> This w/a (WaClearTdlStateAckDirtyBits) was only used for preproduction hw,
> which is no longer in use. Remove the workaround to simplify the code.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Regards, Joonas
-- 
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Open Source Technology Center
Intel Corporation
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Re: [PATCH 2/6] drm/i915: Remove BXT incoherent seqno write workaround

[Joonas Lahtinen]

On ma, 2017-01-23 at 13:05 +0000, Chris Wilson wrote:
> This w/a was only used for preproduction hw, which is no longer in use.
> Remove the workaround to simplify the code.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Regards, Joonas
-- 
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Open Source Technology Center
Intel Corporation
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Re: [PATCH 4/6] drm/i915: Remove BXT disable pixel mask clamping w/a

[Joonas Lahtinen]

On ma, 2017-01-23 at 13:05 +0000, Chris Wilson wrote:
> This w/a (WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken) was only
> used for preproduction hw, which is no longer in use. Remove the
> workaround to simplify the code.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Regards, Joonas
-- 
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Open Source Technology Center
Intel Corporation
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Re: [PATCH 2/6] drm/i915: Remove BXT incoherent seqno write workaround

[Ville Syrjälä]

On Mon, Jan 23, 2017 at 01:05:57PM +0000, Chris Wilson wrote:
> This w/a was only used for preproduction hw, which is no longer in use.
> Remove the workaround to simplify the code.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_lrc.c | 17 -----------------
>  1 file changed, 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 8ffa4961aa40..202ce1e6e499 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1638,21 +1638,6 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
>  	return 0;
>  }
>  
> -static void bxt_a_seqno_barrier(struct intel_engine_cs *engine)
> -{
> -	/*
> -	 * On BXT A steppings there is a HW coherency issue whereby the
> -	 * MI_STORE_DATA_IMM storing the completed request's seqno
> -	 * occasionally doesn't invalidate the CPU cache. Work around this by
> -	 * clflushing the corresponding cacheline whenever the caller wants
> -	 * the coherency to be guaranteed. Note that this cacheline is known
> -	 * to be clean at this point, since we only write it in
> -	 * bxt_a_set_seqno(), where we also do a clflush after the write. So
> -	 * this clflush in practice becomes an invalidate operation.
> -	 */
> -	intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
> -}

Ahem. Don't we have hardware in the pipeline which is going to need
this stuff?

> -
>  /*
>   * Reserve space for 2 NOOPs at the end of each request to be
>   * used as a workaround for not being allowed to do lite
> @@ -1800,8 +1785,6 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
>  	engine->irq_enable = gen8_logical_ring_enable_irq;
>  	engine->irq_disable = gen8_logical_ring_disable_irq;
>  	engine->emit_bb_start = gen8_emit_bb_start;
> -	if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
> -		engine->irq_seqno_barrier = bxt_a_seqno_barrier;
>  }
>  
>  static inline void
> -- 
> 2.11.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 2/6] drm/i915: Remove BXT incoherent seqno write workaround

[Chris Wilson]

On Mon, Jan 23, 2017 at 03:43:27PM +0200, Ville Syrjälä wrote:
> On Mon, Jan 23, 2017 at 01:05:57PM +0000, Chris Wilson wrote:
> > This w/a was only used for preproduction hw, which is no longer in use.
> > Remove the workaround to simplify the code.
> > 
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_lrc.c | 17 -----------------
> >  1 file changed, 17 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> > index 8ffa4961aa40..202ce1e6e499 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -1638,21 +1638,6 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> >  	return 0;
> >  }
> >  
> > -static void bxt_a_seqno_barrier(struct intel_engine_cs *engine)
> > -{
> > -	/*
> > -	 * On BXT A steppings there is a HW coherency issue whereby the
> > -	 * MI_STORE_DATA_IMM storing the completed request's seqno
> > -	 * occasionally doesn't invalidate the CPU cache. Work around this by
> > -	 * clflushing the corresponding cacheline whenever the caller wants
> > -	 * the coherency to be guaranteed. Note that this cacheline is known
> > -	 * to be clean at this point, since we only write it in
> > -	 * bxt_a_set_seqno(), where we also do a clflush after the write. So
> > -	 * this clflush in practice becomes an invalidate operation.
> > -	 */
> > -	intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
> > -}
> 
> Ahem. Don't we have hardware in the pipeline which is going to need
> this stuff?

I sincerely hope we don't have such broken hw again. Less functional
than gen2. Anyway, restoring it, or whatever is actually required, is
trivial. Deciding whether that interrupt signaling doesn't work in
future and what we need to do instead is a whole new ballgame.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Remove disable_lite_restore_wa

[Patchwork]

== Series Details ==

Series: series starting with [1/6] drm/i915: Remove disable_lite_restore_wa
URL   : https://patchwork.freedesktop.org/series/18406/
State : success

== Summary ==

Series 18406v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/18406/revisions/1/mbox/


fi-bdw-5557u     total:246  pass:232  dwarn:0   dfail:0   fail:0   skip:14 
fi-bsw-n3050     total:246  pass:207  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205     total:246  pass:224  dwarn:0   dfail:0   fail:0   skip:22 
fi-byt-j1900     total:246  pass:219  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820     total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770      total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-4770r     total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-ivb-3520m     total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-ivb-3770      total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6260u     total:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-skl-6700hq    total:246  pass:226  dwarn:0   dfail:0   fail:0   skip:20 
fi-skl-6700k     total:246  pass:222  dwarn:3   dfail:0   fail:0   skip:21 
fi-skl-6770hq    total:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-snb-2520m     total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31 
fi-snb-2600      total:246  pass:214  dwarn:0   dfail:0   fail:0   skip:32 
fi-bxt-t5700 failed to collect. IGT log at Patchwork_3582/fi-bxt-t5700/igt.log

5c31c0247c4b947cd0af336ddfc5798c74402863 drm-tip: 2017y-01m-23d-12h-27m-17s UTC integration manifest
c130e5e drm/i915: Remove unused per-bb wa_ctx for gen9
b37a1cf drm/i915: Remove BXT TDL state w/a
1cae116 drm/i915: Remove BXT disable pixel mask clamping w/a
7d92234 drm/i915: Remove BXT restore arbitration around ctx switch
ce9c295 drm/i915: Remove BXT incoherent seqno write workaround
ec84aea drm/i915: Remove disable_lite_restore_wa

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3582/
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Re: [PATCH 2/6] drm/i915: Remove BXT incoherent seqno write workaround

[Ville Syrjälä]

On Mon, Jan 23, 2017 at 01:52:02PM +0000, Chris Wilson wrote:
> On Mon, Jan 23, 2017 at 03:43:27PM +0200, Ville Syrjälä wrote:
> > On Mon, Jan 23, 2017 at 01:05:57PM +0000, Chris Wilson wrote:
> > > This w/a was only used for preproduction hw, which is no longer in use.
> > > Remove the workaround to simplify the code.
> > > 
> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_lrc.c | 17 -----------------
> > >  1 file changed, 17 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> > > index 8ffa4961aa40..202ce1e6e499 100644
> > > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > > @@ -1638,21 +1638,6 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> > >  	return 0;
> > >  }
> > >  
> > > -static void bxt_a_seqno_barrier(struct intel_engine_cs *engine)
> > > -{
> > > -	/*
> > > -	 * On BXT A steppings there is a HW coherency issue whereby the
> > > -	 * MI_STORE_DATA_IMM storing the completed request's seqno
> > > -	 * occasionally doesn't invalidate the CPU cache. Work around this by
> > > -	 * clflushing the corresponding cacheline whenever the caller wants
> > > -	 * the coherency to be guaranteed. Note that this cacheline is known
> > > -	 * to be clean at this point, since we only write it in
> > > -	 * bxt_a_set_seqno(), where we also do a clflush after the write. So
> > > -	 * this clflush in practice becomes an invalidate operation.
> > > -	 */
> > > -	intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
> > > -}
> > 
> > Ahem. Don't we have hardware in the pipeline which is going to need
> > this stuff?
> 
> I sincerely hope we don't have such broken hw again. Less functional
> than gen2. Anyway, restoring it, or whatever is actually required, is
> trivial. Deciding whether that interrupt signaling doesn't work in
> future and what we need to do instead is a whole new ballgame.

Hmm. Looks like the plans have changed since I last looked at that
specific case and apparently snooping is back. Which is nice.
Consider my objections lifted.

-- 
Ville Syrjälä
Intel OTC
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