[PATCH 00/11] DC Patches Jan 24, 2017

[PATCH 00/11] DC Patches Jan 24, 2017

[Harry Wentland]

* Mostly bug fixes here this time

Dmytro Laktyushkin (1):
  drm/amd/display: prevent setting cursor position with no surface

Harry Wentland (2):
  drm/amd/display: Don't reserve pipe for underlay on ASIC without
    underlay
  drm/amd/display: Remove power gating debug flags

Hersen Wu (1):
  drm/amd/display: Check we got a stream in update_info_frame

Joshua Aberback (1):
  drm/amd/display: Proper de-allocation of OPP

Leon Elazar (1):
  drm/amd/display: check surface size is at least as large as stream

Tony Cheng (3):
  drm/amd/display: improve debug-ability
  drm/amd/display: refactor dc_update_surfaces_for_stream
  drm/amd/display: clean up redundant logic

Yongqiang Sun (2):
  drm/amd/display: Change update surface condition, fix surface
    transition corruption.
  drm/amd/display: Fixed 4K black issue by refactor update surface.

 drivers/gpu/drm/amd/display/dc/core/dc.c           | 370 ++++++++++++---------
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c    |   4 +-
 drivers/gpu/drm/amd/display/dc/core/dc_surface.c   |  23 +-
 drivers/gpu/drm/amd/display/dc/dc.h                |   3 -
 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c       |  10 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h       |  35 --
 .../drm/amd/display/dc/dce100/dce100_resource.c    |  30 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c    |   5 +
 .../drm/amd/display/dc/dce110/dce110_resource.c    |   4 +-
 .../drm/amd/display/dc/dce112/dce112_resource.c    |  32 +-
 .../gpu/drm/amd/display/dc/dce80/dce80_resource.c  |   2 +-
 drivers/gpu/drm/amd/display/dc/inc/core_status.h   |  26 +-
 drivers/gpu/drm/amd/display/dc/inc/core_types.h    |   2 +
 13 files changed, 259 insertions(+), 287 deletions(-)

-- 
2.9.3

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[PATCH 01/11] drm/amd/display: Don't reserve pipe for underlay on ASIC without underlay

[Harry Wentland]

Change-Id: I961ed1bf9cb255cddf05b24c9915c830df492f89
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c                | 2 +-
 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 4 ++--
 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c   | 2 +-
 drivers/gpu/drm/amd/display/dc/inc/core_types.h         | 2 ++
 5 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f9b7fc85d71a..270f8c5cfeda 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -621,7 +621,7 @@ struct dc *dc_create(const struct dc_init_data *init_params)
 	core_dc->hwss.init_hw(core_dc);
 
 	full_pipe_count = core_dc->res_pool->pipe_count;
-	if (core_dc->res_pool->underlay_pipe_index >= 0)
+	if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
 		full_pipe_count--;
 	core_dc->public.caps.max_streams = min(
 			full_pipe_count,
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index ae0e7eac2c9d..dc4f270ae44a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -934,7 +934,7 @@ static bool construct(
 
 	pool->base.res_cap = &res_cap;
 	pool->base.funcs = &dce100_res_pool_funcs;
-	pool->base.underlay_pipe_index = -1;
+	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
 
 	bp = ctx->dc_bios;
 
@@ -1004,7 +1004,7 @@ static bool construct(
 	/*************************************************
 	*  Resource + asic cap harcoding                *
 	*************************************************/
-	pool->base.underlay_pipe_index = -1;
+	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
 	pool->base.pipe_count = res_cap.num_timing_generator;
 	dc->public.caps.max_downscale_ratio = 200;
 	dc->public.caps.i2c_speed_in_khz = 40;
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 64fae91dd5eb..fa8699d3b9ef 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -1243,7 +1243,7 @@ static bool construct(
 	/*************************************************
 	 *  Resource + asic cap harcoding                *
 	 *************************************************/
-	pool->base.underlay_pipe_index = -1;
+	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
 	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
 	dc->public.caps.max_downscale_ratio = 200;
 	dc->public.caps.i2c_speed_in_khz = 100;
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index bee3a41ffe9f..fea60aa5d297 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -931,7 +931,7 @@ static bool construct(
 	/*************************************************
 	 *  Resource + asic cap harcoding                *
 	 *************************************************/
-	pool->base.underlay_pipe_index = -1;
+	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
 	pool->base.pipe_count = res_cap.num_timing_generator;
 	dc->public.caps.max_downscale_ratio = 200;
 	dc->public.caps.i2c_speed_in_khz = 40;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 66bfcdb57c4c..b349b5768b6e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -230,6 +230,8 @@ struct audio_support{
 	bool hdmi_audio_native;
 };
 
+#define NO_UNDERLAY_PIPE -1
+
 struct resource_pool {
 	struct mem_input *mis[MAX_PIPES];
 	struct input_pixel_processor *ipps[MAX_PIPES];
-- 
2.9.3

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[PATCH 02/11] drm/amd/display: Remove power gating debug flags

[Harry Wentland]

They're not used anywhere

Change-Id: I607045a32ec1af4bb802a90b26301e328ef7f306
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index e0143f9f0421..332ecf8b1157 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -145,8 +145,6 @@ struct dc_debug {
 	bool disable_stutter;
 	bool disable_dcc;
 	bool disable_dfs_bypass;
-	bool disable_dpp_power_gate;
-	bool disable_hubp_power_gate;
 	bool disable_clock_gate;
 	bool disable_dmcu;
 	bool disable_color_module;
-- 
2.9.3

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[PATCH 03/11] drm/amd/display: check surface size is at least as large as stream

[Harry Wentland]

From: Leon Elazar <leon.elazar@amd.com>

Change-Id: Ifd9624e886da98bf1da27cad550faf202c679323
Signed-off-by: Leon Elazar <leon.elazar@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 4 ++--
 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 82cddb6425a0..0b8f8927162f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -967,9 +967,9 @@ static bool dce110_validate_surface_sets(
 			return false;
 
 		if (set[i].surfaces[0]->src_rect.width
-				!= set[i].stream->src.width
+				< set[i].stream->src.width
 				|| set[i].surfaces[0]->src_rect.height
-				!= set[i].stream->src.height)
+				< set[i].stream->src.height)
 			return false;
 		if (set[i].surfaces[0]->format
 				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index fa8699d3b9ef..7c12185b1dbe 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -966,9 +966,9 @@ static bool dce112_validate_surface_sets(
 			return false;
 
 		if (set[i].surfaces[0]->clip_rect.width
-				!= set[i].stream->src.width
+				< set[i].stream->src.width
 				|| set[i].surfaces[0]->clip_rect.height
-				!= set[i].stream->src.height)
+				< set[i].stream->src.height)
 			return false;
 		if (set[i].surfaces[0]->format
 				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
-- 
2.9.3

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[PATCH 04/11] drm/amd/display: Proper de-allocation of OPP

[Harry Wentland]

From: Joshua Aberback <Joshua.Aberback@amd.com>

- refactor opp_destroy functions to dce common file
  - fixes memory leak, dce specific variations didn't free regamma_params
- remove unused dce110_regamma structure

Change-Id: I30b8540c0367001e69b9571819f93866a1d59cb2
Signed-off-by: Joshua Aberback <Joshua.Aberback@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c       | 10 ++++---
 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h       | 35 ----------------------
 .../drm/amd/display/dc/dce100/dce100_resource.c    | 26 +---------------
 .../drm/amd/display/dc/dce112/dce112_resource.c    | 26 +---------------
 4 files changed, 8 insertions(+), 89 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
index 061de9e8249d..62f01911639f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
@@ -986,10 +986,12 @@ bool dce110_opp_construct(struct dce110_opp *opp110,
 
 void dce110_opp_destroy(struct output_pixel_processor **opp)
 {
-	dm_free((*opp)->regamma_params);
-	(*opp)->regamma_params = NULL;
-
-	dm_free(FROM_DCE11_OPP(*opp));
+	if (*opp) {
+		if ((*opp)->regamma_params)
+			dm_free((*opp)->regamma_params);
+		(*opp)->regamma_params = NULL;
+		dm_free(FROM_DCE11_OPP(*opp));
+	}
 	*opp = NULL;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
index f2828f044b96..a5afc0298d6f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
@@ -312,40 +312,6 @@ struct dce_opp_registers {
 	uint32_t FMT_CLAMP_COMPONENT_B;
 };
 
-struct dce110_regamma {
-	struct gamma_curve arr_curve_points[16];
-	struct curve_points arr_points[3];
-	uint32_t hw_points_num;
-	struct hw_x_point *coordinates_x;
-	struct pwl_result_data *rgb_resulted;
-
-	/* re-gamma curve */
-	struct pwl_float_data_ex *rgb_regamma;
-	/* coeff used to map user evenly distributed points
-	 * to our hardware points (predefined) for gamma 256 */
-	struct pixel_gamma_point *coeff128;
-	struct pixel_gamma_point *coeff128_oem;
-	/* coeff used to map user evenly distributed points
-	 * to our hardware points (predefined) for gamma 1025 */
-	struct pixel_gamma_point *coeff128_dx;
-	/* evenly distributed points, gamma 256 software points 0-255 */
-	struct gamma_pixel *axis_x_256;
-	/* evenly distributed points, gamma 1025 software points 0-1025 */
-	struct gamma_pixel *axis_x_1025;
-	/* OEM supplied gamma for regamma LUT */
-	struct pwl_float_data *rgb_oem;
-	/* user supplied gamma */
-	struct pwl_float_data *rgb_user;
-	uint32_t extra_points;
-	bool use_half_points;
-	struct fixed31_32 x_max1;
-	struct fixed31_32 x_max2;
-	struct fixed31_32 x_min;
-	struct fixed31_32 divider1;
-	struct fixed31_32 divider2;
-	struct fixed31_32 divider3;
-};
-
 /* OPP RELATED */
 #define TO_DCE110_OPP(opp)\
 	container_of(opp, struct dce110_opp, base)
@@ -355,7 +321,6 @@ struct dce110_opp {
 	const struct dce_opp_registers *regs;
 	const struct dce_opp_shift *opp_shift;
 	const struct dce_opp_mask *opp_mask;
-	struct dce110_regamma regamma;
 };
 
 bool dce110_opp_construct(struct dce110_opp *opp110,
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index dc4f270ae44a..6ae334b42fbf 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -633,30 +633,6 @@ struct output_pixel_processor *dce100_opp_create(
 	return NULL;
 }
 
-void dce100_opp_destroy(struct output_pixel_processor **opp)
-{
-	struct dce110_opp *dce110_opp;
-
-	if (!opp || !*opp)
-		return;
-
-	dce110_opp = FROM_DCE11_OPP(*opp);
-
-	dm_free(dce110_opp->regamma.coeff128_dx);
-	dm_free(dce110_opp->regamma.coeff128_oem);
-	dm_free(dce110_opp->regamma.coeff128);
-	dm_free(dce110_opp->regamma.axis_x_1025);
-	dm_free(dce110_opp->regamma.axis_x_256);
-	dm_free(dce110_opp->regamma.coordinates_x);
-	dm_free(dce110_opp->regamma.rgb_regamma);
-	dm_free(dce110_opp->regamma.rgb_resulted);
-	dm_free(dce110_opp->regamma.rgb_oem);
-	dm_free(dce110_opp->regamma.rgb_user);
-	dm_free(dce110_opp);
-
-	*opp = NULL;
-}
-
 struct clock_source *dce100_clock_source_create(
 	struct dc_context *ctx,
 	struct dc_bios *bios,
@@ -692,7 +668,7 @@ static void destruct(struct dce110_resource_pool *pool)
 
 	for (i = 0; i < pool->base.pipe_count; i++) {
 		if (pool->base.opps[i] != NULL)
-			dce100_opp_destroy(&pool->base.opps[i]);
+			dce110_opp_destroy(&pool->base.opps[i]);
 
 		if (pool->base.transforms[i] != NULL)
 			dce100_transform_destroy(&pool->base.transforms[i]);
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 7c12185b1dbe..cc826efac58d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -645,30 +645,6 @@ struct output_pixel_processor *dce112_opp_create(
 	return NULL;
 }
 
-void dce112_opp_destroy(struct output_pixel_processor **opp)
-{
-	struct dce110_opp *dce110_opp;
-
-	if (!opp || !*opp)
-		return;
-
-	dce110_opp = FROM_DCE11_OPP(*opp);
-
-	dm_free(dce110_opp->regamma.coeff128_dx);
-	dm_free(dce110_opp->regamma.coeff128_oem);
-	dm_free(dce110_opp->regamma.coeff128);
-	dm_free(dce110_opp->regamma.axis_x_1025);
-	dm_free(dce110_opp->regamma.axis_x_256);
-	dm_free(dce110_opp->regamma.coordinates_x);
-	dm_free(dce110_opp->regamma.rgb_regamma);
-	dm_free(dce110_opp->regamma.rgb_resulted);
-	dm_free(dce110_opp->regamma.rgb_oem);
-	dm_free(dce110_opp->regamma.rgb_user);
-
-	dm_free(dce110_opp);
-	*opp = NULL;
-}
-
 struct clock_source *dce112_clock_source_create(
 	struct dc_context *ctx,
 	struct dc_bios *bios,
@@ -704,7 +680,7 @@ static void destruct(struct dce110_resource_pool *pool)
 
 	for (i = 0; i < pool->base.pipe_count; i++) {
 		if (pool->base.opps[i] != NULL)
-			dce112_opp_destroy(&pool->base.opps[i]);
+			dce110_opp_destroy(&pool->base.opps[i]);
 
 		if (pool->base.transforms[i] != NULL)
 			dce112_transform_destroy(&pool->base.transforms[i]);
-- 
2.9.3

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[PATCH 05/11] drm/amd/display: Change update surface condition, fix surface transition corruption.

[Harry Wentland]

From: Yongqiang Sun <yongqiang.sun@amd.com>

Change-Id: I637bab884686aa244d9d896dbc4facd10bafe66b
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 270f8c5cfeda..de6ef8713ea8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1497,7 +1497,6 @@ void dc_update_surfaces_for_stream(struct dc *dc, struct dc_surface_update *upda
 
 	for (i = 0; i < surface_count; i++) {
 		struct core_surface *surface = DC_SURFACE_TO_CORE(updates[i].surface);
-		bool apply_ctx = false;
 
 		for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
 			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
@@ -1505,13 +1504,9 @@ void dc_update_surfaces_for_stream(struct dc *dc, struct dc_surface_update *upda
 			if (pipe_ctx->surface != surface)
 				continue;
 
-			if (updates[i].flip_addr) {
+			if (updates[i].flip_addr && can_skip_context_building) {
 				core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
-			}
-
-			if (updates[i].plane_info || updates[i].scaling_info
-					|| is_new_pipe_surface[j]) {
-				apply_ctx = true;
+			} else {
 
 				if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
 					core_dc->hwss.pipe_control_lock(
@@ -1546,7 +1541,7 @@ void dc_update_surfaces_for_stream(struct dc *dc, struct dc_surface_update *upda
 			}
 
 		}
-		if (apply_ctx) {
+		if (!can_skip_context_building) {
 			core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context);
 			context_timing_trace(dc, &context->res_ctx);
 		}
-- 
2.9.3

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[PATCH 06/11] drm/amd/display: prevent setting cursor position with no surface

[Harry Wentland]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Change-Id: I98ac559661295af4c2d4d151c4dd6029e27349c1
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 47816c5ee0e0..e1f579bcd789 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -232,8 +232,8 @@ bool dc_stream_set_cursor_position(
 	for (i = 0; i < MAX_PIPES; i++) {
 		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
 
-		if ((pipe_ctx->stream == stream) &&
-				(pipe_ctx->ipp != NULL)) {
+		if (pipe_ctx->stream == stream &&
+				pipe_ctx->ipp && pipe_ctx->surface) {
 			struct input_pixel_processor *ipp = pipe_ctx->ipp;
 			struct dc_cursor_mi_param param = {
 				.pixel_clk_khz = dc_stream->timing.pix_clk_khz,
-- 
2.9.3

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[PATCH 07/11] drm/amd/display: improve debug-ability

[Harry Wentland]

From: Tony Cheng <tony.cheng@amd.com>

- make failure status obvious

Change-Id: If8106b3ac98433817b1fdd414c0776f983b616a9
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/inc/core_status.h | 26 ++++++++++++------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
index 147eb7cac701..23d52aea55dd 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
@@ -29,19 +29,19 @@
 enum dc_status {
 	DC_OK = 1,
 
-	DC_NO_CONTROLLER_RESOURCE,
-	DC_NO_STREAM_ENG_RESOURCE,
-	DC_NO_CLOCK_SOURCE_RESOURCE,
-	DC_FAIL_CONTROLLER_VALIDATE,
-	DC_FAIL_ENC_VALIDATE,
-	DC_FAIL_ATTACH_SURFACES,
-	DC_FAIL_SURFACE_VALIDATE,
-	DC_NO_DP_LINK_BANDWIDTH,
-	DC_EXCEED_DONGLE_MAX_CLK,
-	DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED,
-	DC_FAIL_BANDWIDTH_VALIDATE, /* BW and Watermark validation */
-	DC_FAIL_SCALING,
-	DC_FAIL_CLK_CONSTRAINT,
+	DC_NO_CONTROLLER_RESOURCE = 2,
+	DC_NO_STREAM_ENG_RESOURCE = 3,
+	DC_NO_CLOCK_SOURCE_RESOURCE = 4,
+	DC_FAIL_CONTROLLER_VALIDATE = 5,
+	DC_FAIL_ENC_VALIDATE = 6,
+	DC_FAIL_ATTACH_SURFACES = 7,
+	DC_FAIL_SURFACE_VALIDATE = 8,
+	DC_NO_DP_LINK_BANDWIDTH = 9,
+	DC_EXCEED_DONGLE_MAX_CLK = 10,
+	DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED = 11,
+	DC_FAIL_BANDWIDTH_VALIDATE = 12, /* BW and Watermark validation */
+	DC_FAIL_SCALING = 13,
+	DC_FAIL_CLK_CONSTRAINT = 14,
 
 	DC_ERROR_UNEXPECTED = -1
 };
-- 
2.9.3

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[PATCH 08/11] drm/amd/display: refactor dc_update_surfaces_for_stream

[Harry Wentland]

From: Tony Cheng <tony.cheng@amd.com>

- reuse existing helper functions
- helper function to make it more obvious which cases we can do optimize programming

Change-Id: I5dbc2a9f896528a23364f76a4390c0847f260fd0
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 367 ++++++++++++++++++-------------
 1 file changed, 212 insertions(+), 155 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index de6ef8713ea8..170936bb378a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1007,7 +1007,7 @@ bool dc_commit_streams(
 	struct dc_bios *dcb = core_dc->ctx->dc_bios;
 	enum dc_status result = DC_ERROR_UNEXPECTED;
 	struct validate_context *context;
-	struct dc_validation_set set[MAX_STREAMS] = { 0 };
+	struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } };
 	int i, j, k;
 
 	if (false == streams_changed(core_dc, streams, stream_count))
@@ -1321,80 +1321,167 @@ bool dc_commit_surfaces_to_stream(
 	return dc_post_update_surfaces_to_stream(dc);
 }
 
-void dc_update_surfaces_for_stream(struct dc *dc, struct dc_surface_update *updates,
-		int surface_count, const struct dc_stream *dc_stream)
+static bool is_surface_in_context(
+		const struct validate_context *context,
+		const struct dc_surface *surface)
 {
-	struct core_dc *core_dc = DC_TO_CORE(dc);
-	struct validate_context *context = core_dc->temp_flip_context;
-	int i, j;
-	bool is_new_pipe_surface[MAX_PIPES];
-	const struct dc_surface *new_surfaces[MAX_SURFACES] = { 0 };
-	bool need_apply_clk_constraints = false;
-	bool can_skip_context_building = true;
+	int j;
 
-	update_surface_trace(dc, updates, surface_count);
+	for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
+		const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
 
-	*context = *core_dc->current_context;
+		if (surface == &pipe_ctx->surface->public) {
+			return true;
+		}
+	}
 
-	for (i = 0; i < context->res_ctx.pool->pipe_count; i++) {
-		struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];
+	return false;
+}
 
-		if (cur_pipe->top_pipe)
-			cur_pipe->top_pipe =
-				&context->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
+enum surface_update_type {
+	UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
+	UPDATE_TYPE_MED,  /* a lot of programming needed.  may need to alloc */
+	UPDATE_TYPE_FULL, /* may need to shuffle resources */
+};
 
-		if (cur_pipe->bottom_pipe)
-			cur_pipe->bottom_pipe =
-				&context->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
-	}
+static enum surface_update_type det_surface_update(
+		const struct core_dc *dc,
+		const struct dc_surface_update *u)
+{
+	const struct validate_context *context = dc->current_context;
 
-	for (j = 0; j < MAX_PIPES; j++)
-		is_new_pipe_surface[j] = true;
+	if (u->scaling_info || u->plane_info)
+		/* todo: not all scale and plane_info update need full update
+		 * ie. check if following is the same
+		 * scale ratio, view port, surface bpp etc
+		 */
+		return UPDATE_TYPE_FULL; /* may need bandwidth update */
 
-	for (i = 0 ; i < surface_count; i++) {
-		struct core_surface *surface = DC_SURFACE_TO_CORE(updates[i].surface);
-		bool existing_surface = false;
+	if (!is_surface_in_context(context, u->surface))
+		return UPDATE_TYPE_FULL;
 
-		new_surfaces[i] = updates[i].surface;
+	if (u->in_transfer_func ||
+		u->out_transfer_func ||
+		u->hdr_static_metadata)
+		return UPDATE_TYPE_MED;
 
-		for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
-			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
+	return UPDATE_TYPE_FAST;
+}
 
-			if (surface == pipe_ctx->surface) {
-				existing_surface = true;
-				is_new_pipe_surface[j] = false;
-			}
-		}
+static enum surface_update_type check_update_surfaces_for_stream(
+		struct core_dc *dc,
+		struct dc_surface_update *updates,
+		int surface_count,
+		const struct dc_stream_status *stream_status)
+{
+	int i;
+	enum surface_update_type overall_type = UPDATE_TYPE_FAST;
 
-		if (updates[i].plane_info ||
-			updates[i].scaling_info ||
-			!existing_surface)
-			can_skip_context_building = false;
+	if (stream_status->surface_count != surface_count)
+		return UPDATE_TYPE_FULL;
+
+	for (i = 0 ; i < surface_count; i++) {
+		enum surface_update_type type =
+				det_surface_update(dc, &updates[i]);
+
+		if (type == UPDATE_TYPE_FULL)
+			return type;
+
+		if (overall_type < type)
+			overall_type = type;
 	}
 
-	if (!can_skip_context_building && dc_stream) {
-		const struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
+	return overall_type;
+}
 
-		if (core_dc->current_context->stream_count == 0)
-			return;
+enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
 
-		/* Cannot commit surface to a stream that is not commited */
-		for (i = 0; i < core_dc->current_context->stream_count; i++)
-			if (stream == core_dc->current_context->streams[i])
-				break;
-		if (i == core_dc->current_context->stream_count)
-			return;
+void dc_update_surfaces_for_stream(struct dc *dc,
+		struct dc_surface_update *updates, int surface_count,
+		const struct dc_stream *dc_stream)
+{
+	struct core_dc *core_dc = DC_TO_CORE(dc);
+	struct validate_context *context;
+	int i, j;
+
+	enum surface_update_type update_type;
+	const struct dc_stream_status *stream_status;
+
+	stream_status = dc_stream_get_status(dc_stream);
+	ASSERT(stream_status);
+	if (!stream_status)
+		return; /* Cannot commit surface to stream that is not committed */
+
+	update_type = check_update_surfaces_for_stream(
+			core_dc, updates, surface_count, stream_status);
+
+	if (update_type >= update_surface_trace_level)
+		update_surface_trace(dc, updates, surface_count);
 
+	if (update_type >= UPDATE_TYPE_FULL) {
+		const struct dc_surface *new_surfaces[MAX_SURFACES] = { 0 };
+
+		for (i = 0; i < surface_count; i++)
+			new_surfaces[i] = updates[i].surface;
+
+		/* initialize scratch memory for building context */
+		context = core_dc->temp_flip_context;
+		resource_validate_ctx_copy_construct(
+				core_dc->current_context, context);
+
+		/* add surface to context */
 		if (!resource_attach_surfaces_to_context(
 				new_surfaces, surface_count, dc_stream, context)) {
 			BREAK_TO_DEBUGGER();
 			return;
 		}
+	} else {
+		context = core_dc->current_context;
 	}
-
 	for (i = 0; i < surface_count; i++) {
+		/* save update param into surface */
 		struct core_surface *surface = DC_SURFACE_TO_CORE(updates[i].surface);
+		struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
 
+		if (updates[i].flip_addr) {
+			surface->public.address = updates[i].flip_addr->address;
+			surface->public.flip_immediate =
+					updates[i].flip_addr->flip_immediate;
+		}
+
+		if (updates[i].scaling_info) {
+			surface->public.scaling_quality =
+					updates[i].scaling_info->scaling_quality;
+			surface->public.dst_rect =
+					updates[i].scaling_info->dst_rect;
+			surface->public.src_rect =
+					updates[i].scaling_info->src_rect;
+			surface->public.clip_rect =
+					updates[i].scaling_info->clip_rect;
+		}
+
+		if (updates[i].plane_info) {
+			surface->public.color_space =
+					updates[i].plane_info->color_space;
+			surface->public.format =
+					updates[i].plane_info->format;
+			surface->public.plane_size =
+					updates[i].plane_info->plane_size;
+			surface->public.rotation =
+					updates[i].plane_info->rotation;
+			surface->public.horizontal_mirror =
+					updates[i].plane_info->horizontal_mirror;
+			surface->public.stereo_format =
+					updates[i].plane_info->stereo_format;
+			surface->public.tiling_info =
+					updates[i].plane_info->tiling_info;
+			surface->public.visible =
+					updates[i].plane_info->visible;
+			surface->public.dcc =
+					updates[i].plane_info->dcc;
+		}
+
+		/* not sure if we still need this */
 		for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
 			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
 			struct core_stream *stream = pipe_ctx->stream;
@@ -1402,133 +1489,101 @@ void dc_update_surfaces_for_stream(struct dc *dc, struct dc_surface_update *upda
 			if (pipe_ctx->surface != surface)
 				continue;
 
-			if (updates[i].flip_addr) {
-				surface->public.address = updates[i].flip_addr->address;
-				surface->public.flip_immediate =
-						updates[i].flip_addr->flip_immediate;
-			}
-
-			if (updates[i].plane_info || updates[i].scaling_info
-					|| is_new_pipe_surface[j]) {
-				need_apply_clk_constraints = true;
-
-				if (updates[i].plane_info) {
-					surface->public.color_space =
-						updates[i].plane_info->color_space;
-					surface->public.format =
-						updates[i].plane_info->format;
-					surface->public.plane_size =
-						updates[i].plane_info->plane_size;
-					surface->public.rotation =
-						updates[i].plane_info->rotation;
-					surface->public.horizontal_mirror =
-						updates[i].plane_info->horizontal_mirror;
-					surface->public.stereo_format =
-						updates[i].plane_info->stereo_format;
-					surface->public.tiling_info =
-						updates[i].plane_info->tiling_info;
-					surface->public.visible =
-						updates[i].plane_info->visible;
-					surface->public.dcc =
-						updates[i].plane_info->dcc;
-				}
-
-				if (updates[i].scaling_info) {
-					surface->public.scaling_quality =
-						updates[i].scaling_info->scaling_quality;
-					surface->public.dst_rect =
-						updates[i].scaling_info->dst_rect;
-					surface->public.src_rect =
-						updates[i].scaling_info->src_rect;
-					surface->public.clip_rect =
-						updates[i].scaling_info->clip_rect;
-				}
-
-				resource_build_scaling_params(updates[i].surface, pipe_ctx);
-				if (dc->debug.surface_visual_confirm) {
-					pipe_ctx->scl_data.recout.height -= 2;
-					pipe_ctx->scl_data.recout.width -= 2;
-				}
+			resource_build_scaling_params(updates[i].surface, pipe_ctx);
+			if (dc->debug.surface_visual_confirm) {
+				pipe_ctx->scl_data.recout.height -= 2;
+				pipe_ctx->scl_data.recout.width -= 2;
 			}
+		}
 
-			if (dc->debug.disable_color_module)
-				continue;  /* skip below color updates */
+		if (dc->debug.disable_color_module)
+			continue;  /* skip below color updates */
 
-			if (updates[i].gamma &&
-				updates[i].gamma != surface->public.gamma_correction) {
-				if (surface->public.gamma_correction != NULL)
-					dc_gamma_release(&surface->public.
-							gamma_correction);
+		if (updates[i].gamma &&
+			updates[i].gamma != surface->public.gamma_correction) {
+			if (surface->public.gamma_correction != NULL)
+				dc_gamma_release(&surface->public.
+						gamma_correction);
 
-				dc_gamma_retain(updates[i].gamma);
-				surface->public.gamma_correction =
-							updates[i].gamma;
-			}
+			dc_gamma_retain(updates[i].gamma);
+			surface->public.gamma_correction =
+						updates[i].gamma;
+		}
 
-			if (updates[i].in_transfer_func &&
-				updates[i].in_transfer_func != surface->public.in_transfer_func) {
-				if (surface->public.in_transfer_func != NULL)
-					dc_transfer_func_release(
-							surface->public.
-							in_transfer_func);
-
-				dc_transfer_func_retain(
-						updates[i].in_transfer_func);
-				surface->public.in_transfer_func =
-						updates[i].in_transfer_func;
-			}
+		if (updates[i].in_transfer_func &&
+			updates[i].in_transfer_func != surface->public.in_transfer_func) {
+			if (surface->public.in_transfer_func != NULL)
+				dc_transfer_func_release(
+						surface->public.
+						in_transfer_func);
+
+			dc_transfer_func_retain(
+					updates[i].in_transfer_func);
+			surface->public.in_transfer_func =
+					updates[i].in_transfer_func;
+		}
 
-			if (updates[i].out_transfer_func &&
-				updates[i].out_transfer_func != stream->public.out_transfer_func) {
-				if (stream->public.out_transfer_func != NULL)
-					dc_transfer_func_release(
-							stream->public.
-							out_transfer_func);
-				dc_transfer_func_retain(
-						updates[i].out_transfer_func);
-				stream->public.out_transfer_func =
-						updates[i].out_transfer_func;
-			}
-			if (updates[i].hdr_static_metadata)
-				surface->public.hdr_static_ctx =
-					*(updates[i].hdr_static_metadata);
+		if (updates[i].out_transfer_func &&
+			updates[i].out_transfer_func != dc_stream->out_transfer_func) {
+			if (dc_stream->out_transfer_func != NULL)
+				dc_transfer_func_release(dc_stream->out_transfer_func);
+			dc_transfer_func_retain(updates[i].out_transfer_func);
+			stream->public.out_transfer_func = updates[i].out_transfer_func;
 		}
+		if (updates[i].hdr_static_metadata)
+			surface->public.hdr_static_ctx =
+				*(updates[i].hdr_static_metadata);
 	}
 
+
+	if (!surface_count)  /* reset */
+		core_dc->hwss.apply_ctx_for_surface(core_dc, NULL, context);
+
 	for (i = 0; i < surface_count; i++) {
 		struct core_surface *surface = DC_SURFACE_TO_CORE(updates[i].surface);
 
 		for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
 			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
+			struct pipe_ctx *cur_pipe_ctx;
+			bool is_new_pipe_surface = true;
 
 			if (pipe_ctx->surface != surface)
 				continue;
 
-			if (updates[i].flip_addr && can_skip_context_building) {
-				core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
-			} else {
+			if (update_type != UPDATE_TYPE_FAST &&
+				!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
+				core_dc->hwss.pipe_control_lock(
+						core_dc->hwseq,
+						pipe_ctx->pipe_idx,
+						PIPE_LOCK_CONTROL_GRAPHICS |
+						PIPE_LOCK_CONTROL_SCL |
+						PIPE_LOCK_CONTROL_BLENDER |
+						PIPE_LOCK_CONTROL_MODE,
+						true);
+			}
 
-				if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
-					core_dc->hwss.pipe_control_lock(
-							core_dc->hwseq,
-							pipe_ctx->pipe_idx,
-							PIPE_LOCK_CONTROL_GRAPHICS |
-							PIPE_LOCK_CONTROL_SCL |
-							PIPE_LOCK_CONTROL_BLENDER |
-							PIPE_LOCK_CONTROL_MODE,
-							true);
-				}
+			if (update_type == UPDATE_TYPE_FULL) {
+				core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context);
+			} else if (updates[i].flip_addr) {
+				core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
 			}
 
+			if (update_type == UPDATE_TYPE_FAST)
+				continue;
+
+			cur_pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[j];
+			if (cur_pipe_ctx->surface == pipe_ctx->surface)
+				is_new_pipe_surface = false;
+
 			if (dc->debug.disable_color_module)
 				continue;  /* skip below color updates */
 
-			if (is_new_pipe_surface[j] ||
+			if (is_new_pipe_surface ||
 					updates[i].in_transfer_func)
 				core_dc->hwss.set_input_transfer_func(
 						pipe_ctx, pipe_ctx->surface);
 
-			if (is_new_pipe_surface[j] ||
+			if (is_new_pipe_surface ||
 					updates[i].out_transfer_func)
 				core_dc->hwss.set_output_transfer_func(
 						pipe_ctx,
@@ -1539,14 +1594,12 @@ void dc_update_surfaces_for_stream(struct dc *dc, struct dc_surface_update *upda
 				resource_build_info_frame(pipe_ctx);
 				core_dc->hwss.update_info_frame(pipe_ctx);
 			}
-
-		}
-		if (!can_skip_context_building) {
-			core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context);
-			context_timing_trace(dc, &context->res_ctx);
 		}
 	}
 
+	if (update_type == UPDATE_TYPE_FAST)
+		return;
+
 	for (i = context->res_ctx.pool->pipe_count - 1; i >= 0; i--) {
 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 
@@ -1566,8 +1619,12 @@ void dc_update_surfaces_for_stream(struct dc *dc, struct dc_surface_update *upda
 		}
 	}
 
-	core_dc->temp_flip_context = core_dc->current_context;
-	core_dc->current_context = context;
+	if (core_dc->current_context != context) {
+		resource_validate_ctx_destruct(core_dc->current_context);
+		core_dc->temp_flip_context = core_dc->current_context;
+
+		core_dc->current_context = context;
+	}
 }
 
 uint8_t dc_get_current_stream_count(const struct dc *dc)
-- 
2.9.3

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[PATCH 09/11] drm/amd/display: clean up redundant logic

[Harry Wentland]

From: Tony Cheng <tony.cheng@amd.com>

Change-Id: Ie995e5bd63451c1891d3b76fe08f22a2c9b62eea
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 23 ++++++++---------------
 drivers/gpu/drm/amd/display/dc/dc.h              |  1 -
 2 files changed, 8 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
index d607972b830b..21fedd447bd1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
@@ -121,26 +121,20 @@ const struct dc_surface_status *dc_surface_get_status(
 		const struct dc_surface *dc_surface)
 {
 	struct dc_surface_status *surface_status;
-	struct core_surface *core_surface;
+	struct core_surface *core_surface = DC_SURFACE_TO_CORE(dc_surface);;
 	struct core_dc *core_dc;
 	int i;
 
-	if (dc_surface == NULL)
-		return NULL;
-
-	core_surface = DC_SURFACE_TO_CORE(dc_surface);
-
-	if (core_surface == NULL || core_surface->ctx == NULL)
-		return NULL;
+	if (!dc_surface ||
+		!core_surface->ctx ||
+		!core_surface->ctx->dc) {
+		ASSERT(0);
+		return NULL; /* remove this if above assert never hit */
+	}
 
 	surface_status = &core_surface->status;
-
-	if (core_surface->ctx == NULL || core_surface->ctx->dc == NULL)
-		return NULL;
-
 	core_dc = DC_TO_CORE(core_surface->ctx->dc);
 
-
 	if (core_dc->current_context == NULL)
 		return NULL;
 
@@ -149,8 +143,7 @@ const struct dc_surface_status *dc_surface_get_status(
 		struct pipe_ctx *pipe_ctx =
 				&core_dc->current_context->res_ctx.pipe_ctx[i];
 
-		if (pipe_ctx->surface !=
-				DC_SURFACE_TO_CORE(dc_surface))
+		if (pipe_ctx->surface != core_surface)
 			continue;
 
 		core_dc->hwss.update_pending_status(pipe_ctx);
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 332ecf8b1157..c3aca8d44d4c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -335,7 +335,6 @@ struct dc_transfer_func *dc_create_transfer_func(void);
 struct dc_flip_addrs {
 	struct dc_plane_address address;
 	bool flip_immediate;
-	/* TODO: DCC format info */
 	/* TODO: add flip duration for FreeSync */
 };
 
-- 
2.9.3

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[PATCH 10/11] drm/amd/display: Check we got a stream in update_info_frame

[Harry Wentland]

From: Hersen Wu <hersenxs.wu@amd.com>

Change-Id: I649fd0d9a986a2a7474dafd262fa1b5282666ada
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 6dbfc570b8c6..ce56f23806bc 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -837,6 +837,11 @@ static enum dc_status bios_parser_crtc_source_select(
 
 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
 {
+	ASSERT(pipe_ctx->stream);
+
+	if (pipe_ctx->stream_enc == NULL)
+		return;  /* this is not root pipe */
+
 	if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
 		pipe_ctx->stream_enc->funcs->update_hdmi_info_packets(
 			pipe_ctx->stream_enc,
-- 
2.9.3

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[PATCH 11/11] drm/amd/display: Fixed 4K black issue by refactor update surface.

[Harry Wentland]

From: Yongqiang Sun <yongqiang.sun@amd.com>

Change-Id: Ibff4c15aeddf0a013a9c2edca9b82219818cfccb
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 28 ++++++++++++++++------------
 1 file changed, 16 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 170936bb378a..01d614781def 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1482,17 +1482,19 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 		}
 
 		/* not sure if we still need this */
-		for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
-			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
-			struct core_stream *stream = pipe_ctx->stream;
+		if (update_type == UPDATE_TYPE_FULL) {
+			for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
+				struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
+				struct core_stream *stream = pipe_ctx->stream;
 
-			if (pipe_ctx->surface != surface)
-				continue;
+				if (pipe_ctx->surface != surface)
+					continue;
 
-			resource_build_scaling_params(updates[i].surface, pipe_ctx);
-			if (dc->debug.surface_visual_confirm) {
-				pipe_ctx->scl_data.recout.height -= 2;
-				pipe_ctx->scl_data.recout.width -= 2;
+				resource_build_scaling_params(updates[i].surface, pipe_ctx);
+				if (dc->debug.surface_visual_confirm) {
+					pipe_ctx->scl_data.recout.height -= 2;
+					pipe_ctx->scl_data.recout.width -= 2;
+				}
 			}
 		}
 
@@ -1563,10 +1565,12 @@ void dc_update_surfaces_for_stream(struct dc *dc,
 			}
 
 			if (update_type == UPDATE_TYPE_FULL) {
-				core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context);
-			} else if (updates[i].flip_addr) {
+				/* only apply for top pipe */
+				if (!pipe_ctx->top_pipe)
+					core_dc->hwss.apply_ctx_for_surface(core_dc,
+							 surface, context);
+			} else if (updates[i].flip_addr)
 				core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
-			}
 
 			if (update_type == UPDATE_TYPE_FAST)
 				continue;
-- 
2.9.3

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